ROHM BD91361MUV

Datasheet
2.7V to 5.5V, 4A 1ch
Synchronous Buck Converter Integrated FET
BD91361MUV
●General Description
ROHM’s high efficiency step-down switching regulator
BD91361MUV is a power supply designed to produce
a low voltage including 0.8 volts from 5.5/3.3 volts
power supply line. Offers high efficiency with our
original pulse skip control technology and synchronous
rectifier. Employs a current mode control system to
provide faster transient response to sudden change in
load.
●Key Specifications
 Input voltage range:
 Output voltage range:
 Output current:
 Switching frequency:
 High side FET ON resistance:
 Low side FET ON resistance:
 Standby current:
 Operating temperature range:
●Features
 Offers fast transient response with current mode
PWM control system.
 Offers highly efficiency for all load range with
synchronous rectifier (Nch/Nch FET)
TM
and SLLM (Simple Light Load Mode)
 Incorporates soft-start function.
 Incorporates thermal protection and ULVO
functions.
 Incorporates short-current protection circuit with
time delay function.
 Incorporates shutdown function Icc=0µA (Typ.)
●Package
VQFN020V4040:
2.7V to 5.5V
0.8V to 3.3V
4.0A (Max.)
1MHz(Typ.)
60mΩ(Typ.)
55mΩ(Typ.)
0μA (Typ.)
-40℃ to +105℃
Typ.)
(Typ.)
(Max.)
4.00mm x 4.00mm x 1.00mm
●Applications
Power supply for LSI including DSP, Micro computer
and ASIC
VQFN020V4040
●Typical Application Circuit
Rf
Cf
Cin
VCC
PVCC
EN
VCC
CBST
ADJ
VOUT
ITH
R2
R1
RITH
L
VID<1> VID<0> GND,PGND
SW
VOUT
ESR
RO
CITH
VCC
VCC
CO
Fig.1 Typical Application Circuit
○Product structure：Silicon monolithic integrated circuit
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Datasheet
BD91361MUV
●Pin Configuration (TOP VIEW)
GND
ADJ
ITH
VID<1>
VID<0>
15 14 13 12 11
N.C. 16
EN
PGND
10 VCC
17
9
18
8
19
7
20
6
1
2
3
4
BST
PVCC
5
SW
Fig.2 Pin configuration
●Pin Description
Pin
Pin
No.
name
Function
Pin
No.
Pin
name
Function
1
SW
SW pin
11
GND
Ground
2
SW
SW pin
12
ADJ
3
SW
SW pin
13
ITH
4
SW
SW pin
14
VID<1>
Output voltage detect pin
GmAmp output pin/Connected phase
compensation capacitor
Output voltage control pin<1>
5
SW
SW pin
15
VID<0>
Output voltage control pin<0>
6
PVCC
Highside FET source pin
16
N.C.
7
PVCC
Highside FET source pin
17
EN
Enable pin(High Active）
8
PVCC
Highside FET source pin
18
PGND
Lowside FET source pin
9
BST
Bootstrapped voltage input pin
19
PGND
Lowside source pin
10
VCC
VCC power supply input pin
20
PGND
Lowside source pin
Non Connection
●Block Diagram
V CC
EN
VCC
VREF
BST
Current Comp
VID<0>
SELECTOR
+
VID<1>
R Q
Current
Sense/
Protect
PVCC
Input
S
Gm Amp
+
Soft
Start
SLOPE
CLK
OSC
VCC
SW
+
Driver
Logic
UVLO
Output
PVCC
PGND
TSD
SCP
GND
ITH
ADJ
R2
RITH CITH
R1
Fig.3 Block Diagram
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Datasheet
BD91361MUV
●Absolute Maximum Ratings(Ta=25℃)
Parameter
VCC Voltage
PVCC Voltage
BST Voltage
BST_SW Voltage
EN Voltage
SW,ITH Voltage
Power Dissipation 1
Power Dissipation 2
Power Dissipation 3
Symbol
VCC
PVCC
VBST
VBST-SW
VEN
VSW, VITH
Pd1
Pd2
Pd3
Ratings
1
-0.3 to +7 *
1
-0.3 to +7 *
-0.3 to +13
-0.3 to +7
-0.3 to +7
-0.3 to +7
2
0.34 *
3
0.70 *
4
2.21 *
Power Dissipation 4
Operating temperature range
Storage temperature range
Maximum junction temperature
Pd4
Topr
Tstg
Tjmax
3.56 *
-40 to +105
-55 to +150
+150
*1
*2
*3
*4
*5
Unit
V
V
V
V
V
V
W
W
W
5
W
℃
℃
℃
Pd should not be exceeded.
IC only
1-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, 1st and 4th copper foil area : 10.29mm2 , 2nd and 3rd copper foil area : 5505mm2
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers
●Recommended Operating Ratings (Ta=-40 to +105℃)
Parameter
Power Supply Voltage
EN Voltage
Logic input voltage
Output voltage Setting Range
SW average output current
VCC
Min.
2.7
Ratings
Typ.
3.3
Max.
5.5
V
PVCC
2.7
3.3
5.5
V
VEN
0
-
5.5
V
VID<1:0>
0
-
5.5
VOUT
0.8
-
3.3*
Symbol
ISW
-
-
Unit
V
6
V
7
A
4.0*
*6 In case set output voltage 1.6V or more, VCCMin = Vout+1.2V.
*7 Pd should not be exceeded.
●Electrical Characteristics
(Ta=25℃ VCC=PVCC=3.3V, EN=VCC, VID<1>=VID<0>=0V, R1=10kΩ, R2=5kΩ, unless otherwise specified.)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
Standby current
ISTB
0
10
µA
EN=GND
Active current
ICC
250
500
µA
EN Low voltage
VENL
GND
0.8
V
Standby mode
EN High voltage
VENH
2.0
Vcc
V
Active mode
EN input current
IEN
3
10
µA
VEN=3.3V
VID Low voltage
VVIDL
GND
0.8
VID High voltage
VVIDH
2.0
Vcc
VID input current
IVID
3
10
VVID=3V
Oscillation frequency
FOSC
0.8
1
1.2
MHz
High side FET ON resistance
RONH
60
90
mΩ
PVCC=3.3V
Low side FET ON resistance
RONL
55
85
mΩ
PVCC=3.3V
ADJ Voltage
VADJ
0.788
0.800
0.812
V
VID<1:0>=(0,0)
ITH SInk current
ITHSI
10
18
µA
VADJ=1V
ITH Source Current
ITHSO
10
18
µA
VADJ=0.6V
UVLO threshold voltage
VUVLO1
2.400
2.500
2.600
V
VCC=3.3V→0V
UVLO release voltage
VUVLO2
2.425
2.550
2.700
V
VCC=0V→3.3V
Soft start time
TSS
0.5
1
2
ms
Timer latch time
TLATCH
0.5
1
2
ms
SCP/TSD
Output Short circuit Threshold Voltage
VSCP
0.40
0.56
V
VADJ =0.8V→0V
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Datasheet
BD91361MUV
●Typical Performance Curves
Fig.4 Vcc-VouT
Fig.5 VEN-VOUT
Fig.7 Ta-VOUT
Fig.6 IOUT-VOUT
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Datasheet
BD91361MUV
Fig.8 Efficiency
Fig.9 Ta-Fosc
Fig.10 Ta-RONN,RONP
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Fig.11 Ta-VEN
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Datasheet
BD91361MUV
Fig.12 Ta-ICC
Fig.13 Power supply voltageOperating frequency
Fig.14 Soft start waveform
Fig.15 SW waveform Io=0mA
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Datasheet
BD91361MUV
Fig.16 SW waveform Io=4A
Fig. 17 Transient Response
Io=1A→4A(20µs)
Fig.18 Transient Response
Io=4A→1A(20µs)
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Fig.19 Change Response
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Datasheet
BD91361MUV
Fig.20 Change Response
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Datasheet
BD91361MUV
Application Information
●Operation
BD91361MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by
employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for
heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,
and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a highside MOS FET (while a lowside
MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two
signals, a current feedback control signal (SENSE: Voltage converted from I L) and a voltage feedback control signal
(FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET
(while a lowside MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation.
TM
・SLLM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching
pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation
without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or
vise versa.
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current
Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching
is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces
the switching dissipation and improves the efficiency.
SENSE
Current
Comp
RESET
VOUT
Level
Shift
R Q
FB
SET
Gm Amp.
S
IL
Driver
Logic
VOUT
SW
Load
OSC
ITH
Fig.21 Diagram of current mode PWM control
PVCC
Current
Comp
SENSE
PVCC
SENSE
Current
Comp
FB
SET
FB
GND
SET
GND
RESET
GND
RESET
GND
SW
GND
SW
IL
IL(AVE)
GND
IL
0A
VOUT
VOUT(AVE)
VOUT
VOUT(AVE)
Not switching
TM
Fig.22 PWM switching timing chart
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Fig.23 SLLM
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switching timing chart
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Datasheet
BD91361MUV
●Description of Operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited
during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0µA (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied.
of 50mV (Typ.) is provided to prevent output chattering.
And the hysteresis width
Hysteresis 50mV
VCC
EN
VOUT
Tss
Tss
Tss
Soft start
Standby mode
Operating mode
Standby
mode
Operating mode
UVLO
UVLO
Standby
mode
Operating mode
EN
Standby mode
UVLO
Fig.24 Soft start, Shutdown, UVLO timing chart
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking
UVLO.
EN
1msec
VOUT
Output Current in non-control
1/2VOUT
Until output voltage goes up the half of
Vo or over, timer latch is not operated.
(No timer latch, only limit to the output current)
Limit
Output voltage OFF Latch
IL
Output Current in control by limit value
(With fall of the output voltage, limit value goes down)
Standby mode
Operated mode
Standby mode
EN
Timer Latch
Operated mode
EN
Fig.25 Short-current protection circuit with time delay timing chart
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Datasheet
BD91361MUV
●About Setting the Output Voltage
Output voltage shifts step by step as often as bit setting to control the overshoot/undershoot that happen when changing
the setting value of output voltage. From the bit switching until output voltage reach to setting value, 8 steps(max) delay will
occur.
(0,1)
VID<2:0>
(1,1)
0.96V
0.72V
VOUT
tVID (max)=0.04ms
ⅰ) Switching 2 bit synchronously
ⅲ) Switching the bit during counting
VID<1>
<1>
VID<0>
<0>
Count STOP
Count STOP
VOUT
VOUT
5µs(max)
About 10µs from bit switching
About 10µs from bit switching
ⅱ) Switching 2 bit with the time lag
VID<1>
VID<0>
Count STOP
VOUT
About 10µs from switching the last bit
Fig.26 Timing chart of setting the output voltage
It is possible to set output voltage, shown the diagram 1 below, by setting VID<0> to <1> 0 or 1.
VID<1:0> terminal is set to VID<1:0>=(0,0) originally by the pull down resistor with high impedance inside IC.
By pulling up/ pulling down about 10kΩ, the original value is changeable optionally.
VID<1>
Diagram 1. Table of output voltage setting
VID<0>
VOUT
0
0
VOUT
0
1
0.9*VOUT
1
0
1.1*VOUT
1
1
1.2*VOUT
*After 10µs(max) from the bit change, VOUT change starts.
*Requiring time for one step (10% shift of VOUT) of VOUT is 10µs(max).
*From the bit switching until output voltage reach to setting value, tVID(max)=0.04ms delay will occur.
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Datasheet
BD91361MUV
●Information on Advantages
Advantage 1 : Offers fast transient response with current mode control system.
BD91361MUV (Load response IO=1A→3A)
Conventional product (Load response IO=1A→3A)
VOUT
VOUT
62mV
145mV
IOUT
IOUT
Voltage drop due to sudden change in load was reduced by about 50%.
Fig.27 Comparison of transient response
Advantage 2 :
Offers high efficiency for all load range.
・For lighter load:
Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as
switching dissipation (PSW ), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and
on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor.
ON resistance of High side MOS FET : 60mΩ(Typ.)
ON resistance of Low side MOS FET : 55mΩ(Typ.)
Offers high efficiency for all load range with the improvements mentioned above.
SLLMTM
Efficiency η[%]
Achieves efficiency improvement for heavier load.
100
②
50
①
PWM
①inprovement by SLLM system
②improvement by synchronous rectifier
0
0.001
0.01
0.1
Output current Io[A]
1
Fig.28 Efficiency
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Datasheet
BD91361MUV
Advantage 3 : ・Supplied in smaller package due to small-sized power MOS FET incorporated.
・Output capacitor Co required for current mode control: 22µF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 2.2µH inductor
・Incorporates FET + Boot strap diode
Reduces a mounting area required.
V CC
EN
20mm
VCC
VREF
BST
Current Comp
VID<0>
SELECTOR
+
VID<1>
Gm Amp
+
PVCC
R Q
Current
S
Sense/
Protect
VCC
+
Driver
Soft
Start
UVLO
Rf
Output
SW
SLOPE
CLK
Input
PVCC
15mm
PGND
Logic
TSD
SCP
R1
R2
Cf C BST
L
CIN
R ITH
GND
CITH
Co
ITH
ADJ
R2
R ITH CITH
R1
Fig.29 Example application
●Switching Regulator Efficiency
Efficiency ŋ may be expressed by the equation shown below:
VOUT×IOUT
POUT
POUT
×100[%]=
×100[%]=
×100[%]
Vin×Iin
Pin
POUT+PDα
Efficiency may be improved by reducing the switching regulator power dissipation factors P Dα as follows:
η=
Dissipation factors:
2
1) ON resistance dissipation of inductor and FET : PD(I R)
2) Gate charge/discharge dissipation : PD(Gate)
3) Switching dissipation : PD(SW)
4) ESR dissipation of capacitor : PD(ESR)
5) Operating current dissipation of IC : PD(IC)
2
2
1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω] : DC resistance of inductor, RON[Ω] :
ON resistance of FET, IOUT[A] : Output current.)
2
2)PD(Gate)=Cgs×f×V (Cgs[F] : Gate capacitance of FET, f[H] : Switching frequency, V[V] : Gate driving voltage of FET)
2
Vin ×CRSS×IOUT×f
3)PD(SW)=
(CRSS[F]:Reverse transfer capacitance of FET, IDRIVE[A]:Peak current of gate.)
IDRIVE
2
4)PD(ESR)=IRMS ×ESR (IRMS[A] : Ripple current of capacitor, ESR[Ω] : Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A] : Circuit current.)
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Datasheet
BD91361MUV
●Consideration on Permissible Dissipation and Heat Generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
4
① 4 layers (Copper foil area : 5505mm2)
copper foil in each layers.
θj-a=35.1℃/W
st
th
② 4 layers (1 and 4 copper foil area :
10.29m2)
(2nd and 3rd copper foil area: 5505m2)
θj-a=56.6℃/W
③ 1 layer (Copper foil area : 10.29m2)
θj-a=178.6℃/W
④ IC only.
θj-a=367.6℃/W
Power dissipation:Pd [W]
①3.56W
3
②2.21W
2
P=IOUT ×RON
RON=D×RONP+(1-D)RONN
D
RONH
RONL
IOUT
: ON duty (=VOUT/VCC)
: ON resistance of Highside MOS FET
: ON resistance of Lowside MOS FET
: Output current
2
1
③0.70W
④0.34W
0
0
25
50
75
100 105
125
150
Ambient temperature:Ta [℃]
Fig.30 Thermal derating curve
(VQFN020V4040)
If VCC=3.3V, VOUT=1.8V, RONH=60mΩ, RONL=55mΩ
IOUT=4A, for example,
D=VOUT/VCC=1.8/3.3=0.545
RON=0.545×0.06+(1-0.545)×0.055
=0.0327+0.0250
=0.0577[Ω]
2
P=4 ×0.0577=0.2309[W]
As RONH is greater than RONL in this IC, the dissipation increases as the ON duty becomes greater.
With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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Datasheet
BD91361MUV
●Selection of Components Externally Connected
1. Selection of inductor (L)
The inductance significantly depends on output ripple current.
As seen in the equation (1), the ripple current decreases as
the inductor and/or switching frequency increases.
IL
ΔIL
VCC
ΔIL=
IL
(VCC-VOUT)×VOUT
[A]・・・(1)
L×VCC×f
Appropriate ripple current at output should be 20% more or less of
the maximum output current.
VOUT
L
ΔIL=0.2×IOUTmax. [A]・・・(2)
Co
(VCC-VOUT)×VOUT
L=
[H]・・・(3)
ΔIL×VCC×f
(ΔIL: Output ripple current, and f: Switching frequency)
Fig.31 Output ripple current
※Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases
efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its
current rating.
If VCC =5.0V, VOUT=1.2V, f=1MHz, ΔIL=0.2×3A=0.6A, for example,(BD91361MUV)
(5-1.2)×1.2
L=
=1.52µ → 2.0[µH]
0.6×5×1M
※Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for
better efficiency.
2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability
region and the equivalent series resistance required to smooth ripple voltage.
Output ripple voltage is determined by the equation (4) :
VOUT
L
ESR
ΔVOUT=ΔIL×ESR [V]・・・(4)
Co
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
※Rating of the capacitor should be determined allowing sufficient margin
against output voltage. A 22µF to 100µF ceramic capacitor is recommended.
Less ESR allows reduction in output ripple voltage.
Fig.32 Output capacitor
3. Selection of input capacitor (Cin)
VCC
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage.
The ripple current IRMS is given by the equation (5):
Cin
VOUT
L
IRMS=IOUT×
√VOUT(VCC-VOUT)
Co
[A]・・・(5)
VCC
< Worst case > IRMS(max.)
IOUT
When Vcc=2×VOUT, IRMS=
Fig.33 Input capacitor
2
If VCC=3.3V, VOUT=1.8V, and IOUTmax.=3A, (BD91361MUV)
√1.8(3.3-1.8)
=1.49[ARMS]
3
3.3
.
A low ESR 22µF/10V ceramic capacitor is recommended to 3reduce ESR dissipation of input capacitor for better efficiency.
IRMS=2×
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4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.)
1
2π×RO×CO
1
fz(ESR)=
2π×ESR×CO
fp=
A
Gain
[dB]
fp(Max.)
0
fz(ESR)
IOUTMin.
Phase
[deg]
Pole at power amplifier
IOUTMax.
When the output current decreases, the load resistance
Ro increases and the pole frequency lowers.
0
-90
fp(Min.)=
1
[Hz]←with lighter load
2π×ROMax.×CO
fp(Max.)=
1
2π×ROMin.×CO
Fig.34 Open loop gain characteristics
A
fz(Amp.)
[Hz] ←with heavier load
Zero at power amplifier
Gain
[dB]
Increasing capacitance of the output capacitor lowers the
pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the capacitor
ESR reduces to half.)
0
0
Phase
[deg]
fz(Amp.)=
-90
1
2π×RITH×CITH
Fig.35 Error amp phase compensation characteristics
Rf
Cin
VCC
PVCC
EN
VCC
CBST
ADJ
ITH
VOUT
R2
R1
Cf
RITH
L
VID<1> VID<0> GND,PGND
SW
VOUT
ESR
CITH
VCC
VCC
RO
CO
Fig.36 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.)
1
2π×RITH×CITH
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5. Determination of output voltage
The output voltage VOUT is determined by the equation (6):
VOUT=(R2/R1+1)×VADJ・・・(6) VADJ: Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
Adjustable output voltage range : 0.8V to 3.3V
L
Output
SW
Co
R2
ADJ
R1
Fig.37 Determination of output voltage
Use 1 kΩ to 100 kΩ resistor for R1.
If a resistor of the resistance higher than 100 kΩ is used, check the assembled set carefully for ripple voltage etc.
3.7
3.5
INPUT VOLTAGE : VCC[V]
The lower limit of input voltage depends on the output voltage.
Basically, it is recommended to use in the condition :
VCCmin = VOUT+1.2V.
Fig.38. shows the necessary output current value at the lower limit
of input voltage. (DCR of inductor : 20mΩ)
This data is the characteristic value, so it’ doesn’t guarantee the
operation range,
Vo=2.5V
3.3
Vo=2.0V
3.1
Vo=1.8V
2.9
2.7
0
1
2
3
OUTPUT CURRENT : IOUT[A]
Fig.38 minimum input voltage in each output voltage
●Cautions on PC Board Layout
Fig.39 Layout diagram
①Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to
the pin PGND.
②Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
※VQFN020V4040 (BD91361MUV) has thermal PAD on the reverse of the package.
The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of PCB.
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●Recommended Components Lists on Above Application
Symbol
Value
Manufacturer
Coil
2.0µH
Sumida
CDR6D28MNNP-2R0NC
CIN
Ceramic capacitor
22µF
Murata
GRM32EB11A226KE20
CO
Ceramic capacitor
22µF
Murata
GRM31CB30J226KE18
CITH
Ceramic capacitor
1000pF
Murata
CRM18 Series
6.8kΩ
Rohm
MCR03 Series
1000 pF
Murata
GRM18 Series
L
Part
Series
VOUT=1.2V
RITH
Resistance
Cf
Ceramic capacitor
Rf
Resistance
10Ω
Rohm
MCR03 Series
Ceramic capacitor
0.1µF
Murata
GRM18 Series
CBST
※The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit
characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to
accommodate variations between external devices and this IC when employing the depicted circuit with other circuit
constants modified. Both static and transient characteristics should be considered in establishing these margins. When
switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and
PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins.
●I/O Equivalence Circuit
・EN pin
・SW pin
PVCC
PVCC
PVCC
EN
SW
・ADJ pin
・ITH pin
VCC
ADJ
ITH
・BST pin
・VID pin ( VID<0>, VID<1> are the same composition
PVCC
PVCC
BST
VID
SW
Fig.40 I/O equivalence circuit
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●Operational Notes
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not
be used thereafter for any operation originally intended.
5. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
6. Input to IC terminals
+
This is a monolithic IC with P isolation between P-substrate and each element as illustrated below.
This P-layer and the N-layer of each element form a P-N junction, and various parasitic elements are formed.
If a resistor is joined to a transistor terminal as shown in Fig 41.
○P-N junction works as a parasitic diode if the following relationship is satisfied;
GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin B
B
E
Pin A
N
P+ N
P+
P
N
N
Parasitic
element
P+
N
B
GND
N
Parasitic element
GND
C
E
P substrate
P substrate
Parasitic element
P+
P
GND
Parasitic
element
GND
Other adjacent elements
Fig.41 Simplified structure of monorisic IC
7. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
8. Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 50mΩ or less. Especially, in case output
voltage is set 1.6V or more, note that use of a high DCR inductor will cause an inductor loss, resulting in decreased
output voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit
protection will be activated and output will be latched OFF. When using an inductor over 50mΩ, be careful to ensure
adequate margins for variation between external devices and this IC, including transient as well as static characteristics.
Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within operation range.
Status of this document
The Japanese version of this document is formal specification. A customer may use this translation version only for a reference
to help reading the formal version.
If there are any differences in translation version of this document formal version takes priority.
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BD91361MUV
●Ordering Information
B
D
9
1
3
6
1
M
U
V
-
Package
MUV : VQFN020V4040
E2
Packaging and forming specification
E2: Embossed tape and reel
●Physical Dimension Tape and Reel Information
●Marking Diagram
VQFN020V4040 (TOP VIEW)
Part Number Marking
D 9 1 3 6
LOT Number
1
1PIN MARK
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BD91361MUV
●Revision History
Date
Revision
17.Jan.2012
001
Changes
New Release
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Notice
●Precaution for circuit design
1) The products are designed and produced for application in ordinary electronic equipment (AV equipment, OA
equipment, telecommunication equipment, home appliances, amusement equipment, etc.). If the products are to be
used in devices requiring extremely high reliability (medical equipment, transport equipment, aircraft/spacecraft,
nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose
malfunction or operational error may endanger human life and sufficient fail-safe measures, please consult with the
ROHM sales staff in advance. If product malfunctions may result in serious damage, including that to human life,
sufficient fail-safe measures must be taken, including the following:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits in the case of single-circuit failure
2)
The products are designed for use in a standard environment and not in any special environments. Application of the
products in a special environment can deteriorate product performance. Accordingly, verification and confirmation of
product performance, prior to use, is recommended if used under the following conditions:
[a] Use in various types of liquid, including water, oils, chemicals, and organic solvents
[b] Use outdoors where the products are exposed to direct sunlight, or in dusty places
[c] Use in places where the products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2,
and NO2
[d] Use in places where the products are exposed to static electricity or electromagnetic waves
[e] Use in proximity to heat-producing components, plastic cords, or other flammable items
[f] Use involving sealing or coating the products with resin or other coating materials
[g] Use involving unclean solder or use of water or water-soluble cleaning agents for cleaning after soldering
[h] Use of the products in places subject to dew condensation
3)
The products are not radiation resistant.
4)
Verification and confirmation of performance characteristics of products, after on-board mounting, is advised.
5)
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse) is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
6)
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta).
When used in sealed area, confirm the actual ambient temperature.
7)
Confirm that operation temperature is within the specified range described in product specification.
8)
Failure induced under deviant condition from what defined in the product specification cannot be guaranteed.
●Precaution for Mounting / Circuit board design
1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the remainder of flux may negatively affect
product performance and reliability.
2)
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
Company in advance.
Regarding Precaution for Mounting / Circuit board design, please specially refer to ROHM Mounting specification
●Precautions Regarding Application Examples and External Circuits
1) If change is made to the constant of an external circuit, allow a sufficient margin due to variations of the characteristics
of the products and external components, including transient characteristics, as well as static characteristics.
2)
The application examples, their constants, and other types of information contained herein are applicable only when
the products are used in accordance with standard methods. Therefore, if mass production is intended, sufficient
consideration to external conditions must be made.
Notice - Rev.001
Datasheet
●Precaution for Electrostatic
This product is Electrostatic sensitive product, which may be damaged due to Electrostatic discharge. Please take proper
caution during manufacturing and storing so that voltage exceeding Product maximum rating won't be applied to products.
Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from
charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
●Precaution for Storage / Transportation
1) Product performance and soldered connections may deteriorate if the products are stored in the following places:
[a] Where the products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] Where the temperature or humidity exceeds those recommended by the Company
[c] Storage in direct sunshine or condensation
[d] Storage in high Electrostatic
2)
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using products of which storage time is
exceeding recommended storage time period .
3)
Store / transport cartons in the correct direction, which is indicated on a carton as a symbol. Otherwise bent leads may
occur due to excessive stress applied when dropping of a carton.
4)
Use products within the specified time after opening a dry bag.
●Precaution for product label
QR code printed on ROHM product label is only for internal use, and please do not use at customer site. It might contain a
internal part number that is inconsistent with an product part number.
●Precaution for disposition
When disposing products please dispose them properly with a industry waste company.
●Precaution for Foreign exchange and Foreign trade act
Since concerned goods might be fallen under controlled goods prescribed by Foreign exchange and Foreign trade act,
please consult with ROHM in case of export.
●Prohibitions Regarding Industrial Property
1) Information and data on products, including application examples, contained in these specifications are simply for
reference; the Company does not guarantee any industrial property rights, intellectual property rights, or any other
rights of a third party regarding this information or data. Accordingly, the Company does not bear any responsibility for:
[a] infringement of the intellectual property rights of a third party
[b] any problems incurred by the use of the products listed herein.
2)
The Company prohibits the purchaser of its products to exercise or use the intellectual property rights, industrial
property rights, or any other rights that either belong to or are controlled by the Company, other than the right to use,
sell, or dispose of the products.
Notice - Rev.001