EM MICROELECTRONIC - MARIN SA EM4298 UHF Decoder / Encoder IP-x, ISO 18000-6AB and EPC compliant Description Features The EM4298 is a single chip decoder which enables fast and cost-effective RFID UHF reader designs. EM4298 can be used in mixed populations of RW and RO RFID tags. Supports all of the EM RFID UHF tags air interfaces: EM4122 (iP-X RO) EM4444 (iP-X RW) EM4223 (ISO18000-6A ; FST) EM4324 (ISO18000-6C) Data encoding and decoding options are configurable by an external uC. PIE or PPE encoding can be used for the forward link. The return data link can be in FM0, PPE or Miller coding with data bitrate is variable up to 640 kbit/s. The EM4298 is able to track up to 10% in tag clock frequency variation. The EM4298 is expected to work as a memory mapped peripheral. The chip verifies the received data against CRC but the CRC is also passed to the uC. The configuration can be changed by the uC at any time, but might result in the loss of one word. The EM4298 chip can be reset by the uC when necessary e.g. when synchronization is lost. In this case the chip configuration is kept. One word of up to 552 bits is buffered. ISO18000-6 type A, B and C (EPC C1G2) communication standard compliant Requires only the addition of RF front-end and uC supervision Software configuration of the return link data-rate (tag to reader) Buffer one word up to 552 bits Reset command on the Command bus ° ° Operating temperature range from -40 C to +85 C Applications UHF Reader devices Wireless communication The chip implements status and statistic words which contain information like overflow, error, channel, edge counter, CRC error counter, etc. Typical Operating Configuration Fig 1 Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 1 www.emmicroelectronic.com EM4298 Definitions, abbreviations and symbols Terms and definitions Return link tag to reader communication link Forward link reader to tag communication link Absolute Maximum Ratings Parameter Symbol Supply Voltage Vdd Storage temperature Tstore Operating temperature Top Min -0.3 -50 -40 Max 3.7 150 85 Unit V °C °C Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Abbreviations uC - microcontroller PPE - pulse position encoding FM0 - bi-phase encoding PIE - pulse interval encoding CRC - cyclic-redundancy check FST - Fast super tag ACK - acknowledge NACK - not acknowledge XACK - extended acknowledge FW - forward link RET - return link Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within supply voltage range. Operating conditions Conditions: TA = -40 .. 85 °C; VDD = 3.3V; VSS = 0V (unless otherwise specified) Parameter Symbol Conditions Min. Typ. Supply Voltage VDD 3.0 3.3 Power on reset rising VPORH VDD rising 2.3 2.5 Power on reset falling VPORL VDD falling 1.9 2.2 Input Low Level VIL VSS Input High Level VIH 0.7*VDD Input Hysteresis VHYS 300 Output High Current IOH VOH = VDD – 0.8V Output Low Current IOL Input Pull-up Input Pad Capacity Dynamic cosumption RPU CIN IDYN VOL = VSS + 0.4V -5 mA 60k mA 100k 160k 10 Ohm pF 30 50 mA Timing characteristic Conditions: TA = -40 .. 85 °C; VDD = 3.3V; VSS = 0V (unless otherwise specified) Parameter Symbol Conditions Min. Typ. External clock Fosc VDD = 3 – 3.6V 16 20 frequency External clock period Tosc VDD = 3 – 3.6V 1/Fosc 1/Fosc Max. 24 Unit MHz 1/Fosc s Write operation Fig 2 Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A Unit V V V V V mV 5 clk pin FOSC = 20MHz ; VDD = 3.6V Read operation Max. 3.6 2.8 2.5 0.3* VDD VDD Fig 3 2 www.emmicroelectronic.com EM4298 Read after Write to the same register XACK - transmitted when the correct response of ACK was received. XNACK - transmitted when an error or no response of ACK was received. EM4298 in EPC mode Fig 4 Fig 6 Note: CSn can be de-asserted any time between READ or WRITE operations. Note: The TWTR time needs to be respected only when last WRITE ADDRESS = READ ADDRESS or before the reading of the statistic register. Timing parameters Name Value Min Max TRAH 0 ns TRP 4 x TOSC TRDS TOSC / 2 TRCR 0 ns TRDH 3 ns TRAS 0 ns TRAT TRAH TRRT TWAH TWCR TWAS TWP TWDS TWDH TWAT 20 ns 3 ns 3 ns 0 ns 3 x TOSC 3 ns 3 ns TWDH TWWT TWTR 20 ns TOSC Description Read address hold time Read pulse time Read data setup time RDn to CSn removal time Read data hold time Read address setup time Read Address Turnaround Time RDn Turnaround Time Write address hold time WEn to CSn removal time Write address setup time Write pulse time Write data setup time Write data hold time Write Address Turnaround Time WEn Turnaround Time Read after Write Time Fig 5 The Fig 6 shows when the EM4298 transmits these auto commands, the corresponding timing is on Fig 7. This example demonstrates the usage of EM4298 in EPC mode. These commands could be used as regular commands when their “auto” feature is disabled. This architecture supports all current EM tags and is capable to implement new protocols. EM4298 timing in EPC mode Fig 7 uC interface The EM4298 works as a memory mapped peripheral and generates an interrupt when it needs service. The uC controls the function of the EM4298 by setting of parameters through this interface and can request the transmission of a command. The uC interface pins are described in Fig 8. Functional description After power up, uC shall configure EM4298 and set the correct mode first. Then uC can request execution of a command. The communication parameters can be set individually for each direction. There are 4 possible configurations for forward link and 10 possible configurations for return link. The EM4298 supports 6 commands, 4 of them can be automatically transmitted. These “auto” commands are: ACK - transmitted when the correct data was received. NACK - transmitted when a data error was recognized or after a defined silence on the RF interface. Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A Connection to uC PINOUT a[3:0] In Address csn In Chip select rdn In Read enable wen In Write enable d[7:0] InOut Bidirectional data bus int Out Interrupt request Fig 8 3 www.emmicroelectronic.com EM4298 Most of the registers in EM4298 are realized as LIFOs and data is written in as a byte stream. This feature ensures that only the necessary number of bytes has to be written. The data need to be written in LSB first and read out MSB first. The chip should be stopped during reading or writing of a configuration registers (CONFIG, ACK CONFIG, NACK CONFIG, XACK CONFIG and XNACK CONFIG). RF Interface The EM4298 device has builtin the 3-stage filter at RF Rx data inputs I and Q: HW debouncer - filters out the potential glitches shorter than Tosc EPER filter - eliminates all preamble pulses which are not inside the user programmable bit period range WINDOW - filters out the envelope edges which are outside of allowed position of the user defined encoding External RF circuitry can use the signal tx_active to disable/enable incoming modulation and to control transmitter modulation. The rising edge of tx_active is synchronized to the start of the transmission; the falling edge to the end of transmission after an additional user programmable delay. EM4298 is not sensitive to any activity at I and Q when tx_active is set. Register Address map The registers of EM4298 are mapped as defined below. Register address map A[3:0] Register Description Name Length [Bytes] Type 0x0 0x1 23 5-12 RW RW 4-11 RW 5-12 RW 4-11 RW 1 RW 1 1 7-70 RW RW RW 5-12 RW 1 1 1 RO RO RW 4-72 10 RO RO 0x5 CONFIG ACK CONFIG NACK CONFIG XACK CONFIG XNACK CONFIG INT MASK 0x6 0x7 0x8 CONTROL1 CONTROL2 CMD1 0x9 CMD2 0xA 0xB 0xC STATUS ERROR SLOT 0xE 0xF DATA STATISTIC 0x2 0x3 0x4 I and Q channels filtering Fig 9 Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A Configuration Default ACK configuration Default NACK configuration Default XACK configuration Default XNACK configuration Interrupt source mask register Control register 1 Control register 2 Command 1 register Command 2 register Status register Error register Slot control register Received data Statistic counters Fig 10 4 www.emmicroelectronic.com EM4298 Config register Configuration is performed by writing an appropriate byte stream to the CONFIG register. Config MSB Name EPCLPrm Length 1 bit Return link 3 bits Forward link 2 bits RespLength[9:8] RespLength[7:0] 2 bits 8 bits ZeroPeriod 8 bits OnePeriod 8 bits RTCal 8 bits TRCal 8 bits PWLen 8 bits DelLen 8 bits InsCRCStart point Added CRC 8 bits 2 bits Inserted CRC 2 bits RecCRC 2 bits ReUseSRC0[9:8] ReUseSRC0[7:0] 2 bits 8 bits ReUseLength 6 bits ReUseSRC1[9:8] ReUseSRC1[7:0] 2 bits 8 bits TxWait 8 bits TTOLength 4 bits FSTMute 1 bit StopAfterACK 1 bit DataOnlyAfterACK 1 bit T2_time[8] T2_time[7:0] DataIgnoreCRC 1 bit 8 bits 1 bit DataFM0aa Eper[13:8] 1 bit 6 bits Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A Description Default length of EPC preamble SHORT = 0, LONG = 1 Return link selection 001 – PPE 100 – Miller 2 010 – FM0 ISO 101 – Miller 4 011 – FM0 EPC 110 – Miller 8 Forward link selection 00 – PPE 10 – PIE ISO 01 – Manchester 11 – PIE EPC Default length of the tag responses. This value is loaded into decoder as default length of responses after resets. Define the FW zero bit period Period = ZeroTime value * CLKper025us * Tosc Define the FW one bit period Period = OneTime value * CLKper025us * Tosc Length of RTcall (FW PIE encoding ONLY) Length = RTCalTime value * 4 * CLKper025us * Tosc Length of TRcall (FW PIE encoding ONLY) Length = TRCalTime value * 4 * CLKper025us * Tosc Define the length of the FW pulse Length = PWTime value * CLKper025us * Tosc Define the length of the delimiter of the PIE EPC Length = DelTime value * CLKper025us * Tosc Define the first position of inserted CRC Select CRC, which is added at the end of CMDs 00 – CRC5 CCITT 10 – CRC16 CCITT 01 – CRC5 iPico 11 – CRC16 iPico Select CRC, which is inserted into the CMDs 00 – CRC5 CCITT 10 – CRC16 CCITT 01 – CRC5 iPico 11 – CRC16 iPico Select CRC of the responses. 00 – CRC5 CCITT 10 – CRC16 CCITT 01 – CRC5 iPico 11 – CRC16 iPico Pointer Bank number 0 Define the first bit of the response which has to be stored for future reusing. Define the length of the ReUse part of the response. Length = ReUseLength value + 1 Pointer Bank number 1 Define the first bit of the response which has to be stored for future reusing. Define the delay on Tx_active output. Delay = TxWait value * Tosc Define the expected number of the TTO responses for IP-X protocols. This info can be used by uC to summarize TTO responses. Enables MUTE during preamble. Return link must be FM0ISO. The automatic transmission of the ACKs and NACKs is stopped after ACK transmission when this bit is set. The interrupt is generated when the data is received after ACK. (RND16 in EPC mode doesn‟t generate interrupts when this bit is set) This bit should be used in combination with the StopAfterACK bit. Time from Tag response to Interrogator transmission Time = T2Time value * 4 * CLKper025us * Tosc EM4298 ignores the result of the response CRC when this bit is set. CRC errors statistic counter is not increased when CRC error occurs in response. ACKIgnoreCRC is ignored, ACK is sent when data is received. FM0 auto alignment is enabled when this bit is set. Expected Return Bit Period. 5 www.emmicroelectronic.com EM4298 Name EPer[7:0] Length 8 bits DefLimit[15:8] DefLimit[7:0] 8 bits 8 bits ACKEnable NACKEnable XACKEnable 1 bit 1 bit 1 bit XNACKEnable 1 bit RFU CLKper025us 1 bit 3 bits EPERTol 1 bit RFU TimeOut[9:0] TimeOut[7:0] 5 bits 2 bits 8 bits LSB Description I and Q decoders filter out preamble bits which are out of 25 or 50% tolerance related to this value. Expected Bit Period = EPer value * Tosc This feature is disabled when EPer value = 0. Define limit for detection of default level change on I and Q channels. Time to change default level = DefLimit value * Tosc This feature can be disabled and the default level could be set to „0‟ when DefLimit = 0x00 or to „1‟ when DefLimit = 0xFF Enables ACK feature. Enables NACK feature. Enables XACK feature. ACK feature has to be enabled otherwise XACK cannot be sent. Enables XNACK feature. ACK feature has to be enabled otherwise XNACK cannot be sent. Not used. Define the number of system clock per 0.25 us. Default value for 20 MHz is 0x5 Number of clock = CLKper025us value Define if 25 or 50% tolerance is used for EPER FILTER 25% = 0, 50% = 1 Not used. T1 + T3 time. Time = TIMEOUT value * 4 * CLKper025us * Tosc T1 - Time from Interrogator transmission to Tag response T3 - Time an Interrogator waits, after T1, before it issues another command Fig 11 Application Note: The decoder can be configured to apply a filter to the return (T->R) data stream to accept signals only with periods within a specified range. This is accomplished by specifying the center frequency of the range (EPer in the CONFIG register) and a tolerance (either ±25% or ±50% - selected with the EPERTol bit in the CONFIG register). While waiting for the preamble to a response or unsolicited ID transmission, pulses with periods not within this range will cause the decoder to restart the preamble detection process (and baud rate determination). This feature can be disabled by specifying a value of 0 (zero) for EPer – in this case the decoder will be fully “autobaud” and accept responses/UDs with frequencies between 32kHz and 640kHz. When preamble filtering is disabled any noise on the I and Q data streams before the preamble will result in an incorrect calculation of the T->R data rate and the loss of the message. Application Note: For more information how to setup and use the EM4298, pls refer to separate document – Application Notes: AN4xx_HowToUseEM4298. Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 6 www.emmicroelectronic.com EM4298 ACK Config register The ACK command is automatically transmitted when correct data is received. The EM4298 can be configured to ignore the received CRC. In this case the ACK is always transmitted when a response is received without bit errors. The time between the end of the tag response and the start of the command transmission is programmable (T2_time in CONFIG register). The length of the ACK stream is up to 64 bits and the length of reused part is up to 64 bits also. See Fig 12. The structure of the ACK CONFIG register MSB Name AddCRC Length 1 bit InsertCRC 1 bit PreambleSelect 2 bits ReUse 1 bit StoreResp 1 bit RespLength[9:8] RespLength[7:0] 2 bits 8 bits ReUseSRCSel 1 bit ACKIgnoreCRC 1 bit ReUseTARPtr ReUseXor 6 bits 1 bit RFU ACKLength 1 bit 6 bits ACKStream 1–8 bytes LSB Description CRC is added at the end of the ACK stream when this bit is set. The length is defined by the selected CRC. CRC replaces a part of ACKStream when this bit is set. The start position is defined by CONFIG and the length is defined by the selected CRC. Select preamble waveform. See Forward link encodings. A part of the previous response replaces a part of the ACKStream when this bit is set. A part of the response to the ACK is stored for future use when this bit is set. Define new expected length of responses. This value rewrites the old value in the decoder. Length = RespLength value + 1 Define which bank has to be used. See CONFIG. ReUseSPointer1 when this bit is set else ReUseSPointer0 Ignore the result of CRC for ACK command when this bit is set. ACK is transmitted even if the selected CRC of the response doesn‟t match and CRC errors statistic counter is not increased. Define the insert position in ACK for the part of the response ReUsed data are XORed with the corresponding part of the ACKStream when this bit is set otherwise the ReUse data replaces ACKStream. No used. Define the length of the ACK Length = ACKLength value + 1 ACK stream Last byte must be filled from MSB bits if the length is not rounded to whole bytes. Fig 12 Note: No overlay of ReUse part and InsertedCrc is allowed. NACK Config register The second command which can be automatically transmitted is NACK. The NACK is transmitted when there is no activity on RF side for a defined time (TIMEOUT) or when an error is detected. Errors can be bit error or CRC error. The CRC error may be ignored, see Fig 12. The length of the NACK stream is up to 64 bits. The structure of the NACK CONFIG register is described in Fig 13. The structure of the NACK CONFIG register MSB Name AddCRC Length 1 bit InsertCRC 1 bit PreambleSelect 2 bits StoreResp 1 bit ReUseSRCSel 1 bit RespLength[9:8] RespLength[7:0] 2 bits 8 bits RFU NACKLength 2 bits 6 bits NACKStream 1–8 bytes LSB Description CRC is added at the end of the NACK stream when this bit is set. The length is defined by the selected CRC. CRC replaces a part of NACKStream when this bit is set. The start position is defined by CONFIG and the length is defined by the selected CRC. Select preamble waveform. See Forward link encodings. A part of the response to the NACK is stored for future use when this bit is set. Define which bank has to be used. See CONFIG. ReUseSPointer1 when this bit is set else ReUseSPointer0 Define new expected length of responses. This value rewrites the old value in the decoder. Length = RespLength value + 1 Not used Define the length of the NACK Length = NACKLength value + 1 NACK stream Last byte must be filled from MSB bits if the length is not rounded to whole bytes.. Fig 13 Note: No overlay of ReUse part and InsertedCrc is allowed. Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 7 www.emmicroelectronic.com EM4298 XACK Config register The third command which can be automatically transmitted is XACK. The XACK is transmitted when a correct response of ACK command was received. The length of the XACK stream is up to 64 bits. The time between the end of the tag response and the start of the command transmission is programmable (T2_time in CONFIG register). The structure of the XACK CONFIG register is described in Fig 14. The structure of the XACK CONFIG register MSB Name AddCRC Length 1 bit InsertCRC 1 bit PreambleSelect 2 bits ReUse 1 bit StoreResp 1 bit RespLength[9:8] RespLength[7:0] 2 bits 8 bits ReUseSRCSel 1 bit RFU ReUseTARPtr ReUseXor 1 bit 6 bits 1 bit RFU XACKLength 1 bit 6 bits XACKStream 1–8 bytes LSB Description CRC is added at the end of the ACK stream when this bit is set. The length is defined by the selected CRC. CRC replaces a part of XACKStream when this bit is set. The start position is defined by CONFIG and the length is defined by the selected CRC. Select preamble waveform. See Forward link encodings. A part of the previous response replaces a part of the XACKStream when this bit is set.. A part of the response to the XACK is stored for future use when this bit is set. Define new expected length of responses. This value rewrites the old value in the decoder. Length = RespLength value + 1 Define which bank has to be used. See CONFIG. ReUseSPointer1 when this bit is set else ReUseSPointer0 Not used Define the insert position in ACK for the part of the response ReUsed data are XORed with the corresponding part of the ACKStream when this bit is set otherwise the ReUse data replaces ACKStream. Not used Define the length of the XACK Length = XACKLength value + 1 XACK stream Last byte must be filled from MSB bits if the length is not rounded to whole bytes. Fig 14 Note: No overlay of ReUse part and InsertedCrc is allowed. Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 8 www.emmicroelectronic.com EM4298 XNACK Config register The fourth command which can be automatically transmitted is XNACK. The XNACK is transmitted when an error response or no response of ACK command was received. Errors can be bit error or CRC error. No response is triggered by silence on I and Q for TIMEOUT. The length of the XNACK stream is up to 64 bits. The structure of the XNACK CONFIG register is described in. The structure of the XNACK CONFIG register MSB Name AddCRC Length 1 bit InsertCRC 1 bit PreambleSelect 2 bits StoreResp 1 bit ReUseSRCSel 1 bit RespLength[9:8] RespLength[7:0] 2 bits 8 bits RFU XNACKLength 2 bits 6 bits XNACKStream 1–8 bytes LSB Description CRC is added at the end of the ACK stream when this bit is set. The length is defined by the selected CRC. CRC replaces a part of XACKStream when this bit is set. The start position is defined by CONFIG and the length is defined by the selected CRC. Select preamble waveform. See Forward link encodings. A part of the response to XNACK is stored for future use when this bit is set. Define which bank has to be used. See CONFIG. ReUseSPointer1 when this bit is set else ReUseSPointer0 Define new expected length of responses. This value rewrites the old value in the decoder. Length = RespLength value + 1 Not used Define the length of the XNACK Length = XACKLength value + 1 XNACK stream Last byte must be filled from MSB bits if the length is not rounded to whole bytes. Fig 15 Note: No overlay of ReUse part and InsertedCrc is allowed Interrupt generation and interrupt MASK register There are 8 possible sources of the interrupt. All of them could be masked by writing „1‟s to a correspond position of the INTERRUPT MASK register. See Fig 16 for more details about INTERRUPT MASK register. Interrupt mask register structure IntMask[x] Description 7 Mask ERRORS 6 Mask Inventory round finish 5 Mask AUTO NACK transmission 4 Mask AUTO ACK transmission 3 Mask Command transmission 2 Mask Data ready 1 Mask Rx activity 0 Mask Tx activity Fig 16 The interrupt is indicated by high level of the int signal. The interrupt is asserted anytime when at least one of the interrupt set conditions comes. These conditions are described in Fig 17. It is necessary to manipulate all status bits to deassert the interrupt. The interrupt reset conditions and their corresponding status bit events are described in Fig 17 also. The interrupt set condition Interrupt set condition Status(6) changed to ‟1‟ Description An error detected ERROR register ≠ 0 The inventory slot counter reached max value Interrupt reset condition Clear ERROR See chapter 0. Read STATUS Status(5) = „1‟ NACK or XNACK were automatically transmitted Read STATUS Status(4) = „1‟ Read STATUS Status(2) = „1‟ ACK or XACK were automatically transmitted Command transmission done transmission requested by CONTROL2 [5:0] Unread data available in DATA register Change of Status(1) The EM4298 starts or stops to receive data from RF Read STATUS Change of Status(0) The EM4298 starts or stops to transmit command Read STATUS Status(7) = „1‟ Status(3) = „1‟ Read STATUS Write „1‟ to CONTROL1[0] Fig 17 Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 9 www.emmicroelectronic.com EM4298 Control1 Register This register is used to control the RF part and the internal states of EM4298. See Fig 18 for details. Structure of the Control1 register 7 Name RF ON Length 1 bit 6 ResetFSMs 1 bit 5 ClearStatCnts 1 bit 4 Clear TTO message # 1 bit 3 2 RFU DecTestMux Resume 1 bit 1 bit 1 bit DataRead 1 bit 1 0 Description Registered output. Mapped on RF ON pad. This bit stops the chip, when is set to „0‟. Soft reset of EM4298. Only value of the CONFIG, ACK CONFIG, NACK CONFIG, XACK CONFIG, XNACK CONFIG, INT MASK, CONTROL1, CMD1, CMD2, SLOT and STATISTIC registers is preserved. This bit is auto-cleared. Read always as „0‟. If the uC writes „1‟ the statistic counters are moved to the output register. The statistic counters are cleared and uC shall read the STATISTIC register after this. Clears ERROR[1] bit. This bit is auto-cleared. Read always as „0‟. Clear TTO counter. The messages are numbered from 0. Used for IP-X protocols only. This bit is auto-cleared. Read always as „0‟. Not used Only for test purposes This bit is used in combination with the StopAfterACK bit to control anticollision. When the ACK is sent and StopAfterACK bit is set the EM4298 automatically stops the transmission of the ACKs and NACKs. If the uC writes „1‟ to this bit, the EM4298 restarts with ACK and NACK transmission. This bit is auto-cleared. Read always as „0‟. uC informs that the Data register was read and could be reloaded by new data. Clears Status[2] bit. This bit is auto-cleared. Read always as „0‟. Fig 18 Control2 Register This register is used to control the command transmission. See Fig 19 for details. Structure of the Control2 register 7 Name NoWait TEPCLPrm Length 1 bit 1 bit DoXNACK 1 bit DoXACK 1 bit DoNACK 1 bit DoACK 1 bit DoCMD2 1 bit DoCMD1 1 bit 6 5 4 3 2 1 0 Description Send command immediately, don‟t wait for T2 time. Temporary length of EPC preamble. The preamble length of EPC could be temporary changed to LONG when this bit is set. Only for EPC purposes. Request to transmit XNACK. This feature can be used only when XNACKEnable = 0. This bit is auto-cleared. Read always as „0‟. Request to transmit XACK. This feature can be used only when XACKEnable = 0. This bit is auto-cleared. Read always as „0‟. Request to transmit NACK. This feature can be used only when NACKEnable = 0. This bit is auto-cleared. Read always as „0‟. Request to transmit ACK. This feature can be used only when ACKEnable = 0. This bit is auto-cleared. Read always as „0‟. Request to transmit CMD2. This bit is auto-cleared. Read always as „0‟. uC has to first load the CMD2 register. uC sets this bit to transmit the CMD2. Request to transmit CMD1. This bit is auto-cleared. Read always as „0‟. uC has to first load the CMD1 register. uC sets this bit to transmit the CMD1. Fig 19 Note: The Error[2] bit is set when more than one request is set at the same time and only the request with the highest priority is processed. The priority of requests is from CONTROL2[0] to CONTROL2[5] and the highest priority has CONTROL2[0]. Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 10 www.emmicroelectronic.com EM4298 Command 1 register This address is used for a command which should be transmitted. The command length is up to 512 bits and need not be rounded to whole bytes. When the uC wants to transmit a command the uC shall write a byte stream to this address and then set bit DoCMD1 in the control register. The data are transmitted MSB first. If the command is not rounded to a whole byte, the last byte must be filled from the MSB bits, LSB bits are ignored. The data stream is described in Fig 20. The structure of the CMD1 register MSB Name AddCRC Length 1 bit InsertCRC 1 bit PreambleSelect 2 bits ReUse 1 bit StoreResp 1 bit RespLength[9:8] RespLength[7:0] 2 bits 8 bits ReUseSRCSel 1 bit ReUseXor 1 bit RFU ReUseTARPtr[8] ReUseTARPtr[7:0] RFU CMDLength[8] CMDLength[7:0] CMDStream 5 bits 1 bit 8 bits 7 bits 1 bit 8 bits 1 – 64 bytes LSB Description CRC is added at the end of Command stream when this bit is set CRC replaces a part of the CMDStream when this bit is set. The start position is defined by CONFIG and the length is defined by the selected CRC. Select preamble waveform. See Forward link encodings. A part of the previous response replaces a part of the CMDStream when this bit is set. A part of the response of ACK is stored for future use when this bit is set. Define new expected length of responses. This value rewrites the old value in the decoder. Length = RespLength value + 1 Define which bank has to be used. See CONFIG. ReUseSPointer1 when this bit is set else ReUseSPointer0 ReUsed data are XORed with the corresponding part of the ACKStream when this bit is set otherwise the ReUse data replaces ACKStream. Not used Define the insert position in ACK for the part of the response Not used Define the length of the CMD1 Length = CMDLength value + 1 Command stream Last byte must be filled from MSB bits if the length is not rounded to whole bytes. Fig 20 Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 11 www.emmicroelectronic.com EM4298 Command 2 register The Command stream length of this register is up to 64 bits and need not be rounded to whole bytes. When the uC wants to transmit a command the uC shall write a byte stream to this address and then set bit DoCMD2 in the control register. The data are transmitted MSB first. If the command is not rounded for whole bytes the last byte must be filled from MSB bits. The data stream is described in Fig 21. The structure of CMD2 register MSB Name AddCRC Length 1 bit InsertCRC 1 bit PreambleSelect 2 bits ReUse 1 bit StoreResp 1 bit RespLength[9:8] RespLength[7:0] 2 bits 8 bits ReUseSRCSel 1 bit ReUseXor 1 bit ReUseTARPtr 6 bits RFU CMDLength 2 bits 6 bits CMDStream 1–8 bytes LSB Description CRC is added at the end of Command stream when this bit is set CRC replaces a part of CMDStream when this bit is set. The start position is defined by CONFIG and the length is defined by the selected CRC. Select preamble waveform. See Forward link encodings. A part of the previous response replaces a part of the CMDStream when this bit is set. A part of the response of ACK is stored for future use when this bit is set. Define new expected length of responses. This value rewrites the old value in the decoder. Length = RespLength value + 1 Define which bank has to be used. See CONFIG. ReUseSPointer1 when this bit is set else ReUseSPointer0 ReUsed data are XORed with the corresponding part of the ACKStream when this bit is set otherwise the ReUse data replaces ACKStream. Define the insert position in ACK for the part of the response Not used Define the length of CMD2 Length = CMDLength value + 1 Command stream Last byte must be filled from MSB bits if the length is not rounded to whole bytes. Fig 21 Status Register All status bits are potential interrupt sources but all of them are maskable by the configuration bits in the INT MASK register. The interrupt flag is cleared by reading this register. Reading this register also clears its contents except bits Status[0-2], and Status[7]. Description of the STATUS word Status[x] Description 7 An Error occurred. See error register. Cleared when ERROR register = 0 Inventory round done The defined number of slots for inventory round reached. uC should define new parameters and restart a new round of inventory. Generates interrupt when value goes to „1‟ Cleared by writing „1‟ to SLOT[7]. NACK transmitted. This bit is set after XNACK transmittion when XNACKEnable bit is set else after NACK. ACK transmitted. This bit is set after XACK transmittion when XACKEnable bit is set else after ACK. Command transmitted. This bit is set when command was transmitted as was requested by DoXXX in CONTROL2 register Correct response received from I or Q channel Cleared by writing „1‟ to CONTROL1[0]. I or Q channel active. 1 when Rx is active. Generates interrupt when value is changed. Read only flag. Busy bit. 1 when Tx is active. Generates interrupt when value is changed Read only flag. 6 5 4 3 2 1 0 Fig 22 Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 12 www.emmicroelectronic.com EM4298 ERROR Register EM4298 sets an error flag when error is detected. These error flags are described in Fig 23. All error flags are potential interrupt sources but can be globally masked by bit 7 in the INTERRUPT MASK register. The error byte is cleared by reading of its content except Error[1] and Error[5]. Error[5] is cleared when correct configuration is loaded into CONFIG register. Error[1] is cleared by writing „1‟ to CONTROL1[5] bit. Description of the ERROR word Error[x] Description 7-6 Not used 5 Wrong configuration Data length buffer overflow More than 552 data bits received from RF Bit error detected on I or Q channel CMD transmit request missed A bit of CONTROL2[5:0] set when STATUS[0] high or more than one bit of CONTROL2[5:0] set at the same time At least one statistic counter reached max value Data overflow No free buffer for new RF data Fig 23 4 3 2 1 0 The description when the Wrong configuration bit is set is defined by Fig 24. Description of the Wrong configuration bit Wrong cfg condition Error[5] Config[DataOnlyAfterACK] = „1‟ 1 AND CONFIG[ACKEnable] = „0‟ CONFIG[XACKEnable] = „1‟ 1 AND CONFIG[ACKEnable] = „0‟ CONFIG[StopAfterACK] = „1‟ 1 AND CONFIG[ACKEnable] = „0‟ Unknown CONFIG[Return Link] 1 ELSE 0 Fig 24 Slot control register The slot counter is used to manage the inventory process, when the max number of slots is reached the Status[6] is set and the interrupt can be generated. The uC should react to this event by setting new parameters of the inventory. The event, that the new inventory parameters were set, is signaled to EM4298 by ClrSlotCnt bit of this register. Slot Control Register structure 7 6:4 3:0 Name ClrSlotCnt Length 1 bit RFU MaxSlot 3 bits 4 bits Description Request to clear the Slot counter. This bit is auto-cleared. Read always as „0‟. Not used Define the number of slots per round Number of slots = 2MaxSlot Fig 25 The function of the slot counter is specified in Fig 26. Function of the Slot Counter Condition NACKEnable = „1‟ ACKEnable = „1‟ XACKEnable = „0‟ ACKEnable = „1‟ XACKEnable = „1‟ ACKEnable = „1‟ XNACKEnable = „1‟ Event NACK transmitted ACK transmitted New Slot CNT value N+1 N+1 XACK transmitted N+1 XNACK transmitted N+1 Other N Fig 26 Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 13 www.emmicroelectronic.com EM4298 Data register The received data can be read from the DATA address. The DataValid bit indicates that the content is valid. This bit is automatically cleared when the content is read. The received data are checked against the CRC and its status is signaled by the CRC_OK bit. The DataSource bit informs if the data are from I or Q channel. “1” means Q channel. See Fig 27. The EM4298 buffers one word. The received data is automatically moved to this register when the Status[0] is not set. If the Status[0] is set and new data is received, the STATUS[7] is set and this new data is ignored. The structure of the Data register MSB Name DataValid Length 1 bit DataSource 1 bit RFU CRCStatus 2 bit 2 bit CRCNStatus 2 bits TTO message # 4 bits RFU DataLength[9:8] 2 bits 2 bits DataLength[7:0] 8 bits DataStream 1 – 69 Bytes LSB Description If 1 data is valid and hasn‟t been read by uC. Channel Q = 1 Channel I = 0 Not used The last 2 CRC statuses, 1 if CRC is OK. The last 2 CRC statuses of data with negated last received bit, 1 if CRC is OK. The estimated number of message for TTO responses. The EM4298 tries to number the responses including corrupted message. Used for IP-X protocols only. Not used The number of received bits. Received data stream. The data stream is byte rounded. The latest received byte is read first. Fig 27 Note: TTO message # is computed separately for each channel (I and Q). Statistics Register The statistics counters provide the statistics information which can be used to determine the quality of the field. Structure of the STATISTICS register MSB LSB Name # of I edges[15:8] # of I edges[7:0] # of I preambles # of I bits # of I CRC errors # of Q edges[15:8] # of Q edges[7:0] # of Q preambles # of Q bits # of Q CRC errors Length 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits Description Number of edges from I Number of preamble errors from I Number of bit errors from I Number of CRC errors from I Number of edges from Q Number of preamble errors from Q Number of bit errors from Q Number of CRC errors from Q Fig 28 Forward link The forward link is selected according to following table. Forward link select table Code Mode 00 PPE 01 Manchester 10 PIE – ISO 11 PIE – EPC A ONE is represented by a HIGH in the first quarter of the bit period, while a ZERO is represented by a HIGH in the third quarter of the bit period. The length of a bit period is defined in CONFIG register. PPE data encoding Fig 29 PPE encoding The transmitted data packets always consist of 11 preamble bits followed by data bits. The preamble consists of 8 start bits (ZEROES), followed by a SYNCH. The SYNCH consists of a LOW for two bit periods followed by a ONE. See Fig 30. Fig 30 There is only one type of preamble, therefore the PreambleSelect parameter is ignored. Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 14 www.emmicroelectronic.com EM4298 MANCHESTER encoding The transmitted data packets always consist of 9 preamble bits followed by 5 bits of the delimiter and data bits. There are 4 possible delimiters which one is used is selected by PreambleSelect parameter. See Fig 31. Preamble and delimiters in Manchester encoding Fig 31 There is only one type of preamble PreambleSelect parameter is ignored. PIE - EPC encoding The start of transmission is recognized by a Preamble or a Frame-Sync. The Preamble and the Frame-Sync transmit pivot information. This pivot is equal to half of the RTcal length. RTCal should be between 2.5 and 3 ZeroPeriods (3xTari). TRCal should be between 1.1 and 3 RTCal. The tags decode the data according to this pivot. The bit length of the ZEROs and ONEs is defined by the ZeroPeriod and OnePeriod parameters. OnePeriod should be between 1.5 and 2 ZeroPeriods. All these parameters are defined in CONFIG register. See Fig 34 and Fig 36. Preamble and Frame-Sync A ZERO is represented by a HIGH in the first half of the bit period, while a ONE is represented by a HIGH in the second half of bit period. See Fig 32. The length of a bit period is defined by configuration register. Manchester encoding Fig 34 PreambleSelect[0] defines what is used if Preamble or Frame-Sync. See Fig 35. PreambleSelect[1] bit is ignored. SOF selection PreambleSelect[0] 0 1 Fig 32 PIE - ISO encoding The transmitted data are bounded by unique symbols SOF and EOF. The SOF transmits pivot information. This pivot is equal to the half of RTCal. The RTCal should be equal to 3 ZeroPeriods (3xTari). The tags decode the data according to this pivot. The bit length of the ZEROs and ONEs is defined by the ZeroPeriod and OnePeriod parameters. The OnePeriod should be equal to 2 ZeroPeriods. All these parameters are defined in CONFIG register. See Fig 33. Selection Preamble Frame-Sync Fig 35 PIE symbols PIE – ISO Forward link encoding Fig 36 Return link The return link mode is selected according to following table. Return link select table Code 001 010 011 100 101 110 OTHERS Fig 33 Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 15 Mode PPE FM0 ISO FM0 EPC Miller 2 Miller 4 Miller 8 NOT USED www.emmicroelectronic.com EM4298 Fig 37 recognized as ZERO if there is a change in the middle of bit period. The bit is recognized as ONE if there is no change in the middle. See Fig 39. The dummy 1, which is always at the end of all tag responses, is not added to the received data stream. PPE encoding The received data packets always start with 11 preamble bits followed by data bits. The preamble consists of 8 start bits (ZEROES), followed by a SYNCH. The SYNCH consists of a LOW for two bit periods followed by a ONE. See Fig 30. A ONE is represented by a HIGH in the first quarter of the bit period, while a ZERO is represented by a HIGH in the third quarter of the bit period. Miller 2 The received data packets start with preamble. The preamble is a special sequence according to Fig 42 or Fig 43. Miller 2 short preamble FM0 - ISO The received data packets start with preamble. The preamble is a special sequence according to Fig 38. FM0 - ISO preamble Fig 42 Miller 2 long preamble Tag bit periods 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 Fig 38 Fig 43 The data are encoded by FM0 encoding. Each bit has a change at the beginning of bit period. The bit is recognized as ZERO if there is a change in the middle of bit period. The bit is recognized as ONE if there is no change in the middle. See Fig 39. The data are encoded by Miller subcarrier encoding. See Fig 44. The dummy 1, which is always at the end of all tag responses, is not added to the received data stream. Miller 2 data encoding FM0 data encoding MSB first encoding of Byte 10110001 = 'B1' 1 0 1 1 0 0 0 1 Alternative depending on prior conditions t Trlb Fig 39 FM0 – EPC The received data packets start with preamble. The preamble is a special sequence according to Fig 40 or Fig 41. Fig 44 EPC1 preamble Miller 4 The received data packets start with preamble. The preamble is a special sequence according to Fig 45 or Fig 46. Fig 40 Miller 4 short preamble EPC2 preamble Fig 45 Miller 4 long preamble Fig 41 Fig 46 The data are encoded by FM0 encoding. Each bit has a change at the beginning of bit period. The bit is Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 16 www.emmicroelectronic.com EM4298 The data are encoded by Miller subcarrier encoding. See Fig 47. The dummy 1, which is always at the end of all tag responses, is not added to the received data stream. Miller 4 data encoding Fig 50 Cyclic-redundancy check The EM4298 supports 4 types of cyclic-redundancy check. The selected CRC is defined according to the following table. CRC select table Code Description 00 CRC5 – CCITT 01 CRC5 – iPICO 10 CRC16 – CCITT 11 CRC16 – iPICO Fig 51 Fig 47 Miller 8 The received data packets start with preamble. The preamble is a special sequence according to Fig 48 or Fig 49. Miller 8 short preamble CRC5 - CCITT The polynomial used to calculate the CRC-5 is: 5 3 x + x + 1. The 5-bit register must be preloaded with 09 h (MSB to LSB). After the last bit of the bit stream is clocked through, the 5-bit CRC register should contain all zero‟s. CRC5 - iPICO The polynomial used to calculate the CRC-5 is : 5 3 x + x + 1. Fig 48 The 5-bit register must be preloaded with 12 h (MSB to LSB). After the last bit of the bit stream is clocked through, the 5-bit CRC register should contain all zero‟s. Fig 49 CRC16 - CCITT The polynomial used to calculate the CRC-5 is: 16 12 5 x + x + x + 1. Miller 8 long preamble The data are encoded by Miller subcarrier encoding. See Fig 50. The dummy 1, which is always at the end of all tag responses, is not added to the received data stream. The 16-bit register must be preloaded with FFFFh (MSB to LSB). After the last bit of the bit stream is clocked through, the 16-bit CRC register should contain 1D0Fh. Miller 8 data encoding CRC16 - iPICO The polynomial used to calculate the CRC-5 is: 16 15 2 x + x + x + 1. The 16-bit register must be preloaded with FFFFh (MSB to LSB). After the last bit of the bit stream is clocked through, the 16-bit CRC register should contain all zero‟s. Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 17 www.emmicroelectronic.com EM4298 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name vss csn rdn wen clk a[0] a[1] a[2] a[3] d[0] d[1] d[2] d[3] vdd vss d[4] d[5] d[6] d[7] int test_enn I/O Power In In In In In In In In InOut InOut InOut InOut Power Power InOut InOut InOut InOut Out In q i tx tx_active rfon vdd In In Out Out Out Power PU/PD pu pu pu pu pu pu pu pu pu pu pu pu pu pu pu pu Description Ground Chip select Read enable Write enable Clock Address bus, bit 0 [LSB] Address bus, bit 1 Address bus, bit 2 Address bus, bit 3 [MSB] Data bus – tristate, bit 0 [LSB] Data bus – tristate, bit 1 Data bus – tristate, bit 2 Data bus – tristate, bit 3 Power supply Ground Data bus – tristate, bit 4 Data bus – tristate, bit 5 Data bus – tristate, bit 6 Data bus – tristate, bit 7 [MSB] Interrupt request Test enable. Note 1 NC Digital Q channel Digital I channel Tx data, RF modulate when this signal is high The chip transmits data flag Enable of RF part Power supply Active level low low low - - - high low high high high - Note 1 : It is strongly recommended to connect it to VDD Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 18 www.emmicroelectronic.com EM4298 Package Information TSSOP 28 PACKAGE D E A1 A2 C A L b H SYMBOL A A1 A2 b C D E e H L e 14 15 2 1 28 MIN 0.05 0.85 0.19 0.09 9.60 6.00 0.50 0° TYP 0.90 9.70 6.10 0.65 8.10 0.60 MAX 1.10 0.15 0.95 0.30 0.20 9.80 6.20 0.75 8° Dimensions are in mm EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site. EM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of EM are granted in connection with the sale of EM products, expressly or by implications. EM's products are not authorized for use as components in life support devices or systems. Copyright 2007, EM Microelectronic-Marin SA 11/07 – rev.A 19 www.emmicroelectronic.com