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EM MICROELECTRONIC - MARIN SA
EM6680
Ultra Low Power 8-pin Microcontroller
Features
True Low Power:
Figure 1. Architecture
4.0 µA active mode
3.0 µA standby mode
0.65 µA sleep mode
ROM
1536 x 16Bit
@ 1.5V, 32kHz, 25°C
Low Supply Voltage 1.2 V to 3.6 V
No external component needed
Available in TSSOP-8/14, SO-8/14 packages and die
4-bit ADC or 12 levels Supply Voltage Level
Detector (SVLD)
Max 4 (5*) outputs with 2 high drive outputs of 10mA
Max. 5 (6*) inputs
Sleep Counter Reset (automatic wake-up from sleep
mode (EM patent))
Mask ROM 1536 × 16 bits
RAM 80 × 4 bits
Internal RC oscillator 32 kHz – 800 kHz
2 clocks per instruction cycle
72 basic instructions
External CPU clock source possible
Watchdog timer (2 sec)
Power-On-Reset with Power-Check on Start-Up
3 wire serial port , 8 bit, master and slave mode
Universal 10-bit counter, PWM, event counter
Prescaler down to 1 Hz (freq. = 32 kHz)
Frequency output 1Hz, 2048 Hz, CpuClk, PWM
6 internal interrupt sources ( 2×10-bit counter, 2×
prescaler, SVLD, Serial Interface)
2 external interrupt sources (port A)
Copyright © 2005, EM Microelectronic-Marin SA
Power Supply
Stable
RC oscillator
32 - 128kHz
Power on
Reset
Prescaler
Sleep Counter
Reset
Core
EM6600
10-Bit Univ
Count/Timer
Watchdog
4-bit ADC
SVLD check
Interrupt
Controller
Port A
Serial Interface
PA0
PA1
Reset
PA2
PA3
PA4
PA1 & PA2:
high current
drive outputs
*PA5
* PA5 available only
in 14-pin package
and in die
Figure 2. Pin Configuration
TSSOP-8, SO-8
Description
The EM6680 is an ultra-low voltage, low power
microcontroller coming in a package as small as 8-pin
TSSOP and working up to 0.4 MIPS. It comes with an
integrated 4-bit ADC and 2 high current drive outputs of
10mA and it requires no external component. It has a
sleep counter reset allowing automatic wake-up from sleep
mode. It is designed for use in battery-operated and fieldpowered applications requiring an extended lifetime. A
high integration level make it an ideal choice for cost
sensitive applications.
The EM6680 contains the equivalent of 3kB mask ROM
and a RC oscillator with frequencies between 32 and
800kHz selectable by metal option. It also has a poweron reset, watchdog timer, 10 bit up/down counter, PWM
and several clock functions.
Tools include windows-based simulator and emulator. A
ROMless version is also available for validation in
development stage (EMDK6680A).
VDD
VDD
RAM
80 x 4Bit
TSSOP-14, SO-14
PA0
1
8
VDD
PA1
2
7
VREG
PA2
3
6
PA4 (Reset,ADC)
PA3
4
5
VSS
EM6680
NC
1
14
NC
PA0
2
13
VDD
PA1
3
12
VREG
PA2
4
11
PA5
PA3
5
10
NC
6
9
PA4 (Reset,ADC)
VSS
NC
7
8
NC
EM6680
Typical Applications
1
Household appliances
Safety and security devices
Automotive controls
Sensor interfaces
Watchdog
Intelligent ADC
Driver (LED, triac)
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EM6680
EM6680 at a glance
Power Supply
- Low voltage low power architecture
including internal voltage regulator
- 1.2 V to 3.6 V supply voltage
- 4.0 µA in active mode
- 3.5 µA in standby mode
- 0.35 µA in sleep mode
@ 1.5V, 32kHz, 25°C
RAM
- 80 x 4 bit, directly addressable
ROM
- 1536 x 16 bit (~3k Byte), metal mask programmable
CPU
- 4-bit RISC architecture
- 2 clock cycles per instruction (CPI=2)
- 72 basic instructions
Main Operating Modes and Resets
- Active mode (CPU is running)
- Standby mode (CPU in halt, peripherals running)
- Sleep mode (no clock, data kept)
- Initial Power-On-Reset with Power-Check
- Watchdog reset (logic)
- Reset terminal (software option on PA[3/4])
- Sleep Counter reset from Sleep mode
- Wakeup on change from Sleep mode
Prescaler
- Divider (4 stages) to best fit CPU clock (32kHz – 1MHz
to 32kHz system clock to keep peripherals timing close
to specification
- 15 stage system clock divider from 32kHz down to 1Hz
- 2 Interrupt requests (3 different frequencies)
- Prescaler reset (4kHz to 1Hz)
8-Bit Serial Interface
- 3 wire (Clock, DataIn , DataOut) master/slave mode
- READY output during data transfer
- Maximum shift clock is equal to the main system clock
- Interrupt request to the CPU after 8 bit data transfer
- Supports different serial formats
- pins shared with general 4 bit PA[3:0] I/O port
Oscillator
- RC Oscillator range: 32/50kHz to 500/800kHz
(metal selectable from 32/50, 64/100, 128/200, 256/400
or 500/800 kHz typ. for CPU clock)
- No external components are necessary
- Temperature compensated
- External clock source possible from PA[1]
4(5)-Bit I/O PA[3:0] & PA[4] / PA[5]*
- Direct input read on the port terminals
- 2 Debounce function available muxed on 4 inputs
- 2 Interrupt request on positive or negative edge
- Pull-up or pull-down or none selectable by register,
except PA[4] where pullup/down is mask selection
- 2 Test variables (software) for conditional jumps
- PA[1] and PA[3/4] are inputs for the event counter
- PA[3/4] Reset input (register selectable)
- All outputs can be put tri-state (default)
- Selectable pull-downs in input mode
- CMOS or Nch. open drain outputs
- Weak pull-up selectable in Nch. open drain
mode
4-bit ADC & Voltage Level Det. (SVLD)
- External voltage compare from PA[4] input possible (low
resolution 4 bit AD converter)
-12 different levels from 1.2 V to 3.0 V for SVLD
- Used for Power Check after POR (1.25V or 1.85V)
- Busy flag during measure
- Interrupt generated if SVLD measurement low
10-Bit Universal Counter
- 10, 8, 6 or 4 bit up/down counting
- Parallel load
- Event counting (PA[1] or PA[3/4])
- 8 different input clocks
- Full 10 bit or limited (8, 6, 4 bit) compare function
- 2 interrupt requests (on compare and on 0)
- Hi-frequency input on PA[1] and PA[3/4] or CPUclk/2
- Pulse width modulation (PWM) output
Interrupt Controller
- 2 external and 6 internal interrupt request sources
- Each interrupt request can individually be masked
- Each interrupt flag can individually be reset
- Automatic reset of each interrupt request after read
- General interrupt request to CPU can be disabled
- Automatic enabling of general interrupt request flag
when going into HALT mode
Sleep Counter Reset (SCR)
- wake up the EM6680 from sleep mode
- 4 timings selectable by register
- Inhibit SCR by register
Package form available
- TSSOP-8/14
- SO-8/14
- Die form (9 pin possible due to additional I/O pin)
NB: All frequencies written in this document are related to a typical system clock of 32 kHz !
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EM6680
Table of Contents
8.4
FEATURES______________________________ 1
DESCRIPTION ___________________________ 1
2H
2.
2.1
2.2
2.3
3.
OPERATING MODES ________________
ACTIVE MODE_______________________
STANDBY (HALT) MODE _______________
SLEEP MODE _______________________
POWER SUPPLY____________________
4.
4.1
4.2
4.3
4.4
4.5
4.6
5.
5.1
5.2
5.3
6.
6.1
6.2
RESET ____________________________ 7
POR WITH POWER-CHECK RESET _________ 8
INPUT PORT A RESET __________________ 9
DIGITAL WATCHDOG TIMER RESET ________ 9
SLEEP COUNTER RESET _______________ 10
WAKE-UP ON CHANGE ________________ 10
THE CPU STATE AFTER RESET __________ 10
OSCILLATOR AND PRESCALER _____ 11
RC OSCILLATOR OR EXTERNAL CLOCK_____ 11
SPECIAL 4 STAGE FREQUENCY DIVIDER ____ 12
PRESCALER ________________________ 12
INPUT AND OUTPUT PORT A ________ 14
INPUT / OUTPUT PORT OVERVIEW ________ 14
PORTA AS INPUT AND ITS MULTIPLEXING ___ 15
6.3
6.4
7.
7.1
7.2
52H
10.
ADC/SVLD COMPARATOR
CHARACTERISTICS ______________________ 36
6H
7H
53H
8H
11.
RAM _____________________________ 36
12.
12.1
13.
INTERRUPT CONTROLLER __________ 37
INTERRUPT CONTROL REGISTERS _________ 38
PERIPHERAL MEMORY MAP _________ 39
14.
ACTIVE SUPPLY CURRENT TEST _____ 41
15.
15.1
MASK OPTIONS ____________________ 42
INPUT / OUTPUT PORTS ________________ 42
12H
13H
14H
15H
16H
18H
19H
20H
21H
16.
16.1
2H
23H
Debouncer __________________________15
IRQ on Port A _______________________16
Pull-up/down ________________________16
Software test variables ________________17
Port A for 10-Bit Counter _______________17
Port A Wake-Up on change_____________17
Port A for Serial Interface ______________17
Port A for External Reset_______________17
Port PA[4] as Comparator Input _________17
Reset and Sleep on Port A _____________17
Port A Blocked Inputs _________________17
24H
25H
26H
56H
57H
58H
59H
60H
Port A Metal Options __________________ 42
RC oscillator Frequency Option _________ 43
Debouncer Frequency Option ___________ 43
Power-Check Level Option _____________ 43
ADC/SVLD Voltage Level #15___________ 43
Counter Update option ________________ 44
Voltage Regulator level ________________ 44
61H
62H
63H
64H
65H
6H
67H
TEMP. AND VOLTAGE BEHAVIORS ___ 45
IDD CURRENT (TYPICAL) AND VREG FOR 2
THRESHOLDS AND 1/3 OF POSSIBLE CURRENT
FOR VREG.___________________________ 45
PULL-DOWN RESISTANCE (TYPICAL) _______ 45
PULL-UP RESISTANCE (TYPICAL)__________ 45
OUTPUT CURRENTS (TYPICAL) ___________ 46
ELECTRICAL SPECIFICATION ________ 48
ABSOLUTE MAXIMUM RATINGS ___________ 48
HANDLING PROCEDURES _______________ 48
STANDARD OPERATING CONDITIONS _______ 48
DC CHARACTERISTICS - POWER SUPPLY ___ 49
SUPPLY VOLTAGE LEVEL DETECTOR _______ 51
DC CHARACTERISTICS - I/O PINS _________ 53
RC OSCILLATOR FREQUENCY ____________ 54
SLEEP COUNTER RESET - SCR __________ 55
PACKAGE DIMENSIONS _____________ 56
SO-8/14 ___________________________ 56
TSSOP-8/14 _______________________ 57
ORDERING INFORMATION ___________ 58
PACKAGE MARKING ___________________ 58
CUSTOMER MARKING __________________ 58
68H
69H
16.2
16.3
16.4
17.
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
18.
18.1
18.2
19.
19.1
19.2
27H
28H
29H
30H
31H
32H
3H
34H
PORTA AS OUTPUT AND ITS MULTIPLEXING _ 18
35H
CMOS / Nch. Open Drain Output ________18
36H
19
21
22
22
37H
38H
39H
40H
Output Modes _______________________23
41H
SERIAL INTERFACE REGISTERS __________ 25
10-BIT COUNTER __________________ 26
FULL AND LIMITED BIT COUNTING ________ 26
FREQUENCY SELECT AND UP/DOWN COUNTING27
EVENT COUNTING ____________________ 28
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5H
15.1.1
15.1.2
15.1.3
15.1.4
15.1.5
15.1.6
15.1.7
17H
PORT A REGISTERS___________________
SERIAL PORT _____________________
GENERAL FUNCTIONAL DESCRIPTION ______
DETAILED FUNCTIONAL DESCRIPTION______
54H
9H
1H
7.2.1
7.3
8.
8.1
8.2
8.3
5
5
5
5
6
5H
10H
6.3.1
49H
51H
4H
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
48H
50H
3H
PIN DESCRIPTION FOR EM6680 _______ 4
47H
How the PWM Generator works._________ 29
PWM Characteristics__________________ 30
8.5
COUNTER SETUP _____________________ 30
8.6
10-BIT COUNTER REGISTERS ____________ 31
9.
SUPPLY VOLTAGE LEVEL DETECTOR /
4-BIT ADC ______________________________ 33
EM6680 AT A GLANCE ____________________ 2
1.
PULSE WIDTH MODULATION (PWM) _______ 28
8.4.1
8.4.2
1H
42H
43H
4H
45H
70H
71H
72H
73H
74H
75H
76H
7H
78H
79H
80H
81H
82H
83H
84H
85H
86H
87H
46H
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EM6680
1. Pin Description for EM6680
Table 1 EM6680 pin descriptions
# On
Chip
1
2
3
4
5
6
7*
8
9
SO-8
1
2
3
4
5
6
NC
7
8
Signal
Name
PA0
PA1
PA2
PA3
Vss
PA4
PA5
Vreg
Vdd
Description
general I/O, serial In, Wake-Up on Change, IRQ source,…
general I/O, serial CLK, timer source, external clock
general I/O, serial Out, freq., CPU reset status output,…
general I/O, serial Rdy/Cs, Interrupt source, Reset
ground – negative supply pin
general I, Reset, timer source, Interrupt source, Wake-Up, Compare I
general I/O, freq, Wake-Up on Change, IRQ source
regulated voltage supported by 100nF tw. Vss
positive supply pin – capacitance tw. Vdd (C depends on Vdd noise)
Figure 3. Typical configuration for Vdd > 1.5V
Vdd
Vdd
Vreg
Voltage
regulator
Vbat
SVLD
4-bit ADC
C
I/O pad
Level Shifter
uPUS 4bits core
Digital peripherals
RAM 64 x 4 bits
ROM 1536 x 16 bits
Analog peripherals
RC oscillator
Power-on-Reset
Sleep Reset Cnt
Vreg
Capacitor
100nF
C
Vss
For Vdd > 1.5V
Typ_config_vdd+15.vsd
Figure 4. Typical configuration for Vdd < 1.5V
Vdd
Vdd
Regulated Voltage
Vreg
Voltage
regulator
Vbat
SVLD
4-bit ADC
C
I/O pad
Level Shifter
uPUS 4bits core
Digital peripherals
RAM 64 x 4 bits
ROM 1536 x 16 bits
Analog peripherals
RC oscillator
Power-on-Reset
Sleep Reset Cnt
Vreg
Capacitor
100nF
C
Vss
For Vdd > 1.5V
Typ_config_vdd+15.vsd
NOTE: State of I/O pads may not be defined until Vreg reaches typ. 0.8V and Power-On-Reset logic
supplied by Vreg clears them to Inputs.
On I/O pins there are protective diodes towards Vdd and Vss.
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EM6680
2. Operating modes
The EM6680 can operate in three different modes of which 2 are low-power dissipation modes (Stand-By and
Sleep). The modes and transitions between them are shown in Figure 5.
1.) Active mode
2.) Stand-By mode
3.) Sleep mode
Figure 5. EM6680 operating mode transitions
POWER-ON
START-UP
Power-On-Reset & Power Check Level
POR static level
Power-Check Active
RC oscilator
running
PORwPC
8 oscillator
periods
PORwPC
RESET
reset synchronizer
and
Power-Check
PORwPC
resetPortA
WDreset
PORwPC
8 CPU clock
periods
Reset-pad
WDreset
ACTIVE
or running
mode
HALT instruction
interrupt/event
STAND-BY
or HALT
mode
Clocks active
SleepResCnt
WakeUp on
Change
SLEEP
Everything stopped
Registers and
RAM keep their value
Sleep bit set
2.1 ACTIVE Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Leaving the active mode: via the halt instruction to go into standby mode, writing the SLEEP bit to go
into Sleep mode or detecting the reset to go into reset mode.
2.2 STANDBY (Halt) Mode
Executing a HALT instruction puts the EM6680 into standby mode. The voltage regulator, oscillator, watchdog
timer, interrupts, timers and counters are operating. However, the CPU stops since the clock related to
instruction execution stops. Registers, RAM and I/O pins retain their states prior to STANDBY mode.
STANDBY is cancelled by a RESET or an Interrupt request if enabled.
2.3 SLEEP Mode
Writing to the Sleep bit in the RegSysCntl1 register puts the EM6680 in sleep mode. The oscillator stops and
most functions of the EM6680 are inactive. To be able to write to the Sleep bit, the SleepEn bit in
RegSysCntl2 must first be set to "1". In SLEEP mode only the voltage regulator is active to maintain the RAM
data integrity, the peripheral functions are stopped and the CPU is reset. SLEEP mode may be cancelled by
Wake/Up on change, external reset or by Sleep Reset Counter if any of them is enabled.
Waking up from sleep mode may takes some time to guarantee stable oscillation. Coming back from sleep
mode puts the EM6681 in reset state and as such reinitializes all registers to their reset value. Waking up from
sleep mode clears the Sleep flag but not the SleepEn bit. Inspecting the SleepEn allows to determine if the
EM6680 was powered up (SleepEn = "0") or woken from sleep mode (SleepEn = "1").
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EM6680
Table 2.3.1 Shows the Status of different EM6680 blocks in these three main operating modes.
Peripheral /// EM6680 mode
POR (static)
Voltage regulator
RC-oscillator
Clocks (Prescaler & RC divider)
CPU
Peripheral register
RAM
Timer/Counter
Supply Voltage Level Det.=SVLD
PortA / Reset pad debounced
Interrupts / events
Watch-Dog timer
Wake Up on Change PortA
Sleep Reset Counter
ACTIVE mode
On
On
On
On
Running
“On”
“On”
“On”
can be activated
Yes
Yes - possible
On / Off (soft
selectable)
No
Off
STAND-BY mode
On
On
On
On
In HALT – Stopped
“On” retain value
retain value
“On” if activated before
“On” if activated before
Yes
Yes - possible
On / Off (soft
selectable)
No
Off
SLEEP mode
On
On (Low-Power)
Off
Off
Stopped
retain value
retain value
stopped
Off
No
No – not possible
No
On/Off (soft select.)
On/Off (soft select.)
3. Power Supply
The EM6680 is supplied by a single external power supply between Vdd (VBAT) and VSS (ground). A built-in
voltage regulator generates Vreg providing regulated voltage for the oscillator and the internal logic. The output
drivers are supplied directly from the external supply VDD. Internal power configuration is shown in Figure 3 and
Figure 4.
To supply the internal core logic it is possible to use either the internal voltage regulator (Vreg < VDD) or directly
( Vreg = VDD). The selection is done by metal 1 mask option. By default the voltage regulator is used. Refer to
chapter 0 for the metal mask selection.
8H
The internal voltage regulator is chosen for high voltage systems. It saves power by reducing the internal core
logic’s power supply to an optimum value. However, due to the inherent voltage drop over the regulator the
minimal VDD value is restricted to 1.4V .
A direct VDD connection can be selected for systems running on a 1.5V battery. The 1kΩ resistor together with
the external capacitor on Vreg is filtering the Vdd supply to the internal core. In this case the minimum VDD value
can be as low as 1.2 V.
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EM6680
4. Reset
Figure 6. illustrates the reset structure of the EM6680. One can see that there are five possible reset sources :
(1) Internal initial Power On Reset (POR) circuitry with Power-Check.Æ POR, ResetCold, System Reset, Reset CPU
(2) External reset from PA[3/4] if software enabled
Æ System Reset, Reset CPU
(3) Internal reset from the Digital Watchdog.
Æ System Reset, Reset CPU
(4) Internal reset from the Sleep Counter Reset.
Æ System Reset, Reset CPU
(5) Wake-Up on change from PA[0/5] or PA[3/4] if software enabled. Æ System Reset, Reset CPU
Table 4.1 Reset sources that can be used in different Operating modes
Reset Sources
POR (static) with Power Check
Software enabled reset on PA[3/4]
Digital Watch-Dog Timer
Sleep Counter Reset
Wake Up on Change from Sleep
Going in Sleep mode
XS = software enable
ACTIVE mode
STAND-BY mode
Yes
XS dig. debounce
XS
No
No
Yes
SLEEP mode
Yes
XS dig. debounce
XS
No
No
No
Yes
XS analog debounce
No
XS
XS
No
Figure 6. EM6680 Reset Structure
RESETs generation logic diagram
SCRsel0
SCRsel1
Ck[1]
WDVal
Write- Reset
WDVa
NoWDtim
Watchdog
times
Read Statuts
Write- Active
SleepEn
Sleep Counter
Reset Oscillator
typ . 100Hz
Prescaler
Sleep
Internal Data Bus
Read Statuts
Sleep
resetCold
Analogue
Filter
Wake up (on change)
System Reset
Delay
ResSys
Peripherals
&
CPU
ck[15]
Debounce
POR &
Power-check
POR
InResAH
ck[9]
Set
PORstatus
Reset
Rd RegSysCntl1
PA[3]
PA[4]
PA[3/4]Resin
All signals enter bottom, left, top and output on the right side of the boxes
All reset sources activate the System Reset (ResSys). The ‘System Reset Delay’ ensures that the system reset
remains active long enough for all system functions to be reset (active for 12 system clock cycles. CPU is reset
by the same reset
As well as activating the system reset, the POR also resets all bits in registers marked ‘p’ and the sleep enable
(SleepEn) latch. System reset does not reset these register bits, nor the sleep enable latch.
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EM6680
4.1 POR with Power-Check Reset
POR and Power-Check are supervising the Vreg(digital) which follows more or less the Vdd supply voltage on
start-up to guarantee proper operation after Power-On. The power check initiates a resetcold signal, which
gets released when the Vdd supply voltage is high enough for the IC to function correctly.
Figure 7. EM6680 resetcold signal as a result of Power-On-Reset and Power-Check
Vbat
SVLD
Vreg
Voltage
Regulator
resetcold
Bandgap Reference
EN
Vreg (digital)
To SYSTEM
POR
Static POR
PORstatic
6
2
Vbat, Vreg
3
Vbat
Vreg
~1.25V
SVLD lev5
SVLD lev4
~1.2V
~1.0V
POR level
~0.9V
1
4
5
7
time
POR
resetcold
At power-on a POR cell with a static level of typ. 1.0V is checked.
At time (1) in Figure 7. when the supply is increasing a power-check logic is switched-on with POR signal high.
This logic enables the SVLD-level5 check which keeps resetcold active high until Vdd > SVLD-level5 (2). The
circuit enters the active operating mode after (2), region (3). If afterwards Vdd drops below the selected SVLDlevel4 (4) low supply will be detected, but this does not generate a POR signal. Low supply will be detected only
if the measurement is done at time (4).
If Vreg drops below the static POR level of 0.90V when Vdd Supply is going down (POR static level has a
hysteresys) then the POR and resetcold signals go high immediately (5) , SVLD level5 gets forced and power
check is switched on. Because POR was done, the Vld_lev[3:0] was reset to value 0101, and Power-check
makes resetcold inactive low again at time (6) where Vbat is above SVLD level 5.
If there is only a very short Vdd drop (of few μs), below the POR level, POR will not react because Vreg is
supported by external capacitance and it drops slower than Vdd and the logic still works (7).
IMPORTANT: special care should be taken, when Power Supply starts to fall close to or below Vdd min.
Frequent checking of the SVLD level must be done. Below the minimum Vdd level specified, the circuit operation
is not guaranteed.
To distinguish between POR reset and all other types of reset, the PORstatus bit in RegSysCntl2 is set on at
every POR and is cleared by writing the RegSysCntl1 register.
With metal option SVLD level9 @ 1.85V can be selected at higher RC oscillator frequencies to guarantee
proper operation at higher frequencies.
Note:
Low supply detection may be used to go in protected sleep mode. During sleep mode the circuit operation is
stopped. Resuming from Sleep mode (Reset or Wake-up) will automatically perform a Power-Check . As such
the systems will only resume to active mode if the Power-Check condition is full-filled.
The SVLD level which was selected at the time one entered sleep mode will be used as Power-Check level
(exception: if during Sleep one has a POR condition then the default SVLD level will be applied.)
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EM6680
4.2 Input Port A Reset
By writing the PA[3/4]ResIn in RegFreqRst registers the PA[3] or PA[4] input becomes dedicated for external
reset. This bit is cleared by POR only. Which input is selected is set by IrqPA[3l/4h] bit from RegPACntl2
register which is described in Chapter 6.
Bit InResAH in the RegFreqRst register selects the PA[3/4] reset function in Active and standby (Halt) mode. If
set to ‘0’ the PA[3/4] reset is inhibited. If Set to ‘1’ than PA[3/4] input goes through a debouncer and needs to
respect timing associated with the debounce clock selection made by DebSel bit in RegPresc register.
This InResetAH bit has no action in sleep mode, where a Hi pulse on PA[3/4] always immediately triggers a
system reset (only small analogue debouncer is attached to filter 1 or 2 μs spikes).
89H
Overview of control bits and possible reset from PA[3] or PA[4] is specified in table 4.2.1 below.
Table 4.2.1 Possible Reset from PA[3] or PA[4]
PA[3/4]ResIn InResAH
ACTIVE or STAND-BY mode
NO reset from PA[3] or PA[4]
0
X
NO reset from PA[3] or PA[4]
1
0
Debounce reset with debck of
1
1
* Ck[14]/ Ck[11]/ Ck[8] needing
0.25 ms / 2 ms / 16ms Hi pulse typ.
* Ck[14]/ Ck[11]/ Ck[8] are explained in chapter 5.2 Prescaler.
SLEEP mode
NO reset from PA[3] or PA[4]
Reset with small analog filter
Reset with small analog filter
90H
4.3 Digital Watchdog Timer Reset
The Digital Watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It
will generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by
activating an inhibit digital watchdog bit (NoWDtim) located in RegVLDCntl. At power up, and after any
system reset, the watchdog timer is activated.
If for any reason the CPU stops or stays in a loop where watchdog timer is not periodically cleared, it
activates the system reset signal. This function can be used to detect program overrun, endless loops, etc.
For normal operation, the watchdog timer must be reset periodically by software at least every 2.5 seconds
(system clock = 32 KHz), or a system reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and
timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog
timer also operates in standby mode and thus, to avoid a system reset, standby should not be active for
more than 2.5 seconds.
From a System Reset state, the watchdog timer will become active after 3.5 seconds. However, if the
watchdog timer is influenced from other sources (i.e. prescaler reset), then it could become active after just
2.5 seconds. It is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the
watchdog every second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the
counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’, {WDVal1 WDVal0}). When
reaching the ‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the
system reset which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore
always reads ‘0’.
Table 4.3.1 Watchdog timer register RegSysCntl2
Bit
Name
Reset
R/W
Description
3 WDReset
0
W
Reset the Watchdog (The Read value is always '0')
1 Æ Resets the Logic Watchdog
0 Æ no action
2 SleepEn
0
R/W
See Operating modes (sleep)
1 WDVal1
0
R
Watchdog timer data 1/4 ck[1]
0 WDVal0
0
R
Watchdog timer data 1/2 ck[1]
3 PORstatus
1 P*
R
Power-On-Reset status
1 P* POR sets the PORstatus bit which is cleared by writing register RegSysCntl1
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EM6680
4.4 Sleep Counter Reset
To profit the most from Low Power Sleep Mode and still supervise the circuit surrounding, one can enable the
Sleep Counter Reset which only runs in Sleep mode and periodically wakes up the EM6680. Four (4) different
Wake-Up periods are possible as seen in table below.
Control bits SleepCntDis which is set to default ‘0’by POR enables the Sleep Counter when the circuit goes
into Sleep mode. The SCRsel1, SCRsel0 bits that are used to determine Wake-Up period are in the
RegSleepCR register. To disable the Sleep Counter in Sleep mode SleepCntDis must be set to ‘1’.
Table 4.4.2 Register RegSleepCR
Bit
Name
Reset
3
NoPullPA[4]
0 por
2
SleepCntDis
0 por
1
SCRsel1
0 por
0
SCRsel0
0 por
R/W
R/W
R/W
R/W
R/W
Description
Remove pull-up/down from PA[4] input
Disable Sleep Reset Counter when Hi
Selection bit 1 for Sleep RCWake-Up period
Selection bit 0 for Sleep RCWake-Up period
Table 4.4.3 Wake-Up period from Sleep selection
SCRsel1
SCRsel0
Sleep Reset Counter periods
0
0
1.5 internal low speed RC clock periods
0
1
15.5 internal low speed RC clock periods
1
0
127.5 internal low speed RC clock periods
1
1
1023.5 internal low speed RC clock periods
Refer to table 17.8 or the actual SCR timeout period timings
91H
Sleep Counter Reset (SCR) uses the same prescaler (see chapter 5.3) as the System Clock in Active and
StandBy mode. Prescaler reset is made automatically just before going into Sleep mode if SCR is enable.
This causes the Sleep Reset Counter to have its specified period.
4.5 Wake-Up on Change
By writing the WUchEn[0/5] and/or WUchEn[3/4] bit in RegPaCntl2 registers the PA[0] or PA[5] and/or PA[3]
or PA[4] can generate a reset from sleep on any polaritychange on a selected pin. The port selection is defined
with bits IrqPA[0l/5h] and IrqPA[3l/4h]. See also chapter 6 and Figure 10 for more details.
4.6 The CPU State after Reset
Reset initializes the CPU as shown in Table 4.6.1 below.
92H
Table 4.6.1 Initial CPU value after Reset.
Name
Bits
Program counter 0
12
Program counter 1
12
Program counter 2
12
Stack pointer
2
Index register
7
Carry flag
1
Zero flag
1
Halt
1
Instruction register
16
Periphery registers
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Symbol
PC0
PC1
PC2
SP
IX
CY
Z
HALT
IR
Initial Value
$000 (as a result of Jump 0)
Undefined
Undefined
SP[0] selected
Undefined
Undefined
Undefined
0
Jump 0
Reg.....
See peripheral memory map
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5. Oscillator and Prescaler
5.1 RC Oscillator or external Clock
EM6680 can use the internal RC oscillator or external clock source for its operation.
The built-in RC oscillator without external components generates the system operating clock for the CPU and
peripheral blocks. The RC oscillator is supplied by the regulated voltage.
The RC oscillator frequency can be chosen from 5 possibilities with a metal option with 2 basic frequencies.
These are typically 32kHz, 64kHz, 128kHz, 256kHz or 500kHz for 32kHz basic frequency or 50kHz, 100kHz,
200kHz, 400kHz or 800kHz for 50kHz basic frequency . Depending on the selected RC frequency. A special 4
stage freq. divider is available to be able to deliver to Prescaler which generates all System clock except CPU
clock, a frequency close to 32 or 50 kHz to keep the peripheral timing as close as possible to specifications.
Please note that Vddmin must be higher when working with higher frequencies – contact EM for details.
After POR the circuit always starts with the internal RC oscillator, but it can be switched to the external clock by
setting the ExtCPUclkON bit in the register RegPresc. The external clock is input at PA[1] and must be in
range from min. 10Khz to max. 1MHz. With this external frequency input all timing for peripherals change and
the special 4 stage freq. divider must be adapted to best suit the applied external frequency to keep 32/50kHz
System clock as close as possible. The system clock must be less than 64kHz. The external clock source
must be a square wave with full amplitude from Vss to Vdd. See Table 5.2.2 for advised special divisions
depending on the external clock frequency.
Switching from internal RC oscillator to External clock or back from External clock to RC oscillator is made
without generating a glitch on the internal clock. Once the circuit is running on the external Clock one can
disable the RC oscillator by setting the RCoscOff bit in RegSCntl2 to ‘1’.
In sleep mode the oscillator is stopped. It can be stopped also by setting the RCoscOff bit. This bit can be set
only if ExtCPUClkOn was set before, indicating that the CPUck was switched from the internal RC oscillator to
the external clock which MUST be present. If the External Clock stops without going into Sleep mode first the
EM6680 can block and only POR can reset it.
Figure 8. below shows the connection of the RC oscillator and external clock and generation of CPUclk and
System clock = SysClk which is divided by the special 4 stage Freq. Divider if needed as described in 5.2 and
prescaler described in 5.3.
93H
Figure 8. Clock source for CPU or system peripherals
RC oscillator
32kHz – 512kHz
50kHz - 800kHz
RCClk
metal option selection
0
CPUclk
MUX
PA[1]
External clock
10kHz – 800kHz
1
Frequency
divider
PAout[5]
div16
div8
div4
div2
Automatic clock selection
SysClk = 32kHz or 50kHz
depending on selected
RCClk selection
div1
ExtCPUclkON
MUX
PA[5]
MUX
PA[2]
foutSel[1:0]
MUX
CpuClk
SysClk
Ck[12]
Ck[1]
MUX
Sout
PAout[2]
ResSys
Ck[14]
To Peripherals
Ck[15:1]
SysClk
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PRESCALER
LOW 15 stages divider Ck[15:1]
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EM6680
5.2 Special 4 stage Frequency Divider
If an internal RC clock or external frequency higher than 32 kHz or 50 kHz is selected, then the special 4 stage
Frequency Divider must be used to select a frequency close to 32 kHz or 50 kHz for the SysClk - system clock
used by the Prescaler. This is done by metal option.
If the external clock will be used, the same metal option used to select the division for SysClk. Table below
shows recommended divisions in this 4 stage divider.
Table 5.2.1 PA[1] I/O status depending on its RegPACntl3 and RegPa0OE registers
Ext. clock
RC frequency
(1)base (2) base
RC frequency or External freq.
MUST be divided by
10 kHz – 50 kHz
32
50
No Division to SysClk
55 kHz – 100 kHz
110 kHz – 200 kHz
220 kHz – 400 kHz
400 kHz – 1 MHz
64
128
256
500
100
200
400
800
Divided by 2
Divided by 4
Divided by 8
Divided by 16
Typical Obtained SysClk
Min.- typ. If RC - Max. [kHz]
10 – 32 – 50
27.5
27.5
27.5
10
–
–
–
–
32
32
32
32
–
–
–
–
50
50
50
62.5
5.3 Prescaler
The prescaler consists of a fifteen element divider chain which delivers clock signals for the peripheral circuits
such as timer/counter, debouncer and edge detectors, as well as generating prescaler interrupts. The input to
the prescaler is the system clock signal closest to 32 kHz or 50 kHz which comes from the RC oscillator or
external clock as divided by the preceding divider. Power on initializes the prescaler to Hex(0001).
Table 5.3.1 Prescaler Clock Name Definition
Function
Name
System clock
System clock / 2
System clock / 4
System clock / 8
System clock/ 16
System clock / 32
System clock / 64
System clock / 128
Ck[16]
Ck[15]
Ck[14]
Ck[13]
Ck[12]
Ck[11]
Ck[10]
ck [9]
32 KHz
SysClk
32768 Hz
16384 Hz
8192 Hz
4096 Hz
2048 Hz
1024 Hz
512 Hz
256 Hz
50 KHz
SysClk
50000 Hz
25000 Hz
12500 Hz
6250 Hz
3125 Hz
1562 Hz
781 Hz
390 Hz
Function
Name
System clock / 256
System clock / 512
System clock / 1024
System clock / 2048
System clock / 4096
System clock / 8192
System clock / 16384
System clock / 32768
Ck[8]
Ck[7]
Ck[6]
Ck[5]
Ck[4]
Ck[3]
Ck[2]
Ck[1]
32 KHz
SysClk
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
50 KHz
SysClk
195 Hz
97 Hz
49 Hz
24 Hz
12 Hz
6 Hz
3 Hz
1.5 Hz
Figure 9. Prescaler Frequency Timing
Prescaler Reset
SysClk = System clock Ck[16]
Ck[15]
Ck[14]
Ck[13]
Horizontal Scale change
Ck[2]
Ck[1]
First positive edge of 1 Hz clock Ck[1] is 1 sec after the falling reset edge
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EM6680
Table 5.3.2 Control of Prescaler Register RegPresc
Bit
3
2
Name
ExtCPUclkON
ResPresc
Reset
p
0
R/W
R/W
R/W
1
PrIntSel
0
R/W
0
DebSel
0
R/W
Description
Ext. Clock selection instead of RC oscillator for CPUClk.
Write Reset prescaler
1 Æ Reset the divider chain from Ck[14] to Ck[2], sets Ck[1].
0 Æ No action.
The Read value is always '0'
Prescaler Interrupt select. 0 Æ Interrupt from Ck[4] (typ. 8/12 Hz)
1 Æ Interrupt from Ck[7] (typ. 64/97 Hz)
Debounce clock select. 0 Æ Debouncer with Ck[8]
1 Æ Debouncer with Ck[11] or Ck[14]
p* reset to ‘0’ by POR only.
With DebSel = 1 one may choose either the Ck[11] or Ck[14] debouncer frequency by selecting the
corresponding metal mask option. Relative to 32kHz the corresponding max. debouncer times are then 2 ms or
0.25 ms. For the metal mask selection refer to chapter 15.1.3
94H
Switching the PrIntSel may generate an interrupt request. Avoid it with MaskIRQ64/8 = 0 selection during the
switching operation.
The prescaler contains 2 interrupt sources:
- IRQ64/8 ; this is Ck[7] or Ck[4] positive edge interrupt, the selection is depending on bit PrIntSel.
- IRQHz1 ; this is Ck[1] positive edge interrupt
There is no interrupt generation on reset.
The first IRQHz1 Interrupt occurs typically. 1 sec (if SysClk = 32kHz) after reset. (0.65 sec if SysClk is 50kHz).
NOTE: If not written explicitly all timing in peripherals is calculated for 32 kHz System Clock !
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EM6680
6. Input and Output port A
The EM6680 has:
- one 4-bit input/output port ( port A[3:0] )
- one 1 bit input port. ( port PA[4] )
- one optional 1 bit input/output ( port PA[5] ) available in die form or 14 pin package.
Pull-up and Pull-down resistors can be added to all these ports with metal and/or register options.
6.1 Input / Output Port Overview
Table 6.1.1 Input and Output port overview
Pin n° in 8 pin package
General I/O
Serial interface
PA[0]
1
I/O
Sin I
WakeUp on change
Softw. pullUp/Down
yes* I
yes
PA[1]
2
I/O
Sclk I/O
-yes
--
--
--
--
yes
--
-yes* I
yes I
--
---
yes* I
yes* I
yes* I
yes* I
-yes* I
yes* I
---
--
--
yes* I
---
---
yes I
yes O
--
--yes* O
yes I
yes* I
----
yes* I
---
-yes O
--
yes* I
-yes* I
----
--yes* O
--
--
yes O
--
--
--
Metal option pullUp/Down
Timer input
Irq debounce & active
edge selection.
CPU soft. variable input
Analogue compare Input
External reset input
External CPU clock input
PWM timer out
freq. Output (CpuClk,
SysClk, 2kHz, 1Hz)
CPU reset condition
PA[2]
3
I/O
Sout O
-yes
PA[3]
4
I/O
Rdy/CS O
PA[4]
6
I
--
PA[5]*
NC*
I/O
--
yes* I
yes
yes* I
yes
yes* I
yes
NC* – Pad PA[5] is Not Connected in 8-pin package, available only in die form
Yes* ;
The function is software selectable on one of PA[0],
IrqPA[0l/5h] and IrqPA[3l/4h] settings.
PA[5] or PA[3], PA[4], depending on the
As shown in Figure 10, Logic for the Wake up on change reset which is possible only from Sleep mode,
Debouce and IRQ function on Rising or falling edge are implemented only twice but can be attached and
configured by registers to 4 different pads when used as inputs.
Ports PA[0] and PA[5] can be configured to have wakeup on Change, and debounced or non-debounced IRQ
on the falling or rising edge. The same function is available on ports PA[3] or PA[4] which in addition can be
dedicated to input reset . Registers RegPACntl1 and RegPACntl2 make this selection.
Table 6.1.2 Register RegPACntl1
Bit
3
2
1
0
Name
POR
R/W
Description
DebounceNoPA[3/4]
0
R/W
Debouncer on when Low for PA[3/4] input
DebounceNoPA[0/5]
0
R/W
Debouncer on when Low for PA[0/5] input
EdgeFallingPA[3/4]
0
R/W
IRQ edge selector for interrupt from PA[3/4] input
EdgeFallingPA[0/5]
0
R/W
IRQ edge selector for interrupt from PA[0/5] input
* Default is debouncer On and Rising edge for IRQ
Table 6.1.3 Register RegPACntl2
Bit
3
2
1
0
Name
POR
R/W
Description
WUchEnPA[3/4]
0
R/W
WakeUp on change EN on PA[3] or PA[4]
WUchEnPA[0/5]
0
R/W
WakeUp on change EN on PA[0] or PA[5]
IrqPA[3l/4h]
0
R/W
PA[3] if Low / PA[4] if High for IRQ source
IrqPA[0l/5h]
0
R/W
PA[0] if Low / PA[5] if High for IRQ source
* Default: No wake Up on change and IRQ source, or reset and timer input, would be PA[3], PA[0]
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EM6680
6.2 PortA as Input and its Multiplexing
The EM6680 can have up to 5 (6* in Die form or 14 pin package) 1-bit general purpose CMOS input ports. The
port A input can be read at any time, pull-up or pull-down resistors can be chosen by software and metal
options for PA[3:0] and PA[5] if available.
PA[4] has only metal option pull-up or pull-down resistor.
Figure 10 explains how the inputs are treated with control signals and how they are distributed to different
peripherals and the CPU. This is also listed in Table 6.1.1 Input and Output ports overview.
Figure 10. EM6680 Multiplexed Inputs diagram
PA[4]
extVcheck
TimCk0
PA[1]
Q
Q
Debounce
PA[0]
PA[5]
I1 S
TimCk7
Qdeb
Qdeb
CkDeb
I0
I0
Z
QB
QB
Z
to SVLD Logic
Input to peripherals is blocked if used for SVLD comparator input
extVcheck
debouncerYesPA[0/5]
irqPA[0l/5h]
Sleep
I1 S
PA[1]
Serial Clock Input
PA[0]
Serial Data Input
to Serial Interface
EdgeFallingPA[0/5]
WakeUp on change
In
Out
RdRegPA0
to Timer / Event
Counter
uPVar[1]
to CPU
uPVar[2]
WUchEnPA[0/5]
PA[3:0]
Internal Data Bus DB [3:0]
RdRegPA1
PA[5:4]
Qdeb
CkDeb
Q
Debounce
PA[3]
I0
PA[4]
I1 S
Z
Z
QB
debouncerYesPA[3/4]
IRQPA[0/5]
I0
IRQPA[3/4]
to Interrupt Logic
I1 S
EdgeFallingPA[3/4]
irqPA[3l/4h]
WakeUp on change
In
Out
Sleep
WakeUp on Change
to Reset Logic
WUchEnPA[3/4]
ResDis
InResAH
Small Analogue Filter
In
Out
PA3/4_reset
ResFlt
PA3/4resln
EM6680_fig10.vsd
All signals enter bottom, left, top and output on the right side of the boxes
Some Input functions are explained below.
6.2.1 Debouncer
The debouncer is clocked with one of the possible debounce clocks (Ck[11] / Ck[8] and can be used only in
Active or StandBy mode (as only in these two modes clocks are running). The input signal has to be stable on
two successive debouncer rising clock edges and must not change between them. The debouncer clock Ck[11]
can be replaced with Ck[14] by metal option, refer to 15.1.3 .
95H
Figure 11. Debouncer function
DEBOUNCER function (signal must be stable during two Deb Clk rising edges)
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EM6680
6.2.2 IRQ on Port A
For interrupt request generation (IRQ) one can choose direct or debounced input and rising or falling edge IRQ
triggering. With the debouncer selected debounceYesPA[x/y], the input must be stable for two rising edges of
the selected debouncer clock CkDeb. This means a worst case of 16ms(default) or 2ms (0.25ms by metal
mask) with a system clock of 32kHz.
Either a rising or falling edge on the port A inputs - with or without debouncing - can generate an interrupt
request. This selection is done by edgeFallingPA[x/y].
PortA can generate max 2 different interrupt requests. Each has its own interrupt mask bit in the RegIRQMask1
register. When an IRQ occurs, inspection of the RegIRQ1 and RegIRQ2 registers allow the interrupt to be
identified and treated.
At power on or after any reset the RegIRQMask1 is set to 0, thus disabling any input interrupt. A new interrupt
is only stored with the next active edge after the corresponding interrupt mask is cleared. See also the interrupt
chapter 9.
It is recommended to mask the port A IRQ’s while one changes the selected IRQ edge. Otherwise one may
generate an unwanted IRQ (Software IRQ). I.e. if a bit PA[0/5] is ‘0’ then changing from positive to negative
edge selection on PA[0/5] will immediately trigger an IRQPA[0/5] if the IRQ was not masked.
96H
6.2.3 Pull-up/down
On Each terminal of PA[3:0] and PA[5] an internal pull-up (metal mask MAPU[n]) and pull-down (metal mask
MAPD[n]) resistor can be connected per metal mask option. By default the two resistors are in place. In this
case one can choose by software to have either a pull-up, a pull-down or no resistor. See below for better
understanding.
With the mask option in place, the default pull value is Pull-Down (initialized by POR). Once the software up
and running this may be changed to pull-up if needed.
If the port is used also as output please check Chapter 6.3.1 CMOS / Nch. Open Drain Output.
PA[4] can have only strong Pull-up or Pull-down resistor. This resistor can be disconnected by software in
register RegSleepCR bit NoPullPA[4].
For Metal mask selection and available resistor values refer to chapter 15.
97H
Pull-down ON: MAPD[n] must be in place ,
AND bit NoPdPA[n] must be ‘0’ .
with n=0, 1, 2, 3, 5
Pull-down OFF: MAPD[n] is not in place,
OR if MAPD[n] is in place NoPdPA[n] = ‘1’ cuts off the pull-down.
OR selecting NchOpDrPA[n] = ‘1’ cuts off the pull-down.
Pull-up ON :
MAPU[n] must be in place,
AND bit NchOpDrPA[n] must be ‘1’ ,
AND (bit OEnPA[n] = ‘0’ (input mode) OR if OEnPA[n] = ‘1’ while PAData[n] = 1. )
Pull-up OFF :
MAPU[n] is not in place,
OR if MAPU[n] is in place NchOpDrPA[n] = ‘0’ cuts off the pull-up,
OR if MAPU[n] is in place and if NchOpDrPA[n] = ‘1’ then PAData[n] = 0 cuts off the pull-up.
Never pull-up and pull-down can be active at the same time.
Any port A input must never be left open (high impedance state, not connected, etc. ) unless the internal pull
resistor is in place (mask option) and switched on (register selection). Any open input may draw a significant
cross current which adds to the total chip consumption.
Note: The mask settings MAPU[n]) and MAPD[n] do not define the default pull direction, but the pull
possibilities. It is the software which defines the pull direction (pull-up or pull-down). The only exception is on
PA[4] where the user must decide if he wants pull-up or pull-down. For this input the selected pull direction will
always be valid unless the software disconnects the pull resistor.
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EM6680
6.2.4 Software test variables
As shown in Figure 10 PA[0/5] or PA[3/4] are also used as input conditions for conditional software branches.
These CPU inputs are always debounced and non-inverted.
• debounced PA[0/5] is connected to CPU TestVar1
• debounced PA[3/4] is connected to CPU TestVar2
CPU TestVar3 is connected to VSS and can not be used in Software.
6.2.5 Port A for 10-Bit Counter
The PA[1] and PA[3/4] inputs can be used as the clock input terminal for the 10 bit counter.
• PA[1] is at counter clock selection 0. The input is direct ( no debouncer is possible
• PA[3/4] is at counter clock selection 7. As for the IRQ generation, debounced or input directly and
non-inverted or inverted input is possible. This is defined with the register RegPaCntl1. Debouncing the
input is always recommended.
6.2.6 Port A Wake-Up on change
In sleep mode if configured port PA[0/5] or PA[3/4] inputs are continuously monitored to wake up on change,
which will immediately wake up the EM6680.
6.2.7 Port A for Serial Interface
When the serial interface is used in slave mode, PA[0] is used for serial data input and PA[1] for the serial
clock.
6.2.8 Port A for External Reset
In Active and Stand-by (Halt) mode a positive debounced pulse on PA[3/4] can be the source of a reset when
PA[3/4]ResIn and InResAH are set at ‘1’. When IrqPA[3l/4h] is ‘0’ than PA[3] is selected for Reset source
and when IrqPA[3l/4h] is ‘1’ than PA[4] is selected for Reset source.
6.2.9 Port PA[4] as Comparator Input
When using the PA[4] as an input to the internal SVLD comparator NO pull resistor should be connected on this
terminal. Otherwise the device may draw excessive current.
First PA[4] pull-up/down resistor should be disconnected by software and the ExtVcheck bit can be set to ‘1’.
This dedicates PA[4] as SVLD resistor divider input to the SVLD comparator.
At this point the measurements respect the same timing as any other SVLD measurements as explained in
Chapter Supply Voltage Detector. It can also generate an IRQ if the input voltage is lower as Comparator level.
Thus configured a direct read of PA[4] will result in reading ‘0’.
6.2.10 Reset and Sleep on Port A
During circuit initialisation, all Control registers are reset by Power On Reset and therefore all pull-ups are off
and all pull-downs are on. During Sleep mode, the circuit is in Reset State. However the Reset State does not
reset the Control registers, RAM and pull-downs, if previously turned on. After any reset the serial interface
parameters are reset to : Slave mode, Start and Status = 0, LSB first, negative edge shift , PA[3:0] tri-state.
6.2.11 Port A Blocked Inputs
In sleep mode if PortA inputs are not used and prepared for Wake-Up on Change or Reset these inputs are
blocked. At that time port can be undefined from external and this will not generate an over-consumption.
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
: Blocked if Sleep bit set and no IRQ or Wake-up defined on this input
: Blocked if Sleep bit set
: Blocked if Sleep bit set
: Blocked if Sleep bit set and no IRQ or Wake-up defined on this input
: Blocked if Sleep bit set and no IRQ or Wake-up defined on this input
Also blocked if External VLD check enabled
: Never blocked
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6.3 PortA as Output and its Multiplexing
The EM6680 can have up to 4 (5 in Die form or 14-pin package) bit general purpose CMOS or N-channel Open
Drain Output ports. Table 6.1.1 Input and Output ports overview shows all the possibilities. Figure 12 shows
the output architecture and possible output signals together with software controlled pull-up and pull-down
resistors which are disconnected when the port is an output and in a defined state, to preclude additional
consumption.
The output multiplexing registers are RegPACntl3 and RegPACntl4.
Figure 12. Port A Architecture (Outputs)
Open Drain Control
Register (NchOpPA[n])
Pull-down Register
(NoPdPA[n])
OD[n]
Pd[n]
Vdd
Output Enable Register
(OEnPA[n])
Active Pull-up
in Nch. Open
Drain Mode
OE[n]
Port A
Input / Output
Control Logic
Port A Data Register
(PAout[n])
Metal
Option
MAPu[n]
Output Mux Registers
out[n]
Internal DATA Bus
Vdd
PA[5,3:0]
mux[n]
Metal
Option
MAPd[n]
Multiplexed Outputs from:
- Serial Interface
- PWM, frequency out.
- System Reset
Active
Pull-down
Read Port A
Block Input (Low)
To Irq, Reset, Clock, etc
6.3.1 CMOS / Nch. Open Drain Output
The port A outputs can be configured as either CMOS or Nch. open drain outputs. In CMOS both logic ‘1’ and
‘0’ are driven out on the terminal. In Nch. Open Drain only the logic ‘0’ is driven on the terminal, the logic ‘1’
value is defined by the internal pull-up resistor (if implemented), or high impedance.
Figure 13. CMOS or Nch. Open Drain Outputs
CMOS Output
Nchannel Open Drain Output
Vdd
Active Pull-up
for High State
Daout[n]
Mux
Other Outputs
Daout[n]
PA[5,3:0]
I/O Terminal
Tri-State Output
Buffer is Closed
Out Mux Control
PA[5,3:0]
Mux
Other Outputs
Out Mux Control
Tri-State Output
Buffer : High
Impedance for
Data = ‘1’
I/O Terminal
NOTE: State of I/O pads may not be defined until Vreg reaches typ. 0.8V and Power-On-Reset logic
supplied by Vreg clears them to Inputs.
This time depends on how fast capacitor on Vreg is charged and typ. it can be in range of couple of ms.
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6.4 Port A registers
The two Control registers for Input control, RegPACntl1 and RegPACntl2, were already shown in chapter 6;
Input / Output Ports Overview.
Table 6.4.1 Register RegPA0
98H
Bit
3
2
1
0
Name
Reset
PAData[3]
0
PAData[2]
0
PAData[1]
0
PAData[0]
0
* Direct read on Port A terminals
Table 6.4.2 Register RegPa0OE
R/W
R* /W
R* /W
R* /W
R* /W
Description
PA[3] input and PAout[3] output
PA[2] input and PAout[2] output
PA[1] input and PAout[1] output
PA[0] input and PAout[0] output
Bit
3
2
1
0
Name
Reset
R/W
Description
OEnPA[3]
0
R/W
I/O control for PA[3] , output when OEnPA[3] = Hi
OEnPA[2]
R/W
I/O control for PA[2] , output when OEnPA[2] = Hi
0 P**
OEnPA[1]
0
R/W
I/O control for PA[1] , output when OEnPA[1] = Hi
OEnPA[0]
0
R/W
I/O control for PA[0] , output when OEnPA[0] = Hi
** On POR PA[2] is output (OEnPA[2]=’1’) until System reset is finished to output Reset condition.
After Reset is finished and circuit starts to execute instructions PA[2] becomes tri-state input.
Table 6.4.3 Register Pa0noPDown
Bit
Name
POR*
R/W
Description
3
NoPdPA[3]
0
R/W
No pull-down on PA[3]
2
NoPdPA[2]
0
R/W
No pull-down on PA[2]
1
NoPdPA[1]
0
R/W
No pull-down on PA[1]
0
NoPdPA[0]
0
R/W
No pull-down on PA[0]
POR* Reset only with Power On Reset
Table 6.4.4 Register Pa0NchOpenDr
Bit
3
2
1
0
Name
POR*
R/W
Description
NchOpDrPA[3]
0
R/W
Nch. Open Drain on PA[3]
NchOpDrPA[2]
0
R/W
Nch. Open Drain on PA[2]
NchOpDrPA[1]
0
R/W
Nch. Open Drain on PA[1]
NchOpDrPA[0]
0
R/W
Nch. Open Drain on PA[0]
* Reset only with Power On Reset, Default "0" is: CMOS on PA[3..0]
Table 6.4.5 Register RegPA1
Bit
3
2
1
0
Name
Reset
R/W
Description
NchOpDrPA[5]
p**
R* /W
Nch. Open Drain on PA[5]
OEnPA[5]
0
R* /W
I/O control for PA[5] , output when OEnPA[5] = Hi
PAData[5]
0
R* /W
PA[5] input and PAout[5] output
PAData[4]*
0
R*
PA[4] input
* Direct read on Port A terminals
p** reset to ‘0’ by POR only
Table 6.4.6 Register RegFreqRst
Bit
3
2
1
0
Name
InResAH
PA3/4resIn
foutSel[1]
foutSel[0]
POR
p
p
x
x
R/W
R/W
R/W
R/W
R/W
Description
Input reset On in Active and StandBy mode
PA3/4 dedicated for Input reset when set at ‘1’
Output Frequency selection (foutSel[1:0])
(11) CPUclk, (10) SysClk, (01) 2kHz, (00) 1Hz
Interrupt PortA Control bits MaskIRQPA[0/5] and MaskIRQPA[3/4] used to enable (Mask) the Interrupt
ReQuest IRQ from PortA are in register RegIRQMask1.
Interrupt status bits IRQPA[0/5] and IRQPA[3/4] used to signal the Interrupt from PortA are in register
RegIRQ1. They are both shown in Chapter Interrupt Controller.
Note: CPUClk = RCClk if no external clock used.
In case of external clock, CPUClk is equal to the PA[1] input clock.
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Output multiplexing registers are shown below.
Table 6.4.7 Register RegPACntl3
Bit
Name
POR
R/W
3
SerialStPA[3]
0
R/W
2
SerialCkPA[1]
0
R/W
1
PWMoutPA[1]
0
R/W
0
PWMoutPA[0]
0
R/W
Table 6.4.8 Register RegPACntl4
Bit
Name
POR
R/W
3
NoPdPA[5]
0
R/W
2
freqOutPA[5]
0
R/W
1
Sout/rstPA[2]
1
R/W
0
freqOutPA[2]
1
R/W
Description
Output selection for PA[3] when output
Output selection for PA[1] when output
Output selection for PA[1] when output
Output selection for PA[0] when output
Description
No pull-down on PA[5]
Output selection for PA[5] when output
Output selection for PA[2] when output
Output selection for PA[2] when output
Table 6.4.9 PA[0] I/O status depending on its RegPACntl3 and RegPa0OE registers
OEnPA[0]
PWMoutPA[0]
Description of PA[0] terminal
Input
0
X
PAout[0] general Output
1
0
PWM Output from the 10-Bit Counter
1
1
Table 6.4.10 PA[1] I/O status depending on its RegPACntl3 and RegPa0OE registers
OEnPA[1]
SerialCkPA[1] PWMoutPA[1] Description of PA[1] terminal
Input
0
X
X
PAout[1] general Output
1
0
0
PWM Output from the 10-Bit Counter
1
0
1
Sclk (Serial interface clock output)
1
1
X
Table 6.4.11 PA[2] I/O status depending on its RegPACntl4 and RegPa0OE registers
OEnPA[2]
Sout/rstPA[2] freqOutPA[2]
Description of PA[2] terminal
0
X
X
Input
1
0
0
PAout[2] general Output
1
0
1
Freq. Output (CPUClk, SysClk, 2kHz, 1Hz)
1
1
0
Sout (Serial interface data output)
High level ‘1’ during Reset state output
1
1
1
8kHz frequency output while out of reset state
Low level ‘0’ output during sleep
0
PA[0] = ‘1’
Output: high level during Reset state
1
1
PA[4] = ‘1’
Input: out of reset state and during sleep
PA[1] = ‘0’
Frequency output is selected in 6.4.6 Register RegFreqRst
Table 6.4.12 PA[3] I/O status depending on its RegPACntl3 and RegPa0OE registers
OEnPA[3]
SerialStPA[3]
Description of PA[3] terminal
Input
0
X
PAout[3] general Output
1
0
Rdy/CS (Serial interface status output)
1
1
Table 6.4.13 PA[5] I/O status depending on its RegPACntl4 and RegPA1 registers
OEnPA[5]
freqOutPA[5]
Description of PA[5] terminal
Input
0
X
PAout[5] general Output
1
0
Freq. Output (CPUClk, SysClk, 2kHz, 1Hz)
1
1
Frequency output is selected in 6.4.6 Register RegFreqRst
Note: CPUClk = RCClk if no external clock used.
In case of external clock, CPUClk is equal to the PA[1] input clock.
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7. Serial Port
The EM6680 contains a simple, half duplex three wire synchronous type serial interface., which can be used to
program or read an external EEPROM, ADC, ... etc. Its I/O are multiplexed on Port A.
For data reception, a shift-register converts the serial input data on the SIN(PA[0]) terminal to a parallel format,
which is subsequently read by the CPU in registers RegSDataL and RegSDataH for low and high nibble. To
transmit data, the CPU loads data into the shift register, which then serializes it on the SOUT(PA[2]) terminal. It
is possible for the shift register to simultaneously shift data out on the SOUT terminal and shift data in on the
SIN terminal. In Master mode, the shifting clock is supplied internally by the Prescaler : one of three prescaler
frequencies are available, Ck[16], Ck[15] or Ck[14]. In Slave mode, the shifting clock is supplied externally on
the SCLKIn(PA[1]) terminal. In either mode, it is possible to program : the shifting edge, shift MSB first or LSB
first and direct shift output. All these selection are done in register RegSCntl1 and RegSCntl2.
Figure 14. Serial Interface Architecture
Serial Master Clock Output
SCLKout to SCLK PA[1]
Serial Input Data
from SIN PA[0]
Internal Master Clock
Source (ck[16,15,14])
8-bit Shift Register
Mux
Internal DATA bus
External Slave Clock Source
(SCLKin from SCLK PA[1]
Shift Ck
Clock
Enable
Write Tx Read Tx
Shift complete
(8th Shift Clock)
IRQSerial
Status to
CS/Ready PA[3]
Mode
Control
&
Status Registers
Serial Output Data to
SOUT PA[2]
Start
Status
Direct MSB;LSB
Shift
First
Status
Control Logic
ResetStart
The PA[3..0] terminal configuration is shown in Figure 10 and 12. When the Serial Interface is used then care
should be taken not to use inputs and outputs needed for Serial Interface for other peripherals !:
∗ PA[0] {SIN} must be dedicated to Serial input if needed and can not be used for IRQ, Software Variable
jumps or Output. It can be still used for Wake-Up on Change
∗ PA[1] {SCLK} is an output for Master mode {SCLKOut} and an input for Slave mode {SCLKIn}. But different
functions can be Switched On/Off with care as they are needed.
∗ PA[2] {SOUT} must be dedicated to Serial Data Output if needed and can not be used for Analogue input, or
other Output.
∗ PA[3] {CS / Ready } if used for serial Interface status output. When used for Serial Interface it should not be
used for IRQ, Software Variable jumps or Output. It can be still used for Wake-Up on Change.
Note:
Before using the serial interface, the corresponding circuit terminals must be configured accordingly.
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7.1 General Functional Description
After power on or after any reset the serial interface is in serial slave mode with Start and Status set to 0, LSB
first, negative shift edge and all outputs are in high impedance state.
When the Start bit is set, the shift operation is enabled and the serial interface is ready to transmit or receive
data, eight shift operations are performed: 8 serial data values are read from the data input terminal into the
shift register and the previous loaded 8-bits are send out via the data output terminal. After the eight shift
operation, an interrupt is generated, and the Start bit is reset.
Parallel to serial conversion procedure ( master mode example ).
Setup the circuit IO’s accordingly.
Write to RegSCntl1 serial control (clock freq. in master mode, edge and MSB/LSB select).
Write to RegSDataL and RegSDataH (shift out data values).
Write to RegSCntl2 (Start=1, mode select, status).
Æ Starts the shift out
After the eighth clock an interrupt is generated, Start becomes low. Then, interrupt handling
Serial to parallel conversion procedure (slave mode example).
Setup the circuit IO’s accordingly.
Write to RegSCntl1 (slave mode, edge and MSB/LSB select).
Write to RegSCntl2 (Start=1, mode select, status).
After eight serial clocks an interrupt is generated, Start becomes low.
Interrupt handling.
Shift register RegSDataL and RegSDataH read.
A new shift operation can be authorized.
7.2 Detailed Functional Description
Master or Slave mode is selected in the control register RegSCntl1.
In Slave mode, the serial clock comes from an external device and is input via the PA[1] terminal as a
synchronous clock (SCLKIn) to the serial interface. The serial clock is ignored as long as the Start bit is not set.
After setting Start, only the eight following active edges of the serial clock input PA[1] are used to shift the serial
data in and out. After eight serial clock edges the Start bit is reset. The PA[3] terminal is a copy of the (Start
OR Status) bit values, it can be used to indicate to the external master, that the interface is ready to operate or
it can be used as a chip select signal in case of an external slave.
In Master mode, the synchronous serial clock is generated internally from the system clock. The frequency is
selected from one out of three sources ( MS0 and MS1 bits in RegSCntl1) . The serial shifting clock is only
generated during Start = high and is output to the SCLK terminal as the Master Clock (SCLKOut). When Start
is low, the serial clock output on PA[1] is 0.
An interrupt request IRQSerial is generated after the eight shift operations are done. This signal is set by the
last negative edge of the serial interface clock on PA[1] (master or slave mode) and is reset to 0 by the next
write of Start or by any reset. This interrupt can be masked with register RegIRQMask2. For more details
about the interrupt handling see chapter 11.
Serial data input on PA[0] is sampled by the positive or negative serial shifting clock edge, as selected by the
Control Register POSnNeg bit. Serial data input is shifted in LSB first or MSB first, as selected by the Control
Register MSBnLSB bit.
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7.2.1 Output Modes
Serial data output is given out in two different ways. Refer also to Figures 15 and 16.
Figure 15. Direct or Re-Synchronized Output
Direct Shift Out
Re-Synchronised Shift Out
• OM[0] = 0 :
The serial output data is generated with the selected shift register clock (POSnNeg). The first data bit is
available directly after the Start bit is set.
• OM[0] = 1 :
The serial output data is re-synchronized by the positive serial interface clock edge, independent of the
selected clock shifting edge. The first data bit is available on the first positive serial interface clock edge after
Start=‘1’.
Table 7.2.1 Output Mode Selection in RegSCntl2
OM[0]
Output mode
Description
0
Serial-Direct
Direct shift pos. or neg. edge data out
1
Serial-Synchronized
Re-synchronized positive edge data shift out
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Figure 16. Shift Operation and IRQ Generation
Note : A write operation in the control registers or in the data registers while Start is high will change internal
values and may cause an error condition. The user must take care of the serial interface status before writing
internal registers. In order to read the correct values on the data registers, the shift operation must be halted
during the read accesses.
Figure 17. Example of Basic Serial Port Connections
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7.3 Serial Interface Registers
Table 7.3.1 Register RegSCntl1
Bit
3
2
1
0
Name
Reset
R/W
Description
MS1
0
R/W
Frequency selection
MS0
0
R/W
Frequency selection
POSnNeg
0
R/W
Positive or negative clock edge selection for shift operation
MSBnLSB
0
R/W
Shift MSB or LSB value first (0=LSB first)
Default "0" is: Slave mode external clock, negative edge, LSB first
Table 7.3.2 Frequency and Master Slave Mode Selection
MS1
MS0
Description
Slave mode: Clock from external
0
0
Master mode Ck[14]: System clock / 4
0
1
Master mode Ck[15]: System clock / 2
1
0
Master modeCk[16]: System clock
1
1
Table 7.3.3 Register RegSCntl2
Bit
3
2
1
0
Name
Start
Status
RCoscOff
OM[0]
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Enabling the interface,
Ready or Chip Select output on PA[3]
RC oscill. disable when set @ ‘1’ if ExtCPUclkOn is ‘1’
‘0’: Direct shift Output,
‘1’: Output resynchronized
Default "0" is: Interface disabled, status 0, direct shift output.
Table 7.3.4 Register RegSDataL
Bit
3
2
1
0
Name
Reset
SerDataL[3]
0
SerDataL[2]
0
SerDataL[1]
0
SerDataL[0]
0
Default "0" is: Data equal 0.
R/W
R/W
R/W
R/W
R/W
Description
Serial data low nibble
Serial data low nibble
Serial data low nibble
Serial data low nibble
R/W
R/W
R/W
R/W
R/W
Description
Serial data high nibble
Serial data high nibble
Serial data high nibble
Serial data high nibble
Table 7.3.5 Register RegSDataH
Bit
3
2
1
0
Name
Reset
SerDataH[3]
0
SerDataH[2]
0
SerDataH[1]
0
SerDataH[0]
0
Default "0" is: Data equal 0.
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8. 10-bit Counter
The EM6680 has a built-in universal cyclic counter. It can be configured as 10, 8, 6 or 4-bit counter. If 10-bits
are selected we call that full bit counting, if 8, 6 or 4-bits are selected we call that limited bit counting.
The counter works in up- or down count mode. Eight clocks can be used as the input clock source, six of them
are prescaler frequencies and two are coming from the input pads PA[1] (direct only) and PA[3/4] (direct or
debounced). In this case the counter can be used as an event counter.
The counter generates an interrupt request IRQCount0 every time it reaches 0 in down count mode or 3FF in
up count mode. Another interrupt request IRQCntComp is generated in compare mode whenever the counter
value matches the compare data register value. Each of this interrupt requests can be masked (default). See
section 9 for more information about the interrupt handling.
A 10-bit data register CReg[9:0] is used to initialize the counter at a specific value (load into Count[9:0]). This
data register (CReg[9:0]) is also used to compare its value against Count[9:0] for equivalence.
A Pulse-Width-Modulation signal (PWM) can be generated and output on port A terminal PA[0] or PA[1].
9H
Figure 18. 10-bit Counter Block Diagram
Comparator
Up / Down Counter
Data Registers
Control Registers
8.1 Full and Limited Bit Counting
In Full Bit Counting mode the counter uses its maximum
of 10-bits length (default ). With the BitSel[1,0] bits in
register RegCDataH one can lower the counter length,
for IRQ generation, to 8, 6 or 4 bits. This means that
actually the counter always uses all the 10-bits, but
IRQCount0 generation is only performed on the number
of selected bits. The unused counter bits may or may
not be taken into account for the IRQComp generation
depending on bit SelIntFull. Refer to chapter 8.4.
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Table 8.1.1. Counter length selection
BitSel[1] BitSel[0 ]
0
0
0
1
1
0
1
1
26
counter length
10-Bit
8-Bit
6-Bit
4-Bit
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8.2 Frequency Select and Up/Down Counting
Eight (8) different input clocks can be selected to drive the Counter. The selection is done with bits
CountFSel2…0 in register RegCCntl1. Six (6) of this input clocks are coming from the prescaler. The
maximum prescaler clock frequency for the counter is half the system clock SysClk and the lowest is 1Hz typ.
Therefore a complete counter roll over can take as much as 17.07 minutes (1Hz clock, 10 bit length) or as little
as 977 μs (Ck[15] typ 16.3kHz, 4 bit length). The IRQCount0, generated at each roll over, can be used for time
bases, measurements length definitions, input polling, wake up from Halt mode, etc. The IRQCount0 and
IRQComp are generated with the system clock Ck[16] rising edge. IRQCount0 condition in up count mode is :
reaching 3FF if 10-bit counter length (or FF, 3F, F in 8, 6, 4-bit counter length). In down count mode the
condition is reaching ‘0’. The non-selected bits are ‘don’t care’. For IRQComp refer to section 8.4.
Note: The Prescaler and the Microprocessor clock’s are usually non-synchronous, therefore time bases
generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down mode).
However the prescaler clock can be synchronized with µP commands using for instance the prescaler reset
function.
Figure 19. Counter Clock Timing
Prescaler Frequencies or Debounced Port A Clocks
System Clock
Prescaler Clock
Counting
Counter IRQ’s
Non Debounced Port A Clocks (System Clock Independent)
System Clock
Port A Clock
Divided Clock
Counting
Counter IRQ’s
The two remaining clock sources are coming from the PA[1] or PA[3/4] terminals. Refer to Figure 10 on page
15 for details. Input PA[1] can be only direct non-debounce input, second PA[3/4] can be either debounce
(Ck[11] or Ck[8]) or direct input, the input polarity can also be chosen. The outputs for Timer clock inputs are
named TimCk0 and TimCk7 respectively. For the debouncer and input polarity selection refer to chapter 6.
In the case of port A input clock without debouncer, the counting clock frequency will be half the input clock on
port A. The counter advances on every odd numbered port A negative edge ( divided clock is high level ).
IRQCount0 and IRQComp will be generated on the rising PA[3/4] or PA[1] input clock edge. In this condition
the EM6680 is able to count with a higher clock rate as the internal system clock (Hi-Frequency Input).
Maximum port A input frequency is limited to 500kHz (@Vdd ≥ 1.5 V). If higher frequencies are needed, please
contact EM Microelectronic’s.
In both, up or down count (default) mode, the counter is cyclic. The counting direction is chosen in register
RegCCntl1 bit Up/Down (default ‘0’ is down count). The counter increases or decreases its value with each
positive clock edge of the selected input clock source. Start up synchronization is necessary because one can
not always know the clock status when enabling the counter. With EvCount=0, the counter will only start on the
next positive clock edge after a previously latched negative edge, while the Start bit was already set to ‘1’. This
synchronization is done differently if event count mode (bit EvCount) is chosen. Refer also to Figure 20.
Internal Clock Synchronization.
10H
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8.3 Event Counting
The counter can be used in a special event count mode where a certain number of events (clocks) on the PA[1]
(only non-debounced and only rising edge) or PA[3/4] input are counted. In this mode the counting will start
directly on the next active clock edge on the selected port A input.
Figure 20. Internal Clock Synchronization
Ck
Ck
Start
Start
Count[9:0 ]
+/-1
EvCount = 0
Count[9:0 ]
+/-1
Ck
Ck
Start
Start
Count[9:0 ]
Count[9:0 ]
EvCount = 0
EvCount = 1
+/-1
EvCount = 1
The Event Count mode is switched on by setting bit EvCount in the register RegCCntl2 to ‘1’. PA[3] or PA[4]
input depending on IrqPA[3l/4h] bit in RegPaCntl1 can be inverted depending on edgeFallingPA[3/4] in
register RegPaCntl1 and should be debounced. The debouncer is switched on with debounceNoPA[3/4] at ‘0’
in the same register. Its frequency depends on the bit DebSel from register RegPresc setting. Refer also to
Figure 10 for PortA Inputs Function. As already said for other PA[1] input only possibility is to count rising nondebounced edges.
A previously loaded register value (CReg[9:0]) can be compared against the actual counter value (Count[9:0]).
If the two are matching (equality) then an interrupt (IRQComp) is generated. The compare function is switched
on with the bit EnComp in the register RegCCntl2. With EnComp = 0 no IRQComp is generated. Starting the
counter with the same value as the compare register is possible, no IRQ is generated on start. Full or Limited
bit compare are possible, defined by bit SelIntFull in register RegSysCntl1.
EnComp must be written after a load operation (Load = 1). Every load operation resets the bit EnComp.
Full bit compare function.
Bit SelIntFull is set to ‘1’. The function behaves as described above independent of the selected counter
length. Limited bit counting together with full bit compare can be used to generate a certain amount of
IRQCount0 interrupts until the counter generates the IRQComp interrupt. With PWMOn=‘1’ the counter would
have automatically stopped after the IRQComp, with PWMOn=‘0’ it will continue until the software stops it.
EnComp must be cleared before setting SelIntFull and before starting the counter again. Be careful,
PWMoutPA[0] also redefines the port PA[0] or PWMoutPA[1] the PA[1] output data. (refer to section 0).
The signal PWMOn is acombination of PWMOutPA[0], PWMOutPA[1], SerialCkPA[1]
10H
PWMOn = (PWMOutPA[0] OR PWMOutPA[1]) AND NOT(SeriaCktPA[1]))
Limited bit compare
With the bit SelIntFull set to ‘0’ (default) the compare function will only take as many bits into account as
defined by the counter length selection BitSel[1:0] (see chapter 6.3).
8.4 Pulse Width Modulation (PWM)
The PWM generator uses the behavior of the Compare function (see above) so EnComp must be set to
activate the PWM function.. At each Roll Over or Compare Match the PWM state - which is output on port PA[0]
or PA[1] - will toggle. The start value on PA[0] or PA[1] is forced while EnComp is 0 the value is depending on
the up or down count mode. Every counter value load operation resets the bit EnComp and therefore the PWM
start value is reinstalled.
One can output PWM signal to PA[0] or PA[1]. Setting PWMoutPA[0] to ‘1’ in register RegPaCntl3 routes the
counter PWM output to PA[0]. Insure that PA[0] is set to output mode. Setting PWMoutPA[1] to ‘1’ in register
RegPaCntl3 routes the counter PWM output to PA[1]. Insure that PA[1] is set to output mode. Refer to section
6.3 and 6.4 for the port A output setup.
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The PWM signal generation is independent of the limited or full bit compare selection bit SelIntFull. However if
SelIntFull = 1 (FULL) and the counter compare function is limited to lower than 10 bits one can generate a
predefined number of output pulses. In this case, the number of output pulses is defined by the value of the
unused counter bits. It will count from the start value until the IRQComp match.
One must not use a compare value of hex 0 in up count mode nor a value of hex 3FF (or FF,3F, F if limited bit
compare) in down count mode.
For instance, loading the counter in up count mode with hex 000 and the comparator with hex C52 which will
be identified as :
- bits[11:10] are limiting the counter to limits to 4 bits length, =03
- bits [9:4] are the unused counter bits = hex 05 (bin 000101),
- bits [3:0] (comparator value = 2).
(BitSel[1,0])
(number of PWM pulses)
(length of PWM pulse)
Thus after 5 PWM-pulses of 2 clocks cycles length the Counter generates an IRQComp and stops.
The same example with SelIntFull=0 (limited bit compare) will produce an unlimited number of PWM at a length
of 2 clock cycles.
8.4.1 How the PWM Generator works.
For Up Count Mode; Setting the counter in up count and PWM mode the PA[0] or PA[1] PWM output is
defined to be 0 (EnComp=0 forces the PWM output to 0 in upcount mode, 1 in downcount). Each Roll Over will
set the output to ‘1’ and each Compare Match will set it back to ‘0’. The Compare Match for PWM always only
works on the defined counter length. This, independent of the SelIntFull setting which is valid only for the IRQ
generation. Refer also to the compare setup in chapter 0.
102H
In above example the PWM starts counting up on hex 0,
2 cycles later compare match Æ PWM to ‘0’,
14 cycles later roll over Æ PWM to ‘1’
2 cycles later compare match Æ PWM to ‘0’ , etc. until the completion of the 5 pulses.
The normal IRQ generation remains on during PWM output. If no IRQ’s are wanted, the corresponding masks
need to be set.
Figure 21. PWM Output in Up Count Mode
Figure 22. PWM Output in Down Count Mode
Clock
Clock
Count[9 :0] 03E
03F
000
001
...
Data-1
Data
Roll-over
Compare
IRQCount0
Data+1
Data+2
Count[9 :0] 001
000
3FF
3FE
...
Data+1
Data
Data-1
Data-2
Roll-over
Compare
IRQCount0
IRQComp
IRQComp
PWM output
PWM output
In Down Count Mode everything is inverted. The PWM output starts with the ‘1’ value. Each Roll Over will set
the output to ‘0’ and each Compare Match will set it back to ‘1’. Due to this positive pulse length is always
longer by 1 selected clock period compared to written value. Example: for 25% positive pulse duty cycle on 4 bit
counter one must write 3 in counter instead of 4.
For limited pulse generation one must load the complementary pulse number value. I.e. for 5 pulses counting
on 4 bits load bits[9 :4] with hex 3A (bin 111010).
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8.4.2 PWM Characteristics
PWM resolution is
: 10bits (1024 steps), 8bits (256 steps), 6bits (64 steps) or 4 bits (16 steps)
the minimal signal period is
: 16 (4-bit) x Fmax*
Æ 16 x 1/Ck[15]
Æ 977 µs
(32 KHz)
the maximum signal period is : 1024 x Fmin*
Æ 1024 x 1/Ck[1]
Æ 1024 s
(32 KHz)
the minimal pulse width is
: 1 bit
Æ 1 x 1/Ck[15]
Æ 61 µs
(32 KHz)
* This values are for Fmax or Fmin derived from the internal system clock (32kHz). Much shorter (and longer)
PWM pulses can be achieved by using the port A as frequency input.
One must not use a compare value of hex 0 in up count mode nor a value of hex 3FF (or FF,3F, F if limited bit
compare) in down-count mode.
8.5 Counter Setup
RegCDataL[3:0], RegCDataM[3:0], RegCDataH[1:0] are used to store the initial count value called CReg[9:0]
which is written into the count register bits Count[9:0] when writing the bit Load to ‘1’ in RegCCntl2. This bit is
automatically reset thereafter. The counter value Count[9:0] can be read out at any time, except when using
non-debounced high frequency port A input clock. To maintain data integrity the lower nibble Count[3:0] must
always be read first. The ShCount[9:4] values are shadow registers to the counter. To keep the data integrity
during a counter read operation (3 reads), the counter values [9:4] are copied into these registers with the read
of the count[3:0] register. If using non-debounced high frequency port A input the counter must be stopped
while reading the Count[3:0] value to maintain the data integrity.
In down count mode an interrupt request IRQCount0 is generated when the counter reaches 0. In up count
mode, an interrupt request is generated when the counter reaches 3FF (or FF,3F,F if limited bit counting).
Never an interrupt request is generated by loading a value into the counter register.
When the counter is programmed from up into down mode or vice versa, the counter value Count[9:0] gets
inverted. As a consequence, the initial value of the counter must be programmed after the Up/Down selection.
Loading the counter with hex 000 is equivalent to writing stop mode, the Start bit is reset, no interrupt request is
generated.
How to use the counter;
If PWM output is required one has to decide first on which PA port to put it. After corresponding port
Output Enable OEnPA[n] must be set PWMoutPA[n] = 1 in step 5. ( n= 0 or 1)
1st,
set the counter into stop mode (Start=0).
2nd,
select the frequency and up- or down count mode in RegCCntl1.
3rd,
write the data registers RegCDataL, RegCDataM, RegCDataH (counter start value and length)
4th,
load the counter, Load=1, and choose the mode. (EvCount, EnComp=0)
5th,
select bits PWMoutPA[n] in RegPaCntl3 and SelIntFull in RegSysCntl1
6th,
if compare mode desired , then write RegCDataL, RegCDataM, RegCDataH (compare value)
7th,
set bit Start and select EnComp in RegCCntl2.
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8.6 10-bit Counter Registers
Table 8.6.1. Register RegCCntl1
Bit
3
2
1
0
Name
Reset
R/W
Up/Down
0
R/W
CountFSel2
0
R/W
CountFSel1
0
R/W
CountFsel0
0
R/W
Default : PA0 ,selected as input clock, Down counting
Description
Up or down counting
Input clock selection
Input clock selection
Input clock selection
Table 8.6.2. Counter Input Frequency Selection with CountFSel[2..0]
CountFSel2
CountFSel1
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
Table 8.6.3. Register RegCCntl2
CountFSel0
0
1
0
1
0
1
0
1
clock source selection
Port A PA[1] = non debounced only TimCk0
Prescaler Ck[15] typ. 16 kHz
Prescaler Ck[12] typ. 2 kHz
Prescaler Ck[10] typ. 512 Hz
Prescaler Ck[8] typ. 128 Hz
Prescaler Ck[4] typ. 8 Hz
Prescaler Ck[1] typ. 1 Hz
Port A PA[3/4]
Bit
3
2
1
0
Name
Reset
R/W
Description
Start
0
R/W
Start/Stop control
EvCount
0
R/W
Event counter enable
EnComp
0
R/W
Enable comparator
Load
0
R/W
Write: load counter register;
Read: always 0
Default : Stop, no event count, no comparator, no load
Table 8.6.4. System Control register RegSysCntl1
Bit
Name
Reset
R/W
Description
3 IntEn
0
R/W
General interrupt enable
2 Sleep
0
R/W
Sleep mode
1 SetIntFull
0
R/W
Compare Interrupt select (note 1)
0 ChTmDis
p 0*
R/W
Disable Test modes by setting it to 1 (MUST be DONE)
p 0* ChTmDis is cleared on POR to be able to enter test modes at EM.
Note:
At program start the user must write the ChTmDis bit to ‘1’ to prevent from accidentally going into factory test
mode.
Setting this bit to ‘1’ must be done after a minimum number of instructions, see table 8.6.5 below. Additionally
the Port PA0 must not be declared as output before the same number of cycles are passed.
These precautions are necessary to guarantee proper factory circuit testing.
ChTmDis bit needs to be reconfirmed (write ‘1’ ) at every access to register RegSysCntl1
Table 8.6.5. Number of instructions before cutting Test access
Min Nb. of instructions before ChTmDis is
CPU frequency
set or PortPA[0] declared as an output
Basic frequency (32 kHz or 50 kHz)
4
Basic f. x 2 ( 64 kHz or 100 kHz)
8
Basic f. x 4 ( 128 kHz)
16
By writing to RegSysCntl1 – setting ChTmDis to 1 PORstatus will be cleared.
Test mode is totally disabled also if PortPA[0] is declared as an output. OenPA[0] = ‘1’
(note 1) Default : Interrupt on limited bit compare for Counter
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Table 8.6.6. Register RegCDataL, Counter/Compare Low Data Nibble
Bit
3
2
1
0
3
2
1
0
Name
CReg[3]
CReg[2]
CReg[1]
CReg[0]
Count[3]
Count[2]
Count[1]
Count[0]
Reset
0
0
0
0
0
0
0
0
R/W
W
W
W
W
R
R
R
R
Description
Counter data bit 3
Counter data bit 2
Counter data bit 1
Counter data bit 0
Data register bit 3
Data register bit 2
Data register bit 1
Data register bit 0
Table 8.6.7. Register RegCDataM, Counter/Compare Middle Data Nibble
Bit
3
2
1
0
3
2
1
0
Name
CReg[7]
CReg[6]
CReg[5]
CReg[4]
ShCount[7]
ShCount[6]
ShCount[5]
ShCount[4]
Reset
0
0
0
0
0
0
0
0
R/W
W
W
W
W
R
R
R
R
Description
Counter data bit 7
Counter data bit 6
Counter data bit 5
Counter data bit 4
Data register bit 7
Data register bit 6
Data register bit 5
Data register bit 4
Table 8.6.8. Register RegCDataH, Counter/Compare High Data Nibble
Bit
3
2
1
0
1
0
Name
BitSel[1]
BitSel[0]
CReg[9]
CReg[8]
ShCount[9]
ShCount[8]
Reset
0
0
0
0
0
0
Table 8.6.9. Counter Length Selection
BitSel[1]
BitSel[0 ]
0
0
0
1
1
0
1
1
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R/W
R/W
R/W
W
W
R
R
Description
Bit select for limited bit count/compare
Bit select for limited bit count/compare
Counter data bit 9
Counter data bit 8
Data register bit 9
Data register bit 8
counter length
10-Bit
8-Bit
6-Bit
4-Bit
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9. Supply Voltage Level Detector / 4-bit ADC
The EM6680 has a built-in circuitry made up of a comparator with band-gap reference and a resistor divider
chain with 16 terminals to detect levels from 0.5V to 2.75V with a step of 150mV. This can be used as:
a. Supply Voltage Level Detector (SVLD) to compare the positive power supply level Vdd against levels which
are in the range of Vddmin to Vddmax. There are 12 pre-selected levels in the range from 1.2 to 2.75V. In this
case ExtVcheck must be cleared to ‘0’ (default).
b. Simple 4-bit Analogue to Digital Converter – ADC. Setting the ExtVcheck bit to ‘1’ makes the PA[4] input
an analog ADC input. PA[4] input voltage must not exceed VDD + 0.3V
In Sleep mode both functions are disabled.
Figure 23. SVLD / 4-bit ADC schematic with controls and timing
Supply Voltage Level Detector & 4-bit ADC function
SVLD level5 (1.25V) or SVLD level9 (1.85V) is used during Power On Reset for Power-Check to check the
minimum operating voltage before the POR signal is released as described in Chapter 4.1.
When used as a SVLD the ExtVCheck bit in register RegVldCntl must be cleared to ‘0’. Then Vdd is selected
as the input to the resistive divider which provides the comparator inputs. The SVLD level must be selected by
writing the RegSVLDlev register. For proper operation only levels from #4 to #15 can be selected. Then the
CPU activates the voltage comparison by writing the VLDstart bit to ‘1’ in the register RegVLDCntl. The actual
measurement starts on the next ck[14] (8kHz @ 32kHz SysClk) falling edge and lasts typ. 260 us. The busy
flag VldBusy stays high from the time VLDStart is set to ‘1’ until the measurement is finished. The worst case
time until the result is available is 3.125 * ck[14] prescaler clock periods (32kHz Æ 382us). See figure 24 for
details.
During the actual measurement (typ. 260us) the device will draw typically an additional 4цA of IVDD current @
Vdd=1.5V. After the end of the measurement an interrupt request IRQSvld can be generated if Vdd is lower than
the level which was selected. The interrupt is generated only if the MaskIRQSvld bit is set to ‘1’. The result is
available by inspection of the bit VLDResult. If the result is ’0’, then the power supply voltage was lower than
the detection level value. If ‘1’ the power supply voltage was higher than the detection level value. The value of
VLDResult is not guaranteed while VldBusy=1.
An interrupt can be generated only if Vdd is lower than the selected level. IRQSvld bit is cleared by reading
RegIRQ2.
0H
Table 9.1 register RegVldCntl
Bit
3
3
2
2
1
0
Name
Reset
R/W
Description
ExtVcheck
0
W
PA[4] as positive input of divider chain
VLDResult
0
R*
VLD result flag
VLDStart
0
W
VLD start command
VLDBusy
0
R
VLD busy flag is on Until compare is finished
SVLDen
0
R/W
SVLD comparator is On continuously
NoWDtim
p
R/W
No watchdog timer
R*; VLDResult is not guaranteed while VLDBusy=1
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Figure 24. SVLD timing
The VLDresult bit from the previous measurement stays in the register until the new measurements is finished.
For good measurements external noise or CPU activity should be as low as possible during the comparison.
Table 9.2 register RegSVLDlev
Bit
3
2
1
0
Name
SVLDlev[3]
SVLDlev[2]
SVLDlev[1]
SVLDlev[0]
POR
0*
1*
0
1
R/W
R/W
R/W
R/W
R/W
Description
SVLD level select bit #3
SVLD level select bit #2
SVLD level select bit #1
SVLD level select bit #0
SVLDlev[3:2] depends on Metal option for Power-Check level
Table 9.3 SVLD level selection (typical values VSVLDNom)
SVLDlev[3:0]
MSB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LSB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Nb.:
ADC
Level #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADCNom SVLDNom
0.5 V
Do not set
0.65 V
Do not set
0.80 V
Do not set
0.95 V
Do not set
1.10 V
1.20 V
1.25 V
1.25 V
1.40 V
1.40 V
1.55 V
1.55 V
1.70 V
1.70 V
1.85 V
1.85 V
2.00 V
2.00 V
2.15 V
2.15 V
2.30 V
2.30 V
2.45 V
2.45 V
2.60 V
2.60 V
2.75 V
2.75 V
SVLD
Description of specialitis
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Depends on ExtVCheck - ADC or SVLD
Default level after POR for Power Check
Optional level after POR for Power Check
External source is coming from PA[4] as explained in Chapter 2 and shown on figure 10.
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To implement a 4-bit ADC first ExtVcheck bit must be set to ‘1’, that PA[4] input is connected to positive side of
resistor divider chain. To find the level as fast as possible with successive approximation for instance it is
advised to Set SVLDen bit to ‘1’ to have comparator and resistive divider chain operational all the time when
the PA[4] input is sampled with ck[15] (typ. 16kHz @ 32kHz SysClk) frequency. With SVLDlev[3:0] we can
select one of 16 possible levels to check and by making max. 4 measurements at 4 different levels (if input
PA[4] is stable) we have the result with successive approximation method.
In this case PA[4] input is blocked for all other functions, because its level can be in a zone where logic ‘0’ or ‘1’
are not well defined and this would generate an over consumption otherwise. So it is dedicated only to SVLD
comparator input to be compared with internal band-gap reference. NoPullPA[4] must be set to ‘1’ - PullUP/Down must be removed by register also.
In both cases if Vdd or PA[4] level is tested than if selected tested level lower an IRQ can be generated if
enabled.
With SVLDen bit one can switch on the band-gap, resistive divider and Comparator continuously. Like that one
can monitor VDD or PA[4] level continuously, at higher frequency (ck[15]). Only at the beginning after setting the
SVLDen at ‘1’ one has to wait until VLDbusy drops to ‘0’ indicating that system is powered up (band-gap
reference and resistor divider are stabilized and comparator is ready to give proper result). This will increase
power consumption by typ. 4цA @ Vdd=1.5V while used.
During continuously monitoring one can change RegSVLDlev register value on fly and the new result should be
read only after about 1.5 * ck[15] to be sure it is a result of a new SVLDlev selection. Depending on CPUclk
and divisions to obtained SysClk this can be 2 / 6 / 10 / 20 / 36 instruction after RegSVLDlev change for
multiples by 1 / 2 / 4 / 8 / 16.
When fast monitoring is not necessary any more one can remove it by clearing SVLDen to ‘0’.
When SVLD logic is used for this fast monitoring IRQ can also be generated when checked level falls below its
value.
Figure 25. SVLD timing in “ADC” mode when SVLDen set @ “1”
Due to IRQSvld which can come very fast – with ck[15] there is danger that immediately after coming out from
IRQ subroutine new IRQSvld which came during that time put uC back in IRQ subroutine and software can be
stacked at this place until checked input is lower then SVLD level. Otherwise IntEn register must be cleared in
IRQ subroutine already !! or even better to use this function by reading the SVLD result only and not setting the
MaskIRQSvld.
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10. ADC/SVLD Comparator characteristics
Vvld (levels 0 to 15)
Level
- comparator hyst.
Comparator output
Comparator hysteresis is adaptive in 4 steps controlled by MSB of RegSVLDlev register to cover all tested
levels from 0.5V to 3.0V to give a typ. “tested level” hysteresis of 40mV.
Negative hysteresis on comparator is implemented to eliminate comparator output oscillation arround switching
point.
11. RAM
The EM6680 has one 80x4 bit static RAM built-in located on addresses hex 0 to 4F. All the RAM nibbles are
direct addressable.
Figure 26. RAM Architecture
RAM 80 x 4 = direct addressable
Adr [hex]
4F
4E
4D
4B
.
.
.
.
.
.
.
.
.
.
RAM location
RAM_79
RAM_78
RAM_77
RAM_76
.
.
.
.
.
.
.
.
.
.
Read / Write
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
.
.
.
.
.
.
.
.
.
.
04
03
02
01
00
RAM_04
RAM_03
RAM_02
RAM_01
RAM_00
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
RAM Extension : Unused R/W Registers can often be used as possible RAM extension. Be careful not to use
registers which start, stop, or reset some functions.
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12. Interrupt Controller
The EM6680 has 8 different interrupt request sources masked individually. These are:
External (2)
- Port A,
- Compare
PA[0/5] and PA[3/4] inputs
PA[4] input
Internal (6)
- Prescaler (2x)
- 10-bit Counter (2x)
- SVLD (1)
- Serial Interface (1)
ck[1], 64Hz/8Hz
Count0, CountComp
End of measure when level is low
8 bit transfered
The SVLD and the PA[4] level check share the same interrupt line.
Serial Interface could be put under Internal when Serial clock is coming form EM6680 or External when Serial
clock is external.
To be able to send an interrupt to the CPU, at least one of the interrupt request flags must be set (IRQxx) and
the general interrupt enable bit IntEn located in the register RegSysCntl1 must be set to 1. The interrupt
request flags can only be set by a positive edge of IRQxx with the corresponding mask register bit
(MaskIRQxx) set to 1.
Figure 27. Interrupt control logic for generating and clearing interrupts
Interrupt control logic
At power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any
interrupt request to be stored. Also the general interrupt enable IntEn is set to 0 (No IRQ to CPU) by reset.
After each read operation on the interrupt request registers RegIRQ1 or RegIRQ2 the contents of the
addressed register are reset. Therefore one has to make a copy of the interrupt request register if there was
more than one interrupt to treat. Each interrupt request flag may also be reset individually by writing 1 into it
(ClrIntBit).
Interrupt handling priority must be resolved through software by deciding which register and which flag inside
the register need to be serviced first.
Since the CPU has only one interrupt subroutine and because the IRQxx registers are cleared after reading,
the CPU does not miss any interrupt request which comes during the interrupt service routine. If any occurs
during this time a new interrupt will be generated as soon as the software comes out of the current interrupt
subroutine.
Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the
interrupt request register. All interrupt requests are stored in their IRQxx registers depending only on their
corresponding mask setting and not on the general interrupt enable status. Whenever the EM6680 goes into
HALT Mode the IntEn bit is automatically set to 1, thus allowing to resume from Halt Mode with an interrupt.
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12.1 Interrupt control registers
Table 12.1.1 Register RegIRQ1
Bit
3
2
1
0
Name
Reset
R/W
IRQCount0
0
R/W*
IRQCntComp
0
R/W*
IRQPA[3/4]
0
R/W*
IRQPA[0/5]
0
R/W*
W*; Writing of 1 clears the corresponding bit.
Description
Counter interrupt request when at 0
Counter interrupt request when compare True
Port A PA[3/4] interrupt request
Port A PA[0/5] interrupt request
Table 12.1.2 Register RegIRQ2
Bit
3
2
1
0
Name
Reset
R/W
IRQHz1
0
R/W*
IRQHz64/8
0
R/W*
IRQSvld
0
R/W*
IRQSerial
0
R/W*
W*; Writing of 1 clears the corresponding bit.
Description
Prescaler interrupt request of 1Hz
Prescaler interrupt request of 64 Hz or 8 Hz
SVLD or Compare interrupt request
Serial interface interrupt request
Table 12.1.3 Register RegIRQMask1
Bit
3
2
1
0
Name
Reset
R/W
MaskIRQCount0
0
R/W
MaskIRQCntComp
0
R/W
MaskIRQPA[3/4]
0
R/W
MaskIRQPA[0/5]
0
R/W
Interrupt is not stored if the mask bit is 0.
Description
Counter when at 0 interrupt mask
Counter compare True interrupt mask
Port A PA[3/4] interrupt mask
Port A PA[0/5] interrupt mask
Table 12.1.4 Register RegIRQMask2
Bit
3
2
1
0
Name
Reset
R/W
MaskIRQHz1
0
R/W
MaskIRQHz64/8
0
R/W
MaskIRQSvld
0
R/W
MaskIRQSerial
0
R/W
Interrupt is not stored if the mask bit is 0.
Copyright © 2005, EM Microelectronic-Marin SA
Description
Prescaler 1Hz interrupt mask
Prescaler 64 Hz or 8 Hz interrupt mask
SVLD or Compare interrupt mask
Serial interface interrupt mask
38
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13. PERIPHERAL MEMORY MAP
Reset values are valid after power up or after every system reset.
Register
Name
Ram1_0
Ram1_63
Add Add
Hex Dec.
00
4F
0
79
Reset
Value
b'3210
xxxx
xxxx
RegPA0
50
80
0000
RegPa0OE
51
81
0000
0 = after
PORend
RegPaCntl1
52
82
pppp
p = POR
RegPaCntl2
53
83
pppp
p = POR
Pa0noPDown
54
84
pppp
p = POR
Pa0NchOpenDr
55
85
pppp
p = POR
RegFreqRst
56
86
ppxx
RegSCntl1
57
87
0000
RegSCntl2
58
88
0000
RegSDataL
59
89
0000
RegSDataH
5A
90
0000
RegCCntl1
5B
91
0000
Copyright © 2005, EM Microelectronic-Marin SA
Read Bits
Write Bits
Read / Write Bits
0: Data0
1: Data1
2: Data2
3: Data3
0: Data0
1: Data1
2: Data2
3: Data3
0: PAout[0]
0: PA[0]
1: PAout[1]
1: PA[1]
2: PAout[2]
2: PA[2]
3: PAout[3]
3: PA[3]
0: OEnPA[0]
1: OEnPA[1]
2: OEnPA[2]
3: OEnPA[3]
0: EdgeFallingPA[0/5]
1: EdgeFallingPA[3/4]
2: debunceNoPA[0/5]
3: debunceNoPA[3/4]
0: IrqPA[0l/5h]
1: IrqPA[3l/4h]
2: WUchEnPA[0/5]
3: WUchEnPA[3/4]
0: NoPdPA[0]
1: NoPdPA[1]
2: NoPdPA[2]
3: NoPdPA[3]
0: NchOpDrPA[0]
1: NchOpDrPA[1]
2: NchOpDrPA[2]
3: NchOpDrPA[3]
0: foutSel[0]
1: foutSel[1]
2: PA[3/4]resIn
3: InResAH
0: MSBnLSB
1: POSnNeg
2: MS0
3: MS1
0: OM[0]
1: RCoscOff
2: Status
3: Start
0: SerDataL[0]
1: SerDataL[1]
2: SerDataL[2]
3: SerDataL[3]
0: SerDataH[0]
1: SerDataH[1]
2: SerDataH[2]
3: SerDataH[3]
0: CountFSel0
1: CountFSel1
2: CountFSel2
3: Up/Down
39
Remarks
Direct addressable
Ram 80 x 4 bit
Direct addressable
Ram 80 x 4 bit
PortA [3:0]
Direct input read,
Output data register
PortA [3:0]
Output enable active Hi,
PortA [3:0] control1
Debounce Yes/No &
Faling / Rising edge
PortA [3:0] control2
WakeUp on change enable &
Irq source from PA select
Option register
Pull/down selection on PA[3:0]
Default : pull-down ON
Option register
N/channel Open Drain
Output on PA[3:0]
Default : CMOS output
Output Frequency select
and Input reset Control
Serial interface
control 1
Serial interface
control 2
Serial interface
low data nibble
Serial interface
high data nibble
10-bit counter
control 1;
frequency and up/down
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Register
Name
Add Add
Hex Dec.
Reset
Value
b'3210
RegCCntl2
5C
92
0000
RegCDataL
5D
93
0000
RegCDataM
5E
94
0000
RegCDataH
5F
95
0000
RegPA1
60
96
p000
RegPaCntl3
61
97
pppp
RegPaCntl4
62
98
ppPP
RegIRQMask1
65
101
0000
RegIRQMask2
66
102
0000
RegIRQ1
67
103
0000
REgIRQ2
68
104
0000
RegSysCntl1
69
105
000p
p = POR
RegSysCntl2
6A
106
Pp00
p = POR
RegSleepCR
6B
107
pppp
p = POR
Copyright © 2005, EM Microelectronic-Marin SA
Read Bits
Write Bits
Read / Write Bits
0: Load
0: '0'
1: EnComp
1: EnComp
2: EvCount
2: EvCount
3: Start
3: Start
0: CReg[0]
0: Count[0]
1: CReg[1]
1: Count[1]
2: CReg[2]
2: Count[2]
3: CReg[3]
3: Count[3]
0: CReg[4]
0: Count[4]
1: CReg[5]
1: Count[5]
2: CReg[6]
2: Count[6]
3: CReg[7]
3: Count[7]
0: CReg[8]
0: Count[8]
1: CReg[9]
1: Count[9]
2: BitSel[0]
2: BitSel[0]
3: BitSel[1]
3: BitSel[1]
0: -0: PA[4]
1: PAout[5]
1: PA[5]
2: OEnPA[5]
2: OEnPA[5]
3: NchOpDrPA[5]
3: NchOpDrPA[5]
0: PWMoutPA[0]
1: PWMoutPA[1]
2: SerialCkPA[1]
3: SerialStPA[3]
0: freqOutPA[2]
1: Sout/rstPA[2]
2: : freqOutPA[5]
3: NoPdPA[5]
0: MaskIRQPA[0/5]
1: MaskIRQPA[3/4]
2: MaskIRQCntComp
3: MaskIRQCount0
0: MaskIRQSerial
1: MaskIRQSvld
2: MaskIRQHz64/8
3: MaskIRQHz1
0:RIRQPA[0/5]
0: IRQPA[0/5]
1:RIRQPA[3/4]
1: IRQPA[3/4]
2:RIRQCntComp
2: IRQCntComp
3:RIRQCount0
3: IRQCount0
0:RIRQSerial
0: IRQSerial
1:RIRQSvld
1: IRQSvld
2:RIRQHz64/8
2: IRQHz64/8
3:RIRQHz1
3: IRQHz1
0: ChTmDis
0: ChTmDis
1: SelIntFull
1: SelIntFull
2: '0'
2: Sleep
3: IntEn
3: IntEn
0: -0: WDVal0
1: -1: WDVal1
2: SleepEn
2: SleepEn
3: WDReset
3: PORstatus
0: SCRsel0
1: SCRsel1
2: SleepCntDis
3: NoPullPA[4]
40
Remarks
10-bit counter control 2;
comparison, event counter and
start
10-bit counter
data low nibble
10-bit counter
data middle nibble
10-bit counter
data high bits
PortA [5:4]
Direct input read,
Output data register with
Output enable active Hi
PortA Control3
Output distribution on PA[0],
PA[1] and PA[3]
PortA Control4
Output distribution on PA[2]
and PA[5]
Port A & Counter
interrupt mask;
masking active 0
Prescaler, SVLD & serial interf.
interrupt mask;
masking active low
Read: port A & Counter interrupt
Write: Reset IRQ if data bit = 1.
Read: Prescaler, SVLD & serial
interface interrupt.
Write: Reset IRQ if data bit = 1
System control 1;
ChTmDis only usable only for
EM test modes
System control 2;
watchdog value and periodical
reset, enable sleep mode
Sleep Counter reset control
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EM6680
Register
Name
Add Add
Hex Dec.
Reset
Value
b'3210
RegPresc
6C
108
0000
IXLow
6E
110
xxxx
IXHigh
6F
111
xxxx
RegVldCntl
73
115
000p
RegSVLDlev
74
116
pPpp
RegTestEM1
7E
126
pppp
RegTestEM2
7F
127
pppp
Read Bits
Write Bits
Read / Write Bits
0: DebSel
0: DebSel
1: PrIntSel
1: PrIntSel
2: ResPresc
2: '0'
3: ExtCPUclkON
3: ExtCPUclkON
0: IXLow[0]
1: IXLow[1]
2: IXLow[2]
3: IXLow[3]
0: IXHigh[4]
0: IXHigh[4]
1: IXHigh[5]
1: IXHigh[5]
2: IXHigh[6]
2: IXHigh[6]
3: -3: '0'
0: NoWDtim
0: NoWDtim
1: SVLDen
1: SVLDen
2: VldStart
2: VldBusy
3: ExtVcheck
3: VldResult
0: SVLDlev[0]
1: SVLDlev[1]
2: SVLDlev[2]
3: SVLDlev[3]
0: Tmsel[0]
1: Tmsel[1]
2: Tmsel[2]
3: disablePOR
0: OeTm0
1: OeTm1
2: TestResSys
3: TestPOR
Remarks
Prescaler control;
Debouncer, prescaler interrupt
select and reset,
External CPU clock enable
Internal µP index
register low nibble;
for µP indexed addressing
Internal µP index
register high nibble;
for µP indexed addressing
Voltage level
detector & RC osc. control
SVLD test voltage level select
For EM test only
For EM test only
p = defined by POR at ‘0’ (power on reset) only
P = defined by POR at ‘1’ (power on reset) only
x = undefined state by reset (register must be written before used)
RegTestEm1 and RegTestEm2 can be written only if ChTmDis in RegSysCntl1 is ‘0’. They are used for EM
test only and are Write only. To prevent entering test mode in normal operation one has to set the ChTmDis bit
to ‘1’ as soon as possible after reset. It should be one of first instructions.
14. Active Supply Current test
For this purpose, five instructions at the end of the ROM will be added. This will be done at EM Marin.
User can use only up to 1499 Instructions (the rest – 37 instructions are used for EM tests).
TESTLOOP : STI
LDR
NORX
JPZ
JMP
00H, 0AH
1BH
FFH
TESTLOOP
;TEST LOOP
0
To stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop:
1BH:
0101b
32H:
1010b
6EH:
0010b
6FH:
0011b
Free space after last instruction: JMP 00H (0000)
Remark: empty space within the program are filled with NOP (FOFF).
Copyright © 2005, EM Microelectronic-Marin SA
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EM6680
15. Mask Options
Most options which in many µControllers are realized as metal mask options are directly user selectable with
the control registers, therefore allowing a maximum freedom of choice.
The following options can be selected at the time of programming the metal mask ROM.
15.1 Input / Output Ports
15.1.1 Port A Metal Options
Except for PA[4] which can have only strong Pull-up or Pull-down and where resistor can be removed by
software register NoPullUpDown[4], all other port A inputs can have Pull-up or no pull-up and Pull-down or no
pull-down. The pull-up is only active in Nch. open drain mode.
The total pull value (pull-up or pull-down) is a series resistance out of the resistance R1 (in range from 0 – 110
kΩ) and the switching transistor. As a switching transistor the user can choose between a high impedance
(weak) or a low impedance (strong) switch. Weak , strong or none must be chosen. The default is strong. The
default resistor R1 value is 100 kΩ. The user may choose a different value from 110 kΩ down to10 kΩ.
However the value must first be checked and agreed by EM Microelectronic Marin SA. Allowed typical values
are values between 10 kΩ and 110 kΩ in steps of 10kΩ, Refer also to chapter 15.7 for the pull values.
Figure 28. PA[5], PA[3:0] metal option architecture
Table 15.1.1 Pull-down Metal mask Options
Description
Strong
Pull-down
Weak
Pull-down
R1 Value
Typ.100k
NO
Pull-Down
Option Name
1
2
3
PA[5] input pull-down
MAPD[5]
PA[4] input pull-down
MAPD[4]
PA[3] input pull-down
MAPD[3]
PA[2] input pull-down
MAPD[2]
PA[1] input pull-down
MAPD[1]
PA[0] input pull-down
MAPD[0]
To select an option put an X in column 1,2 and 4 and reconfirm the R1 value in column 3.
4
The default value is : strong pull-down with R1=100 kΩ
Æ Total value of typ. 98 kΩ at Vdd =3.0V
PA[4] can have only Pull-Up OR Pull-Down option, others can have both and then it is software
controlled for PullUp or PullDown,
Note: The mask settings MAPD[n] do not define the default pull direction, but the pull possibilities. It is the
software which defines the pull direction (pull-up or pull-down). The only exception is on PA[4] where the user
must decide if he wants pull-up or pull-down. For this input the selected pull direction will always be valid unless
the software disconnects the pull resistor. If the mask is not present (No Pull selection) then the corresponding
pull resistor is physically cut-off and can not be reconnected by software.
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Table 15.1.2 Pull-up Metal mask Options
Strong
Description
Weak
Pull-up
Pull-up
R1 Value
Typ.100k
NO
Pull-up
Option Name
1
2
3
4
PA[5] input pull-up
MAPU[5]
PA[4] input pull-up
MAPU[4]
PA[3] input pull-up
MAPU[3]
PA[2] input pull-up
MAPU[2]
PA[1] input pull-up
MAPU[1]
PA[0] input pull-up
MAPU[0]
To select an option put an X in column 1,2 and 4 and reconfirm the R1 value in column 3.
The default value is : strong pull-up with R1=100 kΩ
Æ Total value of typ. 99 kΩ at Vdd =3.0V
PA[4] can have only Pull-Up OR Pull-Down option, others can have both and then it is software
controlled for PullUp or PullDown,
Note: The mask settings MAPU[n]) do not define the default pull direction, but the pull possibilities. It is the
software which defines the pull direction (pull-up or pull-down). The only exception is on PA[4] where the user
must decide if he wants pull-up or pull-down. For this input the selected pull direction will always be valid unless
the software disconnects the pull resistor. If the mask is not present (No Pull selection) then the corresponding
pull resistor is physically cut-off and can not be reconnected by software.
15.1.2 RC oscillator Frequency Option
Option
Name
RCfreq
RC osc Frequency
Default
Value
A
32 kHz
User
Value
B
By default the RC oscillator frequency is typ. 32
kHz With option RCfreq. Other possibilities are:
64kHz, 128kHz, 256kHz and 500kHz or 50kHz,
100kHz, 200kHz, 400kHz or max. 800kHz .
15.1.3 Debouncer Frequency Option
Option
Name
MDeb
Debouncer freq.
Default
Value
A
Ck[11]
B
By default the debouncer frequency is Ck[11]. The
user may choose Ck[14] instead of Ck[11].
Ck[14 ]corresponds
to
maximum
0.25ms
debouncer time in case of a 32kHz System Clock –
SysClk.
User
Value
Higher frequency can not work well if Voltage is too
low. So this option must be selected with help of
EM to gurantee proper operation. Possible options
are SVLD#5 @ 1.25V (default – to be used with
“low” frequency) and SVLD#9 @ 1.85V for “high”
frequency.
User
Value
15.1.4 Power-Check Level Option
Option
Name
PClev.
Power-Check level
Default
Value
A
#5(1.25V)
B
15.1.5 ADC/SVLD Voltage Level #15
Option
Name
HisvldLev. ADC/SVLD lev.#15
Default
Value
A
2.75V
Copyright © 2005, EM Microelectronic-Marin SA
User
Value
B
By default the ADC/SVLD Voltage Level #15 is at
2.75V but user can select also the second
possibility which is 3.0V and does not influence on
other ADC/SVLD levels.
43
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EM6680
15.1.6 Counter Update option
Option
Name
CntF
Counter Reg. level
Default User
Value
Value
A
B
SysClk RCclk
By default the counter is updated by Sysclk (32 or
50kHz typ) and the highest counter frequency is
Sysclk/2 (16 or 25kHz Typ). The other possibility is
to select CPUclk/2 for counter update freq. Which
gives a possibility to replace port A input at
selection 7 by CPUclk/2. If DebouncerNoPA[3/4]
in RegPACntl[1] is ‘1’ then the resulting clock on
timer selection 7 is CPUClk divided by 4. If
DebouncerNoPA[3/4] is ‘0’ then the resulting clock
is CpuClk/2 directly.
Note: CPUClk = RCClk if no external clock used.
In case of external clock, CPUClk is equal to the PA[1] input clock.
15.1.7 Voltage Regulator level
Option
Name
LevelReg
Voltage Reg. level
Default
Value
A
2T
By default the internal voltage regulator is based on
2 transistor thresholds (~1.5V). We can add one
threshold (3T, ~2.1V) and additional current to
increase Vreg level. Higher Vreg is needed for higher
CPU frequencies !!!
Possible are: 2T,3T.
User
Value
B
Please contact EM for proper selection. 3T (3 tresholds) must be used for frequencies above 300 kHz.
Figure 29. Minimum VDD = f(RC oscillator)
Rcfreq = CPU freq = f(Vddmin)
1.9
m in Vbat (Vdd ) [V]
1.8
LevelReg
2T<=
1.7
1.6
1.5
1.4
LevelReg
=>3T
1.3
1.2
1.1
1
0
100
200
Copyright © 2005, EM Microelectronic-Marin SA
300
400
44
500
600
700
f [kHz]
800
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16. Temp. and Voltage Behaviors
16.1 IDD Current (Typical) and Vreg for 2 thresholds and 1/3 of possible current for Vreg.
Idd-sleep = f(Vdd,temp)
Vreg = 2 tresholds & 1/3 current
Idd-Halt = f(Vdd,temp), Rcosc = 32 kHz typ.
Vreg = 2 tresholds & 1/3 current, RCtempComp=ON
350
4.50
300
4.00
Idd-Halt [uA]
Idd-sleep [nA]
250
200
150
3.50
3.00
100
1.5V
1.5V
3.0V
3.0V
2.50
50
0
-20
2.00
0
20
40
60
80
temp [ °C]
-20
0
20
40
60
80
temp [°C]
Vreg = f(Vdd,temp), Rcosc = 32 kHz typ.
Vreg = 2 tresholds & 1/3 current
Idd-Run = f(Vdd,temp), Rcosc = 32 kHz typ.
Vreg = 2 tresholds & 1/3 current, RCtempComp=ON
1.60
5.00
1.50
1.40
Vreg [V]
Idd-Run [uA]
4.50
4.00
1.30
3.50
1.20
1.5V
3.0V
1.5V
3.00
-20
3.0V
1.10
0
20
40
60
80
temp [°C]
-20
0
20
40
60
80
temp [°C]
16.2 Pull-down Resistance (Typical)
Pull-down weak = f(Vdd, temp)
Pull-down strong = f(Vdd, temp)
200
110
190
105
180
170
160
1.5V
95
r [kOhm]
r [kOhm]
100
3
150
1.5V
140
3
130
90
120
110
85
100
80
-20
90
0
20
40
60
-20
80
temp [°C]
0
20
40
60
80
tem p [°C]
16.3 Pull-up Resistance (Typical)
Pull-up strong = f(Vdd, temp)
Pull-up weak = f(Vdd, temp)
420
400
380
360
340
320
300
280
260
240
220
200
180
160
140
120
115
r [kOhm]
105
100
1.5
3
r [kOhm]
110
95
90
85
-20
0
20
40
Copyright © 2005, EM Microelectronic-Marin SA
60
80
tem p [°C]
-20
45
1.5V
0
20
40
3
60
80
tem p [°C]
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EM6680
16.4 Output Currents (Typical)
Iol - Buffer output current on PA[5,0] @ Vdd = 1.5V
Iol - Buffer output current on PA[5,0] @ Vdd = 3.0V
30
9
Vol=0.15V
8
Vol=0.3V
Vol=0.5V
Vol=1.0V
25
7
20
Iol [mA]
Iol [mA]
6
5
4
15
10
3
2
5
1
0
0
-20
0
20
40
60
-20
80
temp [°C]
Iol - Buffer output current on PA[2:1] @ Vdd = 1.5V
20
40
60
80
temp [°C]
Iol - Buffer output current on PA[2:1] @ Vdd = 3.0V
20
60
18
Vol=0.15V
Vol=0.3V
Vol=0.5V
50
16
14
40
Iol [mA]
12
Iol [mA]
0
10
8
30
20
6
4
10
2
0
0
-20
0
20
40
60
-20
80
tem p [°C]
0
Iol - Buffer output current on PA[3] @ Vdd = 1.5V
20
40
60
80
tem p [°C]
Iol - Buffer output current on PA[3] @ Vdd = 3.0V
12
45
Vol=0.15V
10
Vol=0.3V
Vol=0.15V
40
Vol=0.5V
Vol=0.3V
Vol=0.5V
Vol=1.0V
35
30
Iol [mA]
Iol [mA]
8
6
25
20
4
15
10
2
5
0
-20
0
0
20
40
Copyright © 2005, EM Microelectronic-Marin SA
60
80
tem p [°C]
-20
46
0
20
40
60
80
tem p [°C]
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EM6680
Ioh - Buffer output current on PA[5,0] @ Vdd = 1.5V
Ioh - Buffer output current on PA[5,0] @ Vdd = 3.0V
0
0
-20
0
20
40
60
-20
80
-0.5
0
-2
20
40
60
80
-4
-1
Iol [mA]
-6
Iol [mA]
-1.5
-2
-8
-10
-2.5
-12
-3
-14
Voh=1.35V
Voh=1.2V
Voh=1.0V
Voh=2.85V
Voh=2.7V
Voh=2.5V
temp [°C]
temp [°C]
Ioh - Buffer output current on PA[2:1] @ Vdd = 1.5V
Ioh - Buffer output current on PA[2:1] @ Vdd = 3.0V
0
0
-20
0
20
-1
40
Voh=1.35V
60
Voh=1.2V
-20
80
Voh=1.0V
20
40
-3
80
-15
-4
-20
-5
-25
Voh=2.85V
Voh=2.7V
Voh=2.5V
Voh=2.0V
-30
-6
tem p [°C]
tem p [°C]
Ioh - Buffer output current on PA[3] @ Vdd = 1.5V
Ioh - Buffer output current on PA[3] @ Vdd = 3.0V
0
0
0
-0.5
60
-10
Iol [mA]
Iol [mA]
0
-5
-2
-20
Voh=2.0V
-16
-3.5
20
40
Voh=1.35V
60
Voh=1.2V
80
-20
Voh=1.0V
-2
0
20
40
60
80
-4
-1
-6
Iol [mA]
Iol [mA]
-1.5
-2
-2.5
-16
-3.5
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-12
-14
-3
-4
-8
-10
-18
Voh=2.85V
Voh=2.7V
Voh=2.5V
Voh=2.0V
-20
tem p [°C]
tem p [°C]
47
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EM6680
17. Electrical Specification
17.1 Absolute Maximum Ratings
Min.
- 0.2
VSS – 0.2
- 40
-2000
Power supply VDD-VSS
Input voltage
Storage temperature
Electrostatic discharge to
Mil-Std-883C method 3015.7 with ref. to VSS
Maximum soldering conditions
Packages are Green-Mold and Lead-free
Max.
+ 3.6
VDD+0.2
+ 125
+2000
Units
V
V
°C
V
As per Jedec J-STD-020C
Stresses above these listed maximum ratings may cause permanent damage to the device.
Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction.
17.2 Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions
should be taken as for any other CMOS component.
Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply
voltage range.
17.3 Standard Operating Conditions
Parameter
Temperature
Vdd _Range1
Vdd _Range2 @25°
Vdd _Range3 @-20°
Ivss max
Ivdd max
VSS
CVDDCA (note 1)
fRC
MIN
-20
1.4
1.2
1.35
TYP
25
3.0
1.5
1.5
MAX
85
3.6
1.8
1.8
80
80
Unit
°C
V
V
V
mA
mA
V
nF
kHz
0
100
30
800
Description
with internal voltage regulator
without internal voltage regulator
without internal voltage regulator
Maximum current out of Vss Pin
Maximum current into of Vdd Pin
Reference terminal
regulated voltage capacitor
Range of typ. RC frequency
Note 1: This capacitor filters switching noise from Vdd to keep it away from the internal logic cells.
In noisy systems the capacitor should be chosen bigger than minimum value.
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17.4 DC Characteristics - Power Supply
Conditions: Vdd =1.5V, T=25°C, RCfreq = 32 kHz .
Parameter
ACTIVE Supply Current
ACTIVE Supply Current
STANDBY Supply Current
STANDBY Supply Current
SLEEP Supply Current
SLEEP Supply Current
POR static level
POR static level
Power-Check level (low f)
(@ RC oscill.high frequency)
RAM data retention
Conditions
-20 ... 85°C
-20 ... 85°C
-20 ... 85°C
-20 ... 85°C
-20 ... 85°C
Symbol
IVDDa1
IVDDa1
IVDDh1
IVDDh1
IVDDs1
IVDDs1
VPOR
VPOR
VPC5
VPC9
Vrd1
Min.
Symbol
IVDDa2
IVDDa2
IVDDh2
IVDDh2
IVDDs2
IVDDs2
Vreg2
Min.
Typ.
4.0
3.5
0.65
1.05
1.05
1.25
1.85
Max.
5.0
7.0
4.8
6.0
0.8
1.5
1.36
1.2
1.41
2.09
Unit
μA
μA
μA
μA
μA
μA
V
V
V
V
V
Max.
5.0
7.0
4.8
6.0
0.8
1.5
Unit
μA
μA
μA
μA
μA
μA
V
1.0
VPOR Typ
1.300
VPOR [V]
1.200
1.100
1.000
0.900
0.800
0.700
-20
0
20
40
60
80
temp [°C]
Conditions: Vdd =3.0V, T=25°C, RCfreq = 32 kHz .
Parameter
ACTIVE Supply Current
ACTIVE Supply Current
STANDBY Supply Current
STANDBY Supply Current
SLEEP Supply Current
SLEEP Supply Current
Vreg
Conditions
-20 ... 85°C
-20 ... 85°C
-20 ... 85°C
3.0
0.65
1.55
Idd @ Voltage regul ator with 3T /W = f(freq[kHz])
Idd @ Voltage regul ator with 2T /W = f(freq[kHz])
30
120
25
100
20
80
I [uA]
I [uA]
Typ.
4.0
15
10
60
40
halt
5
run
halt
run
20
0
0
0
50
100
150
200
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250
f [kHz]
300
200
300
400
500
600
700
800
900
f [kHz]
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EM6680
Conditions: VDD=3.0V, T=25°C, RCfreq = 256 kHz
Parameter
ACTIVE Supply Current
ACTIVE Supply Current
STANDBY Supply Current
STANDBY Supply Current
SLEEP Supply Current
SLEEP Supply Current
Vreg
Conditions
-20 ... 85°C
-20 ... 85°C
-20 ... 85°C
Symbol
IVDDa3
IVDDa3
IVDDh3
IVDDh3
IVDDs3
IVDDs3
Vreg3
Min.
Symbol
IVDDa4
IVDDa4
IVDDh4
IVDDh4
IVDDs4
IVDDs4
Vreg4
Min.
Typ.
36
27
0.65
Max.
45
48
35
38
0.8
1.5
Unit
μA
μA
μA
μA
μA
μA
Max.
140.0
200.0
115
150.0
0.8
1.7
Unit
μA
μA
μA
μA
μA
μA
V
1.55
Conditions: VDD=3.0V, T=25°C, RCfreq = 800 kHz
Parameter
ACTIVE Supply Current
ACTIVE Supply Current
STANDBY Supply Current
STANDBY Supply Current
SLEEP Supply Current
SLEEP Supply Current
Vreg
Copyright © 2005, EM Microelectronic-Marin SA
Conditions
-20 ... 85°C
-20 ... 85°C
-20 ... 85°C
50
Typ.
110.0
80
0.65
2.1
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17.5 Supply Voltage Level Detector
SVLD levels, here below, are specified with a rising voltage on PA[4] or VDD. When voltage is falling a
negative hysteresis has to be removed from the specified value.
Vvld (levels 0 to 15)
VDD or PA[4]
- comparator hyst.
SVLD result
Conditions: VDD=3.0V, T=25°C, with internal voltage regulator (unless otherwise specified)
Parameter
Temperature coefficient
ADC voltage Level0
ADC voltage Level1
ADC voltage Level2
ADC voltage Level3
ADC voltage Level4
SVLD voltage Level4a**
ADC/SVLD voltage Level5
ADC/SVLD voltage Level6
ADC/SVLD voltage Level7
ADC/SVLD voltage Level8
ADC/SVLD voltage Level9
ADC/SVLD voltage Level10
ADC/SVLD voltage Level11
ADC/SVLD voltage Level12
ADC/SVLD voltage Level13
ADC/SVLD voltage Level14
ADC/SVLD voltage Level15
ADC/SVLD voltage Level15b*
ADC/SVLD
level negative hysteresis
Conditions
0 to 50°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
Symbol
Min.
VVLD0
VVLD1
VVLD2
VVLD3
VVLD4
VVLD4a
VVLD5
VVLD6
VVLD7
VVLD8
VVLD9
VVLD10
VVLD11
VVLD12
VVLD13
VVLD14
VVLD15
VVLD15b
-10 to 60°C
Vvld_hyst
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Max.
0.44
0.57
0.70
0.83
0.98
1.07
1.11
1.25
1.38
1.54
1.67
1.81
1.94
2.11
2.25
2.38
2.52
2.75
Typ.
< ± 0.1
0.50
0.65
0.80
0.95
1.10
1.20
1.25
1.40
1.55
1.70
1.85
2.00
2.15
2.30
2.45
2.60
2.75
3.00
0.55
0.73
0.86
1.02
1.17
1.32
1.38
1.54
1.71
1.87
2.04
2.20
2.37
2.53
2.70
2.86
3.03
3.30
Unit
mV/°C
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
10
40
100
mV
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EM6680
Conditions: Vdd =3.0V, T=25°C, with internal voltage regulator (unless otherwise specified)
Parameter
ADC voltage Level0
ADC voltage Level1
ADC voltage Level2
ADC voltage Level3
ADC voltage Level4
SVLD voltage Level4a**
ADC/SVLD voltage Level5
ADC/SVLD voltage Level6
ADC/SVLD voltage Level7
ADC/SVLD voltage Level8
ADC/SVLD voltage Level9
ADC/SVLD voltage Level10
ADC/SVLD voltage Level11
ADC/SVLD voltage Level12
ADC/SVLD voltage Level13
ADC/SVLD voltage Level14
ADC/SVLD voltage Level15
ADC/SVLD voltage Level15b*
Conditions
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
Symbol
VVLD0
VVLD1
VVLD2
VVLD3
VVLD4
VVLD4a
VVLD5
VVLD6
VVLD7
VVLD8
VVLD9
VVLD10
VVLD11
VVLD12
VVLD13
VVLD14
VVLD15
VVLD15b
Min.
Typ.
0.43
0.55
0.68
0.81
0.95
1.04
1.08
1.21
1.34
1.49
1.62
1.75
1.88
2.04
2.17
2.31
2.44
2.66
Max.
0.50
0.65
0.80
0.95
1.10
1.20
1.25
1.40
1.55
1.70
1.85
2.00
2.15
2.30
2.45
2.60
2.75
3.00
Unit
0.57
0.75
0.90
1.07
1.24
1.36
1.41
1.58
1.75
1.92
2.09
2.26
2.43
2.60
2.77
2.94
3.11
3.39
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
** ADC level #4 (from PA[4] input) and SVLD level #4 (from VDD) are not identical. Due to VDD min = Vdd min of
1.2V level4a corresponds to SVLD level4 (1.2V typ.) only when VDD is controlled. When used for ADC Voltage
Level4 of 1.1V typ is selected to have linear scale on ADC levels.
* ADC/SVLD Voltage Level 15 / 15b. For the highest ADC/SVLD level we have a metal option where user can
select 2.75V typ. or 3.0V typ. This option does not have any influence on other ADC/SVLD levels. See Option
14.1.6.ADC/SVLD Voltage Level #15 on page 43.
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17.6 DC characteristics - I/O Pins
Conditions: T= -20 ... 85°C (unless otherwise specified)
Vdd =1.5V means; measures without voltage regulator
Vdd =3.0V means; measures with voltage regulator
Parameter
Conditions
Symb.
Min.
Typ.
Max.
Unit
Input Low voltage
Port A[5:0]
Vdd < 1.5V
VIL
Vss
0.2 Vdd
V
Port A[5:0]
Vdd > 1.5V
VIL
Vss
0.3 Vdd
V
VIH
0.7 Vdd
Vdd
V
Input High voltage
Port A[5:0]
Input Pull-down
Vdd =1.5V, Pin at 1.5V, 25°C
RPD
100k
170k
400k
Ω
PA[5:0] (note 3) weak
Vdd =3.0V, Pin at 3.0V, 25°C
RPD
80k
110k
250k
Ω
Input Pull-up
Vdd =1.5V, Pin at 0.0V, 25°C
RPU
300k
400k
900k
Ω
PA[5:0] (note 3) weak
Vdd =3.0V, Pin at 0.0V, 25°C
RPU
115k
150k
350k
Ω
Input Pull-down
Vdd =1.5V, Pin at 1.5V, 25°C
RPD
81k
99k
123k
Ω
PA[5:0] (note 3) strong
Vdd =3.0V, Pin at 3.0V, 25°C
RPD
80k
98k
122k
Ω
Input Pull-up
Vdd =1.5V, Pin at 0.0V, 25°C
RPU
85k
103k
127k
Ω
PA[5:0] (note 3) strong
Vdd =3.0V, Pin at 0.0V, 25°C
RPU
81k
99k
123k
Output Low Current
Vdd =1.5V , VOL=0.15V
IOL
2.6
mA
PA[5,0]
Vdd =1.5V , VOL =0.30V
IOL
4.9
mA
Vdd =1.5V , VOL =0.50V
IOL
7.6
mA
Vdd =3.0V , VOL =0.15V
IOL
3.6
mA
Vdd =3.0V , VOL =0.30V
IOL
7.2
mA
Vdd =3.0V , VOL =0.50V
IOL
12
mA
Vdd =3.0V , VOL =1.00V
IOL
23
mA
Output Low Current
Vdd =1.5V , VOL =0.15V
IOL
5
mA
PA[2,1]
Vdd =1.5V , VOL =0.30V
IOL
9.5
mA
Vdd =1.5V , VOL =0.50V
IOL
14.6
mA
Vdd =3.0V , VOL =0.15V
IOL
7
mA
Vdd =3.0V , VOL =0.30V
IOL
13.9
mA
Vdd =3.0V , VOL =0.50V
IOL
23
mA
Vdd =3.0V , VOL =1.00V
IOL
45
mA
Output Low Current
Vdd =1.5V , VOL =0.15V
IOL
3.4
mA
PA[3]
Vdd =1.5V , VOL =0.30V
IOL
6.6
mA
Vdd =1.5V , VOL =0.50V
IOL
10.2
mA
Vdd =3.0V , VOL =0.15V
IOL
5
mA
Vdd =3.0V , VOL =0.30V
IOL
9.9
mA
Vdd =3.0V , VOL =0.50V
IOL
16.5
mA
Vdd =3.0V , VOL =1.00V
IOL
32.0
mA
4.0
7.0
7.0
16.0
5.4
12.0
Ω
Note 3 : Weak or strong are standing for weak pull or strong pull transistor. Values are for R1=100kΩ
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Parameter
Conditions
Symb.
Min.
Typ.
Max.
Unit
Output High Current
Vdd =1.5V, VOH= Vdd -0.15V
IOH
-1.0
mA
PA[5,0]
Vdd =1.5V, VOH = Vdd -0.30V
IOH
-1.9
mA
Vdd =1.5V, VOH = Vdd -0.50V
IOH
-2.8
Vdd =3.0V, VOH = Vdd -0.15V
IOH
-1.7
mA
Vdd =3.0V , VOH = Vdd -0.30V
IOH
-3.4
mA
Vdd =3.0V , VOH = Vdd -0.50V
IOH
-5.5
Vdd =3.0V , VOH = Vdd -1.00V
IOH
-10.4
mA
Output High Current
Vdd =1.5V, VOH = Vdd -0.15V
IOH
-2.0
mA
PA[2,1]
Vdd =1.5V, VOH = Vdd -0.30V
IOH
-3.7
mA
Vdd =1.5V, VOH = Vdd -0.50V
IOH
-5.4
Vdd =3.0V, VOH = Vdd -0.15V
IOH
-2.9
mA
Vdd =3.0V , VOH = Vdd -0.30V
IOH
-5.7
mA
Vdd =3.0V , VOH = Vdd -0.50V
IOH
-9.4
Vdd =3.0V , VOH = Vdd -1.00V
IOH
-17
mA
Output High Current
Vdd =1.5V, VOH = Vdd -0.15V
IOH
-1.3
mA
PA[3]
Vdd =1.5V, VOH = Vdd -0.30V
IOH
-2.5
mA
Vdd =1.5V, VOH = Vdd -0.50V
IOH
-3.6
Vdd =3.0V, VOH = Vdd -0.15V
IOH
-2.2
mA
Vdd =3.0V , VOH = Vdd -0.30V
IOH
-4.3
mA
Vdd =3.0V , VOH = Vdd -0.50V
IOH
-7.1
Vdd =3.0V , VOH = Vdd -1.00V
IOH
-13.0
-1.5
mA
-2.5
mA
-3.0
mA
-6.4
mA
-2.0
mA
-3.2
mA
mA
17.7 RC oscillator frequency
Conditions: Vdd =3.0V, T=25°C, with internal voltage regulator, Not trimmed absolute RC frequency.
Parameter
Voltage stability (note 4)
Voltage stability (note 5)
Basic 32 kHz
Basic 32 kHz x 2
Basic 32 kHz x 4
Basic 32 kHz x 8
Basic 32 kHz x 16
Basic 50 kHz
Basic 50 kHz x 2
Basic 50 kHz x 4
Basic 50 kHz x 8
Basic 50 kHz x 16
Conditions
Vdd =1.8 – 3.0 V
Vdd =1.4 – 1.6 V
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
Symbol
df/f x dU
df/f x dU
fb1
fb1x2
fb1x4
fb1x8
fb1x16
fb2
fb2x2
fb2x4
fb2x8
fb2x16
Min.
Typ.
0.4
-25%
-25%
-25%
-25%
-25%
-25%
-25%
-25%
-25%
-25%
32
64
128
256
500
50
100
200
400
800
Max.
1.0
5.0
+25%
+25%
+25%
+25%
+25%
+25%
+25%
+25%
+25%
+25%
Unit
%/V
%/V
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
Note 4 : Applicable only for the versions with the internal voltage regulator
Note 5 : Applicable only for the versions without the internal voltage regulator.
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Conditions: Vdd =3.0V, T=25°C, with internal voltage regulator, Trimmed absolute RC frequency
Parameter
Basic 32 kHz
Basic 32 kHz x 2
Basic 32 kHz x 4
Basic 32 kHz x 8
Basic 32 kHz x 16
Basic 50 kHz
Basic 50 kHz x 2
Basic 50 kHz x 4
Basic 50 kHz x 8
Basic 50 kHz x 16
Oscillator start voltage
Oscillator start time
System start time
(oscillator + cold-start + reset)
Conditions
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
-10 to 60°C
Tstart < 10 ms
Vdd > VDDMin
Vdd > VDDMin
Symbol
fb1
fb1x2
fb1x4
fb1x8
fb1x16
fb2
fb2x2
fb2x4
fb2x8
fb2x16
Ustart
tdosc
tdsys
Min.
-10%
-10%
-10%
-10%
-10%
-10%
-10%
-10%
-10%
-10%
VDDmin
Typ.
32
64
128
256
500
50
100
200
400
800
Max.
-10%
-10%
-10%
-10%
-10%
-10%
-10%
-10%
-10%
-10%
0.1
0.5
5.0
6.0
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
V
ms
ms
17.8 Sleep Counter Reset - SCR
Conditions: Vdd =3.0V, T=25°C, with internal voltage regulator
Parameter
SCR timeout 0
SCR timeout 1
SCR timeout of 2
SCR timeout of 3
Conditions
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
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Symbol
tSCR00
tSCR01
tSCR10
tSCR11
55
Min.
Typ.
3.6
35
280
2240
Max.
Unit
ms
ms
ms
ms
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EM6680
18. Package Dimensions
18.1 SO-8/14
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EM6680
18.2 TSSOP-8/14
4
1.00
B
1.00 DIA.
3
2
C
B
1
B
E/2
1.00
CL
E
E1
5
4X
0.20
H A-B
D
0.20
C A-B
D
N
2X N/2 TIPS
7
D
A
4
SEE
DETAIL "A"
4
TOP VIEW
END VIEW
THIS TABLE FOR 0.65mm PITCH
B
O
L
A
A1
A2
aaa
b
b1
bbb
c
c1
D
E1
e
E
L
N
P
P1
C
OC
COMMON
DIMENSIONS
MIN.
NOM.
MAX.
0.05
0.85
0.90
0.076
0.19
0.19
0.22
0.10
0.09
0.09
0.127
SEE VARIATIONS
4.30
4.40
0.65 BSC
6.40 BSC
0.50
0.60
SEE VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
0°
N
O
T
1.10
0.15
0.95
0.30
0.25
9
E
NOTE
VARIATIONS
AA/AAT
AB-1/ABT
AB/ABT
AC/ACT
AD/ADT
AE/AET
5
D
3.00 BSC
5.00 BSC
5.00 BSC
6.50 BSC
7.80 BSC
9.70 BSC
P
MAX.
7
N
P1
MAX.
2.2
3.1
3.0
4.2
5.5
5.5
3.2
3.0
3.0
3.0
3.0
3.0
8
14
16
20
24
28
- DESIGNED BUT NOT TOOLED
0.20
0.16
5
5
4.50
b
bbb
M C A-B
A2
6
7
13
13
0.70
0.05
D
9
C
A
8°
H
M
3
aaa
e
A1
(14°)
D
5
C
Y
C
S
SEATING
PLANE
0.25
PARTING
LINE
H
L 6
C
(O
)C
e/2
X
X = A AND B
X
(1.00)
DETAIL 'A'
ODD LEAD SIDES
TOPVIEW
(14°)
(SCALE: 30/1)
(VIEW ROTATED 90° C.W.)
Copyright © 2005, EM Microelectronic-Marin SA
57
X = A AND B
EVEN LEAD SIDES
TOPVIEW
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8
R
EM6680
19. Ordering Information
Packaged Device:
Device in DIE Form:
EM6680 SO8 A - %%%
EM6680 WS 11 - %%%
Package:
SO8 = 8 pin SOIC
TP8 = 8 pin TSSOP
DL8 = 8 pin DIP (note 1)
SO14 = 14 pin SOIC
TP14 = 14 pin TSSOP
Die form:
WW = Wafer
WS = Sawn Wafer/Frame
WP = Waffle Pack
Thickness:
11 = 11 mils (280um), by default
27 = 27 mils (686um), not backlapped
(for other thickness, contact EM)
Delivery Form:
A = Stick
B = Tape&Reel (for SO8 and TP8 only)
Customer Version:
customer-specific number
given by EM Microelectronic
Customer Version:
customer-specific number
given by EM Microelectronic
Note 1: Please contact EM Microelectronic-Marin S.A. for availability of DIP package.
Ordering Part Number (selected examples)
Part Number
EM6680SO8A-%%%
EM6680SO8B-%%%
EM6680SO14A-%%%
EM6680TP8A-%%%
EM6680TP8B-%%%
EM6680WS11-%%%
EM6680WP11-%%%
Package/Die Form
8 pin SOIC
8 pin SOIC
14 pin SOIC
8 pin TSSOP
8 pin TSSOP
Sawn wafer
Die in waffle pack
Delivery Form/ Thickness
Stick
Tape&Reel
Stick
Stick
Tape&Reel
11 mils
11 mils
Please make sure to give the complete Part Number when ordering, including the 3-digit customer version. The customer
version is made of 3 numbers %%% (e.g. 008 , 012, 131, etc.)
19.1 Package Marking
8-pin SOIC marking:
First line:
Second line:
Third line:
8-pin TSSOP marking:
6 6 8 0 % % %
P P P P P P P
C C C Y P
6 6
8
% % % C
14-pin SOIC marking:
First line:
Second line:
Third line:
0
P
14-pin TSSOP marking:
E M 6 6 8 0 % %
P P P P P P P P
C C C C C C Y P
6 6
P P
8
P
P
0 % %
P P P
P P Y
Where: %%% or %% = customer version, specific number given by EM (e.g. 008, 012, 131, etc.)
PP…P = Production identification (date & lot number) of EM Microelectronic
Y = year of assembly
CC…C = Customer specific package marking on third line, selected by customer
19.2 Customer Marking
There are 3 digits available for customer marking on SO8, 1 for TSSOP8, 6 for SO14 and 0 for TSSOP14.
Please specify the desired customer marking:
EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressly contained in the Company's
standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site. EM assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual
property of EM are granted in connection with the sale of EM products, expressly or by implications. EM's products are not authorized for
use as components in life support devices or systems.
© EM Microelectronic-Marin SA, 01/06, Rev. M
Copyright © 2005, EM Microelectronic-Marin SA
58
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