EM4097 Data Sheet - EM Microelectronic

EM MICROELECTRONIC - MARIN SA
EM4097
READ/WRITE ANALOG FRONT END IC WITH SERIAL µC
INTERFACE FOR USAGE IN 125 / 134.2 KHZ RFID
BASESTATION APPLICATIONS
Description
The EM4097 (previously named P4097) chip is a
CMOS integrated transceiver circuit intended for use in
an RFID basestation to perform the following functions:
 Antenna driving with carrier frequency to transfer
energy to the transponder
 Data transfer to writable transponder by amplitude
modulation (ASK) of the field (100% modulation
ratio, called OOK, “on”-“off” keying)
 Data transfer from transponder by amplitude- or
phase demodulation (ASK or PSK)
 µC
Interface
to
communicate
with
a
microprocessor
Features
 Integrated PLL system to achieve self adaptive
carrier frequency to antenna resonant frequency
 Chip can be forced to run with external clock,
division ratio 32
 100kHz to 150kHz carrier frequency range
Read/Write Mode using internal PLL signal









Direct antenna driving using bridge driver
Data transmission by OOK (100% Amplitude
Modulation) using bridge driver
Multiple transponder protocol compatibility, (Ex.:
EM4102,
EM4200,
EM4450
and
EM4205/EM4305)
Two sampling points for demodulation, allowing
extended system tolerances
Serial µC interface for diagnosis and status control
Very low sleep mode current consumption of 1µA
typically
USB compatible power supply range
-40 to +85°C automotive temperature range
Small outline plastic package SO16
Applications


Animal ID reader
Hand held Low Frequency reader
Pin Assignment
EM4097
Fig. 1
Read/Write Mode using external reference signal
Fig. 3 Pinning Diagram
EM4097
Fig. 2
Copyright 2015, EM Microelectronic-Marin SA
4097-DS, Version 1.0, 26-Mar-15
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EM4097
System Principle
Fig. 4
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EM4097
Absolute Maximum Ratings
Parameter
Storage temperature
Maximum voltage at VDD
Minimum voltage at VDD
Maximum voltage at other
pins
Minimum voltage at other
pins
Maximum junction
temperature
Electrostatic discharge
according to MIL-STD-883C
method 3015 (pins ANT1
and ANT2)
Electrostatic discharge
according to MIL-STD-883C
method 3015 (other pins)
Maximum Input/Output
current for each pin except
VDD, VSS, DVDD, DVSS, ANT1,
ANT2
Maximum AC peak current
for ANT1 and ANT2 pins @
100 kHz, 50% duty cycle
Symbol
TStore
VDDma
VDDmin
Vmax
Conditions
-55°C to
+125°C
VSS + 6V
VSS - 0.3V
VDD + 0.3V
Vmin
VSS - 0.3V
TJmax
+125°C
VESD_
10000V
voltages are kept within the voltage range. Unused inputs
must always be tied to a defined logic voltage level.
Operating Conditions
Parameter
Symbol Min Typ Max Unit
Operating
junction TJ
-40
+11 °C
temperature
0
VDD
Supply voltage
4.1
5
5.5
V
Antenna
circuit FRes
100 125 150 kHz
resonance frequency
Q of antenna circuit
10
Current through ANT1 IAnt
250 mAp
and ANT2 pins
CF
**
*
10
*
nF
(not needed if external ***
100
clock is used)
CDEC
*
100 *
nF
CDC
*
10
*
nF
CAGND
100
220 nF
Thermal resistance of RthJA
69
70
71
°C/W
SO16, soldered on
1.5mm FR4 board with ****
35µm copper, standard
footprint
Ant
VESD
4000V
IImax/O
10mA
max
IANTma
400mAp
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device reliability or
cause malfunction.
Handling Procedures
This device has built-in protection against high static voltages
or electric fields; however, anti-static precautions must be
taken as for any other CMOS component. Unless otherwise
specified, proper operation can only occur when all terminal
Copyright 2015, EM Microelectronic-Marin SA
4097-DS, Version 1.0, 26-Mar-15
*: 10% tolerance capacitors should be used
**: Phase demodulation with PLL is used (see Bit#1 of serial
interface register)
***: Phase demodulation with PLL is not used (Bit#1 should
be set to “0”)
****: Due to the antenna driver losses the internal junction
temperature is higher than the ambient temperature. Please
calculate the allowed ambient temperature range by using the
maximum antenna current and the maximum package
thermal resistance. It is the user's responsibility to guarantee
that TJ remains always below 110°C.
Supply voltage (VDD and DVDD pads) must be blocked by a
100nF capacitor (to VSS) as close as possible to the chip
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EM4097
Electrical and Switching Characteristics
Parameters specified below are valid only in case the device is used according to Operating Conditions defined on previous page.
VSS = DVSS = 0V, VDD = DVDD = 5V, Tj = -40°C to 110°C; unless otherwise specified.
Symbol
Parameter
Supply current in power down mode
IDDsleep
Supply current excluding antenna current
IDDon
CAGND level
VCAGND
Logic signals
Input logic high
Input logic low
Output logic high
Output logic low
IN, CLK, EC pull down
resistor
PLL
Antenna capture
frequency range
Antenna locking
frequency range
Antenna driver
ANT driver output
resistance, full path
Diagnostic ANT driver
threshold “high”
Diagnostic ANT driver
threshold “low”
AM demodulation
DEMOD_IN common
mode range
Test Conditions
Note 1
Min
Typ
Max
Units
2.35
1
5
2.5
5
10
2.65
µA
mA
V
VIH
VIL
VOH
VOL
ISOURCE = 1mA
ISINK = 1mA
0.9VDD
RPD
0.3VDD
25
0.7VDD
0.1VDD
V
V
V
V
85
k
0.3VDD
50
FANT_C
100
150
kHz
FANT_L
100
150
kHz
15

RAD
IAnt = 100mA
VdiagOutH
8
0.7VDD
VdiagOutL
VCM
VSS + 0.5
V
0.3VDD
V
VDD - 0.5
V
mVpp
DEMOD_IN input
Vsense
Note 2
0.8
1.4
sensitivity, at gain = 480
Diagnostic DEMOD_IN
VdiagIn
1.0
1.6
Vpp
threshold
Note 1: AGND is an EM4097 internal reference point. Any external connection except specified capacitor to V SS may lead to
device malfunction.
Note 2: Modulating signal 2kHz square wave on 125kHz carrier, within boundaries of V CM.
Fig. 5
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EM4097
Timing Characteristics
Parameters specified below are valid only in case the device is used according to Operating Conditions defined on previous page.
VSS = DVSS = 0V, VDD = DVDD = 5V, T = 25°C; unless otherwise specified.
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Set-up time after a sleep period (fast
TsetF
25
35
ms
start-up)
Set-up time after a mode change (slow TsetS
100
140
ms
start-up)
AM demodulation: Delay time from
Tpd
Modulating signal 2kHz
40
100
µs
input to output
square wave 10mVpp
at fRes= 125kHz
Recovery time of reception after
Trec
550
µs
antenna modulation
Note 1
External clock frequency
fext
3.2
4.0
4.8
MHz
range
External clock duty cycle
40
60
%
External clock input
CEC
5
pF
capacitance
Maximum clock
fmax
1
MHz
frequency
Minimum pulse width
tW(H)
400
ns
(CLK) “high”
Minimum pulse width
tW(L)
400
ns
(CLK) “low”
Minimum setup time
ts
50
ns
Minimum hold time
th
5
ns
Note 1: The condition is of course that the amplitude on antenna has already reached its steady state by that time (this depends
on Q of antenna). See also Application Notes.
Block Diagram
Fig. 6
Functional Description
General
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EM4097
The EM4097 is intended to be used either with an attached
antenna circuit and a µcontroller or in an active but nonintelligent antenna configuration. Few external components
are needed to achieve DC and RF filtering and power supply
decoupling.
A stabilised power supply with sufficient current rating to
supply the coil driver has to be provided. Any ripple on V SS
causes a modulation of the antenna voltage and therefore a
modulation of the received signal at DEMOD_IN. Please
note that operating configurations in this document present
only elements, which are essential for EM4097 operation.
Additional power supply filtering capacitors, which are
necessary to filter power supply are not shown.
Serial Interface
Device operation is controlled by 8 bit Configuration
Register. This register is written via serial interface. The
functionality is as follows:
Serial Interface is controlled by signal CLK. When power
supply is applied (Power on Reset) Serial Interface is set in
Initial State (beginning of timing on figure 7). The CLK signal
has to be low. First pulse on CLK will transition Serial
Interface in Command State. In Command State the
functionality of the IN and OUT pins changes: IN pin is used
to enter 8 bit data, OUT pin is used as diagnostic output.
During clock cycles 2 to 9 the Serial Interface receives 8 bit
information. The 8 bits are shifted in 8 bit shift register on
rising edge of CLK. On the falling edge of pulse 9 the 8 bit
information is loaded in Configuration Register. During
cycles 10 to 12 the µController gets status information back
from the device. The status bits are put on pin OUT after
rising edge on signal CLK. With the 13 th clock pulse Serial
Interface transition in Active State, pins IN and OUT resume
their normal function. Additional pulses on pin CLK do not
have any influence on EM4097 operation. An Interface
Reset is needed to transition Serial Interface back in Initial
State.
Change of EM4097 Configuration register and thus
operation of device is done by performing Interface Reset
and shifting in new 8 configuration bits.
Power on Reset: After the power is switched on the internal
POR circuitry set Serial Interface in Initial State. Power
Down bit of Configuration Register is set to 0 (power down
mode). EM4097 is thus in inactive sleep mode with low
current consumption.
Fig. 7
As explained above the Configuration Register changes its
state with the falling edge of clock 9 in the Command Mode.
Changing the Power Down bit, changing the gain, the
demodulation phase or the clock source causes a delay of
about 100ms until the operating points of analog blocks are
settled. This time can be reduced to about 25ms if the fast
analog start-up has been set. In order to receive a correct
diagnostic output an appropriate pause has to be inserted
between CLK pulses 9 and 10.
Anyway the chip can be forced to return an answer
immediately after sending the 8 configuration bits but the
diagnostic data like PLL-Status may be incorrect since the
analog operating points are not set yet. See also figure 8,
which present possible states of Serial Interface and
conditions for transitions between them.
Interface Reset: A high Signal at the CLK pin and a rising
edge at the IN pin causes transition of Serial Interface in
Initial State. Interface Reset is accepted in all states of Serial
Interface.
Fig. 8
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EM4097
Configuration Register Definition
Bit #
1
2
3
4
5
6
7
8
9
10
11
Description
Sample Point
Power Down
EC=1
Data Direction
Bit#4=0
EC=0
Data/Clock
Bit#4=0
EC=X
Data/Clock
Bit#4=1
Clock source
Analog start-up
Gain setting
Gain setting
Test mode
Antenna Status
Input Status
PLL-Status
Reset
0
0
0
0
0
0
0
0
0
0
0
Bit #1: The relative demodulation phase can be changed
with this bit allowing higher tolerances in the transponder to
antenna matching.
Bit #2: This bit determines whether the chip is in sleep mode
with low power consumption or active. Active mode means
the chip is using the current contents Configuration register
for operation. Note that there is no answer from the chip after
sending the power down bit. This means that on falling edge
of bit 9 Serial Interface transition in Initial State if Power
Down bit is set to 0.
Bit #3: The meaning of this bit is controlled by the EC pin
and bit #4.
If EC is pulled to VDD and bit #4 is 0, the direction of data is
switched with this bit, pins IN and OUT are not used at the
same time. Depending on the Data Direction bit either the
OUT pin is outputting the data sent by the Transponder or
the IN pin is modulating the Antenna Driver. When OUT pin
is used, IN pin has no influence on antenna drivers (they are
always ON independent of IN pin). When IN pin is used OUT
pin is always driven to VSS. Such set up allows to connect
OUT and IN pin together to achieve a two wire connection in
an active antenna configuration (see also figure 13. Typical
operating configuration as Active Antenna).
If the EC pin is pulled to VSS or left open and bit #4 is 0, the
meaning of Bit #3 is different. Now it switches either the Data
Comparator (output of the demodulation chain) or the Clock
Reference (signal driving the antenna) divided by 32 to the
OUT pin.
In case the “External clock” mode is selected with Bit #4, the
EC pin is used for different purpose and the meaning of Bit
#3 is independent of this pin. The bit is used for the
Data/Clock selection in this case.
The state of this bit does not affect the behaviour of the serial
interface; in any case the serial register can be written and
read by the IN and OUT pins.
Bit #4: The clock for driving the antenna and demodulating
the received signal can be generated by an internal PLL if
this bit is set to “0” or by an external source connected to the
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4097-DS, Version 1.0, 26-Mar-15
if Bit is set to “0”
Amplitude demodulation
Power Down
Data from Txp at OUT-pin
IN pin has no function
Txp-Data at OUT-pin
if Bit is set to “1”
Phase demodulation
Active
Data to Txp with IN-pin
OUT pin pulled to VSS
Clock at OUT-pin
Txp-Data at OUT-pin
Clock at OUT-pin
Internal PLL
no change
External clock
fast start-up
see below
see below
Normal mode
Correct load
Correct signal
Locked
Test mode
Short circuit
No input signal
Not locked
pin EC if Bit #4 is set to “1”. In case the EC-pin is not used it
should be left open or connected to VSS.
Bit #5: This decides whether the analog circuitry is doing a
fast start-up or not. The settling time can be reduced from
about 100ms to about 25ms if parameters like sample point
or gain setting have been changed. If fast analog start-up is
set it is active from falling edge of pulse 9 to the rising edge
of pulse 10 on pin CLK.
Bit #6 & Bit#7: These bits control the gain of the amplifier.
By combining both bits the gain can be set in four steps of
6dB. Note that Bit #6 is decreasing the gain by 50% whereas
Bit #7 is increasing the gain by 100%. The default state is a
gain of 480.
Gain setting
Bit #6
Bit #7
Gain
0
1
960
0
0
480
1
1
240
1
0
120
Bit #8: This bit switches into a test mode when set. The test
mode will be left after clock pulse 13 on pin CLK. Therefore
the test mode is volatile even if it has been selected by
accident. Note that the functionality and pin assignment in
this mode is different. It should be avoided in the application.
Bit #9 – Bit#11: These bits are the diagnostic output of the
EM4097. The detectable faults are an unlocked PLL (due to
antenna mistuning for example), a short circuited connection
to the antenna or a signal below a certain threshold. The
short circuit detection is done by a voltage level comparison
of the antenna driver. If the driver can not pull the output
close enough to VSS or VDD, a short circuit is detected and
the driver is switched off immediately. This state is steady
until the next command is sent. Note that short circuit on
antennas driver shall be avoided as the maximum peak
current will go beyond absolute maximum ratings. In the
case bit #4 is 1 (external clock) the PLL is not used, PLLstatus bit is set to 0.
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Entering Data in Serial Interface
Figure below presents case where bit with value 1 is
entered. IN has to be high at least t S (50ns) before rising
edge of CLK. In the opposite case, not only that data 1 is
not accepted also Serial Interface reset might be activated.
The position of falling edge is not critical.
Fig. 9
Interface Reset Timing
As defined in the EM4097 specification, Interface Reset is
done when rising edge on IN happens while CLK is high.
We recommend that rising edge on IN appears minimum t S
(50ns) after rising edge on CLK. Internal reset signal is
active until falling edge on CLK happens. We recommend
keeping reset minimum 200ns. Falling edge on pin IN is not
important. IN can transition to 0 even before CLK.
Fig. 10
Interface reset is realised by a FF where low state of CLK is
reset and IN is clock signal. Due to this respect of tS in both
cases (before rising edge of CLK to send data and after
rising edge of CLK to make Interface reset is important).
Pins IN and OUT in Initial and Active state of Serial
Interface
The signal at the IN pin is modulating the antenna signal. A
“high” signal switches the antenna driver on, whereas a “low”
signal is forcing the antenna driver into tri-state mode to
achieve a fast de-energizing of the coil.
Output OUT is behaving according to the setting in Bit #3.
Analog Blocks
The circuit performs the two functions of an RFID
basestation, namely: transmission and reception.
Transmission involves antenna driving and AM modulation
of the RF field. The antenna driver delivers a current into the
external antenna to generate the magnetic field.
Reception involves the ASK or PSK demodulation of the
antenna signal which is modulated by the transponder. This
is achieved by sensing the absorption modulation applied by
the transponder.
Transmission
Referring to the block diagram, transmission is achieved by
a Phase Locked Loop (PLL) and the antenna driver.
Driver
The antenna driver supplies the reader basestation antenna
with the appropriate energy. It delivers current at the
resonant frequency which is typically 125 kHz. The current
delivered by the driver depends on the Q of the external
resonance circuit.
It is strongly recommended that the design of the antenna
circuit is done in a way that the maximum peak current of
250mAp is never exceeded (see Typical Operating
Configuration for antenna current calculation). Another
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limiting factor for the antenna current is the limited amount
of thermal energy which could be dissipated by the package
by radiation and convection. The maximum peak current
should be designed in a way that the internal junction
temperature does not exceed the maximum junction
temperature at allowed maximum ambient temperature.
100% modulation (OOK) is done by switching off the drivers.
The antenna driver is protected against antenna DC short
circuit to the power supplies. If an short circuit of the antenna
or from the driver to ground or supply is detected, the status
“Short Circuit” (Bit #9) is set to “1”.
Phase locked loop / External Clock
The clock for the antenna driver is either generated using
the integrated PLL or it is connected from outside through
the EC pin (External Clock Input) as 4 MHz square wave.
The EC clock is divided by 32.
The PLL is composed of the loop filter, the voltage controlled
oscillator (VCO) and the phase comparator blocks. By using
an external capacitive divider, pin DEMOD_IN gets a divided
antenna signal.
The phase of this signal is compared with the signal which
is driving the antenna driver. Therefore the PLL is able to
lock the carrier frequency to the resonant frequency of the
antenna. Depending on the antenna type the resonant
frequency of the system can be anywhere in the range from
100kHz to 150kHz. Wherever the resonant frequency is in
this range it will be maintained by the phase lock loop.
Reception
The demodulation input signal for the reception block is the
voltage sensed at the antenna. The DEMOD_IN pin is used
as input to the reception chain. The signal level on the
DEMOD_IN input must be lower than VDD - 0.5V and higher
than VSS + 0.5V. The input level is adjusted by the use of an
external capacitive divider. The additional capacitance of the
divider must be compensated by an accordingly smaller
resonance capacitor. The AM/PM demodulation scheme is
based on the "AM Synchronous Demodulation" technique.
The reception chain is composed of a sample and hold
circuit, a DC offset cancellation, a bandpass filter and a
comparator. The DC voltage of the signal on DEMOD_IN is
set to the AGND voltage by an internal resistor. The AM
signal is sampled, synchronised with the VCO. Any DC
component is removed from this signal by the CDEC
capacitor. Further filtering to remove the remaining carrier
signal, as well as high- and low frequency noise, is made by
a second order highpass filter and CDC. The amplified and
filtered demodulated signal is fed to an asynchronous
comparator. By the Sample-Point command the kind of
demodulation can be chosen. The phase shift between VCO
and sample frequency for both kinds of demodulations is
fixed in a way that pure amplitude- and pure phase
demodulation is possible. With this technique the EM4097
could demodulate also the phase shift which occurs in
certain tuning conditions between the transponder and the
antenna circuit.
TXP-Modulation / Reference-CLK
In Active Status either the Transponder modulation
information or the Reference-CLK signal is transmitted
through the OUT-Pin, but only if the Modulation Bit is not set.
The Reference-CLK is the Clock for the ANT1 and ANT2
Clock signal divided by 32, so that the controller can
calculate the actual clock signal frequency.
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EM4097
Typical Applications
Read/Write mode (Low Q factor antenna) using internal
PLL signal to generate the carrier frequency
EM4097 used as active antenna
Fig. 11
Read/Write mode (Low Q factor antenna) using external
reference signal to generate the carrier frequency
PCB Layout
Refer to "EM4095 Application Note" (App. Note 404)
Fig. 13
Fig. 12
Pin Description
SOIC 16 Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
VSS
ANT1
DVDD
ANT2
DVSS
VDD
DEMOD_IN
CDEC_OUT
CDEC_IN
CLK
IN
OUT
CAGND
CDC
CF
EC
Description
negative supply voltage
antenna driver output
positive supply voltage for antenna driver
antenna output
negative supply voltage for antenna driver
positive supply voltage
receiver input
DC blocking capacitor connection “out”
DC blocking capacitor connection “in”
µC interface, serial clock input
µC interface, serial data input, modulation pin
µC interface, serial data output, clock reference
Analog ground
DC decoupling capacitor
PLL loop filter capacitor
external clock
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Type
power supply
output
power supply
output
power supply
power supply
analog input
analog signal
analog signal
input (pull down)
input (pull down)
output
analog signal
analog signal
analog signal
input (pull down)
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EM4097
Package Information
Dimensions in millimeters
Fig. 13 Dimensions of SO16 Package
Symbol
A
A1
B
C
D
E
H
L
Min.
1.55
0.13
0.35
0.19
9.80
3.81
5.84
0.41
Nom.
1.63
0.15
0.41
0.20
9.93
3.94
5.99
0.64
Max.
1.73
0.25
0.49
0.25
9.98
3.99
6.20
0.89
Ordering Information
EM4097
V2
SO16
A
+
Version
RoHS Compliance
+ = Leadfree
[blank] otherwise
Delivery form
A = Stick
B = Tape & reel
Package
SO16 = SOIC16
Product Support
Check our Web Site under Products/RF Identification section.
Questions can be sent to [email protected]
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applicable General Terms of Sale, located at http://www.emmicroelectronic.com. EM assumes no responsibility for any errors which may
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make any commitment to update the information contained herein.
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Important note: The use of EM products as components in medical devices and/or medical applications, including but not limited
to, safety and life supporting systems, where malfunction of such EM products might result in damage to and/or injury or death of
persons is expressly prohibited, as EM products are neither destined nor qualified for use as components in such medical devices
and/or medical applications. The prohibited use of EM products in such medical devices and/or medical applications is exclusively
at the risk of the customer
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