G.975 I.4 EFEC IP Core DS-1036 Data Sheet The Altera G.975 I.4 Enhanced Forward Error Correction (G.975 I.4 EFEC) IP core demonstrates the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T) G.975 standardized Reed-Solomon (RS) and BoseChaudhuri-Hocquenghem (BCH) super FEC algorithms. G.975 I.4 EFEC implements the standardized RS (1023, 1007) and BCH (2047, 1952) codes for Optical Transport Network (OTN) data transmission at 10 gigabits per second (Gbps)/Optical Channel Transport Unit (OTU)2 and 40 Gbps/OTU3. Features G.975 I.4 EFEC includes the following features: 101 Innovation Drive San Jose, CA 95134 www.altera.com February 2012 ■ High-performance encoder and decoder for error detection and correction ■ Data transmission available for two OTN rates: ■ 10 Gbps with 64 bit datapath width ■ 40 Gbps with 256 bit datapath width ■ 7% overhead for Stratix® IV and Stratix V devices ■ Latency of 107.3 µs for 10 Gbps and 24.3 µs for 40 Gbps ■ Net electrical coding gain (NECG) of ~8.26 dB ■ Error statistic monitoring, including the following types: ■ Corrected zeros and ones errors ■ Corrected errors and uncorrectable errors ■ 10 Gbps/OTU2 and 40 Gbps/OTU3 frame count © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Altera Corporation Subscribe Page 2 Architecture Architecture Figure 1 illustrates the system architecture of the I.4 EFEC IP core. Data from an incoming client is adapted to OTN before it is written to the OTN mapper. The data is encoded with redundant data at the FEC encoder before it is transmitted across the network. The redundant data is decoded at the FEC decoder and identified errors are corrected before the data is written to the OTN framer. The data is then adapted back to the original client. Figure 1. G.975 I.4 EFEC System Architecture Customer or Altera IP Client Adaptation Altera IP Core OTN Mapper OTN FEC Encoder Altera IP Core OTN Customer or Altera IP OTN FEC Decoder OTN Framer Client Adaptation Device Family Support Table 1 defines the device support levels for Altera IP cores. Table 1. Altera IP Core Device Support Levels FPGA Device Families HardCopy® Device Families Preliminary support—The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution. HardCopy Companion—The IP core is verified with preliminary timing models for the HardCopy companion device. The IP core meets all functional requirements, but might still be undergoing timing analysis for the HardCopy device family. It can be used in production designs with caution. Final support—The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. HardCopy Compilation—The IP core is verified with final timing models for the HardCopy device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. Table 2 lists the level of support for I.4 EFEC in each of the Altera device families. Table 2. Device Family Support Device Family Support Stratix IV GT Final Stratix IV E/GX Preliminary Stratix V E/GX/GS/GT Preliminary All other device families Not available IP Core Verification Before releasing a version of the G.975 I.4 EFEC IP core, Altera runs comprehensive regression tests to verify its quality and correctness. G.975 I.4 EFEC IP Core February 2012 Altera Corporation Performance and Resource Utilization Page 3 Performance and Resource Utilization Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic registers. Table 3 shows the typical performance for 10 Gbps G.975 I.4 EFEC on the Stratix IV GT (EP4S100G5H40I1(N)) device as reported by the Quartus® II software. Table 3. Performance - 10 Gbps G.975 I.4 EFEC on Stratix IV GT Options Logic Registers ALUTS Decoder Memory (M9K) Memory (144K) fMAX (MHz) Encoder 8,794 9,558 80 blocks 2 blocks 225 Decoder 46,980 44,675 114 blocks 8 blocks 254 Net Electrical Gain (NECG) ~8.26 dB Latency 107.3 µs Table 4 shows the typical performance for 40 Gbps G.975 I.4 EFEC on the Stratix IV GT (EP4S100G5H40I1(N)) device as reported by the Quartus II software. Table 4. Performance - 40 Gbps G.975 I.4 EFEC on Stratix IV GT Options Logic Registers ALUTS Decoder Memory (M9K) Memory (144K) fMAX (MHz) Encoder 18,269 15,358 176 blocks 0 blocks 202 Decoder 107,587 85,617 214 blocks 0 blocks 205 Net Electrical Gain (NECG) 8.26 dB Latency 24.3 µs Port Listing Table 5 lists the encoder input and output ports for connecting to the G.975 I.4 EFEC IP core. Table 5. Encoder I/O Port Listing (Part 1 of 2) I/O Input Port sys_clk 10 Gbps Port Width (Bits) 40 Gbps Port Width (Bits) 1 1 Clock port. Description Input rst 1 1 This reset port is expected to meet removal and recovery constraints for sys_clk. This is an asynchronous reset and is active high. Input rs_enable_n 1 1 Enable the RS encoder. This is a synchronous signal and is active low. Input bch_enable_n 1 1 Enables the BCH encoder port. This is a synchronous signal and is active low. Input otn_row 2 2 Input OTN frame row port. This is a synchronous signal. Input otn_col 9 7 Input OTN frame column port. This is a synchronous signal. Input data_in 64 256 Input enable data port. This is a synchronous signal and is active high. Output otn_row_out 2 2 Output OTN frame row port. This is a synchronous signal. February 2012 Altera Corporation G.975 I.4 EFEC IP Core Page 4 Port Listing Table 5. Encoder I/O Port Listing (Part 2 of 2) I/O Port 10 Gbps Port Width (Bits) 40 Gbps Port Width (Bits) Description Output otn_col_out 9 7 Output OTN frame column port. This is a synchronous signal. Output data_out 64 256 Output data port. Table 6 lists the decoder input and output ports for connecting to the G.975 I.4 EFEC IP core. All error counts are accumulated on a per-clock cycle basis. Table 6. Decoder I/O Port Listing (Part 1 of 4) I/O Input Port sys_clk 10 Gbps Port Width (Bits) 40 Gbps Port Width (Bits) 1 1 Clock port. Description Input rst 1 1 This reset port is expected to meet removal and recovery constraints for sys_clk. This is an asynchronous reset and is active high. Input rs1_enable_n 1 1 Enables the first RS decoder. This is a synchronous signal and is active low. Input rs2_enable_n 1 1 Enables the second RS decoder. This is a synchronous signal and is active low. Input bch1_enable_n 1 1 Enables the first BCH decoder. This is a synchronous signal and is active low. Input bch2_enable_n 1 1 Enables the second BCH decoder port. This is a synchronous signal and is active low. Input rs1_error_scrambler_en_n 1 1 This input enables the first RS decoder’s error scrambling. This is a synchronous signal and is active low. Input rs2_error_scrambler_en_n 1 1 This input enables the second RS decoder’s error scrambling. This is a synchronous signal and is active low. Input bch1_error_scrambler_en_n 1 1 This input enables the first BCH decoder’s error scrambling. This is a synchronous signal and is active low. Input bch2_error_scrambler_en_n 1 1 This input enables the second BCH decoder’s error scrambling. This is a synchronous signal and is active low. Input otn_row 2 2 Input OTN frame row port. This is a synchronous signal. Input otn_col 9 7 Input OTN frame column port. This is a synchronous signal. Input data_in 64 256 Input data port. Output otn_row_out 2 2 Output OTN frame row port. This is a synchronous signal. G.975 I.4 EFEC IP Core February 2012 Altera Corporation Port Listing Page 5 Table 6. Decoder I/O Port Listing (Part 2 of 4) I/O Port 10 Gbps Port Width (Bits) 40 Gbps Port Width (Bits) 9 7 Output OTN frame column port. This is a synchronous signal. 1 This output is the valid signal for rs1_uncorrectable_code_ errors. This is a synchronous signal and is active high. 1 This output is the valid signal for rs2_uncorrectable_code_ errors. This is a synchronous signal and is active high. 1 This output is the valid signal for bch1_uncorrectable_code_ errors. This is a synchronous signal and is active high. 1 This output is the valid signal for bch2_uncorrectable_code_ errors. This is a synchronous signal and is active high. 1 This output is the valid signal for rs1_correctable_code_ errors. This is a synchronous signal and is active high. 1 This output is the valid signal for rs2_correctable_code_ errors. This is a synchronous signal and is active high. 1 This output is the valid signal for bch1_correctable_code_ errors. This is a synchronous signal and is active high. Description Output otn_col_out Output rs1_uncorrectable_code_ errors_valid Output rs2_uncorrectable_code_ errors_valid Output bch1_uncorrectable_code_ errors_valid Output bch2_uncorrectable_code_ errors_valid Output rs1_correctable_code_ errors_valid Output rs2_correctable_code_ errors_valid Output bch1_correctable_code_ errors_valid Output bch2_correctable_code_ errors_valid 1 1 This output is the valid signal for bch2_correctable_code_ errors. This is a synchronous signal and is active high. Output rs1_ones_errors_valid 1 1 This output is the valid signal for rs1_ones_errors. This is a synchronous signal and is active high. Output rs2_ones_errors_valid 1 1 This output is the valid signal for rs2_ones_errors. This is a synchronous signal and is active high. Output rs1_zeros_errors_valid 1 1 This output is the valid signal for rs1_zeros_errors. This is a synchronous signal and is active high. Output rs2_zeros_errors_valid 1 1 This output is the valid signal for rs2_zeros_errors. This is a synchronous signal and is active high. February 2012 Altera Corporation 1 1 1 1 1 1 1 G.975 I.4 EFEC IP Core Page 6 Port Listing Table 6. Decoder I/O Port Listing (Part 3 of 4) I/O Port 10 Gbps Port Width (Bits) 40 Gbps Port Width (Bits) Description Output rs1_ones_errors 7 9 This output signals the number of ones errors corrected by the first RS decoder. Output rs1_zeros_errors 7 9 This output signals the number of zeros errors corrected by the first RS decoder. Output rs2_ones_errors 7 9 This output signals the number of ones errors corrected by the second RS decoder. Output rs2_zeros_errors 7 9 This output signals the number of zeros errors corrected by the second RS decoder. Output bch1_ones_errors 7 9 This output signals the number of ones errors corrected by the first BCH decoder. Output bch1_zeros_errors 7 9 This output signals the number of zeros errors corrected by the first BCH decoder. Output bch2_ones_errors 7 9 This output signals the number of ones errors corrected by the second BCH decoder. Output bch2_zeros_errors 7 9 This output signals the number of zeros errors corrected by the second BCH decoder. 1 This output signals the number of uncorrectable codes from the first RS decoder. This is a synchronous signal and is active high. 1 This output signals the number of correctable codes from the first RS decoder. This is a synchronous signal and is active high. 1 This output signals the number of uncorrectable codes from the second RS decoder. This is a synchronous signal and is active high. 1 This output signals the number of correctable codes from the second RS decoder. This is a synchronous signal and is active high. 2 This output signals the number of uncorrectable codes from the first BCH decoder. This is a synchronous signal and is active high. 2 This output signals the number of correctable codes from the first BCH decoder. This is a synchronous signal and is active high. Output Output Output Output Output Output rs1_uncorrectable_code_ errors rs1_correctable_code_ errors rs2_uncorrectable_code_ errors rs2_correctable_code_ errors bch1_uncorrectable_code_errors bch1_correctable_code_ errors G.975 I.4 EFEC IP Core 1 1 1 1 1 1 February 2012 Altera Corporation Additional Information Page 7 Table 6. Decoder I/O Port Listing (Part 4 of 4) I/O 10 Gbps Port Width (Bits) Port Output bch2_uncorrectable_code_ errors 1 40 Gbps Port Width (Bits) Description 2 This output signals the number of uncorrectable codes from the second BCH decoder. This is a synchronous signal and is active high. Output bch2_correctable_code_ errors 1 2 This output signals the number of correctable codes from the second BCH decoder. This is a synchronous signal and is active high. Output data_out 64 256 Output data port. Additional Information f Recommendation G.975: Forward Error Correction for High Bit-Rate DWDM Submarine Systems available on the ITU website (www.itu.int) has complete details on G.975 I.4 FEC. Document Revision History Table 7 shows the revision history for this document. Table 7. Document Revision History Date Version February 2012 February 2012 1.0 Altera Corporation Changes Initial release. G.975 I.4 EFEC IP Core Page 8 G.975 I.4 EFEC IP Core Additional Information February 2012 Altera Corporation