Understanding Timing in Altera CPLDs AN-629-1.0 Application Note This application note describes external and internal timing parameters, and illustrates the timing models for MAX® II and MAX V devices. Altera® devices provide predictable device performance that is consistent from simulation-to-application. Before programming a device, you can determine the worst-case timing delays for your design. To approximate propagation delays, you can use: 1 ■ Quartus® II TimeQuest Timing Analyzer ■ Timing models provided in this application note ■ Timing parameters listed in the DC and Switching Characteristics chapter in the MAX II Device Handbook and DC and Switching Characteristics for MAX V Devices chapter in the MAX V Device Handbook. For the most precise timing results, you use the Quartus II TimeQuest Timing Analyzer. For more information, refer to “Timing Model Versus the Quartus II TimeQuest Timing Analyzer” on page 9. f Familiarity with device architecture and characteristics is assumed. For a complete description of the architecture and the specific values of timing parameters listed in this application note, refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook and DC and Switching Characteristics for MAX V Devices chapter in the MAX V Device Handbook. This application note contains the following sections: 101 Innovation Drive San Jose, CA 95134 www.altera.com December 2010 ■ “External Timing Parameters” on page 2 ■ “Internal Timing Parameters” on page 2 ■ “Internal Timing Parameters for User Flash Memory in MAX II and MAX V Devices” on page 4 ■ “Timing Models” on page 5 ■ “Calculating Timing Delays” on page 5 ■ “Programmable Input Delay” on page 8 ■ “Timing Model Versus the Quartus II TimeQuest Timing Analyzer” on page 9 © 2010 Altera Corporation. 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Altera Corporation Subscribe Page 2 External Timing Parameters External Timing Parameters External timing parameters represent actual pin-to-pin timing characteristics. Each external timing parameter consists of a combination of internal timing parameters. f You can find the values of the external timing parameters in the DC and Switching Characteristics chapter in the MAX II Device Handbook and DC and Switching Characteristics for MAX V Devices chapter in the MAX V Device Handbook. These external timing parameters are worst-case values, derived from extensive performance measurements and ensured by testing. Table 1 lists external timing parameters for MAX II and MAX V devices. Table 1. External Timing Parameters for MAX II and MAX V Devices Parameter Description tPD1 Pin-to-pin delay for the worst case I/O placement with a diagonal path across the device with combinational logic implemented in a single look-up table (LUT) in a logic array block (LAB) adjacent to the output pin. Use the fast I/O connection from the adjacent logic element (LE) to the output pin. tPD2 Pin-to-pin delay for the best case I/O placement with combinational logic (2-input AND gate) implemented in a single edge LE adjacent to the input pin. The longest pin path of the two inputs is shown. Use the fast I/O connection from the adjacent LE to the output pin. tCLR Time to clear register delay. The time required for a low signal to appear at the external output and measured from the input transition. tSU Global clock setup time. The time that data must be present at the input pin before the global (synchronous) clock signal is asserted at the clock pin. tH Global clock hold time. The time that data must be present at the input pin after the global clock signal is asserted at the clock pin. tCO Global clock to output delay. The time required to obtain a valid output after the global clock is asserted at the clock pin. tCNT Minimum global clock period. The minimum period maintained by a globally clocked counter. Internal Timing Parameters Within a device, the timing delays contributed by individual architectural elements are called internal timing parameters, which cannot be measured explicitly. All internal parameters are shown in italic type. Table 2 lists the internal timing microparameters for MAX II and MAX V devices. Table 2. Internal Timing Microparameters for MAX II and MAX V Devices (Part 1 of 2) Parameter Description tLUT LE combinational LUT delay for data-in to data-out. tCOMB Combinational path delay. The delay from the time when a combinational logic signal from the LUT bypasses the LE register to the time it becomes available at the LE output. tCLR LE register clear delay. The delay from the assertion of the register’s asynchronous clear input to the time the register output stabilizes at logical low. tPRE LE register preset delay. The delay from the assertion of the register’s asynchronous preset input to the time the register output stabilizes at logical high. Understanding Timing in Altera CPLDs December 2010 Altera Corporation Internal Timing Parameters Page 3 Table 2. Internal Timing Microparameters for MAX II and MAX V Devices (Part 2 of 2) Parameter Description tSU LE register setup time before clock. The time required for a signal to be stable at the register's data and enable inputs before the register clock rising edge to ensure that the register correctly stores the input data. tH LE register hold time after clock. The time required for a signal to be stable at the register's data and enable inputs after the register clock's rising edge to ensure that the register correctly stores the input data. tCO LE register clock-to-output delay. The delay from the rising edge of the register's clock to the time the data appears at the register output. tC Register control delay. The time required for a signal to be routed to the clock, preset, or clear input of an LE register. tFASTIO Combinational output delay. tFASTIO is the time required for a combinational signal from the LE adjacent to the I/O block using the fast I/O connection. tIN I/O input pad and buffer delay. The tIN applies to I/O pins used as inputs. tGLOB tGLOB applies to GCLK pins when used for global signals. tGLOB is the delay required for a global signal to be routed from the GCLK pins to the LAB column clocks through the global clock network. tIOE Internal generated output enable delay. The delay from an internally generated signal on the interconnect to the output enable of the tri-state buffer. tDL Input routing delay. The delay incurred from the row I/O pin used as input to the LE adjacent to it. tIODR Output data delay for the row interconnect. The delay incurred by the signals routed from an interconnect to an I/O cell. tOD Output delay buffer and pad delay. For more information about delay adders associated with different I/O standards, drive strengths, and slew rates, refer to the Timing Model and Specifications section in the DC and Switching Characteristics chapter in the MAX II Device Handbook and the DC and Switching Characteristics for MAX V Devices chapter in the MAX V Device Handbook. tXZ Output buffer disable delay. The delay required for high impedance to appear at the output pin after the output buffer’s enable control is disabled. For more information about delay adders associated with different I/O standards, drive strengths, and slew rates, refer to the Timing Model and Specifications section in the DC and Switching Characteristics chapter in the MAX II Device Handbook and the DC and Switching Characteristics for MAX V Devices chapter in the MAX V Device Handbook. tZX Output buffer enable delay required for the output signal to appear at the output pin after the tri-state buffer's enable control is enabled. For more information about delay adders associated with different I/O standards, drive strengths, and slew rates, refer to the Timing Model and Specifications section in the DC and Switching Characteristics chapter in the MAX II Device Handbook and the DC and Switching Characteristics for MAX V Devices chapter in the MAX V Device Handbook. tC4 Delay for a column interconnect with average loading. tC4 covers a distance of four LAB rows. tR4 Delay for a row interconnect with average loading. tR4 covers a distance of four LAB columns. tLOCAL Local interconnect delay. December 2010 Altera Corporation Understanding Timing in Altera CPLDs Page 4 Internal Timing Parameters for User Flash Memory in MAX II and MAX V Devices Internal Timing Parameters for User Flash Memory in MAX II and MAX V Devices Timing parameters for user flash memory (UFM) in MAX II and MAX V devices are the timing delays contributed by the UFM architectural elements, which cannot be measured explicitly. All timing parameters are shown in italic type. Table 3 lists the timing microparameters for UFM in MAX II and MAX V devices. Table 3. Internal Timing Microparameters for UFM in MAX II and MAX V Devices Parameter Description tASU Address register shift signal setup to the address register clock. tAH Address register shift signal hold from the address register clock. tADS Address register data in setup to the address register clock. tADH Address register data in hold from the address register clock. tDSS Data register shift signal setup to the data register clock. tDSH Data register shift signal hold from the data register clock. tDDS Data register data in setup to the data register clock. tDDH Data register data in hold from the data register clock. tDCO Delay incurred from the data register clock to the data register output when shifting the data out. tDP PROGRAM signal to the data clock hold time. tPB Maximum delay between the PROGRAM rising edge and the UFM BUSY signal rising edge. tBP Minimum delay allowed from the UFM BUSY signal going low to the PROGRAM signal going low. tPPMX Maximum length of the busy pulse during a program. tAE Minimum ERASE signal to the address clock hold time. tEB Maximum delay between the ERASE rising edge and the UFM BUSY signal rising edge. tBE Minimum delay allowed from the UFM BUSY signal going low to the ERASE signal going low. tEPMX Maximum length of the busy pulse during an erase. tRA Maximum read-access time. The delay incurred between the DRSHFT signal going low to the first bit of data observed at the data register output. tOE Delay from the OSC_ENA signal reaching UFM to the rising clock of OSC leaving UFM. tOSCS Maximum delay between the OSC_ENA rising edge and the ERASE/PROGRAM signal rising edge. tOSCH Minimum delay allowed from the ERASE/PROGRAM signal going low to the OSC_ENA signal going low. Understanding Timing in Altera CPLDs December 2010 Altera Corporation Timing Models Page 5 Timing Models Timing models are simplified block diagrams that illustrate delays through Altera devices. Logic can be implemented on different paths. You can trace the actual paths used in your design by examining the equations listed in the Quartus II Text-Format Report File (.rpt) for the project. You can then add up the appropriate internal timing parameters to estimate the delays through the device. MAX II and MAX V device architecture has a globally routed clock. The MultiTrack interconnect ensures predictable performance, accurate simulation, and accurate timing analysis across all MAX II and MAX V device densities and speed grades. Figure 1 shows the timing model for MAX II and MAX V devices. Figure 1. Timing Model for MAX II and MAX V Devices Output and Output Enable Data Delay t R4 tIODR tIOE Data-In/LUT Chain User Flash Memory I/O Pin Input Routing Delay tDL t LOCAL I/O Input Delay t IN Logic Element LUT Delay t LUT Register Control Delay tC tCOMB t FASTIO tCO tSU tH tPRE tCLR Global Input Delay Output Delay t OD t XZ t ZX I/O Pin From Adjacent LE t GLOB INPUT Output Routing Delay t C4 Combinational Path Delay To Adjacent LE Register Delays Data-Out Calculating Timing Delays You can calculate approximate pin-to-pin timing delays for MAX II and MAX V devices with the timing model shown in Figure 1. f For more information, refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook and the DC and Switching Characteristics for MAX V Devices chapter in the MAX V Device Handbook. Each external timing parameter is calculated from a combination of internal timing parameters. Figure 2 through Figure 6 show the external timing parameters for MAX II and MAX V devices. To calculate the delay for a signal that follows a different path through MAX II and MAX V devices, refer to the timing model to determine which internal timing parameters to add together. December 2010 Altera Corporation Understanding Timing in Altera CPLDs Page 6 Calculating Timing Delays 1 For the most precise timing results, use the Quartus II TimeQuest Timing Analyzer, which accounts for the effects of secondary factors such as placement and fan-out. Figure 2. External Timing Parameter (tPD1 ) (Note 1) MAX II/ MAX V Device TRI LUT Note to Figure 2: (1) tPD1 = tIN + N x t R4/4 + M x tC4/4 + tLUT + tCOMB + tFASTIO + (tOD + tOD ) tOD is the adder delay (refer to Figure 2) for the tOD microparameter when using an I/O standard other than 3.3-V LVTTL with 16 mA current strength. f For more information about adder delay values, refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook and the DC and Switching Characteristics for MAX V Devices chapter in the MAX V Device Handbook. Table 4 lists the numbers of LABs according to device density. Table 4. Numbers of LABs According to Device Density Device Family MAX II MAX V Device Density N LAB Rows M LAB Columns EPM240 4 6 EPM570 7 12 EPM1270 10 16 EPM2210 13 20 5M40Z 4 6 5M80Z 4 6 5M160Z 4 6 5M240Z (1) 4 6 5M240Z (2) 7 12 5M570Z 7 12 5M1270Z (3) 10 16 5M1270Z (4) 13 20 5M2210Z 13 20 Notes to Table 4: (1) Not applicable to the T144 package of the 5M240Z device. (2) Only applicable to the T144 package of the 5M240Z device. (3) Not applicable to the F324 package of the 5M1270Z device. (4) Only applicable to the F324 package of the 5M1270Z device. Understanding Timing in Altera CPLDs December 2010 Altera Corporation Calculating Timing Delays Page 7 The following is an external timing example: tPD1 for the 5M240Z device using an I/O standard of 3.3-V LVTTL fast slew rate with a drive strength of 16 mA: tPD1 = tIN + 4 × tR4/4 + 6 x tC4/4 + tLUT + tCOMB + tFASTIO + tOD……(a) tPD1 for the 5M240Z device using an I/O standard of 2.5-V LVTTL fast slew rate with a drive strength of 7 mA: tPD1 = (a) + (tOD of 2.5-V LVTTL fast slew 7 mA) Figure 3. External Timing Parameter (tPD2 ) (Note 1) TRI MAX II/ MAX V Device LUT Note to Figure 3: (1) tPD2 = tIN + tDL + tLUT + tCOMB + tFASTIO + (tOD + tOD) Figure 4. External Timing Parameter (tCO) (Note 1), (2) LE Register Notes to Figure 4: (1) tCO = tGLOB + tC + tCO + (N x tR4/4 + M x tC4/4) + (tIODC or tIODR) + (tOD + tOD) (2) The constants N and M are subject to change according to the position of the LAB in the entire device. Figure 5. LE Register Clear and Preset Time (tCLR) (Note 1) LE Register Note to Figure 5: (1) tCLR = tGLOB + tC + tCLR + (N x tR4/4 + M x tC4/4) + (tIODC or tIODR) + (tOD + tOD) Figure 6. LE Register Clear and Preset Time (tPRE) (Note 1) LE Register Note to Figure 6: (1) tPRE = tGLOB + t LOCAL + tC + tPRE + (N x tR4/4 + M x tC4/4) + (tIODC or tIODR) + (tOD + tOD) December 2010 Altera Corporation Understanding Timing in Altera CPLDs Page 8 Programmable Input Delay Setup and Hold Time from an I/O Data and Clock Input The Quartus II software might insert additional routing delays from the input pin to the register input to ensure a zero hold time for the LE register. Altera recommends using the Quartus II TimeQuest Timing Analyzer to obtain the setup and hold time. Figure 7 and Figure 8 show the setup and hold time for MAX II and MAX V devices. Figure 7. Setup and Hold Time (tSU) (Note 1) Combinational Logic LE Register Note to Figure 7: (1) tSU = (tIN + N x tR4/4 + M x tC4/4 + tLUT) - (tGLOB + tC) + tSU Figure 8. Setup and Hold Time (tH) (Note 1) Combinational Logic LE Register Note to Figure 8: (1) tH = (tGLOB + tC) - (tIN + N x tR4/4 + M x tC4/4 + tLUT) + tH 1 For Figure 4 through Figure 8, the constants N and M are subject to change according to the position of the LAB in the entire device for combinational logic implementation. Programmable Input Delay To guarantee a zero hold time, the programmable input delay provides an option to add a delay to the input pin. You can set this option in the Assignment Editor (Assignments menu) on a pin-by-pin basis. To turn on the input delay for the selected input pin in the Quartus II software, perform the following steps: 1. Select the input pin name in the design file. 2. Right-click and select Locate in the Assignment Editor. 3. Double-click the cell under Assignment Name and select Input Delay from Pin to Internal Cells from the pull-down list. 4. Double-click the Value cell to the right of the assignment name just made and enter 1. 5. On the File menu, click Save. Understanding Timing in Altera CPLDs December 2010 Altera Corporation Timing Model Versus the Quartus II TimeQuest Timing Analyzer Page 9 Timing Model Versus the Quartus II TimeQuest Timing Analyzer While hand calculations based on the timing model can provide you with an estimate of your design performance, Altera recommends using the Quartus II TimeQuest Timing Analyzer to obtain the most accurate information on design performance because it takes into account secondary factors that influence the routing microparameters such as: ■ Fan-out for each signal in the delay path ■ Positions of other loads relative to the signal source and destination ■ Distance between the signal source and destination ■ Various interconnect lengths where some interconnects are truncated at the edge of the device Document Revision History Table 5 lists the revision history for this application note. Table 5. Document Revision History Date Version December 2010 December 2010 1.0 Altera Corporation Changes Initial release. Understanding Timing in Altera CPLDs Page 10 Understanding Timing in Altera CPLDs Document Revision History December 2010 Altera Corporation