DC and Switching Characteristics

4. DC and Switching
Characteristics
C51004-1.7
Operating
Conditions
Cyclone® devices are offered in both commercial, industrial, and
extended temperature grades. However, industrial-grade and extendedtemperature-grade devices may have limited speed-grade availability.
Tables 4–1 through 4–16 provide information on absolute maximum
ratings, recommended operating conditions, DC operating conditions,
and capacitance for Cyclone devices.
Table 4–1. Cyclone Device Absolute Maximum Ratings
Symbol
VCCINT
Parameter
Notes (1), (2)
Conditions
With respect to ground (3)
Supply voltage
VCCIO
With respect to ground (3)
Minimum
Maximum
Unit
–0.5
2.4
V
–0.5
4.6
V
VCCA
Supply voltage
–0.5
2.4
V
VI
DC input voltage
–0.5
4.6
V
IOUT
DC output current, per pin
–25
25
mA
TSTG
Storage temperature
No bias
–65
150
°C
TAMB
Ambient temperature
Under bias
–65
135
°C
TJ
Junction temperature
BGA packages under bias
—
135
°C
Table 4–2. Cyclone Device Recommended Operating Conditions (Part 1 of 2)
Conditions
Minimum
Maximum
Unit
VCCINT
Symbol
Supply voltage for internal logic
and input buffers
(4)
1.425
1.575
V
VCCIO
Supply voltage for output buffers,
3.3-V operation
(4)
3.00
3.60
V
Supply voltage for output buffers,
2.5-V operation
(4)
2.375
2.625
V
Supply voltage for output buffers,
1.8-V operation
(4)
1.71
1.89
V
Supply voltage for output buffers,
1.5-V operation
(4)
1.4
1.6
V
(3), (5)
–0.5
4.1
V
VI
Parameter
Input voltage
Altera Corporation
May 2008
4–1
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–2. Cyclone Device Recommended Operating Conditions (Part 2 of 2)
Symbol
Parameter
Conditions
VO
Output voltage
TJ
Operating junction temperature
Minimum
Maximum
Unit
0
VCCIO
V
0
85
° C
For industrial use
–40
100
° C
For extendedtemperature use
–40
125
° C
For commercial
use
Table 4–3. Cyclone Device DC Operating Conditions
Symbol
Parameter
Note (6)
Conditions
Minimum Typical Maximum Unit
II
Input pin leakage current
VI = VC C I O m a x to 0 V (8)
–10
—
10
μA
IOZ
Tri-stated I/O pin leakage
current
VO = VC C I O m a x to 0 V (8)
–10
—
10
μA
ICC0
VCC supply current (standby)
(All M4K blocks in power-down
mode) (7)
EP1C3
—
4
—
mA
EP1C4
—
6
—
mA
EP1C6
—
6
—
mA
EP1C12
—
8
—
mA
EP1C20
—
12
—
mA
RCONF (9) Value of I/O pin pull-up resistor VI = 0 V; VCCI0 = 3.3 V
before and during configuration
VI = 0 V; VCCI0 = 2.5 V
15
25
50
kΩ
20
45
70
kΩ
VI = 0 V; VCCI0 = 1.8 V
30
65
100
kΩ
VI = 0 V; VCCI0 = 1.5 V
50
100
150
kΩ
—
1
2
kΩ
Recommended value of I/O pin
external pull-down resistor
before and during configuration
—
Table 4–4. LVTTL Specifications
Conditions
Minimum
Maximum
Unit
VCCIO
Symbol
Output supply voltage
—
3.0
3.6
V
VIH
High-level input voltage
—
1.7
4.1
V
VIL
Low-level input voltage
—
–0.5
0.7
V
VOH
High-level output voltage
IOH = –4 to –24 mA (11)
2.4
—
V
VOL
Low-level output voltage
IOL = 4 to 24 mA (11)
—
0.45
V
4–2
Preliminary
Parameter
Altera Corporation
May 2008
Operating Conditions
Table 4–5. LVCMOS Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCIO
Output supply voltage
—
3.0
3.6
V
VIH
High-level input voltage
—
1.7
4.1
V
VIL
Low-level input voltage
VOH
High-level output voltage
VCCIO = 3.0,
IOH = –0.1 mA
VOL
Low-level output voltage
VCCIO = 3.0,
IOL = 0.1 mA
—
–0.5
0.7
V
VCCIO – 0.2
—
V
—
0.2
V
Conditions
Minimum
Maximum
Unit
Table 4–6. 2.5-V I/O Specifications
Symbol
Parameter
VCCIO
Output supply voltage
—
2.375
2.625
V
VIH
High-level input voltage
—
1.7
4.1
V
VIL
Low-level input voltage
—
–0.5
0.7
V
VOH
High-level output voltage
IOH = –0.1 mA
2.1
—
V
IOH = –1 mA
2.0
—
V
IOH = –2 to –16 mA (11)
1.7
—
V
IOL = 0.1 mA
—
0.2
V
IOH = 1 mA
—
0.4
V
IOH = 2 to 16 mA (11)
—
0.7
V
Minimum
Maximum
Unit
VOL
Low-level output voltage
Table 4–7. 1.8-V I/O Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
—
1.65
1.95
V
VI H
High-level input voltage
—
0.65 ×
VCCIO
2.25 (12)
V
VIL
Low-level input voltage
—
–0.3
0.35 ×
VCCIO
V
VOH
High-level output voltage
IOH = –2 to –8 mA (11)
VCCIO – 0.45
—
V
VOL
Low-level output voltage
IOL = 2 to 8 mA (11)
—
0.45
V
Altera Corporation
May 2008
4–3
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–8. 1.5-V I/O Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCIO
Output supply voltage
—
1.4
1.6
V
VI H
High-level input voltage
—
0.65 ×
VCCIO
VCCIO + 0.3
(12)
V
VIL
Low-level input voltage
—
–0.3
0.35 ×
VCCIO
V
VOH
High-level output voltage
IOH = –2 mA (11)
0.75 ×
VCCIO
—
V
VOL
Low-level output voltage
IOL = 2 mA (11)
—
0.25 ×
VCCIO
V
Table 4–9. 2.5-V LVDS I/O Specifications
Symbol
Parameter
Note (13)
Conditions
Minimum
Typical
Maximum
Unit
—
2.375
2.5
2.625
V
VCCIO
I/O supply voltage
VOD
Differential output voltage
RL = 100 Ω
250
—
550
mV
Δ VOD
Change in VOD between
high and low
RL = 100 Ω
—
—
50
mV
VOS
Output offset voltage
RL = 100 Ω
1.125
1.25
1.375
V
Δ VOS
Change in VOS between
high and low
RL = 100 Ω
—
—
50
mV
VTH
Differential input threshold
VCM = 1.2 V
–100
—
100
mV
VIN
Receiver input voltage
range
—
0.0
—
2.4
V
RL
Receiver differential input
resistor
—
90
100
110
Ω
Conditions
Minimum
Typical
Maximum
Unit
Table 4–10. 3.3-V PCI Specifications (Part 1 of 2)
Symbol
Parameter
VCCIO
Output supply voltage
—
3.0
3.3
3.6
V
VIH
High-level input voltage
—
0.5 ×
VCCIO
—
VCCIO +
0.5
V
VIL
Low-level input voltage
—
–0.5
—
0.3 ×
VCCIO
V
4–4
Preliminary
Altera Corporation
May 2008
Operating Conditions
Table 4–10. 3.3-V PCI Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VOH
High-level output voltage
IOUT = –500 μA
0.9 ×
VCCIO
—
—
V
VOL
Low-level output voltage
IOUT = 1,500 μA
—
—
0.1 ×
VCCIO
V
Table 4–11. SSTL-2 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
—
2.375
2.5
2.625
V
VTT
Termination voltage
—
VR E F – 0.04
VR E F
VR E F + 0.04
V
VREF
Reference voltage
—
1.15
1.25
1.35
V
VIH
High-level input voltage
—
VR E F + 0.18
—
3.0
V
VIL
Low-level input voltage
—
–0.3
—
VR E F – 0.18
V
VOH
High-level output voltage
IOH = –8.1 mA
(11)
VTT + 0.57
—
—
V
VOL
Low-level output voltage
IOL = 8.1 mA (11)
—
—
VT T – 0.57
V
Conditions
Minimum
Typical
Maximum
Unit
Table 4–12. SSTL-2 Class II Specifications
Symbol
Parameter
VCCIO
Output supply voltage
—
2.3
2.5
2.7
V
VTT
Termination voltage
—
VR E F – 0.04
VR E F
VR E F + 0.04
V
VREF
Reference voltage
—
1.15
1.25
1.35
V
VIH
High-level input voltage
—
VR E F + 0.18
—
VCCIO + 0.3
V
VIL
Low-level input voltage
—
–0.3
—
VR E F – 0.18
V
VOH
High-level output voltage
IOH = –16.4 mA
(11)
VTT + 0.76
—
—
V
VOL
Low-level output voltage
IOL = 16.4 mA
(11)
—
—
VT T – 0.76
V
Minimum
Typical
Maximum
Unit
Table 4–13. SSTL-3 Class I Specifications (Part 1 of 2)
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
—
3.0
3.3
3.6
V
VTT
Termination voltage
—
VR E F – 0.05
VR E F
VR E F + 0.05
V
Altera Corporation
May 2008
4–5
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–13. SSTL-3 Class I Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VREF
Reference voltage
—
1.3
1.5
1.7
V
VIH
High-level input voltage
—
VR E F + 0.2
—
VCCIO + 0.3
V
VIL
Low-level input voltage
—
–0.3
—
VR E F – 0.2
V
VOH
High-level output voltage
IOH = –8 mA (11)
VTT + 0.6
—
—
V
VOL
Low-level output voltage
IOL = 8 mA (11)
—
—
VT T – 0.6
V
Conditions
Minimum
Typical
Maximum
Unit
Table 4–14. SSTL-3 Class II Specifications
Symbol
Parameter
VCCIO
Output supply voltage
—
3.0
3.3
3.6
V
VTT
Termination voltage
—
VR E F – 0.05
VR E F
VR E F + 0.05
V
VREF
Reference voltage
—
1.3
1.5
1.7
V
VIH
High-level input voltage
—
VR E F + 0.2
—
VCCIO + 0.3
V
VIL
Low-level input voltage
—
–0.3
—
VR E F – 0.2
V
VOH
High-level output voltage
IOH = –16 mA
(11)
VT T + 0.8
—
—
V
VOL
Low-level output voltage
IOL = 16 mA (11)
—
—
VTT – 0.8
V
Table 4–15. Bus Hold Parameters
VC C I O Level
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Min
Max
Low sustaining
current
VIN > VIL
(maximum)
—
—
30
—
50
—
70
—
μA
High sustaining VIN < VIH
current
(minimum)
—
—
–30
—
–50
—
–70
—
μA
Low overdrive
current
0 V < VIN <
VCCIO
—
—
—
200
—
300
—
500
μA
High overdrive
current
0 V < VIN <
VCCIO
—
—
—
–200
—
–300
—
–500
μA
4–6
Preliminary
1.5 V
1.8 V
2.5 V
Unit
3.3 V
Altera Corporation
May 2008
Operating Conditions
Table 4–16. Cyclone Device Capacitance
Symbol
Note (14)
Parameter
Typical
Unit
CIO
Input capacitance for user I/O pin
4.0
pF
CLVDS
Input capacitance for dual-purpose LVDS/user I/O pin
4.7
pF
CVREF
Input capacitance for dual-purpose VR E F /user I/O pin.
12.0
pF
CDPCLK
Input capacitance for dual-purpose DPCLK/user I/O pin.
4.4
pF
CCLK
Input capacitance for CLK pin.
4.7
pF
Notes to Tables 4–1 through 4–16:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
Refer to the Operating Requirements for Altera Devices Data Sheet.
Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
Typical values are for TA = 25° C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
VI = ground, no load, no toggling inputs.
This value is specified for normal device operation. The value may vary during power-up. This applies for all
VCCIO settings (3.3, 2.5, 1.8, and 1.5 V).
RCONF is the measured value of internal pull-up resistance when the I/O pin is tied directly to GND. RCONF value
will be lower if an external source drives the pin higher than VC C I O .
Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
Drive strength is programmable according to values in Cyclone Architecture chapter in the Cyclone Device Handbook.
Overdrive is possible when a 1.5 V or 1.8 V and a 2.5 V or 3.3 V input signal feeds an input pin. Turn on “Allow
voltage overdrive” for LVTTL/LVCMOS input pins in the Assignments > Device > Device and Pin Options > Pin
Placement tab when a device has this I/O combination. However, higher leakage current is expected.
The Cyclone LVDS interface requires a resistor network outside of the transmitter channels.
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5 pF.
Altera Corporation
May 2008
4–7
Preliminary
Cyclone Device Handbook, Volume 1
Power
Consumption
Designers can use the Altera web Early Power Estimator to estimate the
device power.
Cyclone devices require a certain amount of power-up current to
successfully power up because of the nature of the leading-edge process
on which they are fabricated. Table 4–17 shows the maximum power-up
current required to power up a Cyclone device.
Table 4–17. Cyclone Maximum Power-Up Current (ICCINT) Requirements (In-Rush Current)
Device
Commercial Specification
Industrial Specification
Unit
EP1C3
150
180
mA
EP1C4
150
180
mA
EP1C6
175
210
mA
EP1C12
300
360
mA
EP1C20
500
600
mA
Notes to Table 4–17:
(1)
(2)
(3)
The Cyclone devices (except for the EP1C20 device) meet the power up specification for Mini PCI.
The lot codes 9G0082 to 9G2999, or 9G3109 and later comply to the specifications in Table 4–17 and meet the Mini
PCI specification. Lot codes appear at the top of the device.
The lot codes 9H0004 to 9H29999, or 9H3014 and later comply to the specifications in this table and meet the Mini
PCI specification. Lot codes appear at the top of the device.
Designers should select power supplies and regulators that can supply
this amount of current when designing with Cyclone devices. This
specification is for commercial operating conditions. Measurements were
performed with an isolated Cyclone device on the board. Decoupling
capacitors were not used in this measurement. To factor in the current for
decoupling capacitors, sum up the current for each capacitor using the
following equation:
I = C (dV/dt)
The exact amount of current that is consumed varies according to the
process, temperature, and power ramp rate. If the power supply or
regulator can supply more current than required, the Cyclone device may
consume more current than the maximum current specified in Table 4–17.
However, the device does not require any more current to successfully
power up than what is listed in Table 4–17.
The duration of the ICCINT power-up requirement depends on the VCCINT
voltage supply rise time. The power-up current consumption drops when
the VCCINT supply reaches approximately 0.75 V. For example, if the
VCCINT rise time has a linear rise of 15 ms, the current consumption spike
drops by 7.5 ms.
4–8
Preliminary
Altera Corporation
May 2008
Timing Model
Typically, the user-mode current during device operation is lower than
the power-up current in Table 4–17. Altera recommends using the
Cyclone Power Calculator, available on the Altera web site, to estimate
the user-mode ICCINT consumption and then select power supplies or
regulators based on the higher value.
Timing Model
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Cyclone device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The
Quartus® II software issues an informational message during the design
compilation if the timing models are preliminary. Table 4–18 shows the
status of the Cyclone device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 4–18. Cyclone Device Timing Model Status
Altera Corporation
May 2008
Device
Preliminary
Final
EP1C3
—
v
EP1C4
—
v
EP1C6
—
v
EP1C12
—
v
EP1C20
—
v
4–9
Preliminary
Cyclone Device Handbook, Volume 1
Performance
The maximum internal logic array clock tree frequency is limited to the
specifications shown in Table 4–19.
Table 4–19. Clock Tree Maximum Performance Specification
-6 Speed Grade
Parameter
Clock tree
fM A X
-7 Speed Grade
-8 Speed Grade
Definition
Units
Maximum frequency
that the clock tree
can support for
clocking registered
logic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
—
405
—
—
320
—
—
275
MHz
Table 4–20 shows the Cyclone device performance for some common
designs. All performance values were obtained with the Quartus II
software compilation of library of parameterized modules (LPM)
functions or megafunctions. These performance values are based on
EP1C6 devices in 144-pin TQFP packages.
Table 4–20. Cyclone Device Performance
Resources Used
Resource
Used
LE
4–10
Preliminary
Design Size and
Function
LEs
M4K
Memory
Bits
Mode
Performance
M4K
-6 Speed -7 Speed -8 Speed
Memory
Grade
Grade
Grade
Blocks
(MHz)
(MHz)
(MHz)
16-to-1
multiplexer
—
21
—
—
405.00
320.00
275.00
32-to-1
multiplexer
—
44
—
—
317.36
284.98
260.15
16-bit counter
—
16
—
—
405.00
320.00
275.00
64-bit counter (1)
—
66
—
—
208.99
181.98
160.75
Altera Corporation
May 2008
Timing Model
Table 4–20. Cyclone Device Performance
Resources Used
Resource
Used
M4K
memory
block
Design Size and
Function
Mode
RAM 128 × 36 bit
Performance
LEs
M4K
Memory
Bits
Single port
—
4,608
1
256.00
222.67
197.01
RAM 128 × 36 bit
Simple
dual-port
mode
—
4,608
1
255.95
222.67
196.97
RAM 256 × 18 bit
True dualport mode
—
4,608
1
255.95
222.67
196.97
FIFO 128 × 36 bit
—
40
4,608
1
256.02
222.67
197.01
11
4,536
1
255.95
222.67
196.97
Shift register
9 × 4 × 128
Shift
register
M4K
-6 Speed -7 Speed -8 Speed
Memory
Grade
Grade
Grade
Blocks
(MHz)
(MHz)
(MHz)
Note to Table 4–20:
(1)
The performance numbers for this function are from an EP1C6 device in a 240-pin PQFP package.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 4–21 through 4–24 describe the
Cyclone device internal timing microparameters for LEs, IOEs, M4K
memory structures, and MultiTrack interconnects.
Table 4–21. LE Internal Timing Microparameter Descriptions
Symbol
Altera Corporation
May 2008
Parameter
tSU
LE register setup time before clock
tH
LE register hold time after clock
tCO
LE register clock-to-output delay
tLUT
LE combinatorial LUT delay for data-in to data-out
tCLR
Minimum clear pulse width
tPRE
Minimum preset pulse width
tCLKHL
Minimum clock high or low time
4–11
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–22. IOE Internal Timing Microparameter Descriptions
Symbol
Parameter
tSU
IOE input and output register setup time before clock
tH
IOE input and output register hold time after clock
tCO
IOE input and output register clock-to-output delay
tPIN2COMBOUT_R
Row input pin to IOE combinatorial output
tPIN2COMBOUT_C
Column input pin to IOE combinatorial output
tCOMBIN2PIN_R
Row IOE data input to combinatorial output pin
tCOMBIN2PIN_C
Column IOE data input to combinatorial output pin
tCLR
Minimum clear pulse width
tPRE
Minimum preset pulse width
tCLKHL
Minimum clock high or low time
Table 4–23. M4K Block Internal Timing Microparameter Descriptions
Symbol
4–12
Preliminary
Parameter
tM4KRC
Synchronous read cycle time
tM4KWC
Synchronous write cycle time
tM4KWERESU
Write or read enable setup time before clock
tM4KWEREH
Write or read enable hold time after clock
tM4KBESU
Byte enable setup time before clock
tM4KBEH
Byte enable hold time after clock
tM4KDATAASU
A port data setup time before clock
tM4KDATAAH
A port data hold time after clock
tM4KADDRASU
A port address setup time before clock
tM4KADDRAH
A port address hold time after clock
tM4KDATABSU
B port data setup time before clock
tM4KDATABH
B port data hold time after clock
tM4KADDRBSU
B port address setup time before clock
tM4KADDRBH
B port address hold time after clock
tM4KDATACO1
Clock-to-output delay when using output registers
tM4KDATACO2
Clock-to-output delay without output registers
tM4KCLKHL
Minimum clock high or low time
tM4KCLR
Minimum clear pulse width
Altera Corporation
May 2008
Timing Model
Table 4–24. Routing Delay Internal Timing Microparameter Descriptions
Symbol
Parameter
tR4
Delay for an R4 line with average loading; covers a distance
of four LAB columns
tC4
Delay for an C4 line with average loading; covers a distance
of four LAB rows
tLOCAL
Local interconnect delay
Figure 4–1 shows the memory waveforms for the M4K timing parameters
shown in Table 4–23.
Figure 4–1. Dual-Port RAM Timing Microparameter Waveform
wrclock
tWEREH
tWERESU
wren
tWADDRH
tWADDRSU
wraddress
an-1
an
a0
a1
a2
a3
a4
a5
a6
din4
din5
din6
tDATAH
data-in
din-1
din
tDATASU
rdclock
tWEREH
tWERESU
rden
tRC
bn
rdaddress
b1
b0
b2
b3
tDATACO1
reg_data-out
doutn-2
doutn-1
doutn
dout0
tDATACO2
unreg_data-out
Altera Corporation
May 2008
doutn-1
doutn
dout0
4–13
Preliminary
Cyclone Device Handbook, Volume 1
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 4–25 through 4–28 show the
internal timing microparameters for LEs, IOEs, TriMatrix memory
structures, DSP blocks, and MultiTrack interconnects.
Table 4–25. LE Internal Timing Microparameters
-6
-7
-8
Symbol
Unit
Min
Max
Min
Max
Min
Max
tSU
29
—
33
—
37
—
ps
tH
12
—
13
—
15
—
ps
tCO
—
173
—
198
—
224
ps
tLUT
—
454
—
522
—
590
ps
tCLR
129
—
148
—
167
—
ps
tPRE
129
—
148
—
167
—
ps
1,234
—
1,562
—
1,818
—
ps
tCLKHL
Table 4–26. IOE Internal Timing Microparameters
-6
-7
-8
Symbol
Max
Min
Max
Min
Max
tSU
348
—
400
—
452
—
ps
tH
0
—
0
—
0
—
ps
tCO
—
511
—
587
—
664
ps
tPIN2COMBOUT_R
—
1,130
—
1,299
—
1,469
ps
tPIN2COMBOUT_C
—
1,135
—
1,305
—
1,475
ps
tCOMBIN2PIN_R
—
2,627
—
3,021
—
3,415
ps
tCOMBIN2PIN_C
—
2,615
—
3,007
—
3,399
ps
tCLR
280
—
322
—
364
—
ps
tPRE
280
—
322
—
364
—
ps
1,234
—
1,562
—
1,818
—
ps
tCLKHL
4–14
Preliminary
Unit
Min
Altera Corporation
May 2008
Timing Model
Table 4–27. M4K Block Internal Timing Microparameters
-6
-7
-8
Symbol
Unit
Min
Max
—
4,379
tM4KWC
—
2,910
3,783
ps
tM4KWERESU
72
—
82
—
93
—
ps
tM4KWEREH
43
—
49
—
55
—
ps
tM4KBESU
72
—
82
—
93
—
ps
tM4KBEH
43
—
49
—
55
—
ps
tM4KDATAASU
72
—
82
—
93
—
ps
tM4KDATAAH
43
—
49
—
55
—
ps
tM4KADDRASU
72
—
82
—
93
—
ps
tM4KADDRAH
43
—
49
—
55
—
ps
tM4KDATABSU
72
—
82
—
93
—
ps
tM4KDATABH
43
—
49
—
55
—
ps
tM4KADDRBSU
72
—
82
—
93
—
ps
tM4KADDRBH
43
—
49
—
55
—
ps
tM4KDATACO1
—
621
—
714
—
807
ps
tM4KDATACO2
—
4,351
—
5,003
—
5,656
ps
1,234
—
1,562
—
1,818
—
ps
286
—
328
—
371
—
ps
tM4KRC
tM4KCLKHL
tM4KCLR
Min
Max
Min
Max
5,035
5,691
3,346
ps
Table 4–28. Routing Delay Internal Timing Microparameters
-6
-7
-8
Symbol
Unit
Min
Max
Min
Max
Min
Max
tR4
—
261
—
300
—
339
ps
tC4
—
338
—
388
—
439
ps
tLOCAL
—
244
—
281
—
318
ps
External Timing Parameters
External timing parameters are specified by device density and speed
grade. Figure 4–2 shows the timing model for bidirectional IOE pin
timing. All registers are within the IOE.
Altera Corporation
May 2008
4–15
Preliminary
Cyclone Device Handbook, Volume 1
Figure 4–2. External Timing in Cyclone Devices
OE Register
Dedicated
Clock
D
PRN
Q
tXZ
tZX
tINSU
tINH
tOUTCO
CLRN
Output Register
D
PRN
Q
Bidirectional
Pin
CLRN
Input Register
PRN
D
Q
CLRN
All external I/O timing parameters shown are for 3.3-V LVTTL I/O
standard with the maximum current strength and fast slew rate. For
external I/O timing using standards other than LVTTL or for different
current strengths, use the I/O standard input and output delay adders in
Tables 4–40 through 4–44.
Table 4–29 shows the external I/O timing parameters when using global
clock networks.
Table 4–29. Cyclone Global Clock External I/O Timing Parameters
Symbol
Notes (1), (2) (Part 1 of 2)
Parameter
Conditions
tI N S U
Setup time for input or bidirectional pin using IOE input
register with global clock fed by CLK pin
—
tI N H
Hold time for input or bidirectional pin using IOE input
register with global clock fed by CLK pin
—
tO U T C O
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock fed by CLK pin
tI N S U P L L
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
—
tI N H P L L
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
—
4–16
Preliminary
CLOAD = 10 pF
Altera Corporation
May 2008
Timing Model
Table 4–29. Cyclone Global Clock External I/O Timing Parameters
Symbol
tO U T C O P L L
Notes (1), (2) (Part 2 of 2)
Parameter
Conditions
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock enhanced PLL with default
phase setting
CLOAD = 10 pF
Notes to Table 4–29:
(1)
(2)
These timing parameters are sample-tested only.
These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II
software to verify the external timing for any pin.
Tables 4–30 through 4–31 show the external timing parameters on column
and row pins for EP1C3 devices.
Table 4–30. EP1C3 Column Pin Global Clock External I/O Timing
Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tI N S U
3.085
—
3.547
—
4.009
—
ns
tI N H
0.000
—
0.000
—
0.000
—
ns
tO U T C O
2.000
4.073
2.000
4.682
2.000
5.295
ns
tI N S U P L L
1.795
—
2.063
—
2.332
—
ns
tI N H P L L
0.000
—
0.000
—
0.000
—
ns
tO U T C O P L L
0.500
2.306
0.500
2.651
0.500
2.998
ns
Table 4–31. EP1C3 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Altera Corporation
May 2008
Unit
Min
Max
Min
Max
Min
Max
tI N S U
3.157
—
3.630
—
4.103
—
ns
tI N H
0.000
—
0.000
—
0.000
—
ns
tO U T C O
2.000
3.984
2.000
4.580
2.000
5.180
ns
tI N S U P L L
1.867
—
2.146
—
2.426
—
ns
tI N H P L L
0.000
—
0.000
—
0.000
—
ns
tO U T C O P L L
0.500
2.217
0.500
2.549
0.500
2.883
ns
4–17
Preliminary
Cyclone Device Handbook, Volume 1
Tables 4–32 through 4–33 show the external timing parameters on column
and row pins for EP1C4 devices.
Table 4–32. EP1C4 Column Pin Global Clock External I/O Timing
Parameters Note (1)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tI N S U
2.471
—
2.841
—
3.210
—
ns
tI N H
0.000
—
0.000
—
0.000
—
ns
tO U T C O
2.000
3.937
2.000
4.526
2.000
5.119
ns
tI N S U P L L
1.471
—
1.690
—
1.910
—
ns
tI N H P L L
0.000
—
0.000
—
0.000
—
ns
tO U T C O P L L
0.500
2.080
0.500
2.392
0.500
2.705
ns
Table 4–33. EP1C4 Row Pin Global Clock External I/O Timing
Parameters Note (1)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tI N S U
2.600
—
2.990
—
3.379
—
ns
tI N H
0.000
—
0.000
—
0.000
—
ns
tO U T C O
2.000
3.991
2.000
4.388
2.000
5.189
ns
tI N S U P L L
1.300
—
1.494
—
1.689
—
ns
tI N H P L L
0.000
—
0.000
—
0.000
—
ns
tO U T C O P L L
0.500
2.234
0.500
2.569
0.500
2.905
ns
Note to Tables 4–32 and 4–33:
(1)
4–18
Preliminary
Contact Altera Applications for EP1C4 device timing parameters.
Altera Corporation
May 2008
Timing Model
Tables 4–34 through 4–35 show the external timing parameters on column
and row pins for EP1C6 devices.
Table 4–34. EP1C6 Column Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tI N S U
2.691
—
3.094
—
3.496
—
ns
tI N H
0.000
—
0.000
—
0.000
—
ns
tO U T C O
2.000
3.917
2.000
4.503
2.000
5.093
ns
tI N S U P L L
1.513
—
1.739
—
1.964
—
ns
tI N H P L L
0.000
—
0.000
—
0.000
—
ns
tO U T C O P L L
0.500
2.038
0.500
2.343
0.500
2.651
ns
Table 4–35. EP1C6 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
tI N S U
2.774
tI N H
tO U T C O
Max
Min
—
3.190
0.000
—
2.000
3.817
tI N S U P L L
1.596
tI N H P L L
tO U T C O P L L
Max
Min
—
3.605
0.000
—
2.000
4.388
—
1.835
0.000
—
0.500
1.938
Max
—
ns
0.000
—
ns
2.000
4.963
ns
—
2.073
—
ns
0.000
—
0.000
—
ns
0.500
2.228
0.500
2.521
ns
Tables 4–36 through 4–37 show the external timing parameters on column
and row pins for EP1C12 devices.
Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing
Parameters (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Altera Corporation
May 2008
Unit
Min
Max
Min
Max
Min
Max
tI N S U
2.510
—
2.885
—
3.259
—
ns
tI N H
0.000
—
0.000
—
0.000
—
ns
tOU T C O
2.000
3.798
2.000
4.367
2.000
4.940
ns
tI N S U P L L
1.588
—
1.824
—
2.061
—
ns
4–19
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing
Parameters (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tI N H P L L
0.000
—
0.000
—
0.000
—
ns
tO U T C O P L L
0.500
1.663
0.500
1.913
0.500
2.164
ns
Table 4–37. EP1C12 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tI N S U
2.620
—
3.012
—
3.404
—
ns
tI N H
0.000
—
0.000
—
0.000
—
ns
tO U T C O
2.000
3.671
2.000
4.221
2.000
4.774
ns
tI N S U P L L
1.698
—
1.951
—
2.206
—
ns
tI N H P L L
0.000
—
0.000
—
0.000
—
ns
tO U T C O P L L
0.500
1.536
0.500
1.767
0.500
1.998
ns
Tables 4–38 through 4–39 show the external timing parameters on column
and row pins for EP1C20 devices.
Table 4–38. EP1C20 Column Pin Global Clock External I/O Timing
Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
4–20
Preliminary
Unit
Min
Max
Min
Max
Min
Max
tI N S U
2.417
—
2.779
—
3.140
—
ns
tI N H
0.000
—
0.000
—
0.000
—
ns
tO U T C O
2.000
3.724
2.000
4.282
2.000
4.843
ns
tI N S U P L L
1.417
—
1.629
—
1.840
—
ns
tI N H P L L
0.000
—
0.000
—
0.000
—
ns
tO U T C O P L L
0.500
1.667
0.500
1.917
0.500
2.169
ns
Altera Corporation
May 2008
Timing Model
Table 4–39. EP1C20 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tI N S U
2.417
—
2.779
—
3.140
—
ns
tI N H
0.000
—
0.000
—
0.000
—
ns
tO U T C O
2.000
3.724
2.000
4.282
2.000
4.843
ns
—
3.645
—
4.191
—
4.740
ns
tX Z
tZ X
—
3.645
—
4.191
—
4.740
ns
tI N S U P L L
1.417
—
1.629
—
1.840
—
ns
tI N H P L L
0.000
—
0.000
—
0.000
—
ns
tO U T C O P L L
0.500
1.667
0.500
1.917
0.500
2.169
ns
tX Z P L L
—
1.588
—
1.826
—
2.066
ns
tZ X P L L
—
1.588
—
1.826
—
2.066
ns
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by
speed grade independent of device density.
Tables 4–40 through 4–45 show the adder delays associated with column
and row I/O pins for all packages. If an I/O standard is selected other
than LVTTL 4 mA with a fast slew rate, add the selected delay to the
external tCO and tSU I/O parameters shown in Tables 4–25 through
4–28.
Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Max
Min
Max
Min
Max
LVCMOS
—
0
—
0
—
0
ps
3.3-V LVTTL
—
0
—
0
—
0
ps
2.5-V LVTTL
—
27
—
31
—
35
ps
1.8-V LVTTL
—
182
—
209
—
236
ps
1.5-V LVTTL
—
278
—
319
—
361
ps
I/O Standard
Unit
SSTL-3 class I
—
–250
—
–288
—
–325
ps
SSTL-3 class II
—
–250
—
–288
—
–325
ps
SSTL-2 class I
—
–278
—
–320
—
–362
ps
Altera Corporation
May 2008
4–21
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Max
Min
Max
Min
Max
SSTL-2 class II
–278
—
–320
—
–362
ps
LVDS
–261
—
–301
—
–340
ps
I/O Standard
Unit
Table 4–41. Cyclone I/O Standard Row Pin Input Delay Adders
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Max
Min
Max
Min
Max
LVCMOS
—
0
—
0
—
0
ps
3.3-V LVTTL
—
0
—
0
—
0
ps
2.5-V LVTTL
—
27
—
31
—
35
ps
1.8-V LVTTL
—
182
—
209
—
236
ps
1.5-V LVTTL
—
278
—
319
—
361
ps
3.3-V PCI (1)
—
0
—
0
—
0
ps
I/O Standard
Unit
SSTL-3 class I
—
–250
—
–288
—
–325
ps
SSTL-3 class II
—
–250
—
–288
—
–325
ps
SSTL-2 class I
—
–278
—
–320
—
–362
ps
SSTL-2 class II
—
–278
—
–320
—
–362
ps
LVDS
—
–261
—
–301
—
–340
ps
Table 4–42. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Max
Min
Max
Min
Max
2 mA
—
0
—
0
—
0
ps
4 mA
—
–489
—
–563
—
–636
ps
8 mA
—
–855
—
–984
—
–1,112
ps
Standard
LVCMOS
3.3-V LVTTL
4–22
Preliminary
Unit
12 mA
—
–993
—
–1,142
—
–1,291
ps
4 mA
—
0
—
0
—
0
ps
8 mA
—
–347
—
–400
—
–452
ps
12 mA
—
–858
—
–987
—
–1,116
ps
16 mA
—
–819
—
–942
—
–1,065
ps
24 mA
—
–993
—
–1,142
—
–1,291
ps
Altera Corporation
May 2008
Timing Model
Table 4–42. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Min
Min
Standard
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
Unit
Max
Max
Max
2 mA
—
329
—
378
—
427
ps
8 mA
—
–661
—
–761
—
–860
ps
12 mA
—
–655
—
–754
—
–852
ps
16 mA
—
–795
—
–915
—
–1034
ps
2 mA
—
4
—
4
—
5
ps
8 mA
—
–208
—
–240
—
–271
ps
12 mA
—
–208
—
–240
—
–271
ps
2 mA
—
2,288
—
2,631
—
2,974
ps
4 mA
—
608
—
699
—
790
ps
8 mA
—
292
—
335
—
379
ps
SSTL-3 class I
—
–410
—
–472
—
–533
ps
SSTL-3 class II
—
–811
—
–933
—
–1,055
ps
SSTL-2 class I
—
–485
—
–558
—
–631
ps
SSTL-2 class II
—
–758
—
–872
—
–986
ps
LVDS
—
–998
—
–1,148
—
–1,298
ps
Table 4–43. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Max
Min
Max
Min
Max
2 mA
—
0
—
0
—
0
ps
4 mA
—
–489
—
–563
—
–636
ps
8 mA
—
–855
—
–984
—
–1,112
ps
Standard
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
Unit
12 mA
—
–993
—
–1,142
—
–1,291
ps
4 mA
—
0
—
0
—
0
ps
8 mA
—
–347
—
–400
—
–452
ps
12 mA
—
–858
—
–987
—
–1,116
ps
16 mA
—
–819
—
–942
—
–1,065
ps
24 mA
—
–993
—
–1,142
—
–1,291
ps
2 mA
—
329
—
378
—
427
ps
8 mA
—
–661
—
–761
—
–860
ps
12 mA
—
–655
—
–754
—
–852
ps
16 mA
—
–795
—
–915
—
–1,034
ps
Altera Corporation
May 2008
4–23
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–43. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Max
Min
Max
Min
Max
Standard
1.8-V LVTTL
Unit
2 mA
—
1,290
—
1,483
—
1,677
ps
8 mA
—
4
—
4
—
5
ps
12 mA
—
–208
—
–240
—
–271
ps
2 mA
—
2,288
—
2,631
—
2,974
ps
4 mA
—
608
—
699
—
790
ps
8 mA
—
292
—
335
—
379
ps
3.3-V PCI (1)
—
–877
—
–1,009
—
–1,141
ps
SSTL-3 class I
—
–410
—
–472
—
–533
ps
SSTL-3 class II
—
–811
—
–933
—
–1,055
ps
SSTL-2 class I
—
–485
—
–558
—
–631
ps
SSTL-2 class II
—
–758
—
–872
—
–986
ps
LVDS
—
–998
—
–1,148
—
–1,298
ps
1.5-V LVTTL
Table 4–44. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Min
Min
I/O Standard
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
4–24
Preliminary
Unit
Max
Max
Max
2 mA
—
1,800
—
2,070
—
2,340
ps
4 mA
—
1,311
—
1,507
—
1,704
ps
8 mA
—
945
—
1,086
—
1,228
ps
12 mA
—
807
—
928
—
1,049
ps
4 mA
—
1,831
—
2,105
—
2,380
ps
8 mA
—
1,484
—
1,705
—
1,928
ps
12 mA
—
973
—
1,118
—
1,264
ps
16 mA
—
1,012
—
1,163
—
1,315
ps
24 mA
—
838
—
963
—
1,089
ps
2 mA
—
2,747
—
3,158
—
3,570
ps
8 mA
—
1,757
—
2,019
—
2,283
ps
12 mA
—
1,763
—
2,026
—
2,291
ps
16 mA
—
1,623
—
1,865
—
2,109
ps
2 mA
—
5,506
—
6,331
—
7,157
ps
8 mA
—
4,220
—
4,852
—
5,485
ps
12 mA
—
4,008
—
4,608
—
5,209
ps
Altera Corporation
May 2008
Timing Model
Table 4–44. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Min
Min
I/O Standard
1.5-V LVTTL
Unit
Max
Max
Max
2 mA
—
6,789
—
7,807
—
8,825
ps
4 mA
—
5,109
—
5,875
—
6,641
ps
8 mA
SSTL-3 class I
—
4,793
—
5,511
—
6,230
ps
—
1,390
—
1,598
—
1,807
ps
SSTL-3 class II
—
989
—
1,137
—
1,285
ps
SSTL-2 class I
—
1,965
—
2,259
—
2,554
ps
SSTL-2 class II
—
1,692
—
1,945
—
2,199
ps
LVDS
—
802
—
922
—
1,042
ps
Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Min
Min
I/O Standard
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
Unit
Max
Max
Max
2 mA
—
1,800
—
2,070
—
2,340
ps
4 mA
—
1,311
—
1,507
—
1,704
ps
8 mA
—
945
—
1,086
—
1,228
ps
12 mA
—
807
—
928
—
1,049
ps
4 mA
—
1,831
—
2,105
—
2,380
ps
8 mA
—
1,484
—
1,705
—
1,928
ps
12 mA
—
973
—
1,118
—
1,264
ps
16 mA
—
1,012
—
1,163
—
1,315
ps
24 mA
—
838
—
963
—
1,089
ps
2 mA
—
2,747
—
3,158
—
3,570
ps
8 mA
—
1,757
—
2,019
—
2,283
ps
12 mA
—
1,763
—
2,026
—
2,291
ps
16 mA
—
1,623
—
1,865
—
2,109
ps
2 mA
—
5,506
—
6,331
—
7,157
ps
8 mA
—
4,220
—
4,852
—
5,485
ps
12 mA
—
4,008
—
4,608
—
5,209
ps
2 mA
—
6,789
—
7,807
—
8,825
ps
4 mA
—
5,109
—
5,875
—
6,641
ps
8 mA
—
4,793
—
5,511
—
6,230
ps
—
923
—
1,061
—
1,199
ps
3.3-V PCI
Altera Corporation
May 2008
4–25
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min
Max
Min
Max
Min
Max
SSTL-3 class I
—
1,390
—
1,598
—
1,807
ps
SSTL-3 class II
—
989
—
1,137
—
1,285
ps
I/O Standard
Unit
SSTL-2 class I
—
1,965
—
2,259
—
2,554
ps
SSTL-2 class II
—
1,692
—
1,945
—
2,199
ps
LVDS
—
802
—
922
—
1,042
ps
Note to Tables 4–40 through 4–45:
(1)
EP1C3 devices do not support the PCI I/O standard.
Tables 4–46 through 4–47 show the adder delays for the IOE
programmable delays. These delays are controlled with the Quartus II
software options listed in the Parameter column.
Table 4–46. Cyclone IOE Programmable Delays on Column Pins
-6 Speed Grade
Parameter
-8 Speed Grade
Unit
Min
Decrease input delay to
internal cells
-7 Speed Grade
Setting
Max
Min
Max
Min
Max
Off
—
155
—
178
—
201
ps
Small
—
2,122
—
2,543
—
2,875
ps
Medium
—
2,639
—
3,034
—
3,430
ps
Large
—
3,057
—
3,515
—
3,974
ps
On
—
155
—
178
—
201
ps
Decrease input delay to
input register
Off
—
0
—
0
—
0
ps
On
—
3,057
—
3,515
—
3,974
ps
Increase delay to output
pin
Off
—
0
—
0
—
0
ps
On
—
552
—
634
—
717
ps
4–26
Preliminary
Altera Corporation
May 2008
Timing Model
Table 4–47. Cyclone IOE Programmable Delays on Row Pins
-6 Speed Grade
Parameter
-8 Speed Grade
Unit
Min
Decrease input delay to
internal cells
-7 Speed Grade
Setting
Max
Min
Max
Min
Max
Off
—
154
—
177
—
200
ps
Small
—
2,212
—
2,543
—
2,875
ps
Medium
—
2,639
—
3,034
—
3,430
ps
Large
—
3,057
—
3,515
—
3,974
ps
On
—
154
—
177
—
200
ps
Decrease input delay to input Off
register
On
—
0
—
0
—
0
ps
—
3,057
—
3,515
—
3,974
ps
Increase delay to output pin
Off
—
0
—
0
—
0
ps
On
—
556
—
639
—
722
ps
Note to Table 4–47:
(1)
EPC1C3 devices do not support the PCI I/O standard.
Maximum Input and Output Clock Rates
Tables 4–48 and 4–49 show the maximum input clock rate for column and
row pins in Cyclone devices.
Table 4–48. Cyclone Maximum Input Clock Rate for Column Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
464
428
387
MHz
2.5 V
392
302
207
MHz
1.8 V
387
311
252
MHz
I/O Standard
Altera Corporation
May 2008
1.5 V
387
320
243
MHz
LVCMOS
405
374
333
MHz
SSTL-3 class I
405
356
293
MHz
SSTL-3 class II
414
365
302
MHz
SSTL-2 class I
464
428
396
MHz
SSTL-2 class II
473
432
396
MHz
LVDS
567
549
531
MHz
4–27
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–49. Cyclone Maximum Input Clock Rate for Row Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
464
428
387
MHz
2.5 V
392
302
207
MHz
1.8 V
387
311
252
MHz
I/O Standard
1.5 V
387
320
243
MHz
LVCMOS
405
374
333
MHz
SSTL-3 class I
405
356
293
MHz
SSTL-3 class II
414
365
302
MHz
SSTL-2 class I
464
428
396
MHz
SSTL-2 class II
473
432
396
MHz
3.3-V PCI (1)
464
428
387
MHz
LVDS
567
549
531
MHz
Note to Tables 4–48 through 4–49:
(1)
EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
Tables 4–50 and 4–51 show the maximum output clock rate for column
and row pins in Cyclone devices.
Table 4–50. Cyclone Maximum Output Clock Rate for Column Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
304
304
304
MHz
2.5 V
220
220
220
MHz
1.8 V
213
213
213
MHz
1.5 V
166
166
166
MHz
I/O Standard
LVCMOS
304
304
304
MHz
SSTL-3 class I
100
100
100
MHz
SSTL-3 class II
100
100
100
MHz
SSTL-2 class I
134
134
134
MHz
SSTL-2 class II
134
134
134
MHz
LVDS
320
320
275
MHz
Note to Table 4–50:
(1)
4–28
Preliminary
EP1C3 devices do not support the PCI I/O standard.
Altera Corporation
May 2008
Timing Model
Table 4–51. Cyclone Maximum Output Clock Rate for Row Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
296
285
273
MHz
2.5 V
381
366
349
MHz
1.8 V
286
277
267
MHz
I/O Standard
1.5 V
219
208
195
MHz
LVCMOS
367
356
343
MHz
SSTL-3 class I
169
166
162
MHz
SSTL-3 class II
160
151
146
MHz
SSTL-2 class I
160
151
142
MHz
SSTL-2 class II
131
123
115
MHz
3.3-V PCI (1)
66
66
66
MHz
LVDS
320
303
275
MHz
Note to Tables 4–50 through 4–51:
(1)
EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
PLL Timing
Table 4–52 describes the Cyclone FPGA PLL specifications.
Table 4–52. Cyclone PLL Specifications (Part 1 of 2)
Symbol
Min
Max
Unit
Input frequency (-6 speed
grade)
15.625
464
MHz
Input frequency (-7 speed
grade)
15.625
428
MHz
Input frequency (-8 speed
grade)
15.625
387
MHz
fIN DUTY
Input clock duty cycle
40.00
60
%
tIN JITTER
Input clock period jitter
—
± 200
ps
fOUT_EXT (external PLL
clock output)
PLL output frequency
(-6 speed grade)
15.625
320
MHz
PLL output frequency
(-7 speed grade)
15.625
320
MHz
PLL output frequency
(-8 speed grade)
15.625
275
MHz
fIN
Altera Corporation
May 2008
Parameter
4–29
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–52. Cyclone PLL Specifications (Part 2 of 2)
Symbol
Min
Max
Unit
PLL output frequency
(-6 speed grade)
15.625
405
MHz
PLL output frequency
(-7 speed grade)
15.625
320
MHz
PLL output frequency
(-8 speed grade)
15.625
275
MHz
tOUT DUTY
Duty cycle for external clock
output (when set to 50%)
45.00
55
%
tJITTER (1)
Period jitter for external clock
output
—
±300 (2)
ps
tLOCK (3)
Time required to lock from end
of device configuration
10.00
100
μs
fVCO
PLL internal VCO operating
range
500.00
1,000
MHz
-
Minimum areset time
10
—
ns
N, G0, G1, E
Counter values
1
32
integer
fOUT (to global clock)
Parameter
Notes to Table 4–52:
(1)
(2)
(3)
The tJITTER specification for the PLL[2..1]_OUT pins are dependent on the I/O pins in its VCCIO bank, how many
of them are switching outputs, how much they toggle, and whether or not they use programmable current strength
or slow slew rate.
fOUT ≥ 100 MHz. When the PLL external clock output frequency (fOUT) is smaller than 100 MHz, the jitter
specification is 60 mUI.
fIN/N must be greater than 200 MHz to ensure correct lock detect circuit operation below –20 C. Otherwise, the PLL
operates with the specified parameters under the specified conditions.
4–30
Preliminary
Altera Corporation
May 2008
Referenced Document
Referenced
Document
This chapter references the following documents:
Document
Revision History
Table 4–53 shows the revision history for this chapter.
■
■
Cyclone Architecture chapter in the Cyclone Device Handbook
Operating Requirements for Altera Devices Data Sheet
Table 4–53. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
May 2008
v1.7
Minor textual and style changes. Added “Referenced Document”
section.
—
January 2007
v1.6
●
●
●
●
●
●
●
Added document revision history.
Added new row for VCCA details in Table 4–1.
—
Updated RCONF information in Table 4–3.
Added new Note (12) on voltage overdrive information to
Table 4–7 and Table 4–8.
Updated Note (9) on RCONF information to Table 4–3.
Updated information in “External I/O Delay Parameters”
section.
Updated speed grade information in Table 4–46 and
Table 4–47.
●
Updated LVDS information in Table 4–51.
August 2005
v1.5
Minor updates.
February 2005
v1.4
●
●
●
●
January 2004
v.1.3
●
●
October 2003
v.1.2
●
●
●
Altera Corporation
May 2008
—
Updated information on Undershoot voltage. Updated Table
4-2.
Updated Table 4-3.
Updated the undershoot voltage from 0.5 V to 2.0 V in Note 3
of Table 4-16.
Updated Table 4-17.
—
Added extended-temperature grade device information.
Updated Table 4-2.
Updated IC C 0 information in Table 4-3.
—
Added clock tree information in Table 4-19.
Finalized timing information for EP1C3 and EP1C12 devices.
Updated timing information in Tables 4-25 through 4-26 and
Tables 4-30 through 4-51.
Updated PLL specifications in Table 4-52.
—
4–31
Preliminary
Cyclone Device Handbook, Volume 1
July 2003
v1.1
Updated timing information. Timing finalized for EP1C6 and
EP1C20 devices. Updated performance information. Added PLL
Timing section.
—
May 2003
v1.0
Added document to Cyclone Device Handbook.
—
4–32
Preliminary
Altera Corporation
May 2008