ACT8930 - Active-Semi

ACT8930
Rev 5, 17-Sep-13
Advanced PMU for Portable Handheld Equipment
FEATURES
GENERAL DESCRIPTION
• Three Step-Down DC/DC Converters
• Four Low-Dropout Linear Regulators
• Dedicated enable pins for the voltage regulators
The ACT8930 is a complete, cost effective, highlyefficient ActivePMUTM power management solution,
for portable handheld equipment such as
Smartphones, Mobile Internet Devices (MID),
eBooks and etc.
for flexible power sequencing.
• Integrated ActivePathTM Charger
This device features three step-down DC/DC
converters and four low-noise, low-dropout linear
regulators, along with a complete battery charging
solution featuring the advanced ActivePathTM
system-power selection function.
• I C Serial Interface
• Minimal External Components
• Tiny 5×5mm TQFN55-40 Package
2 TM
− 0.75mm Package Height
− Pb-Free and RoHS Compliant
The three DC/DC converters utilize a highefficiency, fixed-frequency (2MHz), current-mode
PWM control architecture that requires a minimum
number of external components. Two DC/DCs are
capable of supplying up to 1100mA of output
current, while the third supports up to 1300mA. All
four low-dropout linear regulators are highperformance, low-noise regulators that supply up to
320mA each.
The ACT8930 is available in a compact, Pb-Free
and RoHS-compliant TQFN55-40 package.
SYSTEM BLOCK DIAGRAM
ActivePMU
TM
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
-1-
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
TABLE OF CONTENTS
General Information ..................................................................................................................................... p. 01
Functional Block Diagram ............................................................................................................................ p. 03
Ordering Information .................................................................................................................................... p. 04
Pin Configuration ......................................................................................................................................... p. 04
Pin Descriptions ........................................................................................................................................... p. 05
Absolute Maximum Ratings ......................................................................................................................... p. 07
I2C Interface Electrical Characteristics ........................................................................................................ p. 08
Global Register Map .................................................................................................................................... p. 09
Register and Bit Descriptions ...................................................................................................................... p. 10
System Control Electrical Characteristics.................................................................................................... p. 14
Step-Down DC/DC Electrical Characteristics .............................................................................................. p. 15
Low-Noise LDO Electrical Characteristics ................................................................................................... p. 16
ActivePathTM Charger Electrical Characteristics.......................................................................................... p. 17
Typical Performance Characteristics ........................................................................................................... p. 19
System control information .......................................................................................................................... p. 26
Control Signals ................................................................................................................................. p. 26
Functional Description ................................................................................................................................. p. 27
I2C Interface ..................................................................................................................................... p. 27
Housekeeping Functions.................................................................................................................. p. 27
Step-Down DC/DC Regulators .................................................................................................................... p. 28
General Description.......................................................................................................................... p. 28
100% Duty Cycle Operation ............................................................................................................. p. 28
Synchronous Rectification ................................................................................................................ p. 28
Soft-Start .......................................................................................................................................... p. 28
Compensation .................................................................................................................................. p. 28
Configuration Options....................................................................................................................... p. 28
Output OK[ ] ..................................................................................................................................... p. 29
PCB Layout Considerations ............................................................................................................. p. 29
Low-Noise, Low-Dropout Linear Regulators................................................................................................ p. 30
General Description.......................................................................................................................... p. 30
Output Current Limit ......................................................................................................................... p. 30
Compensation .................................................................................................................................. p. 30
Configuration Options....................................................................................................................... p. 30
OUTPUT OK[ ] ................................................................................................................................. p. 30
PCB Layout Considerations ............................................................................................................. p. 30
ActivePathTM Charger .................................................................................................................................. p. 31
General Description.......................................................................................................................... p. 31
ActivePath Architecture .................................................................................................................... p. 31
System Configuration Optimization .................................................................................................. p. 31
Input Protection ................................................................................................................................ p. 31
Battery Management ........................................................................................................................ p. 31
Charge Current Programming .......................................................................................................... p. 32
Charge-Control State Machine ......................................................................................................... p. 32
Thermal Regulation .......................................................................................................................... p. 34
Charge Safety Timers ...................................................................................................................... p. 34
Charge Status Indicator.................................................................................................................... p. 35
Reverse-Current Protection ............................................................................................................. p. 35
Battery Temperature Monitoring ...................................................................................................... p. 35
TQFN55-40 Package Outline and Dimensions ........................................................................................... p. 36
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
-2-
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
FUNCTIONAL BLOCK DIAGRAM
(Optional)
AC Adaptor
BODY
SWITCH
ACT8930
4.35V to 6V CHGIN
VSYS
System Supply
BAT
Li+ Battery
USB
ACIN
BODY
SWITCH
ActivePath
Control
VSYS
nSTAT
+
102µA
CURRENT SENSE
CHARGE STATUS
TH
VOLTAGE SENSE
Charge
Control
CHGLEV
PRECONDITION
2.85V
VP1
ISET
THERMAL
REGULATION
To VSYS
110°C
SW1
OUT1
OUT1
OUT1
nRSTO
GP12
VP2
ON1
SW2
ON2
OUT2
ON3
GP12
To VSYS
OUT2
ON45
VP3
ON6
SW3
To VSYS
OUT3
ON7
OUT3
System
Control
GP3
SCL
INL
SDA
REG4
LDO
BAT
LBI
1.2V
OUT1
REG5
LDO
+
REG6
LDO
nLBO
REG7
LDO
REFBP
To VSYS
OUT4
OUT4
OUT5
OUT5
OUT6
OUT6
OUT7
OUT7
Reference
GA
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
EP
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
ORDERING INFORMATIONcd
PART NUMBER
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
PACKAGE
PINS
TEMPERATURE
RANGE
ACT8930QJ133-T
3.3V
1.3V
1.3V
1.2V
1.2V
1.2V
3.3V
TQFN55-40
40
-40°C to +85°C
ACT8930QJ134-T
1.35V
3.3V
1.8V
3.3V
1.8V
3.3V
3.3V
TQFN55-40
40
-40°C to +85°C
ACT8930QJ135-T
1.8V
1.2
1.2V
1.2V
3.3V
3.3V
1.8V
TQFN55-40
40
-40°C to +85°C
c: All Active-Semi components are RoHS Compliant and with Pb-free plating unless otherwise specified.
d: Standard product options are listed in this table. Contact factory for custom options. Minimum order quantity is 12,000 units.
PIN CONFIGURATION
VSYS
CHGIN
VSYS
OUT2
VP2
SW2
GP12
SW1
VP1
NC
TOP VIEW
REFBP
BAT
OUT1
BAT
GA
nSTAT
OUT4
SDA
ACTIVE
AA33
DATE CODE
OUT5
INL
OUT7
SCL
ON2
TH
ISET
OUT6
ON6
CHGLEV
EP
ACIN
LBI
nLBO
ON3
OUT3
VP3
SW3
GP3
ON1
ON45
nRSTO
ON7
Thin - QFN (TQFN55-40)
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Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
REFBP
2
OUT1
3
GA
4
OUT4
REG4 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
5
OUT5
REG5 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
6
INL
7
OUT7
REG7 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
8
OUT6
REG6 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
9
ON6
Enable Input for REG6. Drive to VP1 or a logic high to enable REG6. Drive to GA to disable.
10
ON7
Enable Input for REG7. Drive to VP1 or a logic high to enable REG7. Drive to GA to disable.
11
nRSTO
12
ON45
Enable Input for REG4 and REG5. Drive to VP1 or a logic high to enable REG4 and REG5. Drive
to GA to disable.
13
ON1
Enable Input for REG1. Drive to VP1 or a logic high to enable REG1. Drive to GA to disable.
14
GP3
Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the
IC as possible.
15
SW3
Switching Node Output for REG3.
16
VP3
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the
IC as possible.
17
OUT3
18
ON3
Enable Input for REG3. Drive to VP1 or a logic high to enable REG3. Drive to GA to disable.
19
nLBO
Low Battery Indicator Output. nLBO is asserted low whenever the voltage at LBI is lower than
1.2V, and is high-Z otherwise. See the Precision Voltage Detector section for more information.
20
LBI
21
ACIN
22
CHGLEV
Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This pin is
discharged to GA in shutdown.
Output Feedback Sense for REG1.
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12 and GP3
together at a single point as close to the IC as possible.
Power Input for REG4, REG5, REG6, and REG7. Bypass to GA with a high quality ceramic
capacitor placed as close to the IC as possible.
Active Low Reset Output. See the nRSTO Output section for more information.
Output Feedback Sense for REG3.
Low Battery Input. The input voltage is compared to 1.2V and the output of this comparison drives
nLBO. See the Precision Voltage Detector section for more information.
AC Input Supply Detection. See the Charge Current Programming section for more information.
Charge Current Selection Input. See the Charge Current Programming section for more information.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
-5-
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
PIN DESCRIPTIONS CONT’D
PIN
NAME
DESCRIPTION
23
ISET
24
TH
25
ON2
Enable Input for REG2. Drive to VP1 or a logic high to enable REG2. Drive to GA to disable.
26
SCL
Clock Input for I2C Serial Interface.
27
SDA
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
28
nSTAT
29, 30
BAT
31, 32
VSYS
System Output Pin. Bypass to GA with a 10µF or larger ceramic capacitor.
33
CHGIN
Power Input for the Battery Charger. Bypass CHGIN to GA with a capacitor placed as close to
the IC as possible. The battery charger is automatically enabled when a valid voltage is present
on CHGIN .
34
OUT2
Output Feedback Sense for REG2.
35
VP2
Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close to
the IC as possible.
36
SW2
Switching Node Output for REG2.
37
GP12
Power Ground for REG1 and REG2. Connect GA, GP12 and GP3 together at a single point as
close to the IC as possible.
38
SW1
Switching Node Output for REG1.
39
VP1
Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close to
the IC as possible.
40
NC
No Connect. Not internally connected.
EP
EP
Exposed Pad. Must be soldered to ground on PCB.
Charge Current Set. Program the charge current by connecting a resistor (RISET) between ISET
and GA. See the Charge Current Programming section for more information.
Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 102µA (typ) current
internally. See the Battery Temperature Monitoring section for more information.
Active-Low Open-Drain Charger Status Output. nSTAT has a 8mA (typ) current limit, allowing it
to directly drive an indicator LED without additional external components. See the Charge Status
Indicator section for more information.
Battery Charger Output. Connect this pin directly to the battery anode (+ terminal)
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
-6-
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
ABSOLUTE MAXIMUM RATINGSc
PARAMETER
VALUE
UNIT
VP1, VP2 to GP12
VP3 to GP3
-0.3 to +6
V
BAT, VSYS, INL to GA
-0.3 to +6
V
CHGIN to GA
-0.3 to +14
V
SW1, OUT1 to GP12
-0.3 to (VVP1 + 0.3)
V
SW2, OUT2 to GP12
-0.3 to (VVP2 + 0.3)
V
SW3, OUT3 to GP3
-0.3 to (VVP3 + 0.3)
V
-0.3 to +6
V
ON45, ON1, ON6, ACIN, CHGLEV, ISET, LBI, ON7, ON3, REFBP, SCL, SDA, TH,
ON2 to GA
-0.3 to (VSYS+0.3)
V
OUT4, OUT5, OUT6, OUT7 to GA
-0.3 to (VINL + 0.3)
V
-0.3 to +0.3
V
Operating Ambient Temperature
-40 to 85
°C
Maximum Junction Temperature
125
°C
Maximum Power Dissipation
TQFN55-40 (Thermal Resistance θJA = 30oC/W)
2.7
W
-65 to 150
°C
300
°C
nLBO, nRSTO, nSTAT to GA
GP12, GP3 to GA
Storage Temperature
Lead Temperature (Soldering, 10 sec)
c: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
-7-
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
SCL, SDA Input Low
VVSYS = 3.1V to 5.5V, TA = -40ºC to 85ºC
SCL, SDA Input High
VVSYS = 3.1V to 5.5V, TA = -40ºC to 85ºC
TYP
UNIT
0.35
V
1.55
V
SDA Leakage Current
SCL Leakage Current
8
SDA Output Low
MAX
IOL = 5mA
1
µA
18
µA
0.35
V
SCL Clock Period, tSCL
1.5
µs
SDA Data Setup Time, tSU
100
ns
SDA Data Hold Time, tHD
300
ns
Start Setup Time, tST
For Start Condition
100
ns
Stop Setup Time, tSP
For Stop Condition
100
ns
Figure 1:
I2C Compatible Serial Bus Timing
tSCL
SCL
tST
tHD
tSU
tSP
SDA
Start
condition
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
Stop
condition
-8-
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
GLOBAL REGISTER MAP
BITS
OUTPUT ADDRESS
SYS
SYS
0x00
0x01
REG1
0x20
REG1
0x22
REG2
REG2
REG3
REG3
REG4
REG4
REG5
REG5
REG6
REG6
REG7
REG7
APCH
APCH
APCH
APCH
0x30
0x32
0x40
0x42
0x50
0x51
0x54
0x55
0x60
0x61
0x64
0x65
0x70
0x71
0x78
0x7A
NAME
D7
D6
D5
D4
D3
TRST
nSYSMODE
Reserved
nSYSSTAT
SYSLEV[3]
D2
D1
D0
SYSLEV[2] SYSLEV[1] SYSLEV[0]
DEFAULTc
0
1
0
R
0
1
NAME
Reserved
Reserved
Reserved
Reserved
SCRATCH
SCRATCH
1
1
SCRATCH SCRATCH
DEFAULTc
0
0
0
0
0
0
0
0
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
0
1
1
1
0
0
1
OK
NAME
ON
PHASE
MODE
Reserved
Reserved
Reserved
Reserved
DEFAULTc
0
0
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
0
0
1
1
0
1
0
NAME
ON
PHASE
MODE
Reserved
Reserved
Reserved
Reserved
OK
DEFAULTc
0
0
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
0
0
1
1
0
1
0
NAME
ON
Reserved
MODE
Reserved
Reserved
Reserved
Reserved
OK
DEFAULTc
0
0
0
0
0
0
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
0
0
1
1
0
0
0
NAME
ON
DIS
LOWIQ
Reserved
Reserved
Reserved
Reserved
OK
DEFAULTc
0
1
0
0
0
0
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
0
0
1
1
0
0
0
NAME
ON
DIS
LOWIQ
Reserved
Reserved
Reserved
Reserved
OK
DEFAULTc
0
1
0
0
0
0
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
0
0
1
1
0
0
0
NAME
ON
DIS
LOWIQ
Reserved
Reserved
Reserved
Reserved
OK
DEFAULTc
0
1
0
0
0
0
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
0
1
1
1
0
0
1
NAME
ON
DIS
LOWIQ
Reserved
Reserved
Reserved
Reserved
OK
DEFAULTc
0
1
0
0
0
0
0
R
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
1
0
0
0
0
DEFAULTc
0
1
NAME
SUSCHG
Reserved
TOTTIMO[1] TOTTIMO[0] PRETIMO[1] PRETIMO[0] OVPSET[1] OVPSET[0]
DEFAULTc
0
0
1
0
1
0
0
0
NAME
Reserved
Reserved
Reserved
Reserved
TIMRDAT
TEMPDAT
INDAT
CHGDAT
0
0
DEFAULTc
0
0
NAME
Reserved
Reserved
DEFAULTc
0
0
CSTATE[0] CSTATE[1]
R
R
R
R
R
R
Reserved
Reserved
ACINSTAT
Reserved
R
R
R
R
c: Default values of ACT8930QJ133-T.
2: All bits are automatically cleared to default values when the input power is removed or falls below the system UVLO.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
-9-
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
REGISTER AND BIT DESCRIPTIONS
Table 1:
Global Register Map
OUTPUT ADDRESS BIT
NAME
ACCESS
DESCRIPTION
SYS
0x00
[7]
TRST
R/W
Reset Timer Setting. Defines the reset time-out threshold. Reset
time-out is 65ms when value is 1, reset time-out is 260ms when
value is 0. See nRSTO Output section for more information.
SYS
0x00
[6]
nSYSMODE
R/W
SYSLEV Mode Select. Defines the response to the SYSLEV
voltage detector, 1: Do nothing, 0: automatic shutdown when
VVSYS falls below the programmed SYSLEV threshold.
SYS
0x00
[5]
-
R
Reserved.
SYS
0x00
[4]
nSYSSTAT
R
System Voltage Status. Value is 1 when VVSYS is lower than the
SYSLEV voltage threshold, value is 0 when VVSYS is higher than
the system voltage detection threshold.
SYS
0x00
[3:0]
SYSLEV
R/W
System Voltage Detect Threshold. Defines the SYSLEV voltage
threshold. See the Programmable System Voltage Monitor
section for more information.
SYS
0x01
[7:4]
-
R/W
Reserved.
SYS
0x01
[3:0]
SCRATCH
R/W
Scratchpad Bits. Non-functional bits, maybe be used by user to
store system status information. Volatile bits, which are cleared
when system voltage falls below UVLO threshold.
REG1
0x20
[7:6]
-
R
REG1
0x20
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG1
0x22
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG1
0x22
[6]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG1
0x22
[5]
MODE
R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-savings
mode under light-load conditions.
REG1
0x22
[4:1]
-
R
Reserved.
Reserved.
REG1
0x22
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG2
0x30
[7:6]
-
R
Reserved.
REG2
0x30
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG2
0x32
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG2
0x32
[6]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
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- 10 Active-Semi Proprietary―For Authorized Recipients and Customers
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I2CTM is a trademark of NXP.
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT ADDRESS
BIT
NAME
ACCESS
DESCRIPTION
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to powersavings mode under light-load conditions.
REG2
0x32
[5]
MODE
R/W
REG2
0x32
[4:1]
-
R
Reserved.
REG2
0x32
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG3
0x40
[7:6]
-
R
Reserved.
REG3
0x40
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG3
0x42
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG3
0x42
[6]
-
R
REG3
0x42
[5]
MODE
R/W
REG3
0x42
[4:1]
-
R
Reserved.
REG3
0x42
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG4
0x50
[7:6]
-
R
Reserved.
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to powersavings mode under light-load conditions.
Reserved.
REG4
0x50
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG4
0x51
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG4
0x51
[6]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
REG4
0x51
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG4
0x51
[4:1]
-
R
Reserved.
REG4
0x51
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG5
0x54
[7:6]
-
R
Reserved.
REG5
0x54
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG5
0x55
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG5
0x55
[6]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
REG5
0x55
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG5
0x55
[4:1]
-
R
Reserved.
REG5
0x55
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Innovative PowerTM
- 11 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT
ADDRESS
BIT
NAME
ACCESS
REG6
0x60
[7:6]
-
R
DESCRIPTION
Reserved.
REG6
0x60
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG6
0x61
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG6
0x61
[6]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
REG6
0x61
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG6
0x61
[4:1]
-
R
Reserved.
REG6
0x61
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG7
0x64
[7:6]
-
R
Reserved.
REG7
0x64
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG7
0x65
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG7
0x65
[6]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
REG7
0x65
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG7
0x65
[4:1]
-
R
Reserved.
REG7
0x65
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
APCH
0x70
[7:0]
-
R/W
Reserved.
APCH
0x71
[7]
SUSCHG
R/W
Charge Suspend Control Input. Set bit to 1 to suspend
charging, clear bit to 0 to allow charging to resume.
APCH
0x71
[6]
-
R/W
Reserved.
APCH
0x71
[5:4]
TOTTIMO
R/W
Total Charge Time-out Selection. See the Charge Safety
Timers section for more information.
APCH
0x71
[3:2]
PRETIMO
R/W
Precondition Charge Time-out Selection. See the Charge
Safety Timers section for more information.
APCH
0x71
[1:0]
OVPSET
R/W
Input Over-Voltage Protection Threshold Selection. See the
Input Over-Voltage Protection section for more information.
APCH
0x78
[7:4]
-
R
Reserved.
APCH
0x78
[3]
TIMRDAT1
R
Charge Timer Status. Value is 1 when precondition time-out
or total charge time-out occurs. Value is 0 in other case.
APCH
0x78
[2]
TEMPDAT1
R
Temperature Status. Value is 0 when battery temperature is
outside of valid range. Value is 1 when battery temperature is
inside of valid range.
c: Valid only when CHGIN UVLO Threshold<VCHGIN<CHGIN OVP Threshold.
Innovative PowerTM
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I2CTM is a trademark of NXP.
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT
ADDRESS
BIT
NAME
ACCESS
DESCRIPTION
APCH
0x78
[1]
INDAT
R
Input Voltage Status. Value is 1 when a valid input at CHGIN
is present. Value is 0 when a valid input at CHGIN is not
present.
APCH
0x78
[0]
CHGDAT1
R
Charge State Machine Status. Value is 1 indicates the
charger state machine is in EOC state, value is 0 indicates
the charger state machine is in other states.
APCH
0x7A
[7:6]
-
R
Reserved.
APCH
0x7A
[5:4]
CSTATE
R
Charge State. Values indicate the current charging state. See
the State Machine Status section for more information.
APCH
0x7A
[3:2]
-
R
Reserved.
APCH
0x7A
[1]
ACINSTAT
R
ACIN Status. Indicates the state of the ACIN input, typically in
order to identify the type of input supply connected. Value is
1 when ACIN is above the 1.2V precision threshold, value is
0 when ACIN is below this threshold.
APCH
0x7A
[0]
-
R
Reserved.
Innovative PowerTM
- 13 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Input Voltage Range
MIN
TYP
2.7
MAX
UNIT
5.5
V
2.65
V
UVLO Threshold Voltage
VVSYS Rising
UVLO Hysteresis
VVSYS Falling
200
mV
Supply Current
All Regulators Enabled
420
µA
Shutdown Supply Current
All Regulators Disabled
8
18
µA
2
2.2
MHz
2.2
Oscillator Frequency
1.8
Logic High Input Voltage1
1.4
2.45
V
Logic Low Input Voltage
Leakage Current
VnRSTO = 4.2V
LBI Threshold Voltage
VBAT Falling
VBAT Rising
LBI Hysteresis Threshold
Low Level Output Voltage
2
1.2
Temperature rising
Thermal Shutdown Hysteresis
V
1
µA
1.31
V
200
ISINK = 5mA
nRSTO Delay
Thermal Shutdown Temperature
1.03
0.4
mV
0.35
V
260e
ms
160
°C
20
°C
c: ON1, ON3, ON3, ON45, ON6, ON7 are logic inputs.
2: nLBO, nRSTO are open drain outputs.
3: Typical value shown. Actual value may vary from 227.9ms to 291.2ms.
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Operating Voltage Range
MIN
TYP
2.7
UVLO Threshold
Input Voltage Rising
UVLO Hysteresis
Input Voltage Falling
100
Standby Supply Current
Regulator Enabled
65
Shutdown Current
VVP = 5.5V, Regulator Disabled
0
Output Voltage Accuracy
2.5
VOUT ≥ 1.2V, IOUT = 10mA
VOUT < 1.2V, IOUT = 10mA
Line Regulation
VVP = Max (VNOM1 +1, 3.2V) to 5.5V
Load Regulation
IOUT = 10mA to IMAX
-1%
-2%
2
2.6
MAX
UNIT
5.5
V
2.7
V
mV
90
µA
1
µA
VNOM
c
1%
VNOM
c
2%
V
0.15
%/V
0.0017
%/mA
Power Good Threshold
VOUT Rising
93
%VNOM
Power Good Hysteresis
VOUT Falling
2
%VNOM
Oscillator Frequency
VOUT ≥ 20% of VNOM
1.8
VOUT = 0V
2
2.2
MHz
500
kHz
Soft-Start Period
400
µs
Minimum On-Time
75
ns
REG1
Maximum Output Current
1.1
Current Limit
1.55
A
1.8
2.05
A
PMOS On-Resistance
ISW1 = -100mA
0.16
Ω
NMOS On-Resistance
ISW1 = 100mA
0.16
Ω
SW1 Leakage Current
VVP1 = 5.5V, VSW1 = 0 or 5.5V
0
1
µA
REG2
Maximum Output Current
1.1
Current Limit
1.55
PMOS On-Resistance
A
1.8
ISW2 = -100mA
0.16
NMOS On-Resistance
ISW2 = 100mA
0.16
SW2 Leakage Current
VVP2 = 5.5V, VSW2 = 0 or 5.5V
0
2.05
A
Ω
Ω
1
µA
REG3
Maximum Output Current
1.3
Current Limit
1.8
A
2.1
2.5
A
PMOS On-Resistance
ISW3 = -100mA
0.16
Ω
NMOS On-Resistance
ISW3 = 100mA
0.16
Ω
SW3 Leakage Current
VVP3 = 5.5V, VSW3 = 0 or 5.5V
0
1
µA
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
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- 15 Active-Semi Proprietary―For Authorized Recipients and Customers
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
LOW-NOISE LDO ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, COUT4 = COUT5 = COUT6 = COUT7 = 3.3µF, LOWIQ[ ] = [0], TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
Output Voltage Accuracy
Line Regulation
Load Regulation
Power Supply Rejection Ratio
Supply Current per Output
MIN
MAX
UNIT
5.5
V
c
2%
4%
VOUT ≥ 1.2V, TA = 25°C, IOUT = 10mA
-1%
VNOM
VOUT < 1.2V, TA = 25°C, IOUT = 10mA
-2%
VNOMc
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V,
LOWIQ[ ] = [0]
0.05
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
LOWIQ[ ] = [1]
0.5
IOUT = 1mA to IMAX2
0.08
V
mV/V
f = 1kHz, IOUT = 20mA, VOUT =1.2V
75
f = 10kHz, IOUT = 20mA, VOUT =1.2V
65
V/A
dB
Regulator Enabled, LOWIQ[ ] = [0]
37
60
Regulator Enabled, LOWIQ[ ] = [1]
31
52
0
1
Regulator Disabled
Soft-Start Period
TYP
2.5
µA
VOUT = 2.9V
140
µs
Power Good Threshold
VOUT Rising
89
%
Power Good Hysteresis
VOUT Falling
3
%
Output Noise
IOUT = 20mA, f = 10Hz to 100kHz, VOUT =
1.2V
50
µVRMS
Discharge Resistance
LDO Disabled, DIS[ ] = 1
1.5
kΩ
IOUT = 160mA, VOUT > 3.1V
90
REG4
Dropout Voltagee
Maximum Output Current
Current Limitf
VOUT = 95% of regulation voltage
Stable COUT4 Range
180
mV
320
mA
370
mA
3.3
20
µF
280
mV
REG5
Dropout Voltage
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current
Current Limit
VOUT = 95% of regulation voltage
Stable COUT5 Range
140
320
mA
370
mA
3.3
20
µF
180
mV
REG6
Dropout Voltage
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current
Current Limit
VOUT = 95% of regulation voltage
Stable COUT6 Range
90
320
mA
370
mA
3.3
20
µF
280
mV
REG7
Dropout Voltage
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current
Current Limit
140
320
VOUT = 95% of regulation voltage
Stable COUT7 Range
mA
370
mA
3.3
20
µF
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher).
f: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 30% (typ)
Innovative PowerTM
- 16 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
ActivePathTM CHARGER ELECTRICAL CHARACTERISTICS
(VCHGIN = 5.0V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6.0
V
3.9
V
ActivePath
CHGIN Operating Voltage Range
4.35
CHGIN UVLO Threshold
CHGIN Voltage Rising
CHGIN UVLO Hysteresis
CHGIN Voltage Falling
CHGIN OVP Threshold
CHGIN Voltage Rising
CHGIN OVP Hysteresis
CHGIN Voltage Falling
0.4
VCHGIN < VUVLO
35
70
µA
VCHGIN < VBAT + 50mV, VCHGIN > VUVLO
100
200
µA
VCHGIN > VBAT + 150mV, VCHGIN > VUVLO
Charger disabled, IVSYS = 0mA
1.3
2.0
mA
IVSYS = 100mA
0.3
Ω
A
CHGIN Supply Current
CHGIN to VSYS On-Resistance
CHGIN to VSYS Current Limit
3.1
3.5
0.5
6.0
6.6
V
7.2
V
V
ACIN = VSYS
1.5
2
ACIN = GA, CHGLEV = GA
80
90
100
ACIN = GA, CHGLEV = VSYS
400
450
500
IVSYS = 10mA
4.45
4.6
4.8
V
4
8
12
mA
1
µA
mA
VSYS REGULATION
VSYS Regulated Voltage
nSTAT OUTPUT
nSTAT Sink current
VnSTAT = 2V
nSTAT Leakage Current
VnSTAT = 4.2V
ACIN AND CHGLEV INPUTS
CHGLEV Logic High Input Voltage
1.4
V
CHGLEV Logic Low Input Voltage
CHGLEV Leakage Current
VCHGLEV = 4.2V
ACIN Voltage Thresholds
ACIN voltage rising
ACIN Hysteresis voltage threshold
ACIN voltage falling
ACIN Leakage Current
VACIN = 4.2V
1.03
1.2
0.4
V
1
µA
1.31
V
200
mV
1
µA
TH INPUT
TH Pull-Up Current
VCHGIN > VBAT + 100mV, Hysteresis = 50mV
91
102
110
µA
VTH Upper Temperature Voltage
Threshold (VTHH)
Hot Detect NTC Thermistor
2.44
2.51
2.58
V
VTH Lower Temperature Voltage
Threshold (VTHL)
Cold Detect NTC Thermistor
0.47
0.50
0.53
V
VTH Hysteresis
Upper and Lower Thresholds
Innovative PowerTM
- 17 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
30
mV
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
ActivePathTM CHARGER ELECTRICAL CHARACTERISTICS CONT’D
(VCHGIN = 5.0V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CHARGER
BAT Reverse Leakage Current
VCHGIN = 0V, VBAT = 4.2V, IVSYS = 0mA
BAT to VSYS On-Resistance
ISET Pin Voltage
Charge Termination Voltage
Charge Current
Precondition Charge Current
µA
70
mΩ
Fast Charge
1.2
Precondition
0.13
V
TA = -20°C to 70°C
4.179
4.2
4.221
TA = -40°C to 85°C
4.170
4.2
4.230
ACIN = VSYS, CHGLEV = VSYS
-10%
ICHG1
+10%
ACIN = VSYS, CHGLEV = GA
-10%
ICHG/5
+10%
ACIN = GA, CHGLEV = VSYS
400
450
500
ACIN = GA, CHGLEV = GA
80
90
100
VBAT = 3.8V,
RISET = 6.8k
VBAT = 2.7V,
RISET = 6.8k
ACIN = VSYS, CHGLEV = VSYS
10% ICHG
ACIN = VSYS, CHGLEV = GA
10% ICHG
ACIN = GA, CHGLEV = VSYS
45
ACIN = GA, CHGLEV = GA
45
Precondition Threshold Voltage
VBAT Voltage Rising
Precondition Threshold
Hysteresis
VBAT Voltage Falling
END-OF-CHARGE Current
Threshold
8
VBAT = 4.15V
2.75
2.85
10% ICHG
ACIN = VSYS, CHGLEV = GA
10% ICHG
ACIN = GA, CHGLEV = VSYS
45
ACIN = GA, CHGLEV = GA
45
mA
mA
3.0
150
ACIN = VSYS, CHGLEV = VSYS
V
V
mV
mA
Charge Restart Threshold
VVSYS - VBAT, VBAT Falling
Precondition Safety Timer
PRETIMO[ ] = 10
80
min
Total Safety Timer
TOTTIMO[ ] = 10
5
hr
100
°C
Thermal Regulation Threshold
190
205
220
mV
c: RISET (kΩ) = 2336 × (1V/ICHG (mA)) - 0.205
Innovative PowerTM
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
Frequency vs. Temperature
VREF vs. Temperature
0
-0.42
2
Frequency (%)
VREF (%)
0.42
2.5
-20
0
20
40
60
80
100
1.5
1
0.5
0
-0.5
Typical VREF=1.2V
-0.84
-40
ACT8930-002
ACT8930-001
0.84
Typical Oscillator Frequency=2MHz
-1
-40
120
-20
0
20
40
Temperature (°C)
Temperature (°C)
ON1 Startup Sequence
ON2 Startup Sequence
60
ACT8930-004
ACT8930-003
CH1
80 85
CH1
CH2
CH2
CH3
CH1: ON2, 2V/div
CH2: VOUT2, 500mV/div
TIME: 400µs/div
CH1: ON1, 2V/div
CH2: VOUT1, 2V/div
CH3: VnRSTO, 2V/div
TIME: 40ms/div
ON3 Startup Sequence
ON4, 5 Startup Sequence
ACT8930-006
ACT8930-005
CH1
CH1
CH2
CH2
CH3
CH1: ON3, 2V/div
CH2: VOUT3, 500mV/div
TIME: 400µs/div
Innovative PowerTM
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I2CTM is a trademark of NXP.
CH1: ON4, 5, 2V/div
CH2: VOUT4, 500mV/div
CH3: VOUT5, 500mV/div
TIME: 100µs//div
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
ON6 startup sequence
ON7 startup sequence
ACT8930-008
ACT8930-007
CH1
CH1
CH2
CH2
CH1: ON6, 2V/div
CH2: VOUT6, 500mV/div
TIME: 100µs/div
CH1: ON7, 2V/div
CH2: VOUT7, 1V/div
TIME: 100µs/div
REG1 Efficiency vs. Output Current
VIN = 4.2V
60
VOUT = 1.3V
VIN = 3.6V
80
Efficiency (%)
VIN = 3.6V
VIN=5.0V
100
40
ACT8930-010
VOUT = 3.3V
80
Efficiency (%)
REG2 Efficiency vs. Output Current
ACT8930-009
100
VIN=5.0V
VIN = 4.2V
60
40
20
20
0
0
1
10
100
10
1
1000
100
1000
Output Current (mA)
Output Current (mA)
REG3 Efficiency vs. Output Current
VOUT = 1.3V
VIN = 3.6V
Efficiency (%)
80
ACT8930-011
100
VIN=5.0V
VIN = 4.2V
60
40
20
0
1
10
100
1000
Output Current (mA)
Innovative PowerTM
- 20 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG1 Output Voltage vs. Temperature
3.298
3.294
3.290
-40
-20
0
20
40
60
80
100
VOUT2 = 1.3V
ILOAD = 100mA
1.306
Output Voltage (V)
3.302
1.310
1.302
1.298
1.294
1.290
-40
120
-20
0
40
60
80
100
120
REG1, 2, 3 MOSFET Resistance
REG3 Output Voltage vs. Temperature
1.298
ILOAD = 100mA
300
250
RDSON (mΩ)
1.302
ACT8930-015
350
ACT8930-014
VOUT3 = 1.3V
ILOAD = 100mA
1.306
Output Voltage (V)
20
Temperature (°C)
Temperature (°C)
1.310
ACT8930-013
VOUT1 = 3.3V
ILOAD = 100mA
3.306
Output Voltage (V)
REG2 Output Voltage vs. Temperature
ACT8930-012
3.310
200
PMOS
NMOS
150
100
1.294
50
1.290
-40
0
-20
0
20
40
60
80
100
120
Temperature (°C)
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3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG4, 5, 6 Output Voltage vs. Output Current
1.24
REG4, REG5, REG6
1.2
1.16
1.12
1.08
3.58
Output Voltage (V)
Output Voltage (V)
1.28
REG7 Output Voltage vs. Output Current
3.66
ACT8930-017
ACT8930-016
1.32
3.5
3.42
REG7
3.34
3.26
3.18
3.1
1.04
3.02
1
0
50
100
150
200
250
300
0
400
50
Dropout Voltage vs. Output Current
100
50
VIN = 3.3V
200
250
300
400
300
250
REG5, REG7
200
150
100
50
0
150
300
350
Dropout Voltage (mV)
Dropout Voltage (mV)
REG4, REG6
100
250
350
400
Output Current (mA)
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ACT8930-019
ACT89930-018
200
50
200
Dropout Voltage vs. Output Current
250
0
150
Output Current (mA)
Output Current (mA)
150
100
0
VIN = 3.3V
0
50
100
150
200
250
300
350
400
Output Current (mA)
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Output Voltage vs. Temperature
Region of Stable COUT ESR vs. Output Current
2.50
ESR (Ω)
Output Voltage (V)
3.00
2.00
REG4, REG5, REG6
1.50
ACT8930-021
REG7
3.50
1
ACT8930-020
4.00
0.1
Stable ESR
1.00
0.50
0.01
0
-40
-20
0
20
40
60
80
100
120
0
50
100
150
200
250
Output Current (mA)
Temperature (°C)
LDO Output Voltage Noise
ACT8930-022
CH1
CH1: VOUTx, 200µV/div (AC COUPLED)
TIME: 200ms/div
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
VSYS Voltage vs. CHGIN Voltage
VSYS Voltage vs. VSYS Current
4.0
ACIN/CHGLEV = 01
ACIN/CHGLEV = 11
3.0
2.0
5.0
VSYS Voltage (V)
VSYS Voltage (V)
5.0
5.2
ACT8930-024
ACT8930-023
6.0
4.8
VSYS = 4.6V
4.6
4.4
4.2
1.0
4.0
0
0
500
1000
1500
2000
2
0
2500
4
70
60
50
40
30
VCHGIN = 5V
ACIN = 0
CHGLEV = 0
90mA USB
0
0.0
Charger Current (mA)
1.5
2.0
2.5
3.0
3.5
4.0
350
300
250
200
150
VBAT Falling
VBAT Rising
100
0
0.0
4.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Battery Voltage (V)
Battery Voltage (V)
Charger Current vs. Battery Voltage
DCCC and Battery Supplement Modes
RISET = 2.4kΩ
VCHGIN = 5V
ACIN/CHGLEV = 11
800
4.5
ACT8930-028
1000
1.0
CHGLEV = 1
400 450mA USB
50
ACT8930-027
1200
0.5
VCHGIN = 5V
450 ACIN = 0
Charger Current (mA)
Charger Current (mA)
80
500
ACT8930-026
ACT8930-025
90
VBAT Falling
VBAT Rising
10
Charger Current vs. Battery Voltage
Charger Current vs. Battery Voltage
100
10
8
CHGIN Voltage (V)
VSYS Current (mA)
20
6
CH4
CH3
600
CH2
VBAT = 3.5V
VVSYS = 4.6V
IVSYS = 0-1.8A
ICHARGE = 1000mA
VCHGIN = 5.1V-3A
400
VBAT Falling
VBAT Rising
200
CH1
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Battery Voltage (V)
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
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CH1: IVSYS, 1.00A/div
CH2: IBAT, 1.00A/div
CH3: VBAT, 1.00V/div
CH4: VVSYS, 1V/div
TIME: 200ms/div
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
VAC Applied
VAC Removed
CH3
ACT8930-030
ACT8930-029
CH4
CH4
CH3
CH2
CH2
CH1
CH1
CH1: IBAT, 400mA/div
CH2: VBAT, 1V/div
CH3: VVSYS, 2V/div
CH4: VCHGIN, 5V/div
TIME: 40ms/div
VCHGIN = 5V
VBAT = 3.5V
RVSYS = 100Ω
ACIN/CHGLEV = 01
CH1: IBAT, 200mA/div
CH2: VVSYS, 2V/div
CH3: VBAT, 1V/div
CH4: VCHGIN, 5V/div
TIME: 100ms/div
VAC Applied
VAC Removed
CH3
ACT8930-032
ACT8930-031
CH4
VCHGIN = 5V
VBAT = 3.5V
RVSYS = 100Ω
ACIN/CHGLEV = 01
CH4
CH3
CH2
CH2
CH1
CH1
CH1: IBAT, 1A/div
CH2: VBAT, 2V/div
CH3: VVSYS, 2V/div
CH4: VCHGIN, 5V/div
TIME: 40ms/div
VCHGIN = 5V
VBAT = 3.97V
RVSYS = 47Ω
ACIN/CHGLEV = 11
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- 25 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
CH1: IBAT, 1A/div
CH2: VVSYS, 2V/div
CH3: VBAT, 2V/div
CH4: VCHGIN, 5V/div
TIME: 40ms/div
VCHGIN = 5V
VBAT = 3.97V
RVSYS = 47Ω
ACIN/CHGLEV = 11
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
SYSTEM CONTROL INFORMATION
Control Signals
nRSTO Output
Enable Inputs
ON1, ON2, ON3, ON45, ON6 and ON7 are
independent logic inputs for the regulators as
shown in Table 2. Drive to logic high to enable the
corresponding regulator(s); Drive to GA to disable.
nRSTO is an open-drain output which asserts low
when any one or more of the regulator reaches the
power-OK threshold. nRSTO remains low until the
reset time-out period expires. Connect a 10kΩ or
greater pull-up resistor from nRSTO to an
appropriate voltage supply (typically OUT1).
Table 2:
Control Pins
PIN NAME
REGULATOR(S)
ON1
OUT1
ON2
OUT2
ON3
OUT3
ON45
OUT4, OUT5
ON6
OUT6
ON7
OUT7
Figure 2:
Enable/Disable Sequence
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
FUNCTIONAL DESCRIPTION
I2C Interface
2
The ACT8930 features an I C interface that allows
advanced programming capability to enhance overall
system performance. To ensure compatibility with a
wide range of system processors, the I2C interface
supports clock speeds of up to 400kHz (“Fast-Mode”
operation) and uses standard I2C commands. I2C
write-byte commands are used to program the
ACT8930, and I2C read-byte commands are used to
read the ACT8930’s internal registers. The ACT8930
always operates as a slave device, and is addressed
using a 7-bit slave address followed by an eighth bit,
which indicates whether the transaction is a readoperation or a write-operation, [1011011x].
SDA is a bi-directional data line and SCL is a clock
input. The master device initiates a transaction by
issuing a START condition, defined by SDA
transitioning from high to low while SCL is high. Data
is transferred in 8-bit packets, beginning with the
MSB, and is clocked-in on the rising edge of SCL.
Each packet of data is followed by an “Acknowledge”
(ACK) bit, used to confirm that the data was
transmitted successfully.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com.
Housekeeping Functions
Programmable System Voltage Monitor
The ACT8930 features a programmable systemvoltage monitor, which monitors the voltage at VSYS
and compares it to a programmable threshold
voltage. The programmable voltage threshold is
programmed by SYSLEV[3:0], as shown in Table 3.
SYSLEV[ ] is set to 3.0V by default. There is a
200mV rising hysteresis on SYSLEV[ ] threshold
such that VVSYS needs to be 3.2V(typ) or higher in
order to power up the IC.
The nSYSSTAT[-] bit reflects the output of an
internal voltage comparator that monitors VVSYS
relative to the SYSLEV[-] voltage threshold, the
value of nSYSTAT[-] = 1 when VVSYS is lower than
the SYSLEV[-] voltage threshold, and nSYSTAT[-] =
0 when VVSYS is higher than the SYSLEV[-] voltage
threshold. Note that the SYSLEV[-] voltage threshold
is defined for falling voltages, and that the
comparator produces about 200mV of hysteresis at
VSYS. As a result, once VVSYS falls below the
SYSLEV threshold, its voltage must increase by
more than about 200mV to clear that condition.
After the IC is powered up, the ACT8930 responds in
one of two ways when the voltage at VSYS falls
below the SYSLEV[-] voltage threshold:
1) If nSYSMODE[-] = 1 (default case), no action is
taken by ACT8930.
2) If nSYSMODE[-] = 0, when VVSYS falls below the
programmable threshold the ACT8930 shuts
down, immediately disabling all regulators. This
option is useful for implementing a
programmable “under-voltage lockout” function
that forces the system off when the battery
voltage falls below the SYSLEV threshold
voltage. Since this option does not support a
controlled shutdown sequence, it is generally
used as a "fail-safe" to shut the system down
when the battery voltage is too low.
Table 3:
SYSLEV Falling Threshold
SYSLEV[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Precision Voltage Detector
The LBI input connects to one input of a precision
voltage comparator, which can be used to monitor a
system voltage such as the battery voltage. An
external resistive-divider network can be used to set
voltage monitoring thresholds, as shown in
Functional Block Diagram. The output of the
comparator is present at the nLBO open-drain
output.
Thermal Shutdown
The ACT8930 integrates thermal shutdown
protection circuitry to prevent damage resulting from
excessive thermal stress, as may be encountered
under fault conditions. This circuitry disables all
regulators if the ACT8930 die temperature exceeds
160°C, and prevents the regulators from being
enabled until the IC temperature drops by 20°C (typ).
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SYSLEV Falling Threshold
(Hysteresis = 200mV)
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
STEP-DOWN DC/DC REGULATORS
General Description
The ACT8930 features three synchronous, fixedfrequency, current-mode PWM step down converters
that achieve peak efficiencies of up to 97%. REG3 is
capable of supplying up to 1300mA of output
current, while REG1 and REG2 support up to
1100mA. These regulators operate with a fixed
frequency of 2MHz, minimizing noise in sensitive
applications and allowing the use of small external
components.
100% Duty Cycle Operation
Each regulator is capable of operating at up to 100%
duty cycle. During 100% duty-cycle operation, the
high-side power MOSFET is held on continuously,
providing a direct connection from the input to the
output (through the inductor), ensuring the lowest
possible dropout voltage in battery powered
applications.
Synchronous Rectification
REG1, REG2, and REG3 each feature integrated nchannel synchronous rectifiers, maximizing efficiency
and minimizing the total solution size and cost by
eliminating the need for external rectifiers.
Soft-Start
When enabled, each output voltages tracks an
internal 400μs soft-start ramp, minimizing input
current during startup and allowing each regulator to
power up in a smooth, monotonic manner that is
independent of output load conditions.
Compensation
Each buck regulator utilizes current-mode control and
a proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over its full
operating range. No compensation design is
required; simply follow a few simple guidelines
described below when choosing external
components.
Input Capacitor Selection
The input capacitor reduces peak currents and noise
induced upon the voltage source. A 4.7μF ceramic
capacitor is recommended for each regulator in most
applications.
Output Capacitor Selection
For most applications, 22μF ceramic output
capacitors are recommended for REG1, REG2, and
REG3.
Despite the advantages of ceramic capacitors, care
must be taken during the design process to ensure
stable operation over the full operating voltage and
temperature range. Ceramic capacitors are available
in a variety of dielectrics, each of which exhibits
different characteristics that can greatly affect
performance over their temperature and voltage
ranges.
Two of the most common dielectrics are Y5V and
X5R. Whereas Y5V dielectrics are inexpensive and
can provide high capacitance in small packages, their
capacitance varies greatly over their voltage and
temperature ranges and are not recommended for
DC/DC applications. X5R and X7R dielectrics are
more suitable for output capacitor applications, as
their characteristics are more stable over their
operating ranges, and are highly recommended.
Inductor Selection
REG1, REG2, and REG3 utilize current-mode control
and a proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over their full
operating range. These devices were optimized for
operation with 2.2μH inductors, although inductors in
the 1.5μH to 3.3μH range can be used. Choose an
inductor with a low DC-resistance, and avoid inductor
saturation by choosing inductors with DC ratings that
exceed the maximum output current by at least 30%.
Configuration Options
Output Voltage Programming
Each regulator powers up and regulates to its default
output voltage. Once the system is enabled, each
regulator's output voltage may be independently
programmed to a different value, typically in order to
minimize the power consumption of the
microprocessor during some operating modes.
Program the output voltages via the I2C serial
interface by writing to the regulator's VSET[-] register
as shown in Table 4.
Enable / Disable Control
During normal operation, each buck may be enabled
or disabled via the I2C interface by writing to that
regulator's ON[ ] bit. To regulator accept rising or
falling edge of ON[ ] bit as on/off signal. To enable
the regulator, clear ON[ ] to 0 first then set to 1. To
disable the regulator, set ON[ ] to 1 first then clear it
to 0.
Operating Mode
By default, REG1, REG2, and REG3 each operate in
fixed-frequency PWM mode at medium to heavy
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ACT8930
Rev 5, 17-Sep-13
loads, while automatically transitioning to a
proprietary power-saving mode at light loads in order
to maximize standby battery life. In applications
where low noise is critical, force fixed-frequency
PWM operation across the entire load current range,
at the expense of light-load efficiency, by setting the
MODE[ ] bit to 1.
Output OK[ ]
Each DC/DC features a power-OK status bit that can
be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the powerOK threshold, typically 7% below the programmed
regulation voltage, that regulator's OK[ ] bit will be 0.
via if possible. The inductor, input filter capacitor, and
output filter capacitor should be connected as close
together as possible, with short, direct, and wide
traces. The ground nodes for each regulator's power
loop should be connected at a single point in a starground configuration, and this point should be
connected to the backside ground plane with multiple
via. The output node for each regulator should be
connected to its corresponding OUTx pin through the
shortest possible route, while keeping sufficient
distance from switching nodes to prevent noise
injection. Finally, the exposed pad should be directly
connected to the backside ground plane using
multiple via to achieve low electrical and thermal
resistance.
PCB Layout Considerations
High switching frequencies and large peak currents
make PC board layout an important part of step-down
DC/DC converter design. A good design minimizes
excessive EMI on the feedback paths and voltage
gradients in the ground plane, both of which can
result in instability or regulation errors.
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
close as possible to the IC, and avoiding the use of
Table 4:
REGx/VSET[ ] Output Voltage Setting
REGx/VSET[2:0]
REGx/VSET[5:3]
000
001
010
011
100
101
110
111
000
0.600
0.800
1.000
1.200
1.600
2.000
2.400
3.200
001
0.625
0.825
1.025
1.250
1.650
2.050
2.500
3.300
010
0.650
0.850
1.050
1.300
1.700
2.100
2.600
3.400
011
0.675
0.875
1.075
1.350
1.750
2.150
2.700
3.500
100
0.700
0.900
1.100
1.400
1.800
2.200
2.800
3.600
101
0.725
0.925
1.125
1.450
1.850
2.250
2.900
3.700
110
0.750
0.950
1.150
1.500
1.900
2.300
3.000
3.800
111
0.775
0.975
1.175
1.550
1.950
2.350
3.100
3.900
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ACT8930
Rev 5, 17-Sep-13
LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS
General Description
REG4, REG5, REG6, and REG7 are low-noise,
low-dropout linear regulators (LDOs) that supply up
to 320mA. Each LDO has been optimized to
achieve low noise and high-PSRR, achieving more
than 65dB PSRR at frequencies up to 10kHz.
Output Current Limit
Each LDO contains current-limit circuitry featuring a
current-limit fold-back function. During normal and
moderate overload conditions, the regulators can
support more than their rated output currents.
During extreme overload conditions, however, the
current limit is reduced by approximately 30%,
reducing power dissipation within the IC.
Compensation
The LDOs are internally compensated and require
very little design effort, simply select input and
output capacitors according to the guidelines below.
Input Capacitor Selection
Each LDO requires a small ceramic input capacitor
to supply current to support fast transients at the
input of the LDO. Bypassing each INL pin to GA
with 1μF. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
Output Capacitor Selection
Each LDO requires a small 3.3μF ceramic output
capacitor for stability. For best performance, each
output capacitor should be connected directly
between the output and GA pins, as close to the
output as possible, and with a short, direct
connection. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
Configuration Options
Output Voltage Programming
By default, each LDO powers up and regulates to
its default output voltage. Once the system is
enabled, each output voltage may be independently
programmed to a different value by writing to the
regulator's VSET[-] register via the I2C serial
interface as shown in Table 4.
Enable / Disable Control
During normal operation, each LDO may be
enabled or disabled via the I2C interface by writing
to that LDO's ON[ ] bit. To regulator accept rising or
falling edge of ON[ ] bit as on/off signal. To enable
the regulator, clear ON[ ] to 0 first then set to 1. To
disable the regulator, set ON[ ] to 1 first then clear it
to 0.
Output Discharge
Each of the ACT8930’s LDOs features an optional
output discharge function, which discharges the
output to ground through a 1.5kΩ resistance when
the LDO is disabled. This feature may be enabled
or disabled by setting DIS[-]; set DIS[-] to 1 to
enable this function, clear DIS[-] to 0 to disable it.
Low-Power Mode
Each of ACT8930's LDOs features a LOWIQ[-] bit
which, when set to 1, reduces the LDO's quiescent
current by about 16%, saving power and extending
battery lifetime.
Output OK[ ]
Each LDO features a power-OK status bit that
be read by the system microprocessor via
interface. If an output voltage is lower than
power-OK threshold, typically 11% below
programmed regulation voltage, the value of
regulator's OK[-] bit will be 0.
PCB Layout Considerations
The ACT8930’s LDOs provide good DC, AC, and
noise performance over a wide range of operating
conditions, and are relatively insensitive to layout
considerations. When designing a PCB, however,
careful layout is necessary to prevent other circuitry
from degrading LDO performance.
A good design places input and output capacitors
as close to the LDO inputs and output as possible,
and utilizes a star-ground configuration for all
regulators to prevent noise-coupling through
ground. Output traces should be routed to avoid
close proximity to noisy nodes, particularly the SW
nodes of the DC/DCs.
REFBP is a noise-filtered reference, and internally
has a direct connection to the linear regulator
controller. Any noise injected onto REFBP will
directly affect the outputs of the linear regulators,
and therefore special care should be taken to
ensure that no noise is injected to the outputs via
REFBP. As with the LDO output capacitors, the
REFBP bypass capacitor should be placed as close
to the IC as possible, with short, direct connections
to the star-ground. Avoid the use of via whenever
possible. Noisy nodes, such as from the DC/DCs,
should be routed as far away from REFBP as
possible.
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
can
the
the
the
that
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
ActivePathTM CHARGER
General Description
The ACT8930 features an advanced battery
charger that incorporates the patent-pending
ActivePath architecture for system power selection.
This combination of circuits provides a complete,
advanced battery-management system that
automatically selects the best available input
supply, manages charge current to ensure system
power availability, and provides a complete, highaccuracy (±0.5%), thermally regulated, full-featured
single-cell linear Li+ charger that can withstand
input voltages of up to 12V.
In an input over-voltage condition this circuit limits
VVSYS to 4.6V, protecting any circuitry connected to
VSYS from the over-voltage condition, which may
exceed this circuitry's voltage capability. This circuit
is capable of withstanding input voltages of up to
12V.
Table 5:
Input Over-Voltage Protection Setting
OVPSET[1]
OVPSET[0]
OVP THRESHOLD
0
0
6.6V
0
1
7.0V
ActivePath Architecture
1
0
7.5V
The ActivePath architecture
important functions:
1
1
8.0V
performs
three
1) System Configuration Optimization
2) Input Protection
3) Battery-Management
System Configuration Optimization
The ActivePath circuitry monitors the state of the
input supply, the battery, and the system, and
automatically reconfigures itself to optimize the
power system. If a valid input supply is present,
ActivePath powers the system from the input while
charging the battery in parallel. This allows the
battery to charge as quickly as possible, while
supplying the system. If a valid input supply is not
present, ActivePath powers the system from the
battery. Finally, if the input is present and the
system current requirement exceeds the capability
of the input supply, ActivePath allows system power
to be drawn from both the battery and the input
supply.
Input Protection
Input Over-Voltage Protection
The ActivePath circuitry features input over-voltage
protection circuitry. This circuitry disables charging
when the input voltage exceeds the voltage set by
OVPSET[-] as shown in Table 5, but stands off the
input voltage in order to protect the system. Note
that the adjustable OVP threshold is intended to
provide the charge cycle with adjustable immunity
against upward voltage transients on the input, and
is not intended to allow continuous charging with
input voltages above the charger's normal operating
voltage range. Independent of the OVPSET[-]
setting, the charge cycle is not allowed to resume
until the input voltage falls back into the charger's
normal operating voltage range (i.e. below 6.0V).
Input Supply Overload Protection
The ActivePath circuitry monitors and limits the total
current drawn from the input supply to a value set
by the ACIN and CHGLEV inputs, as well as the
resistor connected to ISET. Drive ACIN to a logiclow for “USB Mode”, which limits the input current to
either 100mA, when CHGLEV is driven to a logiclow, or 450mA, when CHGLEV is driven to a logichigh. Drive ACIN to a logic-high for “AC-Mode”,
which limits the input current to 2A, typically.
Input Under Voltage Lockout
If the input voltage applied to CHGIN falls below
3.5V (typ), an input under-voltage condition is
detected and the charger is disabled. Once an input
under-voltage condition is detected, a new charge
cycle will initiate when the input exceeds the undervoltage threshold by at least 500mV.
Battery Management
The ACT8930 features a full-featured, intelligent
charger for Lithium-based cells, and was designed
specifically to provide a complete charging solution
with minimum system design effort.
The core of the charger is a CC/CV (ConstantCurrent/Constant-Voltage), linear-mode charge
controller. This controller incorporates current and
voltage sense circuitry, an internal 70mΩ power
MOSFET, thermal-regulation circuitry, a fullfeatured state machine that implements charge
control and safety features, and circuitry that
eliminates the reverse blocking diode required by
conventional charger designs.
The charge termination voltage is highly accurate
(±0.5%), and features a selection of charge safety
time-out periods that protect the system from
operation with damaged cells. Other features
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ACT8930
Rev 5, 17-Sep-13
include pin-programmable fast-charge current and
one current-limited nSTAT output that can directly
drive LED indicator or provide a logic-level status
signal to the host microprocessor.
Dynamic Charge Current Control (DCCC)
The ACT8930's ActivePath charger features
dynamic charge current control (DCCC) circuitry,
which acts to ensure that the system remains
powered while operating within the maximum output
capability of the power adapter. The DCCC circuitry
continuously monitors VVSYS, and if the voltage at
VSYS drops by more than 200mV, the DCCC
circuitry automatically reduces charge current in
order to prevent VVSYS from continuing to drop.
Charge Current Programming
The ACT8930's ActivePath charger features a
flexible charge current-programming scheme that
combines the convenience of internal charge
current programming with the flexibility of resistor
based charge current programming. Current limits
and charge current programming are managed as a
function of the ACIN and CHGLEV pins, in
combination with RISET, the resistance connected to
the ISET pin.
ACIN is a logic input that configures the current-limit
of ActivePath's linear regulator as well as that of the
battery charger. ACIN features a precise 1.2V logic
threshold, so that the input voltage detection
threshold may be adjusted with a simple resistive
voltage divider. This input also allows a simple, lowcost dual-input charger switch to be implemented
with just a few, low-cost components.
When the voltage at ACIN is above the 1.2V
threshold, the charger operates in “AC-Mode” with a
charge current programmed by RISET, and the RISET
is given by:
RISET (kΩ) = 2336 × (1V/ICHG (mA)) - 0.205
With a given RISET then charge current will reduce 5
times when CHGLEV is driven low.
When ACIN is below the 1.2V threshold, the
charger operates in “USB-Mode”, with a maximum
CHGIN input current and charge current defined by
the CHGLEV input; 450mA, if CHGLEV is driven to
a logic-high, or 100mA, if CHGLEV is driven to a
logic-low.
The ACT8930's charge
summarized in Table 6.
current
settings
are
Note that the actual charge current may be limited
to a current lower than the programmed fast charge
current due to the ACT8930’s internal thermal
regulation loop. See the Thermal Regulation section
for more information.
INDAT[-] indicates the status of the CHGIN input
supply. A value of 1 indicates that a valid CHGIN
input (CHGIN UVLO Threshold<VCHGIN<CHGIN
OVP Threshold) is present, a value of 0 indicates a
valid input is not present. For example, in a dualinput charger application, knowing the state of the
ACIN input can identify which type of input supply
has been connected. The state of the ACIN input
can be read at any time by reading the
ACINSTAT[-] bit, where a value of 1 indicates that
the voltage at ACIN is above the 1.2V threshold
(indicating that a wall-cube has been attached), and
a value of 0 indicates that the voltage is below this
threshold (indicating that ACIN input is not valid and
USB supply input is selected).
Charge-Control State Machine
PRECONDITION State
A new charging cycle begins with the
PRECONDITION state, and operation continues in
this state until VBAT exceeds the Precondition
Threshold Voltage. When operating in
PRECONDITION state, the cell is charged at 10%
of the programmed maximum fast-charge constant
current, ICHG.
Once VBAT reaches the Precondition Threshold
Voltage, the state machine jumps to the FASTCHARGE state. If VBAT does not reach the
Precondition Threshold Voltage before the
Precondition Time-out period expires, then the state
machine jumps to the TIME-OUT-FAULT state in
order to prevent charging a damaged cell. See the
Charge Safety Timers section for more information.
Table 6:
ACIN and CHGLEV Inputs
ACIN
CHGLEV
CHARGE CURRENT
(mA)
PRECONDITION CHARGE CURRENT
(mA)
0
0
90
45
0
1
450
45
1
0
ICHG/5
10% × ICHG
1
1
ICHG
10% × ICHG
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- 32 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
Figure 3:
Typical Li+ charge profile and ACT8930 charge states
A: PRECONDITION State
B: FAST-CHARGE State
C: TOP-OFF State
D: END-OF-CHARGE State
Figure 4:
Charger State Diagram
TEMP NOT OK
ANY STATE
(VCHGIN < VBAT) OR (VCHGIN < VCHGIN UVLO)
OR (VCHGIN > VOVP) OR (SUSCHG[ ] = 1)
SUSPEND
TEMP-FAULT
(VCHGIN > VBAT) AND (VCHGIN > VCHGIN UVLO)
AND (VCHGIN < VOVP) AND (SUSCHG[ ] = 0)
TEMP OK
PRECONDITION
TIME-OUT-FAULT
PRECONDITION
Time-out
Total Time-out
(VBAT > 2.85V) AND
(TQUAL = 32ms)
FAST-CHARGE
(VBAT = VTERM ) AND
(TQUAL = 32ms)
(VBAT < VTERM - 205mV )
AND (TQUAL = 32ms)
TOP-OFF
(IBAT < 10% x ICHG) OR (Total
Time-out) AND (TQUAL = 32ms)
END-OF-CHARGE
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
FAST-CHARGE State
State Machine Status
In the FAST-CHARGE state, the charger operates
in constant-current (CC) mode and regulates the
charge current to the current set by RISET . Charging
continues in CC mode until VBAT reaches the charge
termination voltage (VTERM), at which point the statemachine jumps to the TOP-OFF state. If VBAT does
not reach VTERM before the total time out period
expires then the state-machine will jump to the
“EOC” state and will re-initiate a new charge cycle
after 32ms “relax”. See the Current Limits and
Charge Current Programming sections for more
information about setting the maximum charge
current.
The status of the charge state machine may be
read at any time by reading CSTATE[0:1] to
determine the current charging state.
TOP-OFF State
In the TOP-OFF state, the cell charges in constantvoltage (CV) mode. In CV mode operation, the
charger regulates its output voltage to the 4.20V
charge termination voltage, and the charge current
is naturally reduced as the cell approaches full
charge. Charging continues until the charge current
drops to END-OF-CHARGE current threshold, at
which point the state machine jumps to the ENDOF-CHARGE (EOC) state.
If the state-machine does not jump out of the TOPOFF state before the Total-Charge Time-out period
expires, the state machine jumps to the EOC state
and will re-initiate a new charge cycle if VBAT falls
below termination voltage 205mV (typ). For more
information about the charge safety timers, see the
Charging Safety Times section.
END-OF-CHARGE (EOC) State
In the END-OF-CHARGE (EOC) state, the charger
presents a high-impedance to the battery,
minimizing battery current drain and allowing the
cell to “relax”. The charger continues to monitor the
cell voltage, and re-initiates a charging sequence if
the cell voltage drops to 205mV (typ) below the
charge termination voltage.
SUSPEND State
The state-machine jumps to the SUSPEND state
any time the battery is removed, and any time the
input voltage either falls below the CHGIN UVLO
threshold or exceeds the OVP threshold. Once
none of these conditions are present, a new charge
cycle initiates.
A charging cycle may also be suspended manually
by setting the SUSPEND[ ] bit. In this case, initiate
a new charging sequence by clearing SUSPEND[ ]
to 0.
Table 7:
Charging Status Indication
CSTATE[0] CSTATE[1]
1
1
PRECONDITION State
1
0
FAST-CHARGE/
TOP-OFF State
0
1
END-OF-CHARGE State
0
0
SUSPEND/DISABLED/
FAULT State
Thermal Regulation
The charger features an internal thermal regulation
loop that monitors die temperature and reduces
charging current as needed to ensure that the die
temperature does not exceed the thermal regulation
threshold of 110°C. This feature protects against
excessive junction temperature and makes the
device more accommodating to aggressive thermal
designs. Note, however, that attention to good
thermal designs is required to achieve the fastest
possible charge time by maximizing charge current.
Charge Safety Timers
The charger features programmable charge safety
timers which help ensure a safe charge by
detecting potentially damaged cells. These timers
are programmable via the PRETIMO[1:0] and
TOTTIMO[1:0] bits, as shown in Table 8 and Table
9. Note that in order to account for reduced charge
current resulting from DCCC operation, the charge
time-out periods are extended proportionally to the
reduction in charge current. As a result, the actual
safety period may exceed the nominal timer period.
The status of the charge timers may be read at any
time by reading the TIMRDAT[ ] bit, where a value
of 0 indicates that neither charge timer has expired,
and a value of 1 indicates that one of the charge
timers has expired.
PRETIMO[1]
PRETIMO[0]
PRECONDITION
TIMEOUT PERIOD
0
0
40 mins
0
1
60 mins
1
0
80 mins
1
1
Disabled
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I2CTM is a trademark of NXP.
STATE MACHINE STATUS
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Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
Table 9:
Total Safety Timer Setting
TOTTIMO[1]
TOTTIMO[0]
TOTAL TIME-OUT
PERIOD
0
0
3 hrs
0
1
4 hrs
1
0
5 hrs
1
1
Disabled
Charge Status Indicator
The charger provides a charge-status indicator
output, nSTAT. nSTAT is an open-drain output
which sinks current when the charger is in an
active-charging state, and is high-Z otherwise.
nSTAT features an internal 8mA current limit, and is
capable of directly driving a LED without the need
of a current-limiting resistor or other external
circuitry. To drive an LED, simply connect the LED
between nSTAT pin and an appropriate supply,
such as VSYS. For a logic-level charge status
indication, simply connect a resistor from nSTAT to
an appropriate voltage supply.
Table 10:
Charging Status Indication
STATE
nSTAT
PRECONDITION
Active
FAST-CHARGE
Active
TOP-OFF
Active
END-OF-CHARGE
High-Z
SUSPEND
High-Z
TEMPERATURE FAULT
High-Z
TIMEOUT FAULT
High-Z
temperature of the battery pack by injecting a
102μA (typ) current into the thermistor (via the TH
pin) and sensing the voltage at TH. The voltage at
TH is continuously monitored, and charging is
suspended if the voltage at TH exceeds either of
the internal VTHH and VTHL thresholds of 0.5V and
2.51V, respectively.
The net resistance (from TH to GA) required to
cross the thresholds are given by:
102μA × RNOM × kHOT = 0.5V → RNOM × kHOT
≈ 5kΩ
102μA × RNOM × kCOLD = 2.51V → RNOM ×
kCOLD ≈ 25kΩ
where RNOM is the nominal thermistor resistance
at room temperature, and kHOT and kCOLD
represent the ratios of the thermistor's resistance at
the desired hot and cold thresholds, respectively, to
the resistance at 25°C.
The status of the battery temperature pin may be
read at any time by reading the TEMPDAT[-] bit,
where a value of 1 indicates that battery
temperature is within the valid range, and a value
of 0 indicates that battery temperature has
exceeded either of the thresholds.
Figure 5:
Simple Configuration
Reverse-Current Protection
The charger includes internal reverse-current
protection circuitry that eliminates the need for
blocking diodes, reducing solution size and cost as
well as dropout voltage relative to conventional
battery chargers. When the voltage at CHGIN falls
below VBAT, the charger automatically reconfigures
its power switch to minimize current drawn from the
battery.
Battery Temperature Monitoring
In a typical application, the TH pin is connected to
the battery pack's thermistor input, as shown in
Figure 5. The charger continuously monitors the
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8930
Rev 5, 17-Sep-13
TQFN55-40 PACKAGE OUTLINE AND DIMENSIONS
SYMBOL
A
A1
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
MIN
MAX
MIN
MAX
0.700
0.800
0.028
0.031
0.200 REF
0.008 REF
A2
0.000
0.050
0.000
0.002
b
0.150
0.250
0.006
0.010
D
4.900
5.100
0.193
0.201
E
4.900
5.100
0.193
0.201
D2
3.450
3.750
0.136
0.148
E2
3.450
3.750
0.136
0.148
e
L
R
0.400 BSC
0.300
0.500
0.300
0.016 BSC
0.012
0.020
0.012
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
[email protected] or visit http://www.active-semi.com.
is a registered trademark of Active-Semi.
Innovative PowerTM
- 36 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.