ETC ATTINY10

Features
• Utilizes the AVR® RISC Architecture
• High-performance and Low-power 8-bit RISC Architecture
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– 90 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
Nonvolatile Program and Data Memory
– 1K Byte of Flash Program Memory
QuickFlash™ One-time Programmable (ATtiny10)
In-System Programmable (ATtiny12)
Endurance: 1,000 Write/Erase Cycles (ATtiny11/12)
– 64 Bytes of In-System Programmable EEPROM Data Memory (ATtiny12)
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– Interrupt and Wake-up on Pin Change
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port (ATtiny12)
– Enhanced Power-on Reset Circuit (ATtiny12)
– Internal Calibrated RC Oscillator (ATtiny12)
Specification
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.2 mA
– Idle Mode: 0.5 mA
– Power-down Mode: <1 µA
Packages
– 8-pin PDIP and SOIC
ATtiny10 is the QuickFlash OTP Version of ATtiny11
Operating Voltages
– 1.8 - 5.5V (ATtiny12V-1)
– 2.7 - 5.5V (ATtiny11L-2 and ATtiny12L-4)
– 4.0 - 5.5V (ATtiny11-6 and ATtiny12-8)
Speed Grades
– 0 - 1 MHz (ATtiny12V-1)
– 0 - 2 MHz (ATtiny11L-2)
– 0 - 4 MHz (ATtiny12L-4)
– 0 - 6 MHz (ATtiny11-6)
– 0 - 8 MHz (ATtiny12-8)
8-bit
Microcontroller
with 1K Bytes
Flash
ATtiny10
ATtiny11
ATtiny12
Preliminary
Pin Configuration
ATtiny10/11
PDIP/SOIC
(RESET) PB5
(XTAL1) PB3
(XTAL2) PB4
GND
1
2
3
4
8
7
6
5
ATtiny12
PDIP/SOIC
VCC
PB2 (T0)
PB1 (INT0/AIN1)
PB0 (AIN0)
(RESET) PB5
(XTAL1) PB3
(XTAL2) PB4
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0/AIN1)
PB0 (MOSI/AIN0)
Rev. 1006B–10/99
1
Description
The ATtiny10/11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny10/11/12 achieves throughputs approaching 1 MIPS per MHz, allowing the
system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
Table 1. Parts Description
Device
Flash
EEPROM
Register
Voltage Range
Frequency
ATtiny10/11L
1K
-
32
2.7 - 5.5V
0-2 MHz
ATtiny10/11
1K
-
32
4.0 - 5.5V
0-6 MHz
ATtiny12V
1K
64 B
32
1.8 - 5.5V
0-1 MHz
ATtiny12L
1K
64 B
32
2.7 - 5.5V
0-4 MHz
ATtiny12
1K
64 B
32
4.0 - 5.5V
0-8 MHz
ATtiny10/11 Block Diagram
The ATtiny10/11 provides the following features: 1K bytes of Flash, up to five general-purpose I/O lines, one input line,
32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog
Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to continue functioning. The Power-down Mode saves the register contents but
freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt
on pin change features enable the ATtiny10/11 to be highly responsive to external events, still featuring the lowest power
consumption while in the power-down modes.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU
with Flash on a monolithic chip, the Atmel ATtiny10/11 is a powerful microcontroller that provides a highly-flexible and costeffective solution to many embedded control applications.
The ATtiny10/11 AVR is supported with a full suite of program and system development tools including: macro assemblers,
program debugger/simulators, in-circuit emulators, and evaluation kits.
2
ATtiny10/11/12
ATtiny10/11/12
Figure 1. The ATtiny10/11 Block Diagram
VCC
8-BIT DATA BUS
INTERNAL
OSCILLATOR
GND
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
PROGRAM
FLASH
HARDWARE
STACK
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
GENERALPURPOSE
REGISTERS
INSTRUCTION
DECODER
CONTROL
LINES
TIMING AND
CONTROL
MCU STATUS
REGISTER
Z
TIMER/
COUNTER
ALU
INTERRUPT
UNIT
STATUS
REGISTER
ANALOG
COMPARATOR
+
-
PROGRAMMING
LOGIC
OSCILLATORS
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
PORTB DRIVERS
PB0-PB5
3
ATtiny12 Block Diagram
Figure 2. The ATtiny12 Block Diagram
VCC
8-BIT DATA BUS
INTERNAL
OSCILLATOR
INTERNAL
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
GND
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
PROGRAM
FLASH
HARDWARE
STACK
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
GENERALPURPOSE
REGISTERS
INSTRUCTION
DECODER
CONTROL
LINES
ANALOG
COMPARATOR
+
-
PROGRAMMING
LOGIC
MCU STATUS
REGISTER
Z
TIMER/
COUNTER
ALU
INTERRUPT
UNIT
STATUS
REGISTER
EEPROM
OSCILLATORS
SPI
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
PORTB DRIVERS
PB0-PB5
The ATtiny12 provides the following features: 1K bytes of Flash, 64 bytes EEPROM, up to six general-purpose I/O lines,
32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog
Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to continue functioning. The Power-down Mode saves the register contents but
freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt
on pin change features enable the ATtiny12 to be highly responsive to external events, still featuring the lowest power
consumption while in the power-down modes.
4
ATtiny10/11/12
ATtiny10/11/12
The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU
with Flash on a monolithic chip, the Atmel ATtiny12 is a powerful microcontroller that provides a highly-flexible and costeffective solution to many embedded control applications.
The ATtiny12 AVR is supported with a full suite of program and system development tools including: macro assemblers,
program debugger/simulators, in-circuit emulators, and evaluation kits.
Pin Descriptions
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB5..PB0)
Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny10/11, PB5
is input only. On ATtiny12, PB5 is input or open-drain output. The port pins are tri-stated when a reset condition becomes
active, even if the clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on reset and clock
settings, as shown below.
Table 2. PB5..PB3 Functionality vs. Device Clocking Options
Device Clocking Option
PB4
PB3
(2)
-
Input(3)/I/O(4)
-
-
External Crystal
-
Used
Used
External Low-frequency Crystal
-
Used
Used
External Ceramic Resonator
-
Used
Used
External RC Oscillator
-
I/O(5)
Used
External Clock
-
I/O
Used
Internal RC Oscillator
-
I/O
I/O
External Reset Enabled
External Reset Disabled
Notes:
1.
2.
3.
4.
5.
PB5
Used
(1)
-
“Used” means the pin is used for reset or clock purposes.
“-” means the pin function is unaffected by the option.
Input means the pin is a port input pin.
On ATtiny10/11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output.
I/O means the pin is a port input/output pin.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate
a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
5
Clock Options
The device has the following clock source options, selectable by Flash fuse bits as shown:
Table 3. Device Clocking Options Select
Device Clocking Option
ATtiny10/11 CKSEL2..0
ATtiny12 CKSEL3..0
External Crystal/Ceramic Resonator
111
1111 - 1010
External Low-frequency Crystal
110
1001 - 1000
External RC Oscillator
101
0111 - 0101
Internal RC Oscillator
100
0100 - 0010
External Clock
000
0001 - 0000
Other Options
-
Reserved
Note:
“1” means unprogrammed, “0” means programmed.
The various choices for each clocking option give different start-up times as shown in Table 7 on page 18 and Table 9 on
page 19.
Internal RC Oscillator
The internal RC oscillator option is an on-chip oscillator running at a fixed frequency of 1 MHz. If selected, the device can
operate with no external components. The device is shipped with this option selected. On ATtiny10/11, the Watchdog
Oscillator is used as a clock, while ATtiny12 uses a separate calibrated oscillator.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 3. Either a quartz crystal or a ceramic resonator may be used.
Figure 3. Oscillator Connections
MAX 1 HC BUFFER
HC
C2
C1
XTAL2
XTAL1
GND
Note:
6
When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.
ATtiny10/11/12
ATtiny10/11/12
External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 4.
Figure 4. External Clock Drive Configuration
PB4 (XTAL2)
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
External RC Oscillator
For timing insensitive applications, the external RC configuration shown in Figure 5 can be used. For details on how to
choose R and C, see Table 29 on page 53.
Figure 5. External RC Configuration
VCC
R
PB4 (XTAL2)
XTAL1
C
GND
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single-clock-cycle access
time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock
cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This pointer is called the Z-pointer, and
can address the register file and the Flash program memory.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single-register
operations are also executed in the ALU. Figure 2 shows the ATtiny10/11/12 AVR RISC microcontroller architecture. The
AVR uses a Harvard architecture concept with separate memories and buses for program and data memories. The program memory is accessed with a two-stage pipelining. While one instruction is being executed, the next instruction is prefetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is reprogrammable Flash memory.
With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AVR instructions
have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
7
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a
3-level-deep hardware stack dedicated for subroutines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, timer/counters, and other
I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 6. The ATtiny10/11/12 AVR RISC Architecture
8-bit Data Bus
512 x 16
Program
Flash
Program
Counter
Status
and Test
Control
Registers
Interrupt
Unit
32 x 8
Generalpurpose
Registers
Instruction
Register
SPI Unit
(ATtiny12 only)
8-bit
Timer/Counter
Direct Addressing
Instruction
Decoder
Watchdog
Timer
ALU
Analog
Comparator
Control Lines
64 x 8 EEPROM
(ATtiny12 only)
6
I/O Lines
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
8
ATtiny10/11/12
ATtiny10/11/12
General-purpose Register File
Figure 7 shows the structure of the 32 general-purpose registers in the CPU.
Figure 7. AVR CPU General-purpose Working Registers
7
0
R0
R1
R2
General-
…
purpose
…
Working
R28
Registers
R29
R30 (Z-register low byte)
R31 (Z-register high byte)
All the register operating instructions in the instruction set have direct- and single-cycle access to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a
register and the LDI instruction for load-immediate constant data. These instructions apply to the second half of the registers in the register file – R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two registers or
on a single register apply to the entire register file.
Registers 30 and 31 form a 16-bit pointer (the Z-pointer) which is used for indirect Flash memory and register file access.
When the register file is accessed, the contents of R31 are discarded by the CPU.
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general-purpose working registers. Within a
single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into
three main categories – arithmetic, logic and bit-functions. Some microcontrollers in the AVR product family feature a hardware multiplier in the arithmetic part of the ALU.
Flash Program Memory
The ATtiny10/11/12 contains 1K bytes on-chip Flash memory for program storage. Since all instructions are single 16-bit
words, the Flash is organized as 512 x 16 words. The Flash memory has an endurance of at least 1000 write/erase cycles.
The ATtiny10/11/12 Program Counter is 9 bits wide, thus addressing the 512 words Flash program memory.
See page 39 for a detailed description on Flash memory programming.
Program and Data Addressing Modes
The ATtiny10/11/12 AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes
the different addressing modes supported in the ATtiny10/11/12. In the figures, OP means the operation code part of the
instruction word. To simplify, not all figures show the exact location of the addressing bits.
9
Register Direct, Single Register Rd
Figure 8. Direct Single-register Addressing
The operand is contained in register d (Rd).
Register Indirect
Figure 9. Indirect Register Addressing
REGISTER FILE
0
Z-register
30
31
The register accessed is the one pointed to by the Z-register (R31, R30).
10
ATtiny10/11/12
ATtiny10/11/12
Register Direct, Two Registers Rd and Rr
Figure 10. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
I/O Direct
Figure 11. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
11
Relative Program Addressing, RJMP and RCALL
Figure 12. Relative Program Memory Addressing
+1
Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
Constant Addressing Using the LPM Instruction
Figure 13. Code Memory Constant Addressing
PROGRAM MEMORY
$000
15
1 0
Z-REGISTER
$1FF
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 511), the LSB selects
low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
Subroutine and Interrupt Hardware Stack
The ATtiny10/11/12 uses a 3-level-deep hardware stack for subroutines and interrupts. The hardware stack is 9 bits wide
and stores the program counter (PC) return address while subroutines and interrupts are executed.
RCALL instructions and interrupts push the PC return address onto stack level 0, and the data in the other stack levels 1-2
are pushed one level deeper in the stack. When a RET or RETI instruction is executed the returning PC is fetched from
stack level 0, and the data in the other stack levels 1-2 are popped one level in the stack.
If more than three subsequent subroutine calls or interrupts are executed, the first values written to the stack are overwritten. Pushing four return addresses A1, A2, A3 and A4, followed by four subroutine or interrupt returns, will pop A4, A3, A2
and once more A2 from the hardware stack.
12
ATtiny10/11/12
ATtiny10/11/12
EEPROM Data Memory
The ATtiny12 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes
can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the
EEPROM and the CPU is described on page 33, specifying the EEPROM Address Register, the EEPROM Data Register,
and the EEPROM Control Register.
For SPI data downloading, see “Memory Programming” on page 39 for a detailed description.
Memory Access and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal
clock division is used.
Figure 14 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 14. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 15 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two register
operands is executed and the result is stored back to the destination register.
Figure 15. Single-cycle ALU Operation
T1
T2
T3
T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
13
I/O Memory
The I/O space definition of the ATtiny10/11/12 is shown in the following table:
Table 4. ATtiny10/11/12 I/O Space
Address Hex
Name
Device
Function
$3F
SREG
ATtiny10/11/12
Status Register
$3B
GIMSK
ATtiny10/11/12
General Interrupt Mask Register
$3A
GIFR
ATtiny10/11/12
General Interrupt Flag Register
$39
TIMSK
ATtiny10/11/12
Timer/Counter Interrupt Mask Register
$38
TIFR
ATtiny10/11/12
Timer/Counter Interrupt Flag Register
$35
MCUCR
ATtiny10/11/12
MCU Control Register
$34
MCUSR
ATtiny10/11/12
MCU Status Register
$33
TCCR0
ATtiny10/11/12
Timer/Counter0 Control Register
$32
TCNT0
ATtiny10/11/12
Timer/Counter0 (8-bit)
$31
OSCCAL
ATtiny12
Oscillator Calibration Register
$21
WDTCR
ATtiny10/11/12
Watchdog Timer Control Register
$1E
EEAR
ATtiny12
EEPROM Address Register
$1D
EEDR
ATtiny12
EEPROM Data Register
$1C
EECR
ATtiny12
EEPROM Control Register
$18
PORTB
ATtiny10/11/12
Data Register, Port B
$17
DDRB
ATtiny10/11/12
Data Direction Register, Port B
$16
PINB
ATtiny10/11/12
Input Pins, Port B
$08
ACSR
ATtiny10/11/12
Analog Comparator Control and Status Register
Note:
Reserved and unused locations are not shown in the table.
All the different ATtiny10/11/12 I/O and peripherals are placed in the I/O space. The different I/O locations are accessed by
the IN and OUT instructions transferring data between the 32 general-purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers,
the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set Summary for
more details.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addressed
should never be written.
The different I/O and peripherals control registers are explained in the following sections.
Status Register – SREG
The AVR status register (SREG) at I/O space location $3F is defined as:
Bit
7
6
5
4
3
2
1
0
$3F
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
SREG
• Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is
then performed in separate control registers. If the global interrupt enable register is cleared (zero), none of the interrupts
14
ATtiny10/11/12
ATtiny10/11/12
are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has
occurred, and is set by the RETI instruction to enable subsequent interrupts.
• Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit.
A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in
a register in the register file by the BLD instruction.
• Bit 5 - H: Half Carry Flag
The half carry flag H indicates a half-carry in some arithmetic operations. See the Instruction Set description for detailed
information.
• Bit 4 - S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruction Set description for detailed information.
• Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the Instruction Set description for
detailed information.
• Bit 2 - N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation. See the Instruction Set description
for detailed information.
• Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation. See the Instruction Set description for
detailed information.
• Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruction Set description for detailed
information.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
Reset and Interrupt Handling
The ATtiny10/11 provides four different interrupt sources and the ATtiny12 provides five. These interrupts and the separate
reset vector each have a separate program vector in the program memory space. All the interrupts are assigned individual
enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 5. The list also determines the priority levels of the different interrupts. The lower
the address, the higher the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0, etc.
15
Table 5. Reset and Interrupt Vectors
Vector No.
Device
Program Address
Source
Interrupt Definition
1
ATtiny10/11
$000
RESET
External Pin, Power-on Reset and
Watchdog Reset
1
ATtiny12
$000
RESET
External Pin, Power-on Reset, Brown-out
Reset and Watchdog Reset
2
ATtiny10/11/12
$001
INT0
3
ATtiny10/11/12
$002
I/O Pins
4
ATtiny10/11/12
$003
TIMER0, OVF0
5
ATtiny10/11
$004
ANA_COMP
5
ATtiny12
$004
EE_RDY
6
ATtiny12
$005
ANA_COMP
External Interrupt Request 0
Pin Change Interrupt
Timer/Counter0 Overflow
Analog Comparator
EEPROM Ready
Analog Comparator
The most typical and general program setup for the reset and interrupt vector addresses for the ATtiny10/11 are:
Address
Labels
Code
Comments
$000
rjmp
RESET
; Reset handler
$001
rjmp
EXT_INT0
; IRQ0 handler
$002
rjmp
PIN_CHANGE
; Pin change handler
$003
rjmp
TIM0_OVF
; Timer0 overflow handler
$004
rjmp
ANA_COMP
; Analog Comparator handler
MAIN:
<instr>
xxx
; Main program start
…
…
;
$005
…
…
The most typical and general program setup for the reset and interrupt vector addresses for the ATtiny12 are:
Address
Labels
Code
Comments
$000
rjmp
RESET
; Reset handler
$001
rjmp
EXT_INT0
; IRQ0 handler
$002
rjmp
PIN_CHANGE
; Pin change handler
$003
rjmp
TIM0_OVF
; Timer0 overflow handler
$004
rjmp
EE_RDY
; EEPROM Ready handler
$005
rjmp
ANA_COMP
; Analog Comparator handler
MAIN:
<instr>
xxx
; Main program start
…
…
;
$006
…
16
…
ATtiny10/11/12
ATtiny10/11/12
Reset Sources
The ATtiny10/11/12 provides three or four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (VPOT).
• External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage VCC falls below a certain voltage (ATtiny12 only).
During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The
instruction placed in address $000 must be an RJMP – relative jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at
these locations. The circuit diagram in Figure 16 shows the reset logic for the ATtiny10/11. Figure 17 shows the reset logic
for the ATtiny12. Table 6 defines the electrical parameters of the reset circuitry for ATtiny10/11. Table 8 shows the parameters of the reset circuitry for ATtiny12.
Figure 16. Reset Logic for the ATtiny10/11
Power-on Reset
Circuit
RESET
Reset Circuit
POR
Watchdog
Timer
On-chip
RC Oscillator
S
Q
R
Q
COUNTER RESET
VCC
20-stage Ripple Counter
Q3
Q9
Q13
Q19
INTERNAL
RESET
FSTRT
CKSEL
Table 6. Reset Characteristics for the ATtiny10/11
Symbol
VPOT(1)
VRST
Note:
Parameter
Min
Typ
Max
Units
Power-on Reset Threshold Voltage (rising)
1.0
1.4
1.8
V
Power-on Reset Threshold Voltage (falling)
0.4
0.6
0.8
V
RESET Pin Threshold Voltage
0.6 VCC
V
1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).
17
Power-on Reset for the ATtiny10/11
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 16, an internal timer is
clocked from the watchdog timer. This timer prevents the MCU from starting a certain period after VCC has reached the
Power-on Threshold Voltage – VPOT. See Figure 18. The total reset period is the Delay Time-out period – tTOUT. The FSTRT
fuse bit in the Flash can be programmed to give a shorter start-up time.The start-up times for the different clock options are
shown in the following table. The Watchdog Oscillator is used for timing the start-up time, and this oscillator is voltage
dependent as shown in the section “ATtiny11 Typical Characteristics” on page 54.
Table 7. Start-up Times for the ATtiny10/11 (VCC = 2.7V)
Start-up Time tTOUT
Selected Clock Option
FSTRT Unprogrammed
FSTRT Programmed
External Crystal
67 ms
4.2 ms
External Ceramic Resonator
67 ms
4.2 ms
External Low-frequency Crystal
4.2 s
4.2 s
External RC Oscillator
4.2 ms
67 µs
Internal RC Oscillator
4.2 ms
67 µs
External Clock
4.2 ms
5 clocks from reset,
2 clocks from power-down
If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via an external pull-up resistor. By holding the RESET pin low for a period after VCC has been applied, the Power-on Reset period can be extended. Refer to
Figure 19 for a timing example on this.
Figure 17. Reset Logic for the ATtiny12
DATA BUS
PORF
BORF
EXTRF
WDRF
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
BODEN
BODLEVEL
Brown-out
Reset Circuit
CKSEL[3:0]
On-chip
RC Oscillator
Delay Counters
CK
18
ATtiny10/11/12
Full
ATtiny10/11/12
Table 8. Reset Characteristics for the ATtiny12
Symbol
Parameter
Condition
Min
Typ
Max
Units
Power-on Reset Threshold Voltage
(rising)
BOD disabled
1.0
1.4
1.8
V
BOD enabled
0.6
1.2
1.8
V
Power-on Reset Threshold Voltage
(falling)
BOD disabled
0.4
0.6
0.8
V
BOD enabled
0.6
1.2
1.8
V
VPOT(1)
VRST
RESET Pin Threshold Voltage
VBOT
Brown-out Reset Threshold Voltage
Note:
0.6VCC
V
(BODLEVEL = 1)
1.7
1.8
1.9
(BODLEVEL = 0)
2.6
2.7
2.8
V
1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).
Table 9. ATtiny12 Clock Options and Start-up Times
CKSEL3..0
Note:
Clock Source
Start-up Time, VCC = 1.8V,
BODLEVEL Unprogrammed
Start-up Time, VCC = 2.7V,
BODLEVEL Programmed
1111
Ext. Crystal/Ceramic Resonator(1)
1K CK
1K CK
1110
Ext. Crystal/Ceramic Resonator(1)
3.6 ms + 1K CK
4.2 ms + 1K CK
1101
(1)
Ext. Crystal/Ceramic Resonator
57 ms 1K CK
67 ms + 1K CK
1100
Ext. Crystal/Ceramic Resonator
16K CK
16K CK
1011
Ext. Crystal/Ceramic Resonator
3.6 ms + 16K CK
4.2 ms + 16K CK
1010
Ext. Crystal/Ceramic Resonator
57 ms + 16K CK
67 ms + 16K CK
1001
Ext. Low-frequency Crystal
57 ms + 1K CK
67 ms + 1K CK
1000
Ext. Low-frequency Crystal
57 ms + 32K CK
67 ms + 32K CK
0111
Ext. RC Oscillator
6 CK
6 CK
0110
Ext. RC Oscillator
3.6 ms + 6 CK
4.2 ms + 6 CK
0101
Ext. RC Oscillator
57 ms + 6 CK
67 ms + 6 CK
0100
Int. RC Oscillator
6 CK
6 CK
0011
Int. RC Oscillator
3.6 ms + 6 CK
4.2 ms + 6 CK
0010
Int. RC Oscillator
57 ms + 6 CK
67 ms + 6 CK
0001
Ext. Clock
6 CK
6 CK
0000
Ext. Clock
3.6 ms + 6 CK
4.2 ms + 6 CK
1. Due to the limited number of clock cycles in the start-up period, it is recommended that Ceramic Resonator be used.
This table shows the start-up times from reset. From sleep, only the clock counting part of the start-up time is used. The
Watchdog oscillator is used for timing the real-time part of the start-up time. The number of WDT oscillator cycles used for
each time-out is shown in Table 10.
19
Table 10. Number of Watchdog Oscillator Cycles
BODLEVEL
Time-out
Number of Cycles
Unprogrammed
3.6 ms (at Vcc = 1.8V)
256
Unprogrammed
57 ms (at Vcc = 1.8V)
4K
Programmed
4.2 ms (at Vcc = 2.7V)
1K
Programmed
67 ms (at Vcc = 2.7V)
16K
The frequency of the watchdog oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics”
on page 54.
Note that the BODLEVEL fuse can be used to select start-up times even if the Brown-out Detection is disabled (by leaving
the BODEN fuse unprogrammed).
The device is shipped with CKSEL3..0 = 0010.
Power-on Reset for the ATtiny12
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is nominally 1.4V. The
POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up reset, as
well as detect a failure in supply voltage.
The Power-on Reset (POR) circuit ensures that the device is reset from power-on. Reaching the Power-on Reset threshold
voltage invokes a delay counter, which determines the delay for which the device is kept in Reset after VCC rise. The timeout period of the delay counter can be defined by the user through the CKSEL fuses. The different selections for the delay
period are presented in Table 9. The Reset signal is activated again, without any delay, when the VCC decreases below
detection level.
If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via an external pull-up resistor. See
Figure 18. By holding the RESET pin low for a period after VCC has been applied, the Power-on Reset period can be
extended. Refer to Figure 19 for a timing example on this.
Figure 18. MCU Start-up, RESET Tied to VCC.
VCC
RESET
VPOT
VRST
TIME-OUT
INTERNAL
RESET
20
ATtiny10/11/12
tTOUT
ATtiny10/11/12
Figure 19. MCU Start-up, RESET Extended Externally
VCC
VPOT
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
External Reset
An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even
if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage – VRST – on its positive edge, the delay timer starts the MCU after the Time-out period (tTOUT) has
expired.
Figure 20. External Reset during Operation
VCC
RESET
VRST
t TOUT
TIME-OUT
INTERNAL
RESET
Brown-out Detection (ATtiny12)
ATtiny12 has an on-chip brown-out detection (BOD) circuit for monitoring the VCC level during the operation. The BOD
circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and VCC decreases
below the trigger level, the brown-out reset is immediately activated. When VCC increases above the trigger level, the
brown-out reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal,
in Table 5. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 1.8V (BODLEVEL unprogrammed),
or 2.7V (BODLEVEL programmed). The trigger level has a hysteresis of 50 mV to ensure spike-free brown-out detection.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than 7 µs for trigger level
2.7V, 24 µs for trigger level 1.8V (typical values).
21
Figure 21. Brown-out Reset during Operation (ATtiny12)
VCC
VBOT+
VBOT-
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
Note:
The hysteresis on VBOT: VBOT + = VBOT + 25 mV, VBOT- = VBOT - 25 mV.
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse,
the delay timer starts counting the Time-out period (tTOUT). Refer to page 31 for details on operation of the Watchdog.
Figure 22. Watchdog Reset during Operation
VCC
CK
MCU Status Register – MCUSR of the ATtiny10/11
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
6
5
4
3
2
1
0
$34
-
-
-
-
-
-
EXTRF
PORF
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial value
0
0
0
0
0
0
See bit description
MCUSR
• Bit 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny10/11 and always read as zero.
• Bit 1 - EXTRF: EXTernal Reset Flag
After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit
unchanged.
22
ATtiny10/11/12
ATtiny10/11/12
• Bit 0 - PORF: Power-on Reset Flag
This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged.
To summarize, the following table shows the value of these two bits after the three modes of reset.
Table 11. PORF and EXTRF Values after Reset
Reset Source
Power-on
External Reset
Watchdog Reset
EXTRF
PORF
undefined
1
1
unchanged
unchanged
unchanged
To identify a reset condition, the user software should clear both the PORF and EXTRF bits as early as possible in the program. Checking the PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before an external or
watchdog reset occurs, the source of reset can be found by using the following truth table:
Table 12. Reset Source Identification
EXTRF
PORF
Reset Source
0
0
Watchdog Reset
1
0
External Reset
0
1
Power-on Reset
1
1
Power-on Reset
MCU Status Register – MCUSR for the ATtiny12
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
6
5
4
3
2
1
0
$34
-
-
-
-
WDRF
BORF
EXTRF
PORF
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
MCUSR
See bit description
• Bit 7..4 - Res: Reserved Bits
These bits are reserved bits in the ATtiny12 and always read as zero.
• Bit 3 - WDRF: Watchdog Reset Flag
This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
• Bit 2 - BORF: Brown-out Reset Flag
This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
• Bit 1 - EXTRF: EXTernal Reset Flag
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
• Bit 0 - PORF: Power-on Reset Flag
This bit is set if a power-on reset occurs. The bit is reset by writing a logic zero to the flag.
To use the reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in
the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the
reset flags.
ATtiny12 Internal Voltage Reference
ATtiny12 features an internal voltage reference with a nominal voltage of 1.22V. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator.
23
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The maximum start-up time is TBD.
To save power, the reference is not always turned on. The reference is on during the following situations:
1. When BOD is enabled (by programming the BODEN fuse)
2. When the bandgap reference is connected to the Analog Comparator (by setting the AINBG bit in ACSR)
Thus, when BOD is not enabled, after setting the AINBG bit, the user must always allow the reference to start up before the
output from the Analog Comparator is used. The bandgap reference uses approximately 10 µA, and to reduce power consumption in Power-down mode, the user can turn off the reference when entering this mode.
Interrupt Handling
The ATtiny10/11/12 has two 8-bit Interrupt Mask control registers; GIMSK – General Interrupt Mask register and TIMSK –
Timer/Counter Interrupt Mask register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction –
RETI – is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set
and remembered until the interrupt is enabled, or the flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt
flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is
active.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. After the 4 clock cycles, the
program vector address for the actual interrupt handling routine is executed. During this 4-clock-cycle period, the Program
Counter (9 bits) is pushed onto the Stack. The vector is normally a relative jump to the interrupt routine, and this jump takes
2 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the
interrupt is served. In ATtiny12, if an interrupt occurs when the MCU is in Sleep mode, the interrupt response time is
increased by 4 clock cycles.
A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock cycles, the Program Counter (9 bits)
is popped back from the Stack, and the I-flag in SREG is set. When AVR exits from an interrupt, it will always return to the
main program and execute one more instruction before any pending interrupt is served.
General Interrupt Mask Register – GIMSK
Bit
7
6
5
4
3
2
1
$3B
-
INT0
PCIE
-
-
-
-
0
-
Read/Write
R
R/W
R/W
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
GIMSK
• Bit 7 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny10/11/12 and always reads as zero.
• Bit 6 - INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether
the external interrupt is activated on rising or falling edge, on pin change, or low level of the INT0 pin. Activity on the pin will
24
ATtiny10/11/12
ATtiny10/11/12
cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from program memory address $001. See also “External Interrupts.”
• Bit 5 - PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the interrupt on pin change is
enabled. Any change on any input or I/O pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt
Request is executed from program memory address $002. See also “Pin Change Interrupt.”
• Bits 4..0 - Res: Reserved bits
These bits are reserved bits in the ATtiny10/11/12 and always read as zero.
General Interrupt Flag Register – GIFR
Bit
7
6
5
4
3
2
1
$3A
-
INTF0
PCIF
-
-
-
-
0
-
Read/Write
R
R/W
R/W
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
GIFR
• Bit 7 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny10/11/12 and always reads as zero.
• Bit 6 - INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. The flag is always cleared when INT0
is configured as level interrupt.
• Bit 5 - PCIF: Pin Change Interrupt Flag
When an event on any input or I/O pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the
PCIE bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 4..0 - Res: Reserved bits
These bits are reserved bits in the ATtiny10/11/12 and always read as zero.
Timer/Counter Interrupt Mask Register – TIMSK
Bit
7
6
5
4
3
2
1
$39
-
-
-
-
-
-
TOIE0
0
-
Read/Write
R
R
R
R
R
R
R/W
R
Initial value
0
0
0
0
0
0
0
0
TIMSK
• Bit 7..2 - Res: Reserved bits
These bits are reserved bits in the ATtiny10/11/12 and always read as zero.
• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $003) is executed if an overflow in Timer/Counter0 occurs, i.e., when the
Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 - Res: Reserved bit
This bit is a reserved bit in the ATtiny10/11/12 and always reads as zero.
Timer/Counter Interrupt Flag Register – TIFR
Bit
7
6
5
4
3
2
1
$38
-
-
-
-
-
-
TOV0
0
-
Read/Write
R
R
R
R
R
R
R/W
R
Initial value
0
0
0
0
0
0
0
0
TIFR
• Bits 7..2 - Res: Reserved bits
These bits are reserved bits in the ATtiny10/11/12 and always read as zero.
25
• Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical one to the flag. When the SREG
I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is
executed.
• Bit 0 - Res: Reserved bit
This bit is a reserved bit in the ATtiny10/11/12 and always reads as zero.
External Interrupt
The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trigger even if the INT0 pin is
configured as an output. This feature provides a way of generating a software interrupt. The external interrupt can be triggered by a falling or rising edge, a pin change, or a low level. This is set up as indicated in the specification for the MCU
Control Register – MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt will
trigger as long as the pin is held low.
The external interrupt is set up as described in the specification for the MCU Control Register – MCUCR.
Pin Change Interrupt
The pin change interrupt is triggered by any change on any input or I/O pin. Change on pins PB2..0 will always cause an
interrupt. Change on pins PB5..3 will cause an interrupt if the pin is configured as input or I/O, as described in the section
“Pin Descriptions” on page 5. Observe that, if enabled, the interrupt will trigger even if the changing pin is configured as an
output. This feature provides a way of generating a software interrupt. Also observe that the pin change interrupt will trigger
even if the pin activity triggers another interrupt, for example, the external interrupt. This implies that one external event
might cause several interrupts.
The values on the pins are sampled before detecting edges. If pin change interrupt is enabled, pulses that last longer than
one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
MCU Control Register – MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit
7
6
5
4
3
2
1
0
$35
-
(PUD)
SE
SM
-
-
ISC01
ISC00
Read/Write
R
R(/W)
R/W
R/W
R
R
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Note:
MCUCR
The Pull-up Disable (PUD) bit is only available in ATtiny12.
• Bit 7 - Res: Reserved bit
This bit is a reserved bit in the ATtiny10/11/12 and always reads as zero.
• Bit 6 - Res: Reserved bit in ATtiny10/11
This bit is a reserved bit in the ATtiny10/11 and always reads as zero.
• Bit 6 - PUD: Pull-up Disable in ATtiny12
Setting this bit, disables all pull-ups on port B. If this bit is cleared, the pull-ups can be individually enabled as described in
section “I/O Port B” on page 36.
• Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP instruction is executed. To avoid
the MCU entering the Sleep Mode unless it is the programmer’s purpose, it is recommended to set the Sleep Enable SE bit
just before the execution of the SLEEP instruction.
• Bit 4 - SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode.
When SM is set (one), Power-down Mode is selected as Sleep Mode. For details, refer to the paragraph “Sleep Modes”
below.
26
ATtiny10/11/12
ATtiny10/11/12
• Bits 3, 2 - Res: Reserved bits
These bits are reserved bits in the ATtiny10/11/12 and always read as zero.
• Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control0 bit 1 and bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are
set. The following table shows how to set the ISC bits to generate an external interrupt:
Table 13. Interrupt 0 Sense Control
ISC01
ISC00
0
0
The low level of INT0 generates an interrupt request.
0
1
Any change on INT0 generates an interrupt request
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
Note:
Description
When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register.
Otherwise, an interrupt can occur when the bits are changed.
The value on the INT0 pin is sampled before detecting edges. If edge interrupt is selected, pulses that last longer than one
CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an
interrupt. If enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low.
Sleep Modes for the ATtiny10/11
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM bit
in the MCUCR register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction. If an
enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes
execution from the instruction following SLEEP. On wake-up from Power-down Mode on pin change, the two instructions
following SLEEP are executed before the pin change interrupt routine. The contents of the register file and I/O memory are
unaltered. If a reset occurs during Sleep Mode, the MCU wakes up and executes from the Reset vector.
Idle Mode
When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode, stopping the CPU but allowing
Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external
triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset. If wake-up from the Analog
Comparator interrupt is not required, the analog comparator can be powered down by setting the ACD-bit in the Analog
Comparator Control and Status register – ACSR. This will reduce power consumption in Idle Mode. When the MCU wakes
up from Idle mode, the CPU starts program execution immediately.
Power-down Mode
When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-down Mode. In this mode, the external
oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset,
a watchdog reset (if enabled), an external level interrupt, or an pin change interrupt can wake up the MCU.
Note that if a level-triggered or pin change interrupt is used for wake-up from power-down, the changed level must be held
for a time longer than the reset delay period of tTOUT. Otherwise, the MCU will fail to wake up.
27
Sleep Modes for the ATtiny12
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM bit
in the MCUCR register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction. If an
enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes. The CPU is then halted for four cycles, it
executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register
file and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset
vector.
Idle Mode
When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode stopping the CPU but allowing
Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external
triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset. If wake-up from the Analog
Comparator interrupt is not required, the analog comparator can be powered down by setting the ACD-bit in the Analog
Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle Mode.
Power-down Mode
When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-down Mode. In this mode, the external
oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset,
a watchdog reset (if enabled), an external level interrupt, or a pin change interrupt can wake up the MCU.
Note that if a level triggered or pin change interrupt is used for wake-up from Power-down Mode, the changed level must be
held for a time to wake up the MCU. This makes the MCU less sensitive to noise. The wake-up period is equal to the clockcounting part of the reset period (See Table 9). The MCU will wake up from the power-down if the input has the required
level for two watchdog oscillator cycles. If the wake-up period is shorter than two watchdog oscillator cycles, the MCU will
wake up if the input has the required level for the duration of the wake-up period. If the wake-up condition disappears
before the wake-up period has expired, the MCU will wake up from power-down without executing the corresponding interrupt. The period of the watchdog oscillator is 2.7 µs (nominal) at 3.0V and 25°C. The frequency of the watchdog oscillator is
voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on page 54.
When waking up from Power-down Mode, there is a delay from the wake-up condition occurs until the wake-up becomes
effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by
the same CKSEL fuses that define the reset time-out period.
ATtiny12 Calibrated Internal RC Oscillator
In ATtiny12, the calibrated internal oscillator provides a fixed 1 MHz (nominal) clock at 5V and 25°C. This clock may be
used as the system clock. See the section “Clock Options” on page 6 for information on how to select this clock as the system clock. This oscillator can be calibrated by writing the calibration byte to the OSCCAL register. When this oscillator is
used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the reset time-out. For
details on how to use the pre-programmed calibration value, see the section “Calibration Byte in ATtiny12” on page 40.
Oscillator Calibration Register – OSCCAL
Bit
7
6
5
4
3
2
1
0
$31
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Bits 7..0 - CAL7..0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator
frequency. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will
increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM access. If EEPROM is written, do not calibrate to more than 10% above the
28
ATtiny10/11/12
ATtiny10/11/12
nominal frequency. Otherwise, the EEPROM write may fail. Table 14 shows the range for OSCCAL. Note that the oscillator
is intended for calibration to 1.0 MHz, thus tuning to other values is not guaranteed.
Table 14. Internal RC Oscillator Frequency Range
OSCCAL Value
Min Frequency
Max Frequency
$00
0.5 MHz
1.0 MHz
$7F
0.7 MHz
1.5 MHz
$FF
1.0 MHz
2.0 MHz
Timer/Counter0
The ATtiny10/11/12 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0. The Timer/Counter0 has prescaling selection from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock
timebase or as a counter with an external pin connection that triggers the counting.
Timer/Counter Prescaler
Figure 23 shows the Timer/Counter prescaler.
Figure 23. Timer/Counter0 Prescaler
CK
CK/1024
CK/256
CK/64
CK/8
10-BIT T/C PRESCALER
T0
0
CS00
CS01
CS02
TIMER/COUNTER0 CLOCK SOURCE
TCK0
The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the oscillator clock. CK,
external source and stop, can also be selected as clock sources.
Figure 24 shows the block diagram for Timer/Counter0.
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition, it can be stopped
as described in the specification for the Timer/Counter0 Control Register – TCCR0. The overflow status flag is found in the
Timer/Counter Interrupt Flag Register – TIFR. Control signals are found in the Timer/Counter0 Control Register – TCCR0.
The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register – TIMSK.
When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To
ensure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one
internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.
29
The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high-prescaling opportunities make the Timer/Counter0 useful for lower-speed functions or exact-timing
functions with infrequent actions.
Figure 24. Timer/Counter0 Block Diagram
T0
Timer/Counter0 Control Register – TCCR0
Bit
7
6
5
4
3
2
1
0
$33
-
-
-
-
-
CS02
CS01
CS00
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Bits 7..3 - Res: Reserved bits:
These bits are reserved bits in the ATtiny10/11/12 and always read as zero.
• Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, bit 2,1 and 0:
The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer0.
Table 15. Clock 0 Prescale Select
30
CS02
CS01
CS00
0
0
0
Stop, the Timer/Counter0 is stopped.
0
0
1
CK
0
1
0
CK/8
0
1
1
CK/64
1
0
0
CK/256
1
0
1
CK/1024
1
1
0
External Pin T0, falling edge
1
1
1
External Pin T0, rising edge
ATtiny10/11/12
Description
TCCR0
ATtiny10/11/12
The Stop condition provides a Timer Enable/Disable function. The CK down-divided modes are scaled directly from the CK
oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if
the pin is configured as an output. This feature can give the user SW control of the counting.
Timer Counter 0 – TCNT0
Bit
7
$32
MSB
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
LSB
TCNT0
The Timer/Counter0 is implemented as an up-counter with read and write access. If the Timer/Counter0 is written and a
clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation.
Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the
Watchdog reset interval can be adjusted as shown in Table 16. See characterization data for typical values at other VCC
levels. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. Eight different clock cycle periods can be
selected to determine the reset period. If the reset period expires without another Watchdog reset, the ATtiny10/11/12
resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 22.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is
disabled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 25. Watchdog Timer
Oscillator
1 MHz at VCC = 5V
350 kHz at VCC = 3V
110 kHz at VCC = 2V
31
Watchdog Timer Control Register – WDTCR
Bit
7
6
5
4
3
2
1
0
$21
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
WDTCR
• Bits 7..5 - Res: Reserved bits
These bits are reserved bits in the ATtiny10/11/12 and will always read as zero.
• Bit 4 - WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware
will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
• Bit 3 - WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function
is disabled. WDE can be cleared only when the WDTOE bit is set(one). To disable an enabled watchdog timer, the
following procedure must be followed:
1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though
it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.
• Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The
different prescaling values and their corresponding time-out periods are shown in Table 16.
Table 16. Watchdog Timer Prescale Select
Typical Time-out
at VCC = 2.0V
Typical Time-out
at VCC = 3.0V
Typical Time-out
at VCC = 5.0V
0
16K cycles
0.15s
47 ms
15 ms
0
1
32K cycles
0.30s
94 ms
30 ms
0
1
0
64K cycles
0.60s
0.19 s
60 ms
0
1
1
128K cycles
1.2s
0.38 s
0.12 s
1
0
0
256K cycles
2.4s
0.75 s
0.24 s
1
0
1
512K cycles
4.8s
1.5 s
0.49 s
1
1
0
1,024K cycles
9.6s
3.0 s
0.97 s
1
1
1
2,048K cycles
19s
6.0 s
1.9 s
WDP1
WDP0
0
0
0
Note:
32
Number of WDT
Oscillator cycles
WDP2
The frequency of the Watchdog Oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on
page 54.
The WDR – Watchdog Reset – instruction should always be executed before the Watchdog Timer is enabled. This ensures that
the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without
reset, the Watchdog Timer may not start counting from zero.
ATtiny10/11/12
ATtiny10/11/12
ATtiny12 EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 1.9 - 3.4 ms, depending on the frequency of the calibrated RC oscillator. See Table
17 for details. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM
Ready interrupt can be set to trigger when the EEPROM is ready to accept new data.
In order to prevent unintentional EEPROM writes, a two-state write procedure must be followed. Refer to the description of
the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the
EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.
EEPROM Address Register – EEAR
Bit
7
6
5
4
3
2
1
0
$1E
-
-
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
X
X
X
X
X
X
EEAR
The EEPROM Address Register – EEAR specifies the EEPROM address in the 64-byte EEPROM space. The EEPROM
data bytes are addressed linearly between 0 and 63. During reset, the EEAR register is not cleared. Instead, the data in the
register is kept.
EEPROM Data Register – EEDR
Bit
7
6
5
4
3
2
1
0
$1D
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
EEDR
• Bits 7..0 - EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given
by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the
address given by EEAR.
EEPROM Control Register – EECR
Bit
7
6
5
4
3
2
1
0
$1C
-
-
-
-
EERIE
EEMWE
EEWE
EERE
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
X
0
EECR
• Bit 7..4 - Res: Reserved bits
These bits are reserved bits in the ATtiny12 and will always read as zero.
• Bit 3 - EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared (zero).
• Bit 2 - EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one),
setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect.
When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description
of the EEWE bit for a EEPROM write procedure.
33
• Bit 1 - EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up,
the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written
to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the
EEPROM (the order of steps 2 and 3 is unessential):
1. Wait until EEWE becomes zero.
2. Write new EEPROM address to EEAR (optional).
3. Write new EEPROM data to EEDR (optional).
4. Write a logical one to the EEMWE bit in EECR.
5. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will
time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag
cleared during the four last steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit
and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next
instruction is executed.
• Bit 0 - EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the
EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the
EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE
has been set, the CPU is halted for two cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or
address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.
The calibrated oscillator is used to time EEPROM. In Table 17 the typical programming time is listed for EEPROM access
from the CPU.
Table 17. Typical EEPROM Programming Times
Parameter
Number of Calibrated RC
Oscillator Cycles
EEPROM write (from CPU)
2048
Min Programming Time
Max Programming Time
1.9 ms
3.4 ms
Prevent EEPROM Corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the
EEPROM to operate properly. These issues are the same as for board-level systems using the EEPROM, and the same
design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence
to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly if the supply voltage for executing instructions is too low.
EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling
the internal Brown-out Detector (BOD) if the operating speed matches the detection level. If not, an external low VCC
Reset Protection circuit can be applied.
2. Keep the AVR core in Power-down Sleep Mode during periods of low VCC. This will prevent the CPU from attempting
to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes.
3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash
memory can not be updated by the CPU, and will not be subject to corruption.
34
ATtiny10/11/12
ATtiny10/11/12
Analog Comparator
The Analog Comparator compares the input values on the positive input PB0 (AIN0) and negative input PB1 (AIN1). When
the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output (ACO) is set (one). The comparator’s output can trigger a separate interrupt, exclusive to the Analog
Comparator. The user can select interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 26.
Figure 26. Analog Comparator Block Diagram.
INTERNAL
VOLTAGE
REFERENCE
(ATtiny12 ONLY)
AINBG
MUX
Analog Comparator Control and Status Register – ACSR
Bit
7
6
5
4
3
2
1
0
$08
ACD
(AINBG)
ACO
ACI
ACIE
-
ACIS1
ACIS0
Read/Write
R/W
R(/W)
R
R/W
R/W
R
R/W
R/W
Initial value
0
0
X
0
0
0
0
0
Note:
ACSR
AINBG is only available in ATtiny12.
• Bit 7 - ACD: Analog Comparator Disable
When this bit is set (one), the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the
Analog Comparator. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE
bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
• Bit 6 - AINBG: Analog Comparator Bandgap Select in ATtiny12
In ATtiny12, when this bit is set, a fixed bandgap voltage of 1.22 ± 0.05V replaces the normal input to the positive input
(AIN0) of the comparator. When this bit is cleared, the normal input pin PB0 is applied to the positive input of the
comparator.
• Bit 6- Res: Reserved bit in ATtiny10/11
This bit is a reserved bit in the ATtiny10/11 and will always read as zero.
• Bit 5 - ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
• Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog
Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to
the flag.
35
• Bit 3 - ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator Interrupt is activated.
When cleared (zero), the interrupt is disabled.
• Bit 2 - Res: Reserved bit
This bit is a reserved bit in the ATtiny10/11/12 and will always read as zero.
• Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator Interrupt. The different settings are
shown in Table 18.
Table 18. ACIS1/ACIS0 Settings
Note:
ACIS1
ACIS0
Interrupt Mode
0
0
Comparator Interrupt on Output Toggle
0
1
Reserved
1
0
Comparator Interrupt on Falling Output Edge
1
1
Comparator Interrupt on Rising Output Edge
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its interrupt enable bit in
the ACSR register. Otherwise, an interrupt can occur when the bits are changed.
Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write a one back into ACI if it is read as
set, thus clearing the flag.
I/O Port B
All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction
of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if
configured as input).
Port B is a 6-bit bi-directional I/O port.
Three I/O memory address locations are allocated for Port B, one each for the Data Register – PORTB, $18, Data Direction
Register – DDRB, $17, and the Port B Input Pins – PINB, $16. The Port B Input Pins address is read only, while the Data
Register and the Data Direction Register are read/write.
Ports PB5..3 have special functions as described in the section “Pin Descriptions” on page 5. If PB5 is not configured as
external reset, it is input with no pull-up. On ATtiny12, it can also output a logical zero, acting as an open-drain output. If
PB4 and/or PB3 are not used for clock function, they are I/O pins. All I/O pins have individually selectable pull-ups.
The Port B output buffers on PB0 to PB4 can sink 20 mA and thus drive LED displays directly. On ATtiny12, PB5 can sink
12 mA. When pins PB0 to PB4 are used as inputs and are externally pulled low, they will source current (IIL) if the internal
pull-ups are activated.
The Port B pins with alternate functions are shown in Table 19:
Table 19. Port B Pins Alternate Functions
Port Pin
Alternate Functions
Device
AIN0 (Analog Comparator Positive Input)
ATtiny10/11/12
MOSI (Data Input Line for Memory Downloading)
ATtiny12
INT0 (External Interrupt0 Input)
ATtiny10/11/12
AIN1 (Analog Comparator Negative Input)
ATtiny10/11/12
MOSI (Data Output Line for Memory Downloading)
ATtiny12
PB0
PB1
36
ATtiny10/11/12
ATtiny10/11/12
Table 19. Port B Pins Alternate Functions (Continued)
Port Pin
Alternate Functions
Device
T0 (Timer/Counter0 External Counter Input)
ATtiny10/11/12
SCK (Serial Clock Input for Serial Programming)
ATtiny12
PB3
XTAL1 (Oscillator Input)
ATtiny10/11/12
PB4
XTAL2 (Oscillator Output)
ATtiny10/11/12
PB5
RESET (External Reset Pin)
ATtiny10/11/12
PB2
When the pins PB2..0 are used for the alternate function, the DDRB and PORTB register has to be set according to the
alternate function description. When PB5..3 are used for alternate functions, the values in the corresponding DDRB and
PORTB bits are ignored.
Port B Data Register – PORTB
Bit
7
6
5
4
3
2
1
0
$18
-
-
-
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
PORTB
Port B Data Direction Register – DDRB
Bit
7
6
5
4
3
2
1
0
$17
-
-
(DDB5)
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R
R
R(/W)
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Note:
DDRB
DDB5 is only available in ATtiny12.
Port B Input Pins Address – PINB
Bit
7
6
5
4
3
2
1
0
$16
-
-
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
R
R
R
R
R
R
R
R
Initial value
0
0
N/A
N/A
N/A
N/A
N/A
N/A
PINB
The Port B Input Pins address – PINB – is not a register, and this address enables access to the physical value on each
Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the
pins are read.
37
Port B as General Digital I/O
The lowermost five pins in port B have equal functionality when used as digital I/O pins.
PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is
configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the
pin is configured as an input pin, the MOS pull-up resistor is activated. On ATtiny12 this feature can be disabled by setting
the Pull-up Disable (PUD) bit in the MCUCR register. To switch the pull-up resistor off, the PORTBn can be cleared (zero),
the pin can be configured as an output pin, or in ATtiny12, the PUD bit can be set. The port pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Table 20. DDBn Effects on Port B Pins
DDBn
PORTBn
I/O
Pull-up
Comment
0
0
Input
No
Tri-state (Hi-Z)
0
1
Input
Yes
PBn will source current if ext. pulled low. In ATtiny12 pull-ups can be disabled by setting
the PUD bit.
1
0
Output
No
Push-pull Zero Output
1
1
Output
No
Push-pull One Output
n: 4,3…0, pin number.
Note that in ATtiny10/11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. Because this pin is used for
12V programming, there is no ESD protection diode limiting the voltage on the pin to VCC + 0.5V. Thus, special care should
be taken to ensure that the voltage on this pin does not rise above VCC + 1V during normal operation. This may cause the
MCU to reset or enter programming mode unintentionally.
Alternate Functions of Port B
All port B pins are connected to a pin change detector that can trigger the pin change interrupt. See “Pin Change Interrupt”
on page 26 for details. In addition, Port B has the following alternate functions:
• RESET - Port B, Bit 5
When the RSTDISBL fuse is unprogrammed, this pin serves as external reset. When the RSTDISBL fuse is programmed,
this pin is a general input pin. In ATtiny12, it is also an open-drain output pin.
• XTAL2 - Port B, Bit 4
XTAL2, oscillator output. When this pin is not used for clock purposes, it is a general I/O pin. Refer to section “Pin Descriptions” on page 5 for details.
• XTAL1 - Port B, Bit 3
XTAL1, oscillator or clock input. When this pin is not used for clock purposes, it is a general I/O pin. Refer to section “Pin
Descriptions” on page 5 for details.
• T0/SCK - Port B, Bit 2
This pin can serve as the external counter clock input. See the timer/counter description for further details. If external
timer/counter clocking is selected, activity on this pin will clock the counter even if it is configured as an output. In ATtiny12
and serial programming mode, this pin serves as the serial clock input, SCK.
• INT0/AIN1/MISO - Port B, Bit 1
This pin can serve as the external interrupt0 input. See the interrupt description for details on how to enable this interrupt.
Note that activity on this pin will trigger the interrupt even if the pin is configured as an output. This pin also serves as the
negative input of the on-chip Analog Comparator. In ATtiny12 and serial programming mode, this pin serves as the serial
data input, MISO.
38
ATtiny10/11/12
ATtiny10/11/12
• AIN0/MOSI - Port B, Bit 0
This pin also serves as the positive input of the on-chip Analog Comparator. In ATtiny12 and serial programming mode, this
pin serves as the serial data output, MOSI.
During Power-down Mode, the schmitt triggers of the digital inputs are disconnected on the Analog Comparator input pins.
This allows an analog voltage close to V CC /2 to be present during power-down without causing excessive power
consumption.
Memory Programming
Program (and Data) Memory Lock Bits
The ATtiny10/11/12 MCU provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to
obtain the additional features listed in Table 21. The lock bits can only be erased with the Chip Erase command.
Table 21. Lock Bit Protection Modes
Memory Lock Bits
Mode
LB1
LB2
1
1
1
No memory lock features enabled.
2
0
1
Further programming of the Flash (and EEPROM for ATtiny12) is disabled.(1)
3
0
0
Same as mode 2, and verify is also disabled.
Note:
Protection Type
1. In the High-voltage Serial Programming mode, further programming of the fuse bits are also disabled. Program the fuse bits
before programming the lock bits.
Fuse Bits in ATtiny10/11
The ATtiny10/11 has five fuse bits, FSTRT, RSTDISBL and CKSEL2..0.
• FSTRT: See Table 7, “Start-up Times for the ATtiny10/11 (VCC = 2.7V),” on page 18 for which value to use. Default value
is unprogrammed (“1”).
• When RSTDISBL is programmed (“0”), the external reset function of pin PB5 is disabled.(1) Default value is
unprogrammed (“1”).
• CKSEL2..0: See Table 3, “Device Clocking Options Select,” on page 6, for which combination of CKSEL2..0 to use.
Default value is “100”, internal RC oscillator.
The status of the fuse bits is not affected by Chip Erase.
Note:
1. If the RSTDISBL Fuse is programmed, then the programming hardware should apply +12V to PB5 while the ATtiny10/11 is
in Power-on Reset. If not, the part can fail to enter programming mode caused by drive contention on PB0.
Fuse Bits in ATtiny12
The ATtiny12 has eight fuse bits, BODLEVEL, BODEN, SPIEN, RSTDISBL and CKSEL3..0. All the fuse bits are programmable in both High-voltage and Low-voltage Serial programming modes. Changing the fuses does not have any effect
while in programming mode.
• The BODLEVEL Fuse selects the Brown-out Detection level and changes the start-up times. See “Brown-out Detection
(ATtiny12)” on page 21. See Table 9, “ATtiny12 Clock Options and Start-up Times,” on page 19. Default value is
programmed (“0”).
• When the BODEN Fuse is programmed (“0”), the Brown-out Detector is enabled. See “Brown-out Detection (ATtiny12)”
on page 21. Default value is unprogrammed (“1”).
• When the SPIEN Fuse bit is programmed (“0”), Low-Voltage Serial Program and Data Downloading is enabled. Default
value is programmed (“0”). Unprogramming this fuse while in the Low-Voltage Serial Programming mode will disable
future in-system downloading attempts.
39
• When the RSTDISBL Fuse is programmed (“0”), the external reset function of pin PB5 is disabled.(1) Default value is
unprogrammed (“1”). Programming this fuse while in the Low-Voltage Serial Programming mode will disable future insystem downloading attempts.
• CKSEL3..0 fuses: See Table 3, “Device Clocking Options Select,” on page 6 and Table 9, “ATtiny12 Clock Options and
Start-up Times,” on page 19, for which combination of CKSEL3..0 to use. Default value is “0010”, internal RC oscillator
with long start-up time.
The status of the fuse bits is not affected by Chip Erase.
Note:
1. If the RSTDISBL Fuse is programmed, then the programming hardware should apply +12V to PB5 while the ATtiny12 is in
Power-on Reset. If not, the part can fail to enter programming mode caused by drive contention on PB0 and/or PB5.
Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. The three bytes reside in a separate address space.
For the ATtiny10 they are:
1. $000: $1E (indicates manufactured by Atmel)
2. $001: $90 (indicates 1 Kb QuickFlash memory)
3. $002: $03 (indicates ATtiny10 device when signature byte $001 is $90)
For the ATtiny11 they are:
1. $000: $1E (indicates manufactured by Atmel)
2. $001: $90 (indicates 1 Kb Flash memory)
3. $002: $04 (indicates ATtiny11 device when signature byte $001 is $90)
For the ATtiny12(1) they are:
1. $000: $1E (indicates manufactured by Atmel)
2. $001: $90 (indicates 1 Kb Flash memory)
3. $002: $05 (indicates ATtiny12 device when signature byte $001 is $90)
Note:
1. When both lock bits are programmed (Lock mode 3), the Signature Bytes can not be read in the Low-voltage Serial mode.
Reading the Signature Bytes will return: $00, $01 and $02.
Calibration Byte in ATtiny12
The ATtiny12 has a one-byte calibration value for the internal RC oscillator. This byte resides in the high byte of address
$000 in the signature address space. To make use of this byte, it should be read from this location and written into the
normal Flash Program memory. At start-up, the user software must read this Flash location and write the value to the
OSCCAL register.
Programming the Flash and EEPROM
ATtiny10/11
Atmel’s ATtiny10/11 offers 1K bytes of Flash Program memory.
The ATtiny10/11 is shipped with the on-chip Flash Program memory array in the erased state (i.e. contents = $FF) and
ready to be programmed.
This device supports a High-voltage (12V) Serial programming mode. Only minor currents (<1 mA) are drawn from the
+12V pin during programming.
The program memory array in the ATtiny10/11 is programmed byte-by-byte.
40
ATtiny10/11/12
ATtiny10/11/12
ATtiny12
Atmel’s ATtiny12 offers 1K bytes of in-system reprogrammable Flash Program memory and 64 bytes of in-system reprogrammable EEPROM Data memory.
The ATtiny12 is shipped with the on-chip Flash Program and EEPROM Data memory arrays in the erased state (i.e.
contents = $FF) and ready to be programmed.
This device supports a high-voltage (12V) serial programming mode and a low-voltage serial programming mode. The
+12V is used for programming enable only, and no current of significance is drawn by this pin. The Low-voltage Serial Programming mode provides a convenient way to download program and data into the ATtiny12 inside the user’s system.
The program and data memory arrays in the ATtiny12 are programmed byte-by-byte in either programming mode. For the
EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the Low-voltage Serial Programming
mode.
41
ATtiny10/11/12
During programming, the supply voltage must be in accordance with Table 22.
Table 22. Supply Voltage during Programming
Part
Low-voltage Serial Programming
High-voltage Serial Programming
ATtiny10/11L
Not applicable
4.5 - 5.5V
ATtiny10/11
Not applicable
4.5 - 5.5V
ATtiny12V
2.2 - 5.5V
4.5 - 5.5V
ATtiny12L
2.7 - 5.5V
4.5 - 5.5V
ATtiny12
4.0 - 5.5V
4.5 - 5.5V
High-voltage Serial Programming
This section describes how to program and verify Flash Program memory, EEPROM Data memory (ATtiny12), lock bits
and fuse bits in the ATtiny10/11/12.
Figure 27. High-voltage Serial Programming
11.5 - 12.5V
4.5 - 5.5V
ATtiny
SERIAL CLOCK INPUT
PB5 (RESET)
VCC
PB3 (XTAL1)
PB2
SERIAL DATA OUTPUT
PB1
SERIAL INSTR. INPUT
PB0
SERIAL DATA INPUT
GND
High-voltage Serial Programming Algorithm
To program and verify the ATtiny10/11/12 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 23):
1. Power-up sequence: Apply 4.5 - 5.5V between VCC and GND. Set PB5 and PB0 to “0” and wait at least 100 ns.
Toggle PB3 at least four times with minimum 100 ns pulse-width. Set PB3 to “0”. Wait at least 100 ns. Apply 12V to
PB5 and wait at least 100 ns before changing PB0. Wait 8 µs before giving any instructions.
2. The Flash array is programmed one byte at a time by supplying first the address, then the low and high data byte.
The write instruction is self-timed, wait until the PB2 (RDY/BSY) pin goes high.
3. The EEPROM array (ATtiny12 only) is programmed one byte at a time by supplying first the address, then the data
byte. The write instruction is self-timed, wait until the PB2 (RDY/BSY) pin goes high.
4. Any memory location can be verified by using the Read instruction which returns the contents at the selected
address at serial output PB2.
5. Power-off sequence: Set PB3 to “0”.
Set PB5 to “1”.
Turn VCC power off.
When writing or reading serial data to the ATtiny10/11/12, data is clocked on the rising edge of the serial clock, see Figure
28, Figure 29 and Table 24 for details.
42
ATtiny10/11/12
ATtiny10/11/12
Figure 28. High-voltage Serial Programming Waveforms
SERIAL DATA INPUT
PB0
MSB
LSB
SERIAL INSTR. INPUT
PB1
MSB
LSB
SERIAL DATA OUTPUT
PB2
SERIAL CLOCK INPUT
XTAL1/PB3
MSB
0
LSB
1
2
3
4
5
6
7
8
9
10
Table 23. High-voltage Serial Programming Instruction Set for ATtiny10/11/12
Instruction Format
Instruction
Instr.1
Instr.2
Instr.3
Instr.4
PB0
0_1000_0000_00
0_0000_0000_00
0_0000_0000_00
0_0000_0000_00
PB1
0_0100_1100_00
0_0110_0100_00
0_0110_1100_00
0_0100_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
PB0
0_0001_0000_00
0_0000_000a_00
0_bbbb_bbbb_00
PB1
0_0100_1100_00
0_0001_1100_00
0_0000_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
0_ i i i i_i i i i _00
0_0000_0000_00
0_0000_0000_00
0_0010_1100_00
0_0110_0100_00
0_0110_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
0_0000_0000_00
PB0
0_ i i i i_i i i i _00
0_0000_0000_00
0_0000_0000_00
PB1
0_0011_1100_00
0_0111_0100_00
0_0111_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
0_0000_0000_00
Read Flash
High and Low
Address
PB0
0_0000_0010_00
0_0000_000a_00
0_bbbb_bbbb_00
PB1
0_0100_1100_00
0_0001_1100_00
0_0000_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
Read Flash
Low byte
PB0
0_0000_0000_00
0_0000_0000_00
PB1
0_0110_1000_00
0_0110_1100_00
PB2
x_xxxx_xxxx_xx
o_oooo_ooox_xx
PB0
0_0000_0000_00
0_0000_0000_00
PB1
PB2
0_0111_1000_00
0_0111_1100_00
x_xxxx_xxxx_xx
o_oooo_ooox_xx
Write EEPROM
Low Address
(ATtiny12)
PB0
0_0001_0001_00
0_00bb_bbbb_00
PB1
0_0100_1100_00
0_0000_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
Write EEPROM
byte (ATtiny12)
PB0
0_ i i i i_i i i i _00
0_0000_0000_00
0_0000_0000_00
PB1
0_0010_1100_00
0_0110_0100_00
0_0110_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
0_0000_0000_00
0_0000_0011_00
0_00bb_bbbb_00
0_0100_1100_00
0_0000_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
Chip Erase
Write Flash
High and Low
Address
Write Flash Low PB0
byte
PB1
Write Flash
High byte
Read Flash
High byte
Read EEPROM PB0
Low Address
PB1
(ATtiny12)
PB2
Operation Remarks
Wait after Instr.4 until PB2 goes
high for the Chip Erase cycle to
finish.
Repeat Instr.2 for a new 256 byte
page. Repeat Instr.3 for each new
address.
Wait after Instr.3 until PB2 goes
high. Repeat Instr.1, Instr. 2 and
Instr.3 for each new address.
Wait after Instr.3 until PB2 goes
high. Repeat Instr.1, Instr. 2 and
Instr.3 for each new address.
Repeat Instr.2 and Instr.3 for each
new address.
Repeat Instr.1 and Instr.2 for each
new address.
Repeat Instr.1 and Instr.2 for each
new address.
Repeat Instr.2 for each new
address.
Wait after Instr.3 until PB2 goes
high
Repeat Instr.2 for each new
address.
43
Table 23. High-voltage Serial Programming Instruction Set for ATtiny10/11/12 (Continued)
Instruction Format
Instruction
Instr.1
Instr.2
0_0000_0000_00
0_0000_0000_00
0_0110_1000_00
0_0110_1100_00
PB2
x_xxxx_xxxx_xx
o_oooo_ooox_xx
PB0
0_0100_0000_00
0_0007_6543_00
0_0000_0000_00
0_0000_0000_00
PB1
0_0100_1100_00
0_0010_1100_00
0_0110_0100_00
0_0110_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
PB0
0_0100_0000_00
0_CBA9_8543_00
0_0000_0000_00
0_0000_0000_00
PB1
0_0100_1100_00
0_0010_1100_00
0_0110_0100_00
0_0110_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
PB0
0_0010_0000_00
0_0000_0210_00
0_0000_0000_00
0_0000_0000_00
PB1
0_0100_1100_00
0_0010_1100_00
0_0110_0100_00
0_0110_1100_00
PB2
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
0_0000_0000_00
PB0
PB1
PB2
0_0000_0100_00
0_0000_0000_00
0_0000_0000_00
0_0100_1100_00
0_0110_1000_00
0_0110_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xx76_543x_xx
PB0
PB1
PB2
0_0000_0100_00
0_0000_0000_00
0_0000_0000_00
0_0100_1100_00
0_0110_1000_00
0_0110_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
C_BA98_543x_xx
PB0
PB1
PB2
0_0000_0100_00
0_0000_0000_00
0_0000_0000_00
0_0100_1100_00
0_0111_1000_00
0_0111_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_21xx_xx
PB0
PB1
PB2
0_0000_1000_00
0_0000_00bb_00
0_0000_0000_00
0_0000_0000_00
0_0100_1100_00
0_0000_1100_00
0_0110_1000_00
0_0110_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
o_oooo_ooox_xx
Read
PB0
Calibration Byte PB1
(ATtiny12)
0_0000_1000_00
0_0000_0000_00
0_0000_0000_00
0_0000_0000_00
0_0100_1100_00
0_0000_1100_00
0_0111_1000_00
0_0111_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
o_oooo_ooox_xx
Read EEPROM PB0
byte (ATtiny12) PB1
Write Fuse bits
(ATtiny10/11)
Write Fuse bits
(ATtiny12)
Write Lock bits
Read Fuse bits
(ATtiny10/11)
Read Fuse bits
(ATtiny12)
Read Lock bits
Read Signature
Bytes
PB2
Notes:
44
a = address high bits
b = address low bits
i = data in
o = data out
x = don’t care
1 = Lock Bit1
2 = Lock Bit2
3 = CKSEL0 Fuse
4 = CKSEL1 Fuse
5 = CKSEL2 Fuse
9, 6 = RSTDISBL Fuse
7 = FSTRT Fuse
8 = CKSEL3 Fuse
A = SPIEN Fuse
B = BODEN Fuse
C = BODLEVEL Fuse
ATtiny10/11/12
Instr.3
Instr.4
Operation Remarks
Repeat Instr.2 for each new
address
Wait tWLWH_PFB after Instr.3 for the
Write fuse bits cycle to finish. Write
7 - 3 = “0” to program the fuse bit.
Wait after Instr.4 until PB2 goes
high. Write C - A, 9, 8, 5 - 3 = “0” to
program the fuse bit.
Wait after Instr.4 until PB2 goes
high. Write 2, 1 = “0” to program
the lock bit.
Reading 7 - 3 = “0” means the fuse
bit is programmed.
Reading C - A, 9, 8, 5 - 3 = “0”
means the fuse bit is programmed.
Reading 2, 1 = “0” means the lock
bit is programmed.
Repeat Instr.2 - Instr.4 for each
signature byte address
ATtiny10/11/12
High-voltage Serial Programming Characteristics
Figure 29. High-voltage Serial Programming Timing
SDI (PB0), SII (PB1)
tIVSH
tSLSH
tSHIX
SCI (PB3)
tSHSL
SDO (PB2)
tSHOV
Table 24. High-voltage Serial Programming Characteristics
TA = 25°C ± 10%, VCC = 5.0V ± 10% (Unless otherwise noted)
Symbol
Parameter
Min
Typ
Max
Units
tSHSL
SCI (PB3) Pulse Width High
100
ns
tSLSH
SCI (PB3) Pulse Width Low
100
ns
tIVSH
SDI (PB0), SII (PB1) Valid to SCI (PB3)
High
50
ns
tSHIX
SDI (PB0), SII (PB1) Hold after SCI (PB3)
High
50
ns
tSHOV
SCI (PB3) High to SDO (PB2) Valid
10
16
32
ns
tWLWH_PFB
Wait after Instr. 3 for Write Fuse Bits
1.0
1.5
1.8
ms
Low-voltage Serial Downloading (ATtiny12 only)
Both the program and data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The
serial interface consists of pins SCK, MOSI (input) and MISO (output), see Figure 30. After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed.
Figure 30. Serial Programming and Verify
2.2 - 5.5V
ATtiny12
GND
PB5 (RESET)
GND
VCC
PB2
SCK
PB1
MISO
PB0
MOSI
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first
execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the
program and EEPROM arrays into $FF.
The program and EEPROM memory arrays have separate address spaces:
$0000 to $01FF for program memory and $000 to $03F for EEPROM memory.
45
The device can be clocked by any clock option during Low-voltage Serial Programming. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 MCU clock cycles
High: > 2 MCU clock cycles
Low-voltage Serial Programming Algorithm
When writing serial data to the ATtiny12, data is clocked on the rising edge of SCK. When reading data from the ATtiny12,
data is clocked on the falling edge of SCK. See Figure 31, Figure 32 and Table 26 for timing details. To program and verify
the ATtiny12 in the serial programming mode, the following sequence is recommended (See 4 byte instruction formats in
Table 25):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In accordance with the setting of CKSEL
fuses, apply a crystal/resonator, external clock or RC network, or let the device run on the internal RC oscillator. In
some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be
given a positive pulse of at least two MCU cycles duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable Serial instruction to the
MOSI (PB0) pin.
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the
second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the
echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a
positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is
no functional device connected.
4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a
positive pulse, and start over from Step 2. See Table 27 on page 49 for tWD_ERASE value.
5. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the
appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written.
Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait
tWD_FLASH or tWD_EEPROM before transmitting the next instruction. See Table 28 on page 49 for tWD_FLASH and
tWD_EEPROM values. In an erased device, no $FFs in the data file(s) needs to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the content at the selected
address at the serial output MISO (PB1) pin.
7. At the end of the programming session, RESET can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set XTAL1 to “0” (if external clocking is used).
Set RESET to “1”.
Turn VCC power off.
46
ATtiny10/11/12
ATtiny10/11/12
Data Polling
When a byte is being programmed into the Flash or EEPROM, reading the address location being programmed will give
the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to
determine when the next byte can be written. This will not work for the value $FF, so when programming this value, the
user will have to wait for at least tWD_FLASH or tWD_EEPROM before programming the next byte. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if
the EEPROM is reprogrammed without chip-erasing the device. In that case, data polling cannot be used for the value $FF,
and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 28 for tWD_FLASH and
tWD_EEPROM values.
Figure 31. Low-voltage Serial Programming Waveforms
SERIAL DATA INPUT
PB0(MOSI)
MSB
LSB
SERIAL DATA OUTPUT
PB1(MISO)
MSB
LSB
SERIAL CLOCK INPUT
PB2(SCK)
47
Table 25. Low-voltage Serial Programming Instruction Set
Instruction Format
Instruction
Byte 1
Byte 2
Byte 3
Byte4
1010 1100
0101 0011
xxxx xxxx
xxxx xxxx
Enable serial programming while
RESET is low.
1010 1100
100x xxxx
xxxx xxxx
xxxx xxxx
Chip erase Flash and EEPROM
memory arrays.
0010 H000
xxxx xxxa
bbbb bbbb
oooo oooo
Read H (high or low) data o from
program memory at word address
a:b.
0100 H000
xxxx xxxa
bbbb bbbb
iiii iiii
Write H (high or low) data i to
program memory at word address
a:b.
Read EEPROM
Memory
1010 0000
xxxx xxxx
xxbb bbbb
oooo oooo
Read data o from EEPROM memory
at address b.
Write EEPROM
Memory
1100 0000
xxxx xxxx
xxbb bbbb
iiii iiii
Write data i to EEPROM memory at
address b.
1010 1100
1111 1211
xxxx xxxx
xxxx xxxx
Write lock bits. Set bits 1,2 = “0” to
program lock bits.
0101 1000
xxxx xxxx
xxxx xxxx
xxxx x21x
Read lock bits. “0” = programmed, “1”
= unprogrammed.
Read Signature Bytes
0011 0000
xxxx xxxx
0000 00bb
oooo oooo
Read signature byte o at address b.(1)
Read Calibration Byte
0011 1000
xxxx xxxx
0000 0000
oooo oooo
1010 1100
101x xxxx
xxxx xxxx
A987 6543
Set bits A, 9 - 3 = “0” to program, “1”
to unprogram.
0101 0000
xxxx xxxx
xxxx xxxx
A987 6543
Read fuse bits. “0” = programmed, “1”
= unprogrammed.
Programming Enable
Chip Erase
Read Program Memory
Write Program Memory
Write Lock Bits
Read Lock Bits
Write Fuse Bits
Read Fuse Bits
Operation
Note:
a = address high bits
b = address low bits
H = 0 - Low byte, 1 - High byte
o = data out
i = data in
x = don’t care
1 = Lock bit 1
2 = Lock bit 2
3 = CKSEL0 Fuse
4 = CKSEL1 Fuse
5 = CKSEL2 Fuse
6 = CKSEL3 Fuse
7 = RSTDISBL Fuse
8 = SPIEN Fuse
9 = BODEN Fuse
A = BODLEVEL Fuse
Note:
1. The signature bytes are not readable in Lock mode 3, i.e. both lock bits programmed.
48
ATtiny10/11/12
ATtiny10/11/12
Low-voltage Serial Programming Characteristics
Figure 32. Low-voltage Serial Programming Timing
MOSI
tOVSH
SCK
tSHOX
tSLSH
tSHSL
MISO
tSLIV
Table 26. Low-voltage Serial Programming Characteristics
TA = -40°C to 85°C, VCC = 2.2 - 5.5V (Unless otherwise noted)
Symbol
Parameter
1/tCLCL
Oscillator Frequency (VCC = 2.2 - 2.7V)
tCLCL
Oscillator Period (VCC = 2.2 - 2.7V)
1/tCLCL
Oscillator Frequency (VCC = 2.7 - 4.0V)
tCLCL
Oscillator Period (VCC = 2.7 - 4.0V)
1/tCLCL
Oscillator Frequency (VCC = 4.0 - 5.5V)
tCLCL
Oscillator Period (VCC = 4.0 - 5.5V)
tSHSL
Min
Typ
0
Max
Units
1
MHz
1000
ns
0
4
250
MHz
ns
0
8
MHz
125
ns
SCK Pulse Width High
2 tCLCL
ns
tSLSH
SCK Pulse Width Low
2 tCLCL
ns
tOVSH
MOSI Setup to SCK High
tCLCL
ns
tSHOX
MOSI Hold after SCK High
2 tCLCL
ns
tSLIV
SCK Low to MISO Valid
10
16
32
ns
Table 27. Minimum Wait Delay after the Chip Erase Instruction
Symbol
Minimum Wait Delay
tWD_ERASE
3.4 ms
Table 28. Minimum Wait Delay after Writing a Flash or EEPROM Location
Symbol
Minimum Wait Delay
tWD_FLASH
1.7 ms
tWD_EEPROM
3.4 ms
49
Electrical Characteristics
Absolute Maximum Ratings
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-1.0V to VCC+0.5V
Voltage on RESET with respect to Ground......-1.0V to +13.0V
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins................................ 100.0 mA
50
ATtiny10/11/12
*NOTICE:
Stresses beyond those ratings listed under
“Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at
these or other conditions beyond those indicated
in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ATtiny10/11/12
DC Characteristics – Preliminary Data
TA = -40°C to 85°C, VCC = 2.7V to 5.5V for ATtiny10/11, VCC = 1.8V to 5.5V for ATtiny12 (Unless otherwise noted)
Symbol
Parameter
Condition
Min
VIL
Input Low Voltage
Except (XTAL)
-0.5
0.3 VCC(1)
V
-0.5
(1)
V
0.6 VCC
(2)
VCC + 0.5
V
(2)
VCC + 0.5
V
VCC + 0.5
V
IOL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 3V
0.6
0.5
V
V
0.6
0.5
V
V
VIL1
VIH
Input Low Voltage
XTAL
Input High Voltage
Except (XTAL, RESET)
Typ
0.1 VCC
VIH1
Input High Voltage
XTAL
0.7 VCC
VIH2
Input High Voltage
RESET
0.85 VCC(2)
(3)
Max
Units
VOL
Output Low Voltage
Port B
VOL
Output Low Voltage
PB5 (ATtiny12)
IOL = 12 mA, VCC = 5V
IOL = 6 mA, VCC = 3V
VOH
Output High Voltage(4)
Port B
IOH = -3 mA, VCC = 5V
IOH = -1.5 mA, VCC = 3V
IIL
Input Leakage Current
I/O Pin
VCC = 5.5V, Pin Low
(Absolute value)
8.0
µA
IIH
Input Leakage Current
I/O Pin
VCC = 5.5V, Pin High
(Absolute value)
8.0
µA
RI/O
I/O Pin Pull-Up
122
kΩ
Active 1 MHz, VCC = 3V
(ATtiny12V)
TBD
mA
Active 2 MHz, VCC = 3V
(ATtiny10/11L)
TBD
mA
Active 4 MHz, VCC = 3V
(ATtiny12L)
3.0
mA
Active 6 MHz, VCC = 5V
(ATtiny10/11)
TBD
mA
Active 8 MHz, VCC = 5V
(ATtiny12)
TBD
mA
Idle 1 MHz, VCC = 3V
(ATtiny12V)
TBD
mA
Idle 2 MHz, VCC = 3V
(ATtiny10/11L)
TBD
mA
1.2
mA
Idle 6 MHz, VCC = 5V
(ATtiny10/11)
TBD
mA
Idle 8 MHz, VCC = 5V
(ATtiny12)
TBD
mA
ICC
4.3
2.3
V
V
35
Power Supply Current
Idle 4 MHz, VCC = 3V
(ATtiny12L)
1.0
Power Down(5), VCC = 3V,
WDT enabled
9.0
15
µA
Power Down(5), VCC = 3V.
WDT disabled
<1
2
µA
51
DC Characteristics – Preliminary Data (Continued)
TA = -40°C to 85°C, VCC = 2.7V to 5.5V for ATtiny10/11, VCC = 1.8V to 5.5V for ATtiny12 (Unless otherwise noted)
Symbol
Parameter
Condition
VACIO
Analog Comparator
Input Offset Voltage
VCC = 5V
VIN = VCC/2
IACLK
Analog Comparator
Input Leakage Current
VCC = 5V
VIN = VCC/2
TACPD
Analog Comparator
Propagation Delay
VCC = 2.7V
VCC = 4.0V
Notes:
52
Min
Typ
-50
750
500
Max
Units
40
mV
50
nA
ns
1. “Max” means the highest value where the pin is guaranteed to be read as low.
2. “Min” means the lowest value where the pin is guaranteed to be read as high.
3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 100 mA.
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink current greater than the listed test conditions.
4. Although each I/O port can source more than the test conditions (3 mA at VCC = 5V, 1.5 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 100 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. Minimum VCC for Power-down is 1.5V. (On ATtiny12: only with BOD disabled)
ATtiny10/11/12
ATtiny10/11/12
External Clock Drive Waveforms
Figure 33. External Clock
VIH1
VIL1
External Clock Drive ATtiny10/11
VCC = 2.7V to 4.0V
Symbol
Parameter
1/tCLCL
Oscillator Frequency
VCC = 4.0V to 5.5V
Min
Max
Min
Max
Units
0
2
0
6
MHz
tCLCL
Clock Period
500
167
ns
tCHCX
High Time
200
67
ns
tCLCX
Low Time
200
67
ns
tCLCH
Rise Time
1.6
0.5
µs
tCHCL
Fall Time
1.6
0.5
µs
External Clock Drive ATtiny12
VCC = 1.8V to 2.7V
Symbol
Parameter
1/tCLCL
Oscillator Frequency
VCC = 2.7V to 4.0V
VCC = 4.0V to 5.5V
Min
Max
Min
Max
Min
Max
Units
0
1
0
4
0
8
MHz
tCLCL
Clock Period
1000
250
125
ns
tCHCX
High Time
400
100
50
ns
tCLCX
Low Time
400
100
50
ns
tCLCH
Rise Time
1.6
1.6
0.5
µs
tCHCL
Fall Time
1.6
1.6
0.5
µs
Table 29. External RC Oscillator, Typical Frequencies
Note:
R [kΩ]
C [pF]
f
100
70
100 kHz
31.5
20
1.0 MHz
6.5
20
4.0 MHz
R should be in the range 3-100 kΩ, and C should be at least 20 pF. The C values given in the table includes pin capacitance.
This will vary with package type.
53
ATtiny11 Typical Characteristics
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption
measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source.
The power consumption in Power-down Mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O
pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and
frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance,
VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down Mode with Watchdog Timer enabled and Power-down Mode
with Watchdog Timer disabled represents the differential current drawn by the Watchdog timer.
Figure 34. Active Supply Current vs. Frequency
ACTIVE SUPPLY CURRENT vs. FREQUENCY
TA = 25˚C
18
VCC = 6V
16
VCC = 5.5V
14
VCC = 5V
12
ICC (mA)
VCC = 4.5V
10
VCC = 4V
8
VCC = 3.6V
6
VCC = 3.3V
4
VCC = 3.0V
VCC = 2.7V
2
0
VCC = 2.4V
VCC = 2.1V
VCC = 1.8V
0
1
2
3
4
5
6
7
8
Frequency (MHz)
54
ATtiny10/11/12
9
10
11
12
13
14
15
ATtiny10/11/12
Figure 35. Active Supply Current vs. VCC
ACTIVE SUPPLY CURRENT vs. Vcc
FREQUENCY = 4 MHz
10
9
8
TA = 25˚C
7
TA = 85˚C
ICC (mA)
6
5
4
3
2
1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
VCC (V)
Figure 36. Idle Supply Current vs. Frequency
IDLE SUPPLY CURRENT vs. FREQUENCY
TA = 25˚C
5
VCC = 6V
4.5
4
VCC = 5.5V
3.5
VCC = 5V
ICC (mA)
3
VCC = 4.5V
2.5
VCC = 4V
2
VCC = 3.6V
1.5
VCC = 3.3V
1
VCC = 3.0V
VCC = 2.7V
0.5
0
0
VCC = 2.4V
VCC = 2.1V
VCC = 1.8V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Frequency (MHz)
55
Figure 37. Idle Supply Current vs. VCC
IDLE SUPPLY CURRENT vs. Vcc
FREQUENCY = 4 MHz
3
TA = 25˚C
2
ICC (mA)
TA = 85˚C
2
1
1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
VCC (V)
Figure 38. Power-down Supply Current vs. VCC
POWER-DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER DISABLED
9
TA = 85˚C
8
ICC (µA)
7
6
5
4
3
2
1
TA = 25˚C
0
1.5
2
2.5
3
3.5
VCC (V)
56
ATtiny10/11/12
4
4.5
5
5.5
6
ATtiny10/11/12
Figure 39. Power-down Supply Current vs. VCC
POWER-DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER ENABLED
90
80
70
I CC (µA)
60
TA = 85˚C
TA = 25˚C
50
40
30
20
10
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VCC (V)
Figure 40. Analog Comparator Current vs. VCC
ANALOG COMPARATOR CURRENT vs. Vcc
1
0.9
0.8
TA = 25˚C
I CC (mA)
0.7
TA = 85˚C
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VCC (V)
57
Analog comparator offset voltage is measured as absolute offset.
Figure 41. Analog Comparator Offset Voltage vs. Common Mode Voltage
ANALOG COMPARATOR OFFSET VOLTAGE vs.
COMMON MODE VOLTAGE
Vcc = 5V
18
16
TA = 25˚C
Offset Voltage (mV)
14
12
TA = 85˚C
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Common Mode Voltage (V)
Figure 42. Analog Comparator Offset Voltage vs. Common Mode Voltage
ANALOG COMPARATOR OFFSET VOLTAGE vs.
Vcc = 2.7V
COMMON MODE VOLTAGE
10
TA = 25˚C
Offset Voltage (mV)
8
6
TA = 85˚C
4
2
0
0
0.5
1
1.5
Common Mode Voltage (V)
58
ATtiny10/11/12
2
2.5
3
ATtiny10/11/12
Figure 43. Analog Comparator Input Leakage Current
ANALOG COMPARATOR INPUT LEAKAGE CURRENT
VCC = 6V
TA = 25˚C
60
50
IACLK (nA)
40
30
20
10
0
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
VIN (V)
Figure 44. Watchdog Oscillator Frequency vs. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. Vcc
1600
1400
TA = 25˚C
1200
TA = 85˚C
FRC (kHz)
1000
800
600
400
200
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VCC (V)
59
Sink and source capabilities of I/O ports are measured on one pin at a time.
Figure 45. Pull-up Resistor Current vs. Input Voltage
PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 5V
120
TA = 25˚C
100
TA = 85˚C
I OP (µA)
80
60
40
20
0
0
0.5
1
1.5
2
2.5
VOP (V)
3
3.5
4
4.5
5
Figure 46. Pull-up Resistor Current vs. Input Voltage
PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 2.7V
30
TA = 25˚C
25
TA = 85˚C
I OP (µA)
20
15
10
5
0
0
0.5
1
1.5
VOP (V)
60
ATtiny10/11/12
2
2.5
3
ATtiny10/11/12
Figure 47. I/O Pin Sink Current vs. Output Voltage
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
80
70
TA = 25˚C
60
I OL (mA)
50
40
TA = 85˚C
30
20
10
0
0
0.5
1
1.5
2
2.5
3
VOL (V)
Figure 48. I/O Pin Source Current vs. Output Voltage
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
18
TA = 25˚C
16
14
TA = 85˚C
I OH (mA)
12
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOH (V)
61
Figure 49. I/O Pin Sink Current vs. Output Voltage
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
30
TA = 25˚C
25
20
I OL (mA)
TA = 85˚C
15
10
5
0
0
0.5
1
1.5
2
VOL (V)
Figure 50. I/O Pin Source Current vs. Output Voltage
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
6
TA = 25˚C
5
4
I OH (mA)
TA = 85˚C
3
2
1
0
0
0.5
1
1.5
VOH (V)
62
ATtiny10/11/12
2
2.5
3
ATtiny10/11/12
Figure 51. I/O Pin Input Threshold Voltage vs. VCC
I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
TA = 25˚C
2.5
Threshold Voltage (V)
2
1.5
1
0.5
0
2.7
4.0
5.0
VCC
Figure 52. I/O Pin Input Hysteresis vs. VCC
I/O PIN INPUT HYSTERESIS vs. Vcc
TA = 25˚C
0.18
Input Hysteresis (V)
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
2.7
4.0
5.0
VCC
63
ATtiny12 Typical Characteristics – PRELIMINARY DATA
The following charts show typical behavior. These data are characterized, but not tested. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with
rail-to-rail output is used as clock source.
The power consumption in Power-down Mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O
pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and
frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance,
VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down Mode with Watchdog Timer enabled and Power-down Mode
with Watchdog Timer disabled represents the differential current drawn by the Watchdog timer.
Figure 53. Calibrated Internal RC Oscillator Frequency vs. VCC
Frequency Relative to Frequency at 25˚C and VCC = 5.0V
Calibrated RC Oscillator Frequency vs. Operating Voltage
1.02
TA = 25
˚C
25 C
1.00
TA = 85˚C
0.98
0.96
0.94
0.92
0.90
0.88
2
2.5
3
3.5
4
4.5
Operating Voltage [V]
64
TA = 45˚C
TA = 70˚C
ATtiny10/11/12
5
5.5
6
ATtiny10/11/12
Analog Comparator offset voltage is measured as absolute offset.
Figure 54. Analog Comparator Offset Voltage vs. Common Mode Voltage
ANALOG COMPARATOR OFFSET VOLTAGE vs.
COMMON MODE VOLTAGE
VCC = 5V
18
16
TA = 25˚C
Offset Voltage (mV)
14
12
TA = 85˚C
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Common Mode Voltage (V)
Figure 55. Analog Comparator Offset Voltage vs. Common Mode Voltage
ANALOG COMPARATOR OFFSET VOLTAGE vs.
VCC = 2.7V
COMMON MODE VOLTAGE
10
TA = 25˚C
Offset Voltage (mV)
8
6
TA = 85˚C
4
2
0
0
0.5
1
1.5
2
2.5
3
Common Mode Voltage (V)
65
Figure 56. Analog Comparator Input Leakage Current
ANALOG COMPARATOR INPUT LEAKAGE CURRENT
VCC = 6V
TA = 25˚C
60
50
I ACLK (nA)
40
30
20
10
0
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
VIN (V)
Figure 57. Watchdog Oscillator Frequency vs. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. Vcc
1600
1400
TA = 25˚C
1200
TA = 85˚C
FRC (kHz)
1000
800
600
400
200
0
1.5
2
2.5
3
3.5
4
VCC (V)
66
ATtiny10/11/12
4.5
5
5.5
6
ATtiny10/11/12
Sink and source capabilities of I/O ports are measured on one pin at a time.
Figure 58. Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
120
TA = 25˚C
100
TA = 85˚C
I OP (µA)
80
60
40
20
0
0
0.5
1
1.5
2
2.5
VOP (V)
3
3.5
4
4.5
5
Figure 59. Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
30
TA = 25˚C
25
TA = 85˚C
IOP (µA)
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
VOP (V)
67
Figure 60. I/O Pin Sink Current vs. Output Voltage (VCC = 5V)
70
TA = 25˚C
60
TA = 85˚C
50
I OL (mA)
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
VOL (V)
Figure 61. I/O Pin Source Current vs. Output Voltage (VCC = 5V)
20
TA = 25˚C
18
16
TA = 85˚C
14
I OH (mA)
12
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
VOH (V)
68
ATtiny10/11/12
3
3.5
4
4.5
5
ATtiny10/11/12
Figure 62. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)
25
TA = 25˚C
20
TA = 85˚C
I OL (mA)
15
10
5
0
0
0.5
1
1.5
2
VOL (V)
Figure 63. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)
6
TA = 25˚C
5
TA = 85˚C
I OH (mA)
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
VOH (V)
69
Figure 64. I/O Pin Input Threshold Voltage vs. VCC (TA = 25°C)
2.5
Threshold Voltage (V)
2
1.5
1
0.5
0
2.7
4.0
5.0
VCC
Figure 65. I/O Pin Input Hysteresis vs. VCC (TA = 25°C)
0.18
Input Hysteresis (V)
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
2.7
4.0
VCC
70
ATtiny10/11/12
5.0
ATtiny10/11/12
Register Summary ATtiny10/11
Address
$3F
$3E
$3D
$3C
$3B
$3A
$39
$38
$37
$36
$35
$34
$33
$32
$31
$30
...
$22
$21
$20
$1F
$1E
$1D
$1C
$1B
$1A
$19
$18
$17
$16
$15
...
$0A
$09
$08
…
$00
Notes:
Name
SREG
Reserved
Reserved
Reserved
GIMSK
GIFR
TIMSK
TIFR
Reserved
Reserved
MCUCR
MCUSR
TCCR0
TCNT0
Reserved
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTB
DDRB
PINB
Reserved
Reserved
Reserved
Reserved
ACSR
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
I
T
H
S
V
N
Z
C
page 14
-
INT0
INTF0
-
PCIE
PCIF
-
-
-
-
TOIE0
TOV0
-
page 24
page 25
page 25
page 25
-
-
SE
-
SM
Timer/Counter0 (8 Bit)
CS02
ISC01
EXTRF
CS01
ISC00
PORF
CS00
page 26
page 22
page 30
page 31
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
page 31
-
-
PINB5
PORTB4
DDB4
PINB4
PORTB3
DDB3
PINB3
PORTB2
DDB2
PINB2
PORTB1
DDB1
PINB1
PORTB0
DDB0
PINB0
page 37
page 37
page 37
ACD
-
ACO
ACI
ACIE
-
ACIS1
ACIS0
page 35
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
71
Register Summary ATtiny12
Address
$3F
$3E
$3D
$3C
$3B
$3A
$39
$38
$37
$36
$35
$34
$33
$32
$31
$30
...
$22
$21
$20
$1F
$1E
$1D
$1C
$1B
$1A
$19
$18
$17
$16
$15
...
$0A
$09
$08
...
$00
Note:
Name
SREG
Reserved
Reserved
Reserved
GIMSK
GIFR
TIMSK
TIFR
Reserved
Reserved
MCUCR
MCUSR
TCCR0
TCNT0
OSCCAL
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEAR
EEDR
EECR
Reserved
Reserved
Reserved
PORTB
DDRB
PINB
Reserved
Reserved
Reserved
Reserved
ACSR
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
I
T
H
S
V
N
Z
C
page 14
-
INT0
INTF0
-
PCIE
PCIF
-
-
-
-
TOIE0
TOV0
-
page 24
page 25
page 25
page 25
-
PUD
-
SE
-
BORF
CS02
ISC01
EXTRF
CS01
ISC00
PORF
CS00
page 26
page 23
page 30
page 31
page 28
-
-
-
WDP2
WDP1
WDP0
page 32
-
-
-
-
-
EEWE
EERE
page 33
page 33
page 33
-
-
DDB5
PINB5
PORTB4
DDB4
PINB4
PORTB3
DDB3
PINB3
PORTB2
DDB2
PINB2
PORTB1
DDB1
PINB1
PORTB0
DDB0
PINB0
page 37
page 37
page 37
ACD
AINBG
ACO
ACI
ACIE
-
ACIS1
ACIS0
page 35
SM
WDRF
Timer/Counter0 (8 Bit)
Oscillator Calibration Register
WDTOE
WDE
EEPROM Address Register
EEPROM Data Register
EERIE
EEMWE
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
72
ATtiny10/11/12
ATtiny10/11/12
Instruction Set Summary
Mnemonics
Operands
Description
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
ADC
Rd, Rr
Add with Carry two Registers
SUB
Rd, Rr
Subtract two Registers
SUBI
Rd, K
Subtract Constant from Register
SBC
Rd, Rr
Subtract with Carry two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd,K
Set Bit(s) in Register
CBR
Rd,K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
RCALL
k
Relative Subroutine Call
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less Than Zero, Signed
BRHS
k
Branch if Half Carry Flag Set
BRHC
k
Branch if Half Carry Flag Cleared
BRTS
k
Branch if T Flag Set
BRTC
k
Branch if T Flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Branch if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
Operation
Flags
#Clocks
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd⊕Rr
Rd ← $FF - Rd
Rd ← $00 - Rd
Rd ← Rd v K
Rd ← Rd • (FFh - K)
Rd ← Rd + 1
Rd ← Rd - 1
Rd ← Rd • Rd
Rd ← Rd⊕Rd
Rd ← $FF
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PC ← PC + k + 1
PC ← PC + k + 1
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3
Rd - Rr
Rd - Rr - C
Rd - K
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC + k + 1
if (SREG(s) = 0) then PC←PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2
3
4
4
1/2
1
1
1
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
73
Instruction Set Summary (Continued)
Mnemonics
Operands
Description
DATA TRANSFER INSTRUCTIONS
LD
Rd,Z
Load Register Indirect
ST
Z,Rr
Store Register Indirect
MOV
Rd, Rr
Move Between Registers
LDI
Rd, K
Load Immediate
IN
Rd, P
In Port
OUT
P, Rr
Out Port
LPM
Load Program Memory
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
CBI
P,b
Clear Bit in I/O Register
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left Through Carry
ROR
Rd
Rotate Right Through Carry
ASR
Rd
Arithmetic Shift Right
SWAP
Rd
Swap Nibbles
BSET
s
Flag Set
BCLR
s
Flag Clear
BST
Rr, b
Bit Store from Register to T
BLD
Rd, b
Bit load from T to Register
SEC
Set Carry
CLC
Clear Carry
SEN
Set Negative Flag
CLN
Clear Negative Flag
SEZ
Set Zero Flag
CLZ
Clear Zero Flag
SEI
Global Interrupt Enable
CLI
Global Interrupt Disable
SES
Set Signed Test Flag
CLS
Clear Signed Test Flag
SEV
Set Twos Complement Overflow
CLV
Clear Twos Complement Overflow
SET
Set T in SREG
CLT
Clear T in SREG
SEH
Set Half Carry Flag in SREG
CLH
Clear Half Carry Flag in SREG
NOP
No Operation
SLEEP
Sleep
WDR
Watch Dog Reset
74
ATtiny10/11/12
Operation
Flags
#Clocks
Rd ← (Z)
(Z) ← Rr
Rd ← Rr
Rd ← K
Rd ← P
P ← Rr
R0 ← (Z)
None
None
None
None
None
None
None
2
2
1
1
1
1
3
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)
Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)
Rd(n) ← Rd(n+1), n = 0..6
Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C←1
C←0
N←1
N←0
Z←1
Z←0
I←1
I←0
S←1
S←0
V← 1
V←0
T← 1
T ←0
H←1
H←0
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
ATtiny10/11/12
Ordering Information
Power Supply
Speed (MHz)
Ordering Code
Package
2.7 - 5.5V
2
ATtiny11L-2PC
ATtiny11L-2SC
8P3
8S2
Commercial
(0°C to 70°C)
ATtiny11L-2PI
ATtiny11L-2SI
8P3
8S2
Industrial
(-40°C to 85°C)
ATtiny11-6PC
ATtiny11-6SC
8P3
8S2
Commercial
(0°C to 70°C)
ATtiny11-6PI
ATtiny11-6SI
8P3
8S2
Industrial
(-40°C to 85°C)
ATtiny12V-1PC
ATtiny12V-1SC
8P3
8S2
Commercial
(0°C to 70°C)
ATtiny12V-1PI
ATtiny12V-1SI
8P3
8S2
Industrial
(-40°C to 85°C)
ATtiny12L-4PC
ATtiny12L-4SC
8P3
8S2
Commercial
(0°C to 70°C)
ATtiny12L-4PI
ATtiny12L-4SI
8P3
8S2
Industrial
(-40°C to 85°C)
ATtiny12-8PC
ATtiny12-8SC
8P3
8S2
Commercial
(0°C to 70°C)
ATtiny12-8PI
ATtiny12-8SI
8P3
8S2
Industrial
(-40°C to 85°C)
4.0 - 5.5V
1.8 - 5.5V
2.7 - 5.5V
4.0 - 5.5V
Note:
6
1
4
8
Operation Range
The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscillator
has the same nominal clock frequency for all speed grades.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
75
Packaging Information
8P3, 8-lead, 0.300" Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
8S2, 8-lead, 0.200" Wide,
Plastic Gull Wing Small Outline (EIAJ SOIC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
.020 (.508)
.012 (.305)
.400 (10.16)
.355 (9.02)
PIN
1
.280 (7.11)
.240 (6.10)
.300 (7.62) REF
.210 (5.33) MAX
.037 (.940)
.027 (.690)
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.015 (.380) MIN
.150 (3.81)
.115 (2.92)
.070 (1.78)
.045 (1.14)
.022 (.559)
.014 (.356)
.013 (.330)
.004 (.102)
.325 (8.26)
.300 (7.62)
0
REF
15
.430 (10.9) MAX
76
.330 (8.38)
.300 (7.62)
.100 (2.54) BSC
SEATING
PLANE
.012 (.305)
.008 (.203)
.213 (5.41)
.205 (5.21)
PIN 1
ATtiny10/11/12
0
REF
8
.035 (.889)
.020 (.508)
.010 (.254)
.007 (.178)
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Atmel Operations
Corporate Headquarters
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http://www.atmel.com
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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®
and/or
™
are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
1006B–10/99/xM