EM484M1644VTA

eorex
EM484M1644VTA
Revision History
Revision 0.1 (Jun. 2009)
-First release
Revision 0.2 (July 2013)
-Update DC/AC parameter
-DC parameters update points.
1. ICC2P 1.5ma to 10ma.
2. ICC2PS 1ma to 5ma.
3. ICC2N 20ma to 30ma.
4. ICC2NS 10ma to 25ma.
5. ICC3P 7ma to 30ma.
6. ICC3NS 5ma to 25ma.
7. ICC5 110ma to 115ma.
8. ICC6 0.5ma to 5ma.
-AC parameters update points.
1. tAC CL2 Max 6ns to 5.4ns.
2. tCH -7 Min 3ns to 2.5ns.
3. tCL -7 Min 3ns to 2.5ns.
4. tOH -7 CL3 Min 3ns to 2.5ns.
5. Add tOH -6/-7 CL2 2.5ns.
6. tT -6/-7 Min 0.5ns to 0.3ns , Max 1ns to 1.5ns.
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eorex
EM484M1644VTA
64Mb (1M4Bank16) Synchronous DRAM
Features
Description
• Fully Synchronous to Positive Clock Edge
• Single 3.3V 0.3V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.625us)
The EM484M1644VTA is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
1Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 64Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TSOPII 54P 400mil.
Ordering Information
Part No
Organization
Max. Freq
Package
Grade
Pb
EM484M1644VTA-7F
4M X 16
143MHz @CL3
54pin TSOP(ll)
Commercial
Free
EM484M1644VTA-6F
4M X 16
166MHz @CL3
54pin TSOP(ll)
Commercial
Free
EM484M1644VTA-7FE
4M X 16
143MHz @CL3
54pin TSOP(ll)
Extended
Free
EM484M1644VTA-6FE
4M X 16
166MHz @CL3
54pin TSOP(ll)
Extended
Free
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EM484M1644VTA
Pin Assignment
54pin TSOP-II / (400mil  875mil) / (0.8mm Pin pitch)
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EM484M1644VTA
Pin Description (Simplified)
Pin
Name
38
CLK
19
/CS
37
CKE
23~26, 22, 29~35
A0~A11
20, 21
BA0, BA1
18
/RAS
17
/CAS
16
/WE
39/15
UDQM/LDQM
2, 4, 5, 7, 8, 10,
11, 13, 42, 44, 45,
47, 48, 50, 51, 53
1,14,27/
28,41,54
3, 9, 43, 49/
6, 12, 46, 52
36,40
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
Selects chip when active
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
Row address (A0 to A11) is determined by A0 to A11 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA7) is determined by A0 to A7 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
(Power Supply/Ground)
VDD and VSS are power supply pins for internal circuits.
(Power Supply/Ground)
VDDQ and VSSQ are power supply pins for the output buffers.
(No Connection)
This pin is recommended to be left No Connection on the
device.
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EM484M1644VTA
Absolute Maximum Rating
Symbol
Item
Rating
Units
VIN, VOUT
Input, Output Voltage
-1.0 ~ +4.6
V
VDD, VDDQ
Power Supply Voltage
-1.0 ~ +4.6
Commercial
0 ~ +70
Extended
-25 ~ +85
-55 ~ +150
V
TOP
Operating Temperature Range
TSTG
Storage Temperature Range
PD
Power Dissipation
°C
°C
1.0
W
Short Circuit Current
50
mA
IOS
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could
cause permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Capacitance (VCC=3.3V, f=1MHz, TA=25°C)
Symbol
Parameter
Min.
CCLK
Clock Capacitance
Input Capacitance for CLK, CKE, Address,
/CS, /RAS, /CAS, /WE, DQML, DQMU
Input/Output Capacitance
CI
CO
Typ.
Max.
Units
2.0
3.5
pF
2.0
3.8
pF
3.5
5.5
pF
Recommended DC Operating Conditions (TA=-0°C ~+70°C)
Symbol
Parameter
Min.
Typ.
Max.
Units
VDD
Power Supply Voltage
3.0
3.3
3.6
V
VDDQ
Power Supply Voltage (for I/O Buffer)
3.0
3.3
3.6
V
Input Logic High Voltage
2.0
Vdd
0
VDD+0.3
V
0.8
V
VIH
Input Logic Low Voltage
VIL
Note: * All voltages referred to VSS.
* VIH (max.) = 4.6V for pulse width 3ns
* VIL (min.) = -1.5V for pulse width 3ns
-0.3
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Recommended DC Operating Conditions
(VDD=3.3V0.3V, TA=0°C ~ 70°C/TA=-25°C ~ +85°C for extended grade)
Symbol
Parameter
(Note 1)
ICC1
Operating Current
ICC2P
Precharge Standby Current in
Power Down Mode
ICC2PS
ICC2N
Precharge Standby Current in
Non-power Down Mode
ICC2NS
ICC3P
ICC3PS
ICC3N
Active Standby Current in
Power Down Mode
Active Standby Current in
Non-power Down Mode
ICC3NS
ICC4
Operating Current (Burst
Mode)
(Note 2)
(Note 3)
ICC5
Refresh Current
ICC6
Self Refresh Current
Test Conditions
Max.
Units
80
mA
10
mA
5
mA
30
mA
25
mA
30
mA
25
mA
45
mA
30
mA
tCCD≥2CLKs, IOL=0mA
100
mA
tRC≥tRC(min.)
115
mA
5
mA
Burst length=1,
tRC≥tRC(min.), IOL=0mA,
One bank active
CKE≤VIL(max.), tCK=15ns
CKE≤VIL(max.), tCK= 
CKE≥VIL(min.), tCK=15ns,
/CS≥VIH(min.)
Input signals are changed
one time during 30ns
CKE≥VIL(min.), tCK=  ,
Input signals are stable
CKE≤VIL(max.), tCK=10ns
CKE≤VIL(max.), tCK= 
CKE≥VIL(min.), tCK=15ns,
/CS≥VIH(min.)
Input signals are changed
one time during 30ns
CKE≥VIL(min.), tCK=  ,
Input signals are stable
CKE≤0.2V
*All voltages referenced to VSS.
Note 1: ICC1 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 2: ICC4 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 3: Input signals are changed only one time during tCK (min.)
Recommended DC Operating Conditions (Continued)
Symbol
Parameter
Test Conditions
IIL
Input Leakage Current
IOL
Output Leakage Current
0≤VI≤VDDQ, VDDQ=VDD
All other pins not under test=0V
0≤VO≤VDDQ, DOUT is disabled
VOH
High Level Output Voltage
IO=-4mA
VOL
Low Level Output Voltage
IO=+4mA
Min.
Typ.
Max.
Units
-10
+10
uA
-10
+10
uA
2.4
V
0.4
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EM484M1644VTA
Block Diagram
Auto/Self
Refresh Counter
A0
A1
DQM
A2
A3
A6
A7
A8
A9
AddressRegister
A5
RowDecoder
RowAdd.Buffer
A4
Memory
Array
Write DQM
Control
Data In
DOi
S/A & I/O Gating
A10
A11
Data Out
Col. Decoder
BA0
BA1
Col. Add. Buffer
Read DQM
Control
Mode Register Set
Col. Add. Counter
Burst Counter
Timing Register
CLK
CKE
/CS
/RAS
/CAS
Apr. 2014
/WE
DQM
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EM484M1644VTA
AC Operating Test Conditions
(VDD=3.3V0.3V, TA=0°C ~70°C/TA=-25°C ~ +85°C for extended grade)
Item
Conditions
Output Reference Level
1.4V/1.4V
Output Load
See diagram as below
Input Signal Level
2.4V/0.4V
tr/tf=1/1 ns
Transition Time of Input Signals
Input Reference Level
1.4V
AC Operating Test Characteristics
(VDD=3.3V0.3V, TA=0°C ~70°C/TA=-25°C ~ +85°C for extended grade)
Symbol
tCK
tAC
Clock Cycle Time
Access Time form CLK
(Note 5.1)
CLK High Level Width
tCL
CLK Low Level Width
Data-out Hold Time
tHZ
tLZ
CL=2
10
CL=3
Max.
Min.
7
Max.
Units
ns
10
5.4
5.4
5.4
5.4
ns
2.5
2.5
ns
(Note 5.2)
2.5
2.5
ns
CL=3
2.5
2.5
ns
CL=2
2.5
2.5
CL=3
3
Data-out High Impedance
6
3
7
(Note 5.3)
CL=2
Data-out Low Impedance Time
ns
0
0
ns
(Note 5.2)
1
1
ns
(Note 5.2)
1.5
1.5
ns
(Note 5.1)
tIH
Input Hold Time
tIS
Input Setup Time
Transition time of CLK ,rise & fall
tT
-7
(Note 5.2)
(Note 5.1)
Time
CL=3
Min.
6
CL=2
tCH
tOH
-6
Parameter
0.3
1.5
0.3
1.5
ns
* All voltages referenced to VSS.
Note 5.1: If clock rising time is longer than 1ns, (tT /2-0.5)ns should be added to the parameter.
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Note 5.2: AC characteristics assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., following compensation should be added to the parameter.
For example:
tIS : tr/2 (CLK rising edge )+ tT/2(tf for /cas/ras/we..start edge; tr or tf for address/data pin)-1ns
tIH : tr/2 (CLK rising edge )+ tT/2(tr for /cas/ras/we..end edge; tr or tf for address/data pin)-1ns
Note 5.3: tHZ defines the time at which the output achieve the open circuit condition and is not referenced
to output voltage levels.
AC Operating Test Characteristics (Continued)
(VDD=3.3V0.3V, TA=0°C ~70°C/TA=-25°C ~ +85°C for extended grade)
Symbol
tRC
tRAS
tRP
tRCD
tRRD
tCCD
-6
Parameter
Min.
ACTIVE to ACTIVE Command
60
(Note 6)
Period
ACTIVE to PRECHARGE
Min.
Max.
63
(Note 6)
18
20
ns
18
20
ns
12
14
ns
1
1
CLK
2
2
CLK
1
1
CLK
3
3
(Note 6)
Time
ACTIVE(one) to ACTIVE(another)
(Note 6)
Command
READ/WRITE Command to
READ/WRITE Command
Date-in to PRECHARGE
Command
tBDL
Date-in to BURST Stop Command
Data-out to High
Impedance from
PRECHARGE Command
Refresh Time (4,096 cycle)
CL=3
CL=2
45
ns
42
Command Period
ACTIVE to READ/WRITE Delay
100k
Units
(Note 6)
Command Period
PRECHARGE to ACTIVE
tDPL
tROH
-7
Max.
2
100k
ns
CLK
60
64
70
64
ms
tREF
* All voltages referenced to VSS.
Note 6: These parameters account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole
number)
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EM484M1644VTA
Recommended Power On and Initialization
The following power on and initialization sequence guarantees the device is preconditioned to each user’s
specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on
voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same
time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the
precharge command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be
held high during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR)
are also required, and these may be done before or after programming the Mode Register.
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EM484M1644VTA
Simplified State Diagram
Self
Refresh
LF
SE
Mode
Register
Set
MRS
Ex
LF
SE
REF
IDLE
CBR
Refresh
it
CK
CK
ACT
E
Power
Down
E
CKE
Row
Active
adBS
Write
wit
WRITE
Suspend
CKE
WRITE
Wr hRead
Read
Re
ad R
wit
Write
CKE
Active
Power
Down
CKE
e
CKE
READ
T
CKE
READ
Suspend
h
WRITEA
Suspend
CKE
CKE
WRITEA
CKE
PR
READA
PR
CKE
READA
Suspend
E
E
POWER
ON
Precharge ite
Precharge
Manual Input
Automatic Sequence
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EM484M1644VTA
Address Input for Mode Register Set
BA1
BA0
A11
A10
A9
A8
A7
A6
Operation Mode
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
Burst Length
Sequential
Interleave
A2
A1
A0
1
1
0
0
0
2
2
0
0
1
4
4
0
1
0
8
8
0
1
1
Reserved
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Full Page
Reserved
1
1
1
Burst Type
A3
Interleave
1
Sequential
0
CAS Latency
A6
A5
A4
Reserved
0
0
0
Reserved
0
0
1
2
0
1
0
3
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
BA1
BA0
A11
A10
A9
A8
A7
Operation Mode
0
0
0
0
0
0
0
Normal
0
0
0
0
1
0
0
Burst Read with Single-bit Write
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EM484M1644VTA
Burst Type (A3)
Burst Length
A2
A1
A0
X
X
0
01
01
X
X
0
10
10
X
0
0
0123
0123
X
0
1
1230
1032
X
1
0
2301
2301
X
1
1
3012
3210
0
0
0
01234567
01234567
0
0
1
12345670
10325476
0
1
0
23456701
23016745
0
1
1
34567012
32107654
1
0
0
45670123
45670123
1
0
1
56701234
54761032
1
1
0
67012345
67452301
1
1
1
70123456
76543210
n
n
n
Cn Cn+1 Cn+2……
2
4
8
Full Page*
Sequential Addressing
Interleave Addressing
-
* Page length is a function of I/O organization and column addressing 16 (CA0 ~ CA7):
1. Command Truth Table
Command
Symbol
CKE
n-1 n
H X
/CS
/RAS
/CAS
/WE
BA0,
BA1
A10
A11,
A9~A10
H
X
X
X
X
X
X
H
X
X
X
Ignore Command
DESL
No Operation
NOP
H
X
L
H
H
Burst Stop
BSTH
H
X
L
H
H
L
X
X
X
Read
READ
H
X
L
H
L
H
V
L
V
READA
H
X
L
H
L
H
V
H
V
Write
WRIT
H
X
L
H
L
L
V
L
V
Write with Auto Pre-charge
WRITA
H
X
L
L
H
H
V
H
V
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Pre-charge Select Bank
PRE
H
X
L
L
H
L
V
L
X
Pre-charge All Banks
PALL
H
X
L
L
H
L
X
H
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
V
Read with Auto Pre-charge
Full page = 256bits
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
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EM484M1644VTA
2. DQM Truth Table
Command
CKE
Symbol
n-1
n
/CS
Data Write/Output Enable
ENB
H
X
H
Data Mask/Output Disable
MASK
H
X
L
Upper Byte Write Enable/Output Enable
BSTH
H
X
L
Read
READ
H
X
L
READA
H
X
L
WRIT
H
X
L
WRITA
H
X
L
Bank Activate
ACT
H
X
L
Pre-charge Select Bank
PRE
H
X
L
Pre-charge All Banks
PALL
H
X
Read with Auto Pre-charge
Write
Write with Auto Pre-charge
L
Mode Register Set
MRS
H
X
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
L
3. CKE Truth Table
Item
Command
Activating
Any
Clock
Suspend
Idle
Clock Suspend Mode Entry
Clock Suspend Mode
CBR Refresh Command
Idle
Self Refresh Entry
Self Refresh
Self Refresh Exit
Idle
Symbol
Clock Suspend Mode Exit
CKE
n-1 n
H
L
L
L
/CS
/RAS
/CAS
/WE
Addr.
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
REF
H
H
L
L
L
H
X
SELF
H
L
L
L
L
L
H
X
H
L
H
H
H
X
L
H
H
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
Power Down Entry
Power Down
Power Down Exit
L
H
X
Remark H = High level, L = Low level, X = High or Low level (Don't care)
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EM484M1644VTA
4. Operative Command Table (Note 7)
Current
State
Idle
Row
Active
Read
/CS
/R
/C
/W
Addr.
Command
H
X
X
X
X
DESL
Nop or power down
L
H
H
X
X
NOP or BST
Nop or power down
L
H
L
H
BA/CA/A10
READ/READA
ILLEGAL
L
L
L
H
L
L
L
H
H
L
H
L
BA/CA/A10
BA/RA
BA, A10
WRIT/WRITA
ACT
PRE/PALL
L
L
L
H
X
REF/SELF
ILLEGAL
Row activating
Nop
Refresh or self refresh
L
H
L
L
L
X
H
H
L
X
H
L
L
X
X
H
Op-Code
X
X
BA/CA/A10
MRS
DESL
NOP or BST
READ/READA
Mode register accessing
Nop
Nop
L
H
L
L
BA/CA/A10
WRIT/WRITA
Begin write: Determine AP
L
L
H
H
BA/RA
ACT
L
L
H
L
BA, A10
PRE/PALL
Pre-charge
L
L
H
L
L
L
L
X
H
H
L
L
X
H
H
H
L
X
H
L
X
Op-Code
X
X
X
REF/SELF
MRS
DESL
NOP
BST
L
H
L
H
BA/CA/A10
READ/READA
ILLEGAL
ILLEGAL
Continue burst to end → Row active
Continue burst to end → Row active
Burst stop → Row active
Terminate burst, new read:
L
L
L
L
BA/CA/A10
WRIT/WRITA
Action
L
H
H
BA/RA
ACT
L
L
H
L
BA, A10
PRE/PALL
L
L
L
L
L
L
H
L
X
Op-Code
REF/SELF
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA/CA/A10
READ/READA
Write
L
L
L
L
BA/CA/A10
WRIT/WRITA
(Note 9)
(Note 10)
Begin read: Determine AP
ILLEGAL
L
H
H
BA/RA
ACT
L
L
H
L
BA, A10
PRE/PALL
(Note 11)
(Note 11)
(Note 9)
(Note 12)
(Note 10)
(Note 13)
Determine AP
Terminate burst, start write:
(Note 13, 14)
(Note 9)
ILLEGAL
Terminate burst, pre-charging
(Note 10)
ILLEGAL
ILLEGAL
Continue burst to end → Write
recovering
Continue burst to end → Write
recovering
Burst stop → Row active
Terminate burst, start read:
(Note 13, 14)
Determine AP 7, 8
Terminate burst, new write:
Determine AP 7
L
(Note 8)
(Note 9)
Determine AP
L
(Note 8)
(Note 13)
(Note 9)
ILLEGAL
Terminate burst, pre-charging
(Note 15)
ILLEGAL
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care)
L
L
L
L
L
L
H
L
X
Op-Code
REF/SELF
MRS
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4. Operative Command Table (Continued) (Note 7)
Current
State
Read with
AP
Write with
AP
Pre-charging
Row
Activating
/CS
/R
/C
/W
Addr.
Command
Action
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
L
H
H
H
L
L
H
X
BA/CA/A10
BST
READ/READA
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA/RA
ACT
ILLEGAL
L
L
L
L
L
L
H
L
L
L
H
L
BA, A10
X
Op-Code
PRE/PALL
REF/SELF
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
L
H
H
H
L
L
H
X
BA/CA/A10
BST
READ/READA
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA/RA
ACT
ILLEGAL
L
L
L
H
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
H
L
X
H
L
H
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter idle after tRP
Nop → Enter idle after tRP
ILLEGAL
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA/RA
ACT
L
L
L
H
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
H
L
X
H
L
H
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA/RA
ACT
ILLEGAL
L
L
L
L
L
L
H
L
L
L
H
L
BA, A10
X
Op-Code
PRE/PALL
REF/SELF
MRS
Continue burst to end →
Pre-charging
Continue burst to end →
Pre-charging
ILLEGAL
ILLEGAL
(Note 9)
(Note 9)
(Note 9)
(Note 9)
ILLEGAL
ILLEGAL
ILLEGAL
Burst to end → Write recovering
with auto pre-charge
Continue burst to end → Write
recovering with auto pre-charge
ILLEGAL
ILLEGAL
(Note 9)
(Note 9)
(Note 9)
(Note 9)
ILLEGAL
(Note 9)
(Note 9)
(Note 9)
ILLEGAL
Nop → Enter idle after tRP
ILLEGAL
ILLEGAL
Nop → Enter idle after tRCD
Nop → Enter idle after tRCD
ILLEGAL
ILLEGAL
(Note 9)
(Note 9)
(Note 9, 16)
(Note 9)
ILLEGAL
ILLEGAL
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
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4. Operative Command Table (Continued) (Note 7)
Current
State
Write
Recovering
Write
Recovering
with AP
Refreshing
Mode
Register
Accessing
/CS
/R
/C
/W
Addr.
Command
Action
H
L
L
L
L
X
H
H
H
H
X
H
H
L
L
X
H
L
H
L
X
X
X
BA/CA/A10
BA/CA/A10
DESL
NOP
BST
READ/READA
WRIT/WRITA
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Start read, Determine AP
L
L
H
H
BA/RA
ACT
L
L
L
H
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
H
L
X
H
L
H
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter pre-charge after tDPL
Nop → Enter pre-charge after tDPL
Nop → Enter pre-charge after tDPL
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
L
L
X
H
H
H
H
H
L
L
X
H
L
H
L
X
H
H
L
H
L
H
L
X
X
X
X
X
X
H
L
X
BA/RA
BA, A10
X
Op-Code
X
X
X
X
X
X
X
X
X
L
L
X
X
X
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
NOP
BST
READ/WRIT
ACT/PRE/PALL/
REF/SELF/MRS
New write, Determine AP
ILLEGAL
(Note 14)
(Note 9)
(Note 9)
ILLEGAL
(Note 9, 14)
(Note 9)
(Note 9)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter idle after tRC
Nop → Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Nop
ILLEGAL
ILLEGAL
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle.
Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.
All input buffers except CKE will be disabled.
Note 9: Illegal to bank in specified states;
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of
that bank.
Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
Note 11: Illegal if tRCD is not satisfied.
Note 12: Illegal if tRAS is not satisfied.
Note 13: Must satisfy burst interrupt condition.
Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Note 15: Must mask preceding data which don't satisfy tDPL.
Note 16: Illegal if tRRD is not satisfied.
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5. Command Truth Table for CKE
Current State
Self Refresh
Self Refresh
Recovery
Power Down
Both Banks
Idle
CKE
n-1
n
Any State Other
than Listed above
/R
/C
/W
Addr.
Action
INVALID, CLK(n-1) would exit self
refresh
Self refresh recovery
Self refresh recovery
ILLEGAL
ILLEGAL
Maintain self refresh
Idle after tRC
Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
INVALID, CLK(n-1) would exit
power down
Exit power down → Idle
Maintain power down mode
Refer to operations in Operative
Command Table
H
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
L
L
H
L
L
L
X
H
L
L
L
H
L
L
L
X
H
H
L
X
X
H
H
L
X
H
H
L
X
H
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
L
L
X
X
H
L
L
L
L
H
L
L
L
X
X
X
H
L
L
L
X
H
L
L
X
X
X
X
H
L
L
X
X
H
L
X
X
X
X
X
H
L
X
X
X
H
X
X
L
L
L
L
Op-Code
H
Row Active
/CS
L
X
Op-Code
Refresh
Refer to operations in Operative
Command Table
X
L
X
X
X
X
X
X
H
X
X
X
X
X
X
L
X
X
X
X
X
X
H
H
X
X
X
X
H
L
X
X
X
X
X
L
L
H
L
X
X
X
X
X
X
X
X
X
X
(Note 17)
Self refresh
Refer to operations in Operative
Command Table
(Note 17)
Power down
Refer to operations in Operative
Command Table
(Note 17)
Power down
Refer to operations in Operative
Command Table
Begin clock suspend next cycle
(Note 18)
Exit clock suspend next cycle
Maintain clock suspend
Remark: H = High level, L = Low level, X = High or Low level (Don't care)
Notes 17: Self refresh can be entered only from the both banks idle state.
Power down can be entered only from both banks idle or row active state.
Notes 18: Must be legal command as defined in Operative Command Table
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Package Description
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