eorex EM488M3244VBB 256Mb (2M×4Bank×32) Synchronous DRAM Features Description • Fully Synchronous to Positive Clock Edge • Single 3.3V ±0.3V Power Supply • LVTTL Compatible with Multiplexed Address • Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) • Burst Read with Single-bit Write Operation • All Inputs are Sampled at the Rising Edge of the System Clock • Auto Refresh and Self Refresh • 4,096 Refresh Cycles / 64ms (15.625us) The EM488M3244VBB is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL. Available packages: TFBGA-90B(13mmx8mm). Ordering Information Part No Organization Max. Freq Package Grade Pb EM488M3244VBB-75F 8M X 32 133MHz @CL3 TFBGA-90B Commercial Free EM488M3244VBB-7F 8M X 32 143MHz @CL3 TFBGA-90B Commercial Free EM488M3244VBB-75FE 8M X 32 133MHz @CL3 TFBGA-90B Extend temp. Free EM488M3244VBB-7FE 8M X 32 143MHz @CL3 TFBGA-90B Extend temp. Free * EOREX reserves the right to change products or specification without notice. Jul. 2006 www.eorex.com 1/18 eorex EM488M3244VBB Pin Assignment 1 2 3 7 8 9 DQ26 DQ24 VSS A VDD DQ23 DQ21 DQ28 VDDQ VSSQ B VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 C DQ22 DQ20 VDDQ VSSQ DQ29 DQ30 D DQ17 DQ18 VDDQ VDDQ DQ31 NC E NC DQ16 VSSQ VSS DQM3 A3 F A2 DQM2 VDD A4 A5 A6 G A10 A0 A1 A7 A8 NC H NC BA1 A11 CLK CKE A9 J BA0 /CS /RAS DQM1 NC NC K /CAS /WE DQM0 VDDQ DQ8 VSS L VDD DQ7 VSSQ VSSQ DQ10 DQ9 M DQ6 DQ5 VDDQ VSSQ DQ12 DQ14 N DQ1 DQ3 VDDQ DQ11 VDDQ VSSQ P VDDQ VSSQ DQ4 DQ13 DQ15 VSS R VDD DQ0 DQ2 90ball TFBGA / (13mm x 8mm) Jul. 2006 www.eorex.com 2/18 eorex EM488M3244VBB Pin Description (Simplified) Pin Name J1 CLK J8 /CS J2 CKE G8,G9,F7,F3,G1, G2,G3,H1,H2,J3, G7,H9 A0~A11 J7,H8 BA0,BA1 J9 /RAS K7 /CAS K8 /WE K9,K1,F8,F2 DQM0~DQM3 R8,N7,R9,N8,P9, M8,M7,L8,L2,M3, M2,P1,N2,R1,N3, R2,E8,D7,D8,B9, C8,A9,C7,A8,A2, C3,A1,C2,B1,D2, D3,E2 DQ0~DQ31 A7,F9,L7,R7 VDD A3,F1,L3,R3 VSS B2,B7,C9,D9,E1, L1,M9,N9,P2,P7 VDDQ B8,B3,C1,D1,E9, L9,M1,N1,P3,P8 VSSQ Function (System Clock) Master clock input (Active on the positive rising edge) (Chip Select) Selects chip when active (Clock Enable) Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. (Address) Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA (CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10= High at the pre-charge command cycle, all banks are pre-charged. But when A10= Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output Mask) DQM controls I/O buffers. (Data Input/Output) DQ pins have the same function as I/O pins on a conventional DRAM. (Power Supply) power supply pins for internal circuits. (Ground) ground pins for internal circuits. (Power Supply) power supply pins for the output buffers. (Ground) ground pins for the output buffers. Jul. 2006 www.eorex.com 3/18 eorex E3,E7,H3,H7,K2, K3 EM488M3244VBB NC (No Connection) This pin is recommended to be left No Connection on the device. Jul. 2006 www.eorex.com 4/18 eorex EM488M3244VBB Absolute Maximum Rating Symbol Item Rating Units VIN, VOUT Input, Output Voltage -0.3 ~ +4.6 V VDD, VDDQ Power Supply Voltage -0.3 ~ +4.6 Commercial 0 ~ +70 Extended -25 ~ +85 -55 ~ +150 V °C TOP TSTG Operating Temperature Range Storage Temperature Range °C PD Power Dissipation 1 W IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (VCC=3.3V, f=1MHz, TA=25°C) Symbol Parameter Min. CCLK Clock Capacitance Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output Capacitance CI CO Typ. Max. Units 2.5 4.0 pF 2.5 3.0 pF 4.0 6.5 pF Recommended DC Operating Conditions (TA=0°C ~70°C) Symbol Parameter Min. Typ. Max. Units VDD Power Supply Voltage 3.0 3.3 3.6 V VDDQ Power Supply Voltage (for I/O Buffer) 3.0 3.3 3.6 V VIH Input Logic High Voltage 2.0 VDD+0.3 V VIL Input Logic Low Voltage -0.3 0.8 V Note: * All voltages referred to VSS. * VIH (max.) = 5.6V for pulse width 3ns * VIL (min.) = -2.0V for pulse width 3ns Jul. 2006 www.eorex.com 5/18 eorex EM488M3244VBB Recommended DC Operating Conditions (VDD=3.3V±0.3V, TA=0°C ~70°C , -25°C ~ +85°C) Symbol Parameter (Note 1) ICC1 Operating Current ICC2P Precharge Standby Current in Power Down Mode ICC2PS ICC2N Precharge Standby Current in Non-power Down Mode ICC2NS ICC3P ICC3PS ICC3N Active Standby Current in Power Down Mode Active Standby Current in Non-power Down Mode ICC3NS ICC4 Operating Current (Burst Mode) (Note 2) (Note 3) ICC5 Refresh Current ICC6 Self Refresh Current Test Conditions Burst length=1, tRC≥tRC(min.), IOL=0mA, One bank active CKE≤VIL(max.), tCK=15ns CKE≤VIL(max.), tCK= ∞ CKE≥VIL(min.), tCK=15ns, /CS≥VIH(min.) Input signals are changed one time during 30ns CKE≥VIL(min.), tCK= ∞ , Input signals are stable CKE≤VIL(max.), tCK=15ns Max. Units 125 mA 3 mA 3 mA 30 mA 20 mA 5 mA 5 mA 45 mA 35 mA tCCD≥2CLKs, IOL=0mA 150 mA tRC≥tRC(min.) 270 mA (Note 4) mA CKE≤VIL(max.), tCK= ∞ CKE≥VIL(min.), tCK=15ns, /CS≥VIH(min.) Input signals are changed one time during 30ns CKE≥VIL(min.), tCK= ∞ , Input signals are stable CKE≤0.2V 3 *All voltages referenced to VSS. Note 1: ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Input signals are changed only one time during tCK (min.) Note 4: Standard power version. Recommended DC Operating Conditions (Continued) Symbol Parameter Test Conditions IIL Input Leakage Current IOL Output Leakage Current 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V 0≤VO≤VDDQ, DOUT is disabled VOH High Level Output Voltage IO=-2mA VOL Low Level Output Voltage IO=+2mA Min. Typ. Max. Units -0.5 +0.5 uA -0.5 +0.5 uA 2.4 V 0.4 Jul. 2006 V www.eorex.com 6/18 eorex EM488M3244VBB Block Diagram Auto/Self Refresh Counter A0 A1 DQM A2 A5 A6 A7 A8 A9 Address Register A4 Row Decoder Row Add. Buffer A3 Memory Array Write DQM Control Data In DOi S/A & I/O Gating A10 A11 Data Out Col. Decoder BA0 BA1 Col. Add. Buffer Read DQM Control Mode Register Set Col. Add. Counter Burst Counter Timing Register CLK CKE /CS /RAS /CAS Jul. 2006 /WE DQM www.eorex.com 7/18 eorex EM488M3244VBB AC Operating Test Conditions (VDD=3.3V±0.3V, TA=0°C ~70°C) Item Conditions Output Reference Level 1.4V/1.4V Output Load See diagram as below Input Signal Level 2.4V/0.4V Transition Time of Input Signals 2ns Input Reference Level 1.4V AC Operating Test Characteristics (VDD=3.3V±0.3V, TA=0°C ~70°C, -25°C ~ +85°C) Symbol tCK Clock Cycle Time tAC Access Time form CLK tCH CLK High Level Width tCL CLK Low Level Width tOH tHZ -7 Parameter Data-out Hold Time Data-out High Impedance Time (Note 5) CL=3 Min. 7 CL=2 7.5 Max. -7.5 Min. Max. 7.5 10 CL=3 5.4 5.4 CL=2 5.4 6 ns 2.5 2.5 ns 3 3 CL=3 3 7 3 CL=2 tIH tIS ns 2.5 ns CL=2 Data-out Low Impedance Time ns 2.5 CL=3 tLZ Units 7 ns 0 0 ns Input Hold Time 0.8 1 ns Input Setup Time 1.5 1.5 ns * All voltages referenced to VSS. Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. Jul. 2006 www.eorex.com 8/18 eorex EM488M3244VBB AC Operating Test Characteristics (Continued) (VDD=3.3V±0.3V, TA=0°C ~70°C, -25°C ~ +85°C) Symbol Parameter -7 Min. Max. Min. -75 Max. Units tRC ACTIVE to ACTIVE Command (Note 6) Period 62 tRAS ACTIVE to PRECHARGE (Note 6) Command Period 42 tRP PRECHARGE to ACTIVE (Note 6) Command Period 20 20 ns tRCD ACTIVE to READ/WRITE Delay (Note 6) Time 20 20 ns tRRD ACTIVE(one) to ACTIVE(another) (Note 6) Command 14 15 ns tCCD READ/WRITE Command to READ/WRITE Command 1 1 CLK tDPL Date-in to PRECHARGE Command 2 2 CLK Date-in to BURST Stop Command Data-out to High CL=3 Impedance from CL=2 PRECHARGE Command 1 1 CLK 3 3 2 2 tBDL tROH tREF Refresh Time (4,096 cycle) 67 100k 64 45 ns 100k ns CLK 64 ms * All voltages referenced to VSS. Note 6: These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole number) Recommended Power On and Initialization The following power on and initialization sequence guarantees the device is preconditioned to each user’s specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same time) After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required, and these may be done before or after programming the Mode Register. Jul. 2006 www.eorex.com 9/18 eorex EM488M3244VBB Simplified State Diagram Ex it SE LF SE LF Self Refresh Mode Register Set MRS REF IDLE CBR Refresh E CK E CK Power Down CKE Row Active WRITE Suspend WRITEA Suspend CKE CKE T BS ad e R Write Read CKE Read WRITE CKE Write READ CKE CKE CKE WRITEA READA CKE CKE POWER ON Active Power Down Precharge READ Suspend READA Suspend Precharge Manual Input Automatic Sequence Jul. 2006 www.eorex.com 10/18 eorex EM488M3244VBB Address Input for Mode Register Set BA1 BA0 A11 A10 A9 A8 A7 A6 Operation Mode A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length Burst Length Sequential Interleave A2 A1 A0 1 1 0 0 0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 Reserved Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Full Page Reserved 1 1 1 Burst Type A3 Interleave 1 Sequential 0 CAS Latency A6 A5 A4 Reserved 0 0 0 Reserved 0 0 1 2 0 1 0 3 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 BA1 BA0 A11 A10 A9 A8 A7 0 0 0 0 0 0 0 Normal 0 0 0 0 1 0 0 Burst Read with Single-bit Write Jul. 2006 Operation Mode www.eorex.com 11/18 eorex EM488M3244VBB Burst Type (A3) Burst Length 2 4 8 Full Page* A2 A1 A0 Sequential Addressing Interleave Addressing X X 0 01 01 X X 0 10 10 X 0 0 0123 0123 X 0 1 1230 1032 X 1 0 2301 2301 X 1 1 3012 3210 0 0 0 01234567 01234567 0 0 1 12345670 10325476 0 1 0 23456701 23016745 0 1 1 34567012 32107654 1 0 0 45670123 45670123 1 0 1 56701234 54761032 1 1 0 67012345 67452301 1 1 1 70123456 76543210 n n n Cn Cn+1 Cn+2…… - * Page length is a function of I/O organization and column addressing ×32 (CA0 ~ CA8): Full page = 512bits 1. Command Truth Table Command Symbol CKE n-1 n /CS /RAS /CAS /WE BA0, BA1 A10 A11, A9~A10 Ignore Command DESL H X H X X X X X X No Operation NOP H X L H H H X X X Burst Stop BSTH H X L H H L X X X Read READ H X L H L H V L V READA H X L H L H V H V Write WRIT H X L H L L V L V Write with Auto Pre-charge Read with Auto Pre-charge WRITA H X L L H H V H V Bank Activate ACT H X L L H H V V V Pre-charge Select Bank PRE H X L L H L V L X Pre-charge All Banks PALL H X L L H L X H X Mode Register Set MRS H X L L L L L L V H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input Jul. 2006 www.eorex.com 12/18 eorex EM488M3244VBB 2. DQM Truth Table Command CKE Symbol n-1 n /CS Data Write/Output Enable ENB H X H Data Mask/Output Disable MASK H X L Upper Byte Write Enable/Output Enable BSTH H X L Read READ H X L Read with Auto Pre-charge READA H X L Write WRIT H X L Write with Auto Pre-charge WRITA H X L Bank Activate ACT H X L Pre-charge Select Bank PRE H X L Pre-charge All Banks PALL H X L Mode Register Set MRS H X L H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 3. CKE Truth Table Item Command Activating Any Clock Suspend Idle Clock Suspend Mode Entry Clock Suspend Mode CBR Refresh Command Idle Self Refresh Entry Symbol Clock Suspend Mode Exit CKE n-1 n H L L L /CS /RAS /CAS /WE Addr. X X X X X X X X X X L H X X X X X REF H H L L L H X SELF H L L L L L H X H L H H H X L H H X X X X Self Refresh Self Refresh Exit Idle Power Down Entry H L X X X X X Power Down Power Down Exit L H X X X X X Remark H = High level, L = Low level, X = High or Low level (Don't care) Jul. 2006 www.eorex.com 13/18 eorex EM488M3244VBB 4. Operative Command Table (Note 7) Current State Idle Row Active Read /CS /R /C /W Addr. Command Action H X X X X DESL Nop or power down L H H X X NOP or BST Nop or power down L H L H BA/CA/A10 READ/READA ILLEGAL L L L H L L L H H L H L BA/CA/A10 BA/RA BA, A10 WRIT/WRITA ACT PRE/PALL L L L H X REF/SELF ILLEGAL Row activating Nop Refresh or self refresh L H L L L X H H L X H L L X X H Op-Code X X BA/CA/A10 MRS DESL NOP or BST READ/READA Mode register accessing Nop Nop (Note 11) Begin read: Determine AP L H L L BA/CA/A10 WRIT/WRITA Begin write: Determine AP (Note 9) (Note 8) (Note 8) (Note 9) (Note 9) (Note 10) (Note 11) L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Pre-charge L L H L L L L X H H L L X H H H L X H L X Op-Code X X X REF/SELF MRS DESL NOP BST L H L H BA/CA/A10 READ/READA ILLEGAL ILLEGAL Continue burst to end → Row active Continue burst to end → Row active Burst stop → Row active Terminate burst, new read: (Note 13) Determine AP L L L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA, A10 PRE/PALL L L L L L L H L X Op-Code REF/SELF MRS H X X X X DESL L H H H X NOP L H H L X BST L H L H BA/CA/A10 READ/READA L L L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Write ILLEGAL (Note 12) (Note 10) Terminate burst, start write: (Note 13, 14) Determine AP (Note 9) ILLEGAL Terminate burst, pre-charging (Note 10) ILLEGAL ILLEGAL Continue burst to end → Write recovering Continue burst to end → Write recovering Burst stop → Row active Terminate burst, start read: (Note 13, 14) Determine AP 7, 8 Terminate burst, new write: (Note 13) Determine AP 7 (Note 9) ILLEGAL Terminate burst, pre-charging (Note 15) ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care) L L L L L L H L X Op-Code REF/SELF MRS Jul. 2006 www.eorex.com 14/18 eorex EM488M3244VBB 4. Operative Command Table (Continued) (Note 7) Current State Read with AP Write with AP Pre-charging Row Activating /CS /R /C /W Addr. Command Action H X X X X DESL L H H H X NOP L L H H H L L H X BA/CA/A10 BST READ/READA Continue burst to end → Pre-charging Continue burst to end → Pre-charging ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT ILLEGAL L L L L L L H L L L H L BA, A10 X Op-Code PRE/PALL REF/SELF MRS H X X X X DESL L H H H X NOP L L H H H L L H X BA/CA/A10 BST READ/READA ILLEGAL ILLEGAL ILLEGAL Burst to end → Write recovering with auto pre-charge Continue burst to end → Write recovering with auto pre-charge ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT ILLEGAL L L L H L L L L L L X H H H H L L X H H L L H L X H L H BA, A10 X Op-Code X X X BA/CA/A10 PRE/PALL REF/SELF MRS DESL NOP BST READ/READA ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP Nop → Enter idle after tRP ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L L L H L L L L L L L X H H H H H L L X H H L H L H L X H L H BA/RA BA, A10 X Op-Code X X X BA/CA/A10 ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA ILLEGAL Nop → Enter idle after tRP ILLEGAL ILLEGAL Nop → Enter idle after tRCD Nop → Enter idle after tRCD ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT ILLEGAL L L L L L L H L L L H L BA, A10 X Op-Code PRE/PALL REF/SELF MRS (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9, 16) (Note 9) ILLEGAL ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Jul. 2006 www.eorex.com 15/18 eorex EM488M3244VBB 4. Operative Command Table (Continued) (Note 7) Current State Write Recovering Write Recovering with AP Refreshing Mode Register Accessing /CS /R /C /W Addr. Command Action H L L L L X H H H H X H H L L X H L H L X X X BA/CA/A10 BA/CA/A10 DESL NOP BST READ/READA WRIT/WRITA Nop → Enter row active after tDPL Nop → Enter row active after tDPL Nop → Enter row active after tDPL Start read, Determine AP (Note 14) New write, Determine AP L L H H BA/RA ACT L L L H L L L L L L X H H H H L L X H H L L H L X H L H BA, A10 X Op-Code X X X BA/CA/A10 PRE/PALL REF/SELF MRS DESL NOP BST READ/READA ILLEGAL ILLEGAL ILLEGAL Nop → Enter pre-charge after tDPL Nop → Enter pre-charge after tDPL Nop → Enter pre-charge after tDPL (Note 9, 14) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L L L H L L L L H L L L L L L L X H H L L X H H H H H L L X H L H L X H H L H L H L X X X X X X H L X BA/RA BA, A10 X Op-Code X X X X X X X X X L L X X X ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS ILLEGAL (Note 9) (Note 9) (Note 9) (Note 9) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRC Nop → Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Nop ILLEGAL ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle. Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode. All input buffers except CKE will be disabled. Note 9: Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode. All input buffers except CKE will be disabled. Note 11: Illegal if tRCD is not satisfied. Note 12: Illegal if tRAS is not satisfied. Note 13: Must satisfy burst interrupt condition. Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 15: Must mask preceding data which don't satisfy tDPL. Note 16: Illegal if tRRD is not satisfied. Jul. 2006 www.eorex.com 16/18 eorex EM488M3244VBB 5. Command Truth Table for CKE Current State Self Refresh Self Refresh Recovery Power Down Both Banks Idle CKE n-1 n Any State Other than Listed above /R /C /W Addr. H X X X X X X L L L L L H H H H H H H H H H H H L H H H H L L L L H L L L X H L L L H L L L X H H L X X H H L X H H L X H L X X X H L X X H L X X X X X X X X X X X X X X X X X X X X X X X X X X X H X X X X X X L L H H H H H H H H H H L H H H H H L L L L X X H L L L L H L L L X X X H L L L X H L L X X X X H L L X X H L X X X X X H L X X X H X X L L L L Op-Code H Row Active /CS L Action INVALID, CLK(n-1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) would exit power down Exit power down → Idle Maintain power down mode Refer to operations in Operative Command Table X Op-Code Refresh Refer to operations in Operative Command Table X L X X X X X X H X X X X X X L X X X X X X H H X X X X H L X X X X X (Note 17) Self refresh Refer to operations in Operative Command Table (Note 17) Power down Refer to operations in Operative Command Table (Note 17) Power down Refer to operations in Operative Command Table Begin clock suspend next cycle (Note 18) Exit clock suspend next cycle Maintain clock suspend Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 17: Self refresh can be entered only from the both banks idle state. Power down can be entered only from both banks idle or row active state. Notes 18: Must be legal command as defined in Operative Command Table L L H L X X X X X X Jul. 2006 X X X X www.eorex.com 17/18 eorex EM488M3244VBB Package Description Jul. 2006 www.eorex.com 18/18