ROHM BD9241F

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STRUCTURE
Silicon Monolithic Integrated Circuit
PRODUCT NAME
IC for DC-AC inverter control
TYPE
BD9241F
FUNCTION
1.For 36Vhigh voltage process/1ch Full Bridge control
2.Current, voltage feedback control
3.Built-in soft start circuit
4.Built-in timer-latch circuit
5.Built-in the malfunction preventing circuit (UVLO) when lower voltage
6.Shifting to current consumption save mode from STB terminal
7.External PWM,DC voltage control and current linear control
ABSOLUTE MAXIMUM RATINGS(Ta=25℃)
Parameter
Symbol
Power Supply Voltage
VCC
Operating Temperature Range
Topr
Storage Temperature Range
Tstg
allowable loss
Pd
Junction Temperature
Tjmax
Rating
36
Unit
V
-40~+85
-55~+150
687*
+150
℃
℃
mW
℃
*Reduced by 5.5mW/℃ when Ta=25℃ or over (when 70.0mm×70.0mm×1.6mm board is mounting)
OPERATING Range
Parameter
Power Supply Voltage
Terminal Voltage
(SRT,RT,VS,IS,COMP,DUT
Y)
Drive output frequency
BCT oscillation frequency
Symbol
VCC
Range
9~30
Unit
V
-
-0.3~5.5
V
fOUT
fBCT
30~90
0.10~0.50
kHz
kHz
.
REV. A
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○ELECTRICAL CHARACTERISTICS(Ta=25℃,VCC=15V)
Rating
Symbol
Parameter
MIN
Standard
MAX
Unit
Condition
((devices whole))
Circuit Current when standby
ICC1
ICC2
-
-
2.3
0
5.0
10
mA
μA
((Standby control, SEL control)
Standby Terminal voltageH
Standby Terminal voltageL
VstH
VstL
2.0
-0.3
-
-
VCC
0.8
V
V
Circuit Current at operating
SEL Terminal voltage H
SEL Terminal voltage L
((TimerーLatch))
Voltage setting time
Current setting time
((OSC Block))
Active edge setting current
MAX DUTY
Soft start time
SRT Terminal ON Resistant
((UVLOBLOCK))
Voltage starting operation
Hysteresis width
VSELH
-
2.4
VCC
V
System ON
System OFF
DUTY
Terminal
0.5V→2.0V
Burst
dimming
100%→0%
DUTY
Terminal
0.5V→2.0V
Burst
dimming
0%→100%
VSELL
-0.3
-
0.8
V
VCP
ICP
1.9
0.85
2.0
1.0
2.1
1.15
V
μA
Iact
MAXDUTY
TSS
RSRT
1.25/RT
44
50
-
1.5/RT
46.4
100
100
1.75/RT
49
150
200
A
%
msec
Ω
VuvloH
ΔVuvloH
6
0.15
7
0.3
8
0.6
V
V
VIS
VVS
IIS1
IIS2
IVS
VISC
1.225
1.210
-
40
-
0.45
1.250
1.250
-
50
-
0.50
1.275
1.290
0.9
60
1.0
0.55
V
V
μA
μA
μA
V
VOUTPH
VOUTPL
VOUTNH
VOUTNL
RsinkP1,2
R source P1,2
RsinkN1,2
RsourceN1,2
FOUT
VCC-0.3
VCC-10.3
8.3
-
-
-
-
-
48.5
VCC
VCC-9.3
9.3
0
3
6
4
6
50
-
VCC-8.3
10.3
0.3
10
12
10
12
51.5
V
V
V
V
Ω
Ω
Ω
Ω
kHz
Isink=10mA
Isource=10mA
Isink=10mA
Isource=10mA
RT=100kΩ
VburH
VburL
FBOSC
1.9
0.4
337
2.0
0.5
350
2.1
0.6
363
V
V
Hz
BCT=4700pF
VCOMPH
VCOMP
1.9
0.1
2.00
0.2
2.1
0.4
V
V
RT=100kΩ
((Feedback system))
IS Threshold voltage
VS Threshold voltage
IS Source current1
IS Source current 2
VS Source current
ISCOMP Detecting voltage
((Output block)
)
P1,P2 Output voltage H
P1,P2 Output voltageL
N1,N2 Output voltageH
N1,N2 Output voltageL
P1,P2 Output sink resistance
P1,P2 Output source resistance
N1,N2 Output sink resistance
N1,N2 Output source resistance
Drive output frequency
((Burst mode setting block)
)
Triangular wave upper voltage
Triangular wave lower voltage
Triangular wave frequency
((COMP Block))
Over-voltage detecting voltage
Hysteresis width
(It is not the radiation-proof design for this product.)
REV. A
DUTY=2.0V
DUTY=0V、IS=0.5V
:
:
:
:
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○Dimensional outline drawing
Item No
(The max dimension with burr:11.55)
BD9241
1
Lot No.
SOP18 (Unit:mm)
○ Block diagram
○Terminal description
STB
block
PWM
block
Logic
block
Out
put
block
F/B
block
Terminal
No
Terminal
name
1
N2
External FET drive circuit output terminal
2
P2
External FET drive circuit output terminal
3
VCC
4
SEL
Dimming(POS,NEG)select terminal
5
CP
Timer ー latch setting capacity connection
terminal
6
GND
7
SRT
8
RT
9
VS
Error amplifier input terminal②
10
IS
Error amplifier input terminal①
11
FB
Error amplifier output terminal
12
COMP
Output
block
Reg
block
Internal
REG(5V)
Protection
block
REV. A
13
BCT
14
DUTY
Function
Power terminal
GROUND
Connecting terminal for charging
discharging current setting resistance of
block
Connecting terminal for charging
discharging current setting resistance of
block
and
OSC
and
OSC
Over-voltage detecting terminal
Connecting terminal for charging and
discharging current setting capacity of BOSC
block.
Switching terminal of PWM mode and burst
mode
15
STB
16
PGND
External FET drive circuit GND terminal
Standby switch terminal
17
P1
External FET drive circuit output terminal
18
N1
External FET drive circuit output terminal
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〇Usage notes
1. About the absolute maximum ratings
The damage may occur If absolute maximum rating such as applied voltage and operating temperature range etc. is exceeded,
moreover such destructive conditions as short mode or open mode etc. can not be assumed, so If a particular mode such as exceeding
the absolute maximum rating is assumed, please consider taking physical safety measures such as fuse etc.
2. As long as being operation range, the operation of circuit function will be assured in the range of operating ambient temperature. About
characteristic value, the specification value of electric characteristic can’t be guaranteed, but the characteristic value doesn’t change
rapidly in these ranges.
3. When attaching to the printed substrate, pay special attention to the direction and proper placement of the IC.
If the IC is attached
incorrectly, it may be destroyed. Destruction can also occur when there is a short, which can be caused by foreign objects entering between
outputs or an output and the power GND.
4. Please be careful that there is a possibility of malfunction which is happening when you use it in a strong electromagnetic field.
5. The potential of GND terminal and PGND terminal is used with not over ±0.3V please.
6. This IC has a built-in Temperature Protection Circuit (TSD circuit). The temperature protection circuit (TSD circuit) is only to cut off the IC from
thermal runaway, and has not been designed to protect or compensate the IC.
Therefore, the user should not plan to activate this circuit with
continued operation in mind.
7. Although the quality of this product has been tightly controlled ,the damage may occur If absolute maximum rating such as applied voltage
and operating temperature range etc. is exceeded, moreover such destructive conditions as short mode or open mode etc. can not be
assumed, so If a particular mode such as exceeding the absolute maximum rating is assumed, please consider taking a measures such as
fuse etc.
8. Regarding the external FET, since gate voltage will be changed regarding parasitic capacity between drain gates while switching the drain
voltage, please think over dispersion etc of our company’s IC, please select FET with sufficient margin.
9. CP timer does not operate during the time of soft start.
10.To prevent the destruction from external static electricity, please give resistance to the pin which directly link with connector etc.
11.This IC is a monolithic IC, and between each element there is a P+ isolation and P substrate for element separation. There is a P-N junction
and other parasitic elements formed between this P-layer and each element’s N-layer, as shown in Fig. when the resistors and transistors are
connected to the terminal,
○
When GND>(terminal A) at the resistance, or GND>(terminal B) at the transistor (NPN), the P-N junction operates as a
parasitic diode.
○
Also, when GND>(terminal B) at the transistor, a parasitic NPN transistor operates by the N-layer of other elements which
close to the aforementioned parasitic diode.
With the IC’s configuration, the production of parasitic elements by the relationships of the electrical potentials is inevitable.
The
operation of the parasitic elements can also interfere with the circuit operation, leading to malfunction and even destruction. Therefore,
uses which cause the parasitic elements to operate, such as applying voltage to the input terminal which is lower than the GND
(P-substrate), should be avoided.
トランジスタ(NPN)
Transistor (NPN)
抵抗
Resistance
B
(端子A)
(端子B)
Terminal B
(Terminal A)
P
P+
P
P+
N
N
N
E
C
N
+
GND
P
P
+
N
N
N
P基板
P基板
P Substrate
P Substrate
GND
GND
Parasitic
Element
寄生素子
寄生素子
Parasitic Element
Terminal B
(端子B)
B C
(端子A)
(Terminal A)
E
寄生素子
GND
Parasitic Element
GND
近接するほかの素子
other elements close to
寄生素子
Parasitic Element
Fig.1 Simple Structure of Monolithic IC
図-1 モノリシックICの簡易構造
REV. A
Notice
Notes
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illustrate the standard usage and operations of the Products. The peripheral conditions must
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