ROHM BD9270F

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STRUCTURE
Silicon Monolithic Integrated Circuit
NAME OF PRODUCT
DC-AC Inverter Control IC
TYPE
BD9270F
FUNCTION
・ 1ch control with Full-Bridge (For USE FET Body-Di)
・
・
・
・
・
・
・
・
・
・
Lamp current and voltage sense feed back control
Sequencing easily achieved with Soft Start Control
Striking time can Control independently (STRK pin)
Circuit protection with Timer Latch (COMP)
Circuit protection with quick Shutdown (COMPSD)
Mode-selectable the operating or stand-by mode by stand-by pin
Synchronous operating the other BD9270F ICs
BURST mode controlled by PWM input
Output liner Control by external DC voltage
Built-in Error mode output pin (FAIL pin)
○ Absolute Maximum Ratings(Ta = 25℃)
Parameter
Supply Voltage
OUTPUT DRIVER
Symbol
Limits
Unit
VCC
20
V
LNx, HFNx,
20
V
Operating Temperature Range
Topr
-40~+85
℃
Storage Temperature Range
Tstg
-55~+150
℃
Tjmax
+150
℃
Maximum Junction Temperature
Power Dissipation
Pd
688
*
mW
*
Pd derate at 5.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
○Operating condition
Parameter
Supply voltage
DRIVER frequency
Symbol
Limits
Unit
VCC
8.5~19.0
V
FOUT
30~110
kHz
REV. B
2/4
○Electric Characteristics(Ta=25℃、VCC=12V、STB=3.0V)
Symbol
MIN.
Limits
TYP.
MAX.
Unit
Icc1
Icc2
-
-
4.5
30
8.1
70
mA
uA
VstH
VstL
2
-0.3
-
-
VCC
0.8
V
V
VREG
IREG
3.92
5
4.00
-
4.08
-
V
mA
Vvccuvlo
⊿Vvccuvlo
7.0
0.50
7.5
0.60
8.0
0.70
V
V
FOUT
VRT
RSRT
63.0
1.05
-
65.0
1.50
100
67.0
1.95
200
kHz
V
Ω
ISS
VSS_ST
VSS_ED
ISTRK
VSTRK_ED
0.9
0.18
1.35
0.8
1.94
1.1
0.20
1.50
1.0
2.00
1.3
0.22
1.65
1.2
2.06
uA
V
V
uA
V
VIS1
VIS2
VVS
IIS1
IIS2
IVS
VISCOMP1
VISCOMP2
VREFIN
1.225
-
1.22
-
40
-
0.593
-
0.6
1.25
VREFIN
1.25
-
50
-
0.625
0.50
-
1.275
VIS1
1.28
0.9
60
0.9
0.657
-
1.6
V
V
V
uA
uA
uA
V
V
V
DUTY-th
0.90
1.00
1.10
V
Low = IS high (burst off)
RsinkLN
RsourceLN
RsinkHFN
RsourceHFN
MAX DUTY
1.8
4.5
1.8
4.5
44.0
3.5
9.0
3.5
9.0
45.5
7.0
18.0
7.0
18.0
47.0
Ω
Ω
Ω
Ω
%
VCC=12V
VCC=12V
VCC=12V
VCC=12V
FOUT=65kHz
VCP
ICP
1.94
0.9
2.00
1.0
2.06
1.1
V
uA
VCOMPH
⊿VCOMPH
VCOMPSDH
⊿VCOMPSDH
RFAIL
1.94
0.05
1.94
0.05
-
2.00
0.10
2.00
0.10
100
2.06
0.15
2.06
0.15
200
V
V
V
V
Ω
CT_SYNC_OUT Low voltage
VCT_SYNCH
VCT_SYNCL
CT_SYNC_OUT sink resistance
RSYNC_OUT_sink
3.8
-
-
-
2.5
-0.3
4.0
-
150
300
-
-
4.2
0.5
300
400
V
V
Ω
Ω
V
V
Parameter
((WHOEL DEVICE))
Operating current
Stand-by current
Conditions
FOUT=60kHz, FB=GND, DUTY=0V
((STAND BY CONTROL))
Stand-by voltage H
Stand-by voltage L
((REF4V BLOCK))
REF4V output voltage
REF4V source current
System ON
System OFF
((VCC UVLO BLOCK))
Operating voltage (VCC)
Hysteresis width (VCC)
((OSC BLOCK))
Drive output frequency
RT pin voltage
SRT ON resistance
((SS STRK BLOCK))
Soft start current
SS operation start voltage
SS term END voltage
STRK current
STRK term END voltage
RT=18.9kΩ
((FEED BACK BLOCK))
IS threshold voltage 1
IS threshold voltage 2
VS threshold voltage
IS source current 1
IS source current 2
VS source current
IS COMP detect voltage 1
IS COMP detect voltage 2
VREF input voltage range
VREF applying voltage
DUTY=1.5V
DUTY=0V, IS=1.0V
VREFIN≧1.25V
VREFIN= 1V
No effect at VREF>1.25V
((DUTY BLOCK))
DUTY threshold voltage
((OUTPUT BLOCK))
LN output sink resistance
LN output source resistance
HFN output sink resistance
HFN output source resistance
MAX DUTY
((TIMER LATCH BLOCK))
Timer Latch setting voltage
Timer Latch setting current
((COMP BLOCK))
COMP over voltage detect
Hysteresis width (COMP)
COMPSD over voltage detect
Hysteresis width (COMPSD)
FAIL ON resistance
((SYNCHRONOUS BLOCK))
CT_SYNC_OUT High voltage
CT_SYNC_OUT source resistance
RSYNC_OUT_source
CT_SYNC_IN High voltage input range
VCT_SYNC_IN_H
CT_SYNC_IN Low voltage input range
VCT_SYNC_IN_L
(This product is not designed to be radiation-resistant.)
REV. B
VCT_SYNCH
1
VSS>1.65V, SRT operate, CP timer latch
VSS>1.65V, OSC 2 count
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〇Package Dimensions
〇Pin Description
Device Mark
BD9270F
PIN No.
PIN NAME
1
PGND
2
LN2
3
HFN2
4
CT_SYNC_IN
5
Lot No.
SOP-24 (Unit:mm)
〇Block Diagram
REV. B
FUNCTION
Ground for FET drivers
NMOS FET driver
NMOS FET driver (New Function)
CT synchronous signal input pin
CT_SYNC_OUT CT synchronous signal output pin
6
REF4V
7
SRT
Internal regulator output
External resistor from SRT to RT for adjusting the
start-up triangle oscillator
External resistor from RT to GND for adjusting the
triangle oscillator
8
RT
9
GND
GROUND
10
DUTY
Control PWM mode and BURST mode
11
FAIL
Error mode OUTPUT Pin (open drain)
12
STB
Stand-by switch
13
CP
14
VREF
15
VS
Error amplifier input
16
IS
Error amplifier input
17
FB
Error amplifier output
18
SS
External capacitor from SS to GND for Soft Start
Control
19
STRK
20
COMPSD
Over voltage detect pin with Shutdown
21
COMP
Over voltage detect pin with timer latch
22
VCC
Supply voltage input
23
HFN1
NMOS FET driver (New Function)
24
LN1
External capacitor from CP to GND for Timer Latch
Reference voltage input pin for Error amplifier
Striking time setting pin
NMOS FET driver
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〇NOTE FOR USE
1. This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum
ratings. Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode.
Therefore, physical protection countermeasure, like fuse is recommended in case operating conditions go beyond
the expected absolute maximum ratings.
2. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within
recommended operating range. The standard electrical characteristic values cannot be guaranteed at other
voltages in the operating ranges, however the variation will be small.
3. Mounting failures, such as misdirection or miscounts, may harm the device.
4. A strong electromagnetic field may cause the IC to malfunction.
5. The GND pin should be the location within ±0.3V compared with the PGND pin. ALL Pin Voltage should be under
VCC voltage +0.3V even if the voltage is under each terminal ratings.
6. BD9270F incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD
circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect
the IC or guarantee its operation of the thermal shutdown circuit is assumed.
7. When modifying the external circuit components, make sure to leave an adequate margin for external components
actual value and tolerance as well as dispersion of the IC.
8. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage
is switching. Make sure to leave adequate margin for this IC variation.
9. Under operating CP charge (under error mode) analog dimming and burst dimming are not operate.
10. Under operating Slow Start Control (SS is less than 1.5V), It does not operate Timer Latch.
11. By STB voltage, BD9270F are changed to 2 states. Therefore, do not input STB pin voltage between one state
and the other state (0.8~2.0V).
12. The pin connected a connector need to connect to the resistor for electrical surge destruction.
13. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N
junction is formed from this P layer of each pin. For example, the relation between each potential is as
follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result
in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must
not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P
substrate) voltage to an input pin.
Transistor (NPN)
Resistance
(PinA)
(PinB)
B
E
C
C
GND
N
P
P+
P+
N
N
P substrate
GND
Parasitic diode
N
N
N
P substrate
GND
Parasitic diode
(PinB)
(PinA)
B
CC
B
EE
Parasitic diode
GND
GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. B
Notice
Notes
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R1010A