Micross RetailPlus Datasheet MYX4DDR3L128M16JT

2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
2Gbit - 128M x 16 DDR3L SDRAM
• TC of 0°C to +95°C
Description
• 64ms, 8192-cycle refresh at 0°C to +85°C
The 1.35V DDR3L SDRAM device is a low-voltage version
of the 1.5V DDR3 SDRAM device. Refer to the DDR3 (1.5V)
SDRAM data sheet specifications when running in 1.5V
compatible mode.
• 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
Features
• Output driver calibration
• Tin-lead ball metallurgy
• VDD = VDDQ = 1.35V (1.283–1.45V)
OptionsCode
• Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
• Configuration:
• Differential bidirectional data strobe
• 128 Meg x 16
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
128M16
• FBGA package (Sn63 / Pb37)
• 8 internal banks
• 96-ball FBGA (8mm x 14mm)
• Nominal and dynamic on-die termination (ODT) for data,
strobe, and mask signals
JT
• Timing - cycle time
• 1.25ns @ CL = 11 (DDR3-1600)
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
-125
• Operating temperature
• Programmable CAS (WRITE) latency (CWL)
• Commercial (0°C ≤ TC ≤ +95°C)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via
the mode register set [MRS])
• Industrial (-40°C ≤ TC ≤ +95°C)
None
IT
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
Table 1: Key Timing Parameters
Speed Grade Data Rate (MT/s)
-125*
1600
Table 2: Addressing
Target tRCD-tRP-CL tRCD (ns) tRP (ns)
11-11-11
13.75
Note: Backward compatible to 1066, CL=7 (-187E) and 1333, CL=9 (-15E)
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
CL (ns)
Parameter
128 Meg x 16
Configuration
16 Meg x 16 x 8 banks
Refresh Count
8K
Row Address
16K A[13:0]
Bank Address
8 BA[2:0]
Column Address
1K A[9:0]
1
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Functional Description
Industrial Temperature
DDR3 SDRAM uses a double data rate architecture to achieve
high-speed operation. The double data rate architecture is an
8n-prefetch architecture with an interface designed to transfer
two data words per clock cycle at the I/O pins. A single read
or write operation for the DDR3 SDRAM effectively consists
of a single 8n-bit-wide, four-clockcycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one
half-clock-cycle data transfers at the I/O pins.
The industrial temperature (IT) device requires that the case
temperature not exceed -40°C or 95°C. JEDEC specifications
require the refresh rate to double when TC exceeds 85°C; this
also requires use of the high-temperature self refresh option.
Additionally, ODT resistance and the input/output impedance
must be derated when TC is < 0°C or >95°C.
General Notes
The differential data strobe (DQS, DQS#) is transmitted
externally, along with data, for use in data capture at the DDR3
SDRAM input receiver. DQS is center-aligned with data for
WRITEs. The read data is transmitted by the DDR3 SDRAM
and edge-aligned to the data strobes.
• The functionality and the timing specifications discussed
in this data sheet are for the DLL enable mode of
operation (normal operation).
• Throughout this data sheet, various figures and text refer
to DQs as “DQ.” DQ is to be interpreted as any and all
DQ collectively, unless specifically stated otherwise.
The DDR3 SDRAM operates from a differential clock (CK and
CK#). The crossing of CK going HIGH and CK# going LOW is
referred to as the positive edge of CK. Control, command, and
address signals are registered at every positive edge of CK.
Input data is registered on the first rising edge of DQS after the
WRITE preamble, and output data is referenced on the first
rising edge of DQS after the READ preamble.
• The terms “DQS” and “CK” found throughout this data
sheet are to be interpreted as DQS, DQS# and CK, CK#
respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout
the document; any page or diagram may have been
simplified to convey a topic and may not be inclusive of
all requirements.
Read and write accesses to the DDR3 SDRAM are burstoriented. Accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVATE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row
to be accessed. The address bits registered coincident with
the READ or WRITE commands are used to select the bank
and the starting column location for the burst access.
• Any specific requirement takes precedence over a
general statement.
• Any functionality not specifically stated is considered
undefined, illegal, and not supported, and can result in
unknown operation.
• Row addressing is denoted as A[n:0]. For example,
1Gb: n = 12 (x16); 1Gb: n = 13 (x4, x8); 2Gb: n = 13
(x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and
4Gb: n = 15 (x4, x8).
The device uses a READ and WRITE BL8 and BC4. An auto
precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
• Dynamic ODT has a special use case: when DDR3
devices are architected for use in a single rank memory
array, the ODT ball can be wired HIGH rather than
routed. Refer to the Dynamic ODT Special Use Case
section.
As with standard DDR SDRAM, the pipelined, multibank
architecture of DDR3 SDRAM allows for concurrent operation,
thereby providing high bandwidth by hiding row precharge and
activation time.
A self refresh mode is provided, along with a power-saving,
power-down mode.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
2
Form #: CSI-D-685 Document 009
2Gb: x4, x8, x16 DDR3L SDRAM
Functional Block Diagrams
Figure 4: 256 Meg x 8 Functional Block Diagram
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
ODT
control
ODT
ZQ
ZQ CAL
RESET#
RZQ
Control
logic
CKE
VSSQ
To ODT/output drivers
A12
*Advanced information. Subject to change without notice.
ZQCL, ZQCS
CK, CK#
VDDQ/2
General Notes (continued)
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Mode registers
15
Rowaddress
MUX
18
15
Address
register
Bank
control
logic
• Connect UDM to VDD via 1kΩ* resistor.
3
8
VDDQ/2
RTT,nom
SW1
RTT(WR)
SW2
(1, 2)
64
• Connect DQ[15:8] individually to either VSS, VDD, or
VREF via 1kΩ resistors,* or float DQ[15:8].
8
Data
interface
Data
Column
decoder
10
DQ[7:0]
DQS, DQS#
BC4
BC4
OTF
(128
x64)
Columnaddress
counter/
latch
TDQS#
DQ[7:0]
Read
drivers
I/O gating
DM mask logic
3
18
DQ8
READ
FIFO
and
data
MUX
64
8,192
• Connect UDQS# to VDD via 1kΩ* resistor.
A[14:0]
BA[2:0]
(1 . . . 8)
64
Sense amplifiers
• Connect UDQS to ground via 1kΩ* resistor.
SW2
DLL
Bank 0
Memory
array
(32,768 x 128 x 64)
Bank 0
rowaddress
32,768
latch
and
decoder
15
CK, CK#
SW1
• A x16 device’s DQ bus is comprised of two bytes. If
only one of the bytes needs to be used, use the lower
byte for data transfers and terminate the upper byte as
noted:
Refresh
counter
RTT(WR)
RTT,nom
Write
drivers
and
input
logic
RTT,nom
SW1
RTT(WR)
SW2
7
3
DQS/DQS#
VDDQ/2
DM/TDQS
(shared pin)
Columns 0, 1, and 2
*If ODT is used, 1kΩ resistor should be changed to
4x that of the selected ODT.
CK, CK#
Column 2
(select upper or
lower nibble for BC4)
Figure
1: Functional
Block
Diagram
Figure
5: 128 Meg
x 16
Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
ZQ CAL
RESET#
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQCL, ZQCS
A12
CK, CK#
VDDQ/2
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
17
13
Rowaddress
MUX
14
14
Bank 0
rowaddress
latch
and
decoder
16,384
RTT,nom
Column 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
CK, CK#
DLL
(1 . . . 16)
Bank 0
memory
array
(16,384 x 128 x 128)
128
READ
FIFO
and
data
MUX
16
DQ[15:0]
READ
drivers
VDDQ/2
17
Address
register
3
Data
interface
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
16
Data
WRITE
drivers
and
input
logic
7
3
UDQS, UDQS#
VDDQ/2
128
RTT,nom
SW1
RTT(WR)
SW2
(1, 2)
LDM/UDM
Columns 0, 1, and 2
CK, CK#
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
SW2
LDQS, LDQS#
Column
decoder
10
RTT(WR)
(1 . . . 4)
(128
x128)
Columnaddress
counter/
latch
RTT,nom
SW1
BC4
OTF
I/O gating
DM mask logic
Bank
control
logic
BC4
128
16,384
A[13:0]
BA[2:0]
DQ[15:0]
LDQS, LDQS#, UDQS, UDQS#
Sense amplifiers
3
RTT(WR)
SW2
SW1
15
Column 2
(select upper or
lower nibble for BC4)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
3
Form #: CSI-D-685 Document 009
2Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments
and Descriptions
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
Figure 7: 96-Ball FBGA – x16 Ball Assignments (Top View)
*Advanced information. Subject to change without notice.
Figure 2: 96-Ball
FBGA – x16 Ball
Assignments
(Top View)
A
B
1
2
3
VDDQ
DQ13
VSSQ
4
5
6
7
8
9
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
NC
A8
VSS
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Notes:
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
Notes
1. Ball descriptions
listed in Table 3
on page 5
are listed as
“x16.”
2. A comma
separates the
configuration;
a slash defines
a selectable
function.
1. Ball descriptions listed in Table 4 (page 20) are listed as “x16.”
2. A comma separates the configuration;
a slash defines a selectable function.
4
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 3: 96-Ball FBGA – x16 Ball Descriptions
Symbol
Type
Description
A13, A12/
Input
BC#, A11,
A10/AP, A[9:0]
Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address
inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See Truth Table - Command.
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0]
define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of
CK and the negative edge of CK#. Output data strobe (LDQS, LDQS#, UDQS, UDQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific
circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides
PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding
CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS#
is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command
code. CS# is referenced to VREFCA.
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH
along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the
DQ and LDQS balls. LDM is referenced to VREFDQ.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM.
When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM,
and UDM for the x16. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA.
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail
signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and deassertion are asynchronous.
UDM
Input
Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte input data is masked when UDM is sampled HIGH
along with the input data during a write access. Although the UDM ball is input-only, the UDM loading is designed to match that of the
DQ and UDQS balls. UDM is referenced to VREFDQ.
DQ[7:0]
I/O
Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ.
DQ[15:8]
I/O
Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS#
I/O
Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. LDQS is center-aligned to write data.
UDQS, UDQS#
I/O
Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. UDQS is center-aligned to write data.
VDD
Supply
Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.
VDDQ
Supply
DQ power supply: 1.35V, 1.283–1.45V operational; compatible with 1.5V operation.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
5
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 3: 96-Ball FBGA – x16 Ball Descriptions (continued)
Symbol
Type
Description
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper
device operation.
VREFCAQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
ZQ
Reference
External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.
NC
-
No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls).
Electrical Specifications - Absolute Ratings
Stresses greater than those listed may cause permanent
damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside
those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions
for extended periods may adversely affect reliability.
Table 4: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
VDD
VDD supply voltage relative to VSS
-0.4
1.975
V
1
VDDQ
VDDQ supply voltage relative to VSSQ
-0.4
1.975
V
Voltage on any ball relative to VSS
-0.4
1.975
V
0
95
°C
2, 3
Operating case temperature – Industrial
-40
95
°C
2, 3
Storage temperature
-55
150
°C
VIN, VOUT
TC
TSTG
Operating case temperature – Commercial
Notes:
1. VDD and VDDQ must be within 300mV of each other at all
times, and VREF must not be greater than 0.6 × VDDQ. When
VDD and VDDQ are <500mV, VREF can be ≤300mV.
2. MAX operating case temperature. TC is measured in the
center of the package.
3. Device functionality is not guaranteed if the DRAM device
exceeds the maximum TC during operation.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
6
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 5: Thermal Characteristics
Description
Value
Unit
Symbol
Notes
Operating case temperature –
Commercial
0 to +85
°C
TC
1, 2, 3
0 to +95
°C
TC
1, 2, 3, 4
Operating case temperature –
Industrial
-40 to +85
°C
TC
1, 2, 3
-40 to +95
°C
TC
1, 2, 3, 4
6.5
°C/W
ΘJC
5
Junction-to-case (TOP)
96-ball (JT)
Notes:
1. Maximum operating case temperature. TC is measured in the
center of the package.
2. A thermal solution must be designed to ensure the DRAM
device does not exceed TC MAX during operation.
3. Device functionality is not guaranteed if the DRAM device
exceeds TC MAX during operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally
at 2x refresh, which is a 3.9μs interval refresh rate. The use of
SRT or ASR (if available) must be enabled.
5. Thermal resistance data is based on a number of samples
from multiple lots and should be viewed as a typical number.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
7
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 6: DDR3L Input/Output Capacitance
Note 1 applies to the entire table; gray-shaded cells are DDR3L unique values; all other values are the same for both DDR3L and DDR3.
Capacitance Parameters
Symbol
DDR3L-1600
Min
Max
Unit
Notes
CK and CK#
CCK
0.8
1.4
pF
ΔC: CK to CK#
CDCK
0.0
0.15
pF
Single-end I/O: DQ, DM
CIO
1.4
2.2
pF
2
Differential I/O: DQS, DQS#, TDQS, TDQS#
CIO
1.4
2.2
pF
3
ΔC: DQS to DQS#, TDQS, TDQS#
CDDQS
0.0
0.15
pF
3
ΔC: DQ to DQS
CDIO
-0.5
0.3
pF
4
Inputs (CTRL, CMD, ADDR)
CI
0.75
1.2
pF
5
ΔC: CTRL to CK
CDI_CTRL
-0.4
0.2
pF
6
ΔC: CMD_ADDR to CK
CDI_CMD_ADDR
-0.4
0.4
pF
7
ZQ pin capacitance
CZQ
-
3.0
pF
Reset pin capacitance
CRE
-
3.0
pF
Notes:
1. VDD = 1.35V (1.283–1.45V), VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5 × VDDQ, VOUT = 0.1V (peak-to-peak).
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR = A[n:0], BA[2:0].
6. CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)).
7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)).
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
8
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Electrical Characteristics - IDD Specifications and Conditions
Within the following IDD measurement tables, the following
definitions and conditions are used, unless stated otherwise:
• LOW: VIN ≤ VIL(AC)max; HIGH: VIN ≥ VIH(AC)min
• Burst lengths are BL8 fixed
• Midlevel: Inputs are VREF = VDD/2
• AL equals 0 (except in IDD7)
• RON set to RZQ/7 (34Ω)
• IDD specifications are tested after the device is properly
initialized
• RTT,nom set to RZQ/6 (40Ω)
• Input slew rate is specified by AC parametric test
conditions
• RTT(WR) set to RZQ/2 (120Ω)
• QOFF is enabled in MR1
• Optional ASR is disabled
• ODT is enabled in MR1 (RTT,nom) and MR2 (RTT(WR))
• Read burst type uses nibble sequential (MR0[3] = 0)
• TDQS is disabled in MR1
• Loop patterns must be executed at least once before
current measurements begin
• External DQ/DQS/DM load resistor is 25Ω to VDDQ/2
Table 7: DDR3L Timing Parameters Used for
IDD Measurements – Clock Units
DDR3L-1600
IDD Parameter
-125
Unit
11-11-11
tCK
1.25
na
CL IDD
11
CK
tRCD
11
CK
39
CK
28
CK
11
CK
tRC
(MIN) IDD
(MIN) IDD
tRAS
tRP
(MIN) IDD
(MIN) IDD
(MIN)
tFAW
x16
32
CK
tRRD IDD
x16
6
CK
tRFC
1Gb
88
CK
2Gb
128
CK
4Gb
208
CK
8Gb
280
CK
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
9
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Electrical Characteristics - IDD Specifications
Table 8: IDD Maximum Limits
Speed Bin
DDR3L-1600
Units
Notes
x16
46
mA
1, 2
IDD1
x16
65
mA
1, 2
IDD2P0 (Slow)
All
12
mA
1, 2
IDD2P1 (Fast)
All
14
mA
1, 2
IDD2Q
All
20
mA
1, 2
IDD2N
All
21
mA
1, 2
IDD2NT
x16
34
mA
1, 2
IDD3P
All
21
mA
1, 2
IDD3N
x16
34
mA
1, 2
IDD4R
x16
128
mA
1, 2
IDD4W
x16
138
mA
1, 2
IDD5B
All
180
mA
1, 2
IDD6
All
12
mA
1, 2, 3
IDD6ET
All
15
mA
2, 4
IDD7
x16
195
mA
1, 2
IDD8
All
IDD2P0 + 2mA
mA
1, 2
IDD
Width
IDD0
Notes:
1. TC = 85°C; SRT and ASR are disabled.
2. Enabling ASR could increase IDDx by up to an additional 2mA.
3. Restricted to TC (MAX) = 85°C.
4. TC = 85°C; ASR and ODT are disabled; SRT is enabled.
5. The IDD values must be derated (increased) on IT-option devices when operated outside of the range 0°C ≤ TC ≤ +85°C:
A. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must be derated by 2%; and IDD6, IDD6ET and
IDD7 must be derated by 7%.
B. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
10
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Electrical Specifications – DC and AC
DC Operating Conditions
Table 9: DDR3L 1.35V DC Electrical Characteristics and
Operating Conditions
All voltages referenced to VSS.
Parameter/Condition
Symbol
Supply voltage
Min
Nom
Max
Unit
Notes
1.283
1.35
1.45
V
1-7
II
-2
-
2
µA
-
IVREF
-1
-
1
µA
8, 9
VDD
I/O Supply voltage
VDDQ
Input leakage current
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V (all other pins not under test = 0V)
VREF supply leakage current
VREFDQ = VDD/2 or VREFCA = VDD/2 (all other pins not under test = 0V)
Notes:
1. VDD and VDDQ must track one another. VDDQ must be ≤ VDD.
VSS = VSSQ.
6. Under 1.5V operation, this DDR3L device operates in
accordance with the DDR3 specifications under the same
speed timings as defined for this device.
2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to
20 MHz) in addition to the DC (0 Hz to 250 kHz) specifications.
VDD and VDDQ must be at same level for valid AC timing
parameters.
7. Once initialized for DDR3L operation, DDR3 operation may
only be used if the device is in reset while VDD and VDDQ are
changed for DDR3 operation (see VDD Voltage Switching).
3. Maximum DC value may not be greater than 1.425V. The
DC value is the linear average of VDD/VDDQ(t) over a very long
period of time (for example, 1 second).
8. The minimum limit requirement is for testing purposes. The
leakage current on the VREF pin should be minimal.
9. VREF (see Table 10 on page 12).
4. Under these supply voltages, the device operates to this
DDR3L specification.
5. If the maximum limit is exceeded, input levels shall be
governed by DDR3 specifications.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
11
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Input Operating Conditions
Table 10: DDR3L 1.35V DC Electrical Characteristics and Input Conditions
All voltages referenced to VSS.
Parameter/Condition
Symbol
Min
Nom
Max
Unit
VIN low; DC/commands/address busses
VIL
VSS
NA
See Table 11
V
VIN high; DC/commands/address busses
VIH
See Table 11
NA
VDD
V
Input reference voltage command/address bus
VREFCA(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
1, 2
I/O reference voltage DQ bus
VREFDQ(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
2, 3
I/O reference voltage DQ bus in SELF REFRESH
VREFDQ(SR)
VSS
0.5 × VDD
VDD
V
4
VTT
-
0.5 × VDDQ
-
V
5
Command/address termination voltage (system level, not direct DRAM input)
Notes
Notes:
1. VREFCA(DC) is expected to be approximately 0.5 × VDD and
to track variations in the DC level. Externally generated peak
noise (non-common mode) on VREFCA may not exceed ±1% ×
VDD around the VREFCA(DC) value. Peak-to-peak AC noise on
VREFCA should not exceed ±2% of VREFCA(DC).
2. DC values are determined to be less than 20 MHz in
frequency. DRAM must meet specifications if the DRAM
induces additional AC noise greater than 20 MHz in frequency.
3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and
to track variations in the DC level. Externally generated peak
noise (non-common mode) on VREFDQ may not exceed ±1% ×
VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on
VREFDQ should not exceed ±2% of VREFDQ(DC).
4. VREFDQ(DC) may transition to VREFDQ(SR) and back to
VREFDQ(DC) when in SELF REFRESH, within restrictions
outlined in the SELF REFRESH section.
5. VTT is not applied directly to the device. VTT is a system supply
for signal termination resistors. Minimum and maximum values
are system-dependent.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
12
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 11: DDR3L 1.35V Input Switching Conditions - Command and Address
Parameter/Condition
Symbol
DDR3L-1600
Units
Command and Address
Input high AC voltage: Logic 1
VIH(AC160),min5
160
mV
Input high AC voltage: Logic 1
VIH(AC135),min5
135
mV
Input high DC voltage: Logic 1
VIH(AC125,)min5
-
mV
Input low DC voltage: Logic 1
VIH(DC90),min
90
mV
Input low AC voltage: Logic 0
VIL(DC90),min
-90
mV
Input low AC voltage: Logic 0
VIL(AC125),min5
-
mV
Input low AC voltage: Logic 0
VIL(AC135),min5
-135
mV
Input low AC voltage: Logic 0
VIL(AC160),min5
-160
mV
DQ and DM
Input high AC voltage: Logic 1
VIH(AC160),min5
160
mV
Input high AC voltage: Logic 1
VIH(AC135),min5
135
mV
Input high DC voltage: Logic 1
VIH(AC125,)min5
-
mV
Input low DC voltage: Logic 1
VIH(DC90),min
90
mV
Input low AC voltage: Logic 0
VIL(DC90),min
-90
mV
Input low AC voltage: Logic 0
VIL(AC125),min5
-
mV
Input low AC voltage: Logic 0
VIL(AC135),min5
-135
mV
Input low AC voltage: Logic 0
VIL(AC160),min5
-160
mV
Notes:
1. All voltages are referenced to VREF. VREF is VREFCA for control,
command, and address. All slew rates and setup/hold times
are specified at the DRAM ball. VREF is VREFDQ for DQ and DM
inputs.
the associated setup time for that AC level must also be
used. Additionally, one VIH(AC) value may be used for address/
command inputs and the other VIH(AC) value may be used for
data inputs. For example, for DDR3-800, two input AC levels
are defined: VIH(AC160),min and VIH(AC135),min (corresponding
VIL(AC160),min and VIL(AC135),min). For DDR3-800, the
address/command inputs must use either VIH(AC160),min with
tIS(AC160) of 210ps or VIH(AC150),min with tIS(AC135) of 365ps;
independently, the data inputs must use either VIH(AC160),min
with tDS(AC160) of 75ps or VIH(AC150),min with tDS(AC150) of
125ps.
2. Input setup timing parameters (tIS and tDS) are referenced at
VIL(AC)/VIH(AC), not VREF(DC).
3. Input hold timing parameters (tIH and tDH) are referenced at
VIL(DC)/VIH(DC), not VREF(DC).
4. Single-ended input slew rate = 1 V/ns; maximum input voltage
swing under test is 900mV (peak-to-peak).
5. When two VIH(AC) values (and two corresponding VIL(AC)
values) are listed for a specific speed bin, the user may choose
either value for the input AC level. Whichever value is used,
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
13
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 12: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition
Symbol
Min
Max
Units
Notes
Differential input logic high – slew
VIH,diff(AC)slew
180
NA
mV
4
Differential input logic low – slew
VIL,diff(AC)slew
NA
-180
mV
4
Differential input logic high
VIH,diff(AC)
2 × (VIH(AC) - VREF)
VDD/VDDQ
mV
5
Differential input logic low
VIL,diff(AC)
VSS/VSSQ
2 × (VIL(AC) - VREF)
mV
6
VIX
VREF(DC) - 150
VREF(DC) + 150
mV
5, 7, 9
VIX (175)
VREF(DC) - 175
VREF(DC) + 175
mV
5, 7, 8, 9
Single-ended high level for strobes
VSEH
VDDQ/2 + 160
VDDQ
mV
5
Single-ended high level for CK, CK#
VSEH
VDD/2 + 160
VDD
mV
5
Single-ended low level for strobes
VSEL
VSSQ
VDDQ/2 - 160
mV
6
Single-ended low level for CK, CK#
VSEL
VSS
VDD/2 - 160
mV
6
Differential input crossing voltage relative to VDD/2 for DQS, DQS#; CK, CK#
Differential input crossing voltage relative to VDD/2 for CK, CK#
Notes:
1. Clock is referenced to VDD and VSS. Data strobe is referenced
to VDDQ and VSSQ.
0.5 × VDD of the transmitting device, and VIX(AC) is expected
to track variations in VDD. VIX(AC) indicates the voltage at which
differential input signals must cross.
2. Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe.
8. The VIX extended range (±175mV) is allowed only for the
clock; this VIX extended range is only allowed when the
following conditions are met: The single-ended input signals
are monotonic, have the single-ended swing VSEL, VSEH of at
least VDD/2 ±250mV, and the differential slew rate of CK, CK#
is greater than 3 V/ns.
3. Differential input slew rate = 2 V/ns.
4. Defines slew rate reference points, relative to input crossing
voltages.
5. Minimum DC limit is relative to single-ended signals; overshoot
specifications are applicable.
6. Maximum DC limit is relative to single-ended signals;
undershoot specifications are applicable.
9. VIX must provide 25mV (single-ended) of the voltages
separation.
7. The typical value of VIX(AC) is expected to be about
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
14
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced
to change
without notice.
2Gb:
x4,information.
x8, x16Subject
DDR3L
SDRAM
Electrical Specifications – DC and AC
Figure 3: DDR3L 1.35V Input Signal
Figure 13: DDR3L 1.35V Input Signal
VDD + 0.4V
Narrow pulse width
Minimum VIL and VIH levels
VIH MIN(AC)
VIH MIN(DC)
VIH(AC)
VIH(DC)
VIL MIN(AC)
VDD
VIL(DC)
VIL(AC)
VREF + 125/135/160mV
VIH(AC)
VREF + 90mV
VIH(DC)
VREFDQ - DC error
VREFDQ - AC noise
VIL(DC)
VREF - 125/135/160mV
VIL(AC)
VSS - 0.40V
Narrow pulse width
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
VREFDQ + AC noise
VREFDQ + DC error
VREF - 90mV
0.0V
Note:
VDDQ + 0.4V
Overshoot
VDDQ
VREF DC MAX + 1% VDD
VREF + 1% VDD
VREF = VDD/2
VREF - 1% VDD
VREF DC MIN - 1% VDD
MAX 2% Total
VREF DC MAX
VREF
DC MIN
MAX 2% Total
VIL MIN(DC)
VIL and VIH levels with ringback
VSS
VSS - 0.40V
Undershoot
1. Numbers in diagrams reflect nominal values.
15
Form #: CSI-D-685 Document 009
2Gb:x4,
x4,x8,
x8,x16
x16DDR3L
DDR3LSDRAM
SDRAM
2Gb:
Electrical
Specifications
–
DC
andAC
AC
Electrical Specifications – DC and
DDR3L1.35V
1.35VAC
ACOvershoot/Undershoot
Overshoot/UndershootSpecification
Specification
DDR3L
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
DDR3L-1333
DDR3L-1600
DDR3L-1866
Table26:
26:DDR3L
DDR3LControl
Controland
andAddress
AddressPins
Pins
Table
Parameter
Parameter
Maximum
peak
amplitude
allowed
Maximum
peak
amplitude
allowed
for
overshoot
area
for overshoot area
(see
Figure
14)
(see
Figure
14)
DDR3L-800
DDR3L-800
DRR3L-1066 DDR3L-1333
DRR3L-1066
0.4V
0.4V
for
undershoot
area
for
undershoot
area
0.4V
0.4V
0.4V
0.4V
Maximum
overshoot
area
above
VDD
Maximum
overshoot
area
above
VDD
0.67
Vns
0.67
Vns
(see
Figure
14)
Parameter
(see Figure 14)
Maximum
undershoot
area
below
VSS (see Figure 4)
Maximum
area
VSS
Maximum
peakundershoot
amplitude
allowed
forbelow
overshoot
area
0.67
Vns
0.67
Vns
(see
Figure
15)
(see Figure 15)
Maximum peak amplitude allowed for undershoot area (see Figure 5)
DDR3L-1866
*Advanced information.
without notice.
0.4V
0.4VSubject to change
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
DDR3L
1.35V
AC Overshoot/Undershoot
Specification
Maximum
peak
amplitude
allowed
Maximum
peak
amplitude
allowed
(see
Figure
15) Control and Address Pins
Table
13:
DDR3L
(see
Figure
15)
DDR3L-1600
0.4V
0.4V
0.4V
0.4V
0.5
Vns
0.4 Vns
0.5
Vns
DDR3L-1600 0.4 Vns
0.33
Vns
0.33
Vns
0.28
Vns
0.28
Vns
0.4V
0.5
Vns
0.5
Vns
0.4V
0.33
Vns
0.33
Vns
0.28
Vns
0.28
Vns
Maximum overshoot area above VDD (see Figure 4)
0.4V
0.4V
0.4
Vns
0.4
Vns
0.33 Vns
Table27:
27:DDR3L
DDR3L1.35V
1.35VClock,
Clock,Data,
Data,Strobe,
Strobe,and
andMask
MaskPins
Pins
Table
Maximum undershoot area below VSS (see Figure 5)
Parameter
Parameter
DDR3L-800
DDR3L-800
0.33 Vns
DDR3L-1066
DDR3L-1333 DDR3L-1600
DDR3L-1600 DDR3L-1866
DDR3L-1866
DDR3L-1066
DDR3L-1333
Maximum peak amplitude allowed
Maximum
peak amplitude
allowed
Table
14: DDR3L
1.35V Clock,
Data, Strobe, and
Mask Pins
for overshoot area
0.4V
for overshoot area
0.4V
(see
Figure
14)
(see
Figure
14)
Parameter
Maximum
peak
amplitude
allowed
Maximum
peak
amplitude
allowed
for
undershoot
area
0.4V
for undershoot
areaallowed for overshoot area (see Figure
0.4V
Maximum
peak amplitude
4)
(see
Figure
15)
(see Figure 15)
Maximum
peak amplitude
allowed
for above
undershoot area (see Figure 5)
Maximum
overshoot
area
Maximum
overshoot
area
above
0.25 Vns
VDD
Figure
DDQ (seearea
Maximum
overshoot
above14)
V /V
(see Figure 4) 0.25 Vns
VDD
/V/V
DDQ (see Figure 14) DD DDQ
Maximum
undershoot
area
below
Maximum
undershoot
area
Maximum
undershoot
area below
VSSbelow
/VSSQ (see Figure 5) 0.25 Vns
0.25 Vns
V
/V
(see
Figure
15)
SS
SSQ
V /V
(see Figure 15)
SS
SSQ
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
DDR3L-1600
0.4V
0.4V 0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.19
Vns
0.19
Vns
0.13 Vns
0.15
Vns
0.15
Vns
0.13
Vns
0.13
Vns
0.11
Vns
0.11
Vns
0.13 Vns
0.19
Vns
0.19
Vns
0.15
Vns
0.15
Vns
0.13
Vns
0.13
Vns
0.11
Vns
0.11
Vns
Figure14:
14:Overshoot
Overshoot
Figure
Figure 4: Overshoot
Volts
Volts
(V)(V)
Maximum
amplitude
Maximum
amplitude
VDD
DDQ
/V/V
VDD
DDQ
Overshoot
area
Overshoot
area
Time
(ns)
Time
(ns)
Figure15:
15:Undershoot
Undershoot
Figure
Figure 5: Undershoot
V/V
SS/VSSQ
VSS
SSQ
Volts
Volts
(V)(V)
Maximum
amplitude
Maximum
amplitude
Undershoot
area
Undershoot
area
Time
(ns)
Time
(ns)
PDF: 09005aef83ed2952
PDF:2Gb_DDR3L.pdf
09005aef83ed2952
- Rev. K 9/13 EN
2Gb_DDR3L.pdf - Rev. K 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
4949
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Micron Technology, Inc. reserves the right to change
products
specifications
© 2010
Micron or
Technology,
Inc. without
All rightsnotice.
reserved.
© 2010 Micron Technology, Inc. All rights reserved.
16
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
2Gb: x4,
x8, x16 DDR3L SDRAM
*Advanced information. Subject to change without notice.
Electrical Specifications – DC and AC
Figure
6: VIX16:
forVDifferential
Signals
Figure
IX for Differential Signals
Figure 16: VIX for Differential Signals
VDD, VDDQ
VDD, VDDQ
CK#, DQS#
VDD, VDDQ
VDD,CK#,
VDDQDQS#
CK#, DQS#
CK#, DQS#
V
X
VIX
X
VDD/2, VDDQ/2
X
VIX
VIX
X
VDD/2, VDDQ/2
IX
X
VDD/2, VDDQ/2
X
VDD/2, VDDQ/2
VIX
VIX
X
VIX
X
CK, DQS
VIX
CK, DQS
VSS, VSSQ
CK, DQS
CK, DQS V , V
SS
SSQ
VSS, VSSQ
VSS, VSSQ
Figure 17: Single-Ended Requirements for Differential Signals
Figure17:
7: Single-Ended
Requirements
for Differential
Signals Signals
Figure
Single-Ended
Requirements
for Differential
VDD or VDDQ
VDD or VDDQ
VSEH,min
VSEH,min
VDD/2 or VDDQ/2
VDD/2 or VDDQ/2
VSEL,max
VSEH
VSEH
CK or DQS
CK or DQS
VSEL,max
VSEL
VSS or VSSQ
VSEL
VSS or VSSQ
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
PDF: 09005aef83ed2952
17
50
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
*Advanced
information. Subject–to DC
change
without
notice.
Electrical
Specifications
and
AC
tDVAC
Figure
8: Definition
of Differential
AC-Swing and
Figure
18: Definition
of Differential
AC-Swing
and tDVAC
tDVAC
VIH,diff(AC)min
VIH,diff,min
CK - CK#
DQS - DQS#
0.0
VIL,diff,max
VIL,diff(AC)max
tDVAC
Half cycle
Table
15: Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback
Table 28: DDR3L 1.35V - Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC
Ringback
Slew Rate (V/ns)
Slew Rate >4.0
(V/ns)
DDR3L-1600
DDR3L-800/1066/1333/1600
DDR3L-1866
tDVAC at 320mV (ps)
t
at 270mVt (ps)
tDVAC at
tDVAC
tDVAC at
tDVACDVAC
at
at
DVAC at
189
320mV (ps)
270mV (ps)
270mV (ps)
250mV (ps) 201 260mV (ps)
>4.0 4.0
189
201 189
163
168
201
176
4.0 3.0
3.0 2.0
189
201 162
179 109
163
168
179
176
140
147
134
154
2.0 1.8
1.8 1.6
109
95
105
119
111
91
134 91
119 69
80
91
100
97
1.6
69
100
62
74
78
40
76
37
52
76
Note1
44
5
22
Note1
Note1
Note1
Note1
1.4
1.4
1.2
1.2
1.0
<1.0
162
1.0
Note1
<1.0
Note1
40
Note1
Note1
Note1
Note1
Note1
44
Note1
Note1
55
24
Note1
Note1
1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input
signal shall become equal to or less than VIL(AC) level.
1. Rising input signal shall become equal to or greater than
VIH(AC) level and Falling input signal shall become equal to or
less than VIL(AC) level.
Note:
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
Note:
18
51
Form #: without
CSI-D-685
Document 009
Micron Technology, Inc. reserves the right to change products or specifications
notice.
© 2010 Micron Technology, Inc. All rights reserved.
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
ODT Characteristics
*Advanced information. Subject to change without notice.
ODT Characteristics
ODT Characteristics
The ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the
The ODT effective resistance RTT is defined
MR1[9,
and and•TDQS,
DQ,byDM,
DQS,6,DQS#,
balls
(x8 )/|I
devices
only).the
Thecondition
ODT target
RTT(PU)TDQS#
= (VDDQ
- VOUT
thatvalues
OUT|, under
a functional
representation
are
listed
in
Table
31
and
Table
32
(page
56).
The indi2]. ODT is applied to the DQ, DM, DQS,and
DQS#,
and TDQS,
RTT(PD) is turned off
vidual
pull-up
and
pull-down
resistors
(R
and
R
)
are
defined
as
follows:
TDQS# balls (x8 devices only). The ODT target values and a
TT(PU)
TT(PD)
• RTT(PD) = (VOUT
)/|IOUT|, under
the condition that RTT(PU)
functional representation are listed in Table
16
(page
19)
and
• RTT(PU) = (VDDQ - VOUT)/|IOUT
|, under
is turned
offthe condition that RTT(PD) is turned off
Table 17 (page 20). The individual pull-up
and =pull-down
• RTT(PD)
(VOUT)/|IOUT|, under the condition that RTT(PU) is turned off
resistors (RTT(PU) and RTT(PD)) are defined as follows:
Figure 21: ODT Levels and I-V Characteristics
Figure 9: ODT Levels and I-V
Characteristics
Chip in termination mode
ODT
VDDQ
IPU
To
other
circuitry
such as
RCV, . . .
IOUT = IPD - IPU
RTT(PU)
DQ
IOUT
RTT(PD)
VOUT
IPD
VSSQ
Table 31: On-Die Termination DC Electrical Characteristics
Table 16: On-Die
Termination DC Electrical Characteristics
Parameter/Condition
Symbol
RTT(EFF)
RTT effective impedance
Parameter/Condition
Deviation of VM with respect to Symbol ΔVM
VDDQ/2
RTT effective impedance
RTT(EFF)
Min
Min
–5
Nom
Nom
Max
See Table 32 (page 56)
Max
5 Unit
See Table 17 on page 20
Unit
Notes
1, 2
% Notes
1, 2, 3
1, 2
1. Tolerance
limits are
proper ZQ5 calibration has
ΔVM
-5 applicable after
% been performed
1, 2, 3 at a
stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to ODT Sensitivity
(page 57) if either the temperature or voltage changes after calibration.
Notes:
2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current
to pin under
measure
current
I[Vload:
1. Tolerance limits are applicable after proper ZQI[V
calibration
has apply V3.
Measure
voltagetest
(VM)and
at the
tested pin
with no
IH(AC)], then
IL(AC)
IL(AC)]:
been performed at a stable temperature and voltage (VVDDQ
IH(AC) - VIL(AC)
2 x VM
- 1 x 100
ΔVM =
TT = the
= VDD, VSSQ = VSS). Refer to ODT Sensitivity ifReither
I(VIH(AC)) - I(VIL(AC))
VDDQ
temperature or voltage changes after calibration.
3. to
Measure
voltage
at the
tested
pinthe
with
no load:
For IT
devices,
minimum
values are derated by 6% when
2. Measurement definition for RTT: Apply VIH(AC)
pin under
test (VM)4.
the device operates between -40°C and 0°C (TC).
2 × VM
and measure current I[VIH(AC)], then apply VIL(AC) to pin under
ΔVM =
– 1 × 100
VDDQ
test and measure current I[VIL(AC)]:
Deviation of VM with respect to VDDQ/2
Notes:
(
RTT =
VIH(AC) - VIL(AC)
I(VIH(AC)) - I(VIL(AC))
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
)
4. For IT and AT devices, the minimum values are derated by 6% when the device operates
between –40°C and 0°C (TC).
19
55
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
1.35V ODT Resistors
Table 17 provides an overview of the ODT DC electrical
characteristics. The values provided are not specification
requirements; however, they can be used as design guidelines
to indicate what RTT is targeted to provide:
• RTT 120Ω is made up of RTT120(PD240) and RTT120(PU240)
• RTT 60Ω is made up of RTT60(PD120) and RTT60(PU120)
• RTT 40Ω is made up of RTT40(PD80) and RTT40(PU80)
• RTT 30Ω is made up of RTT30(PD60) and RTT30(PU60)
• RTT 20Ω is made up of RTT20(PD40) and RTT20(PU40)
Table 17: 1.35V RTT Effective Impedance
Gray-shaded cells are DDR3L unique values; All other values
are the same for both DDR3L and DDR3.
MR1 [9, 6, 2]
RTT
Resistor
RTT,120PD240
0, 1, 0
120Ω
RTT,120PU240
120Ω
RTT,60PD120
0, 0, 1
60Ω
RTT,60PU120
60Ω
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
VOUT
Min
Nom
Max
Units
0.2 × VDDQ
0.6
1.0
1.15
RZQ/1
0.5 × VDDQ
0.9
1.0
1.15
RZQ/1
0.8 × VDDQ
0.9
1.0
1.45
RZQ/1
0.2 × VDDQ
0.9
1.0
1.45
RZQ/1
0.5 × VDDQ
0.9
1.0
1.15
RZQ/1
0.8 × VDDQ
0.6
1.0
1.15
RZQ/1
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/2
0.2 × VDDQ
0.6
1.0
1.15
RZQ/2
0.5 × VDDQ
0.9
1.0
1.15
RZQ/2
0.8 × VDDQ
0.9
1.0
1.45
RZQ/2
0.2 × VDDQ
0.9
1.0
1.45
RZQ/2
0.5 × VDDQ
0.9
1.0
1.15
RZQ/2
0.8 × VDDQ
0.6
1.0
1.15
RZQ/2
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/4
20
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 17: 1.35V RTT Effective Impedance (continued)
MR1 [9, 6, 2]
RTT
Resistor
RTT,40PD80
0, 1, 1
40Ω
RTT,40PU80
40Ω
RTT,30PD60
1, 0, 1
30Ω
RTT,30PU60
30Ω
RTT,20PD40
1, 0, 0
20Ω
RTT,20PU40
20Ω
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
VOUT
Min
Nom
Max
Units
0.2 × VDDQ
0.6
1.0
1.15
RZQ/3
0.5 × VDDQ
0.9
1.0
1.15
RZQ/3
0.8 × VDDQ
0.9
1.0
1.45
RZQ/3
0.2 × VDDQ
0.9
1.0
1.45
RZQ/3
0.5 × VDDQ
0.9
1.0
1.15
RZQ/3
0.8 × VDDQ
0.6
1.0
1.15
RZQ/3
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/6
0.2 × VDDQ
0.6
1.0
1.15
RZQ/4
0.5 × VDDQ
0.9
1.0
1.15
RZQ/4
0.8 × VDDQ
0.9
1.0
1.45
RZQ/4
0.2 × VDDQ
0.9
1.0
1.45
RZQ/4
0.5 × VDDQ
0.9
1.0
1.15
RZQ/4
0.8 × VDDQ
0.6
1.0
1.15
RZQ/4
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/8
0.2 × VDDQ
0.6
1.0
1.15
RZQ/6
0.5 × VDDQ
0.9
1.0
1.15
RZQ/6
0.8 × VDDQ
0.9
1.0
1.45
RZQ/6
0.2 × VDDQ
0.9
1.0
1.45
RZQ/6
0.5 × VDDQ
0.9
1.0
1.15
RZQ/6
0.8 × VDDQ
0.6
1.0
1.15
RZQ/6
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/12
21
Form #: CSI-D-685 Document 009
t
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Output Driver Impedance
The output driver impedance is selected by MR1[5,1] during
initialization. The selected value is able to maintain the tight
tolerances specified if proper ZQ calibration is performed.
2Gb: x4, x8, x16 DDR3L SDRAM
Output specifications refer to the default output driver unless
Output Driver Impedance
specifically stated otherwise. A functional representation of the
output buffer is shown below. The output driver impedance
Driver
Impedance
RON is
defined by the value of the external reference resistor
RZQ as follows:
The output driver impedance is selected by MR1[5,1] during initialization. The selected
value is able to maintain the tight tolerances specified if proper ZQ calibration is per• RON,x = RZQ/y (with RZQ = 240Ω ±1%; x = 34Ω or
formed. Output specifications refer to the default output driver unless specifically sta40Ω
y = 7 orA6,
respectively)
ted with
otherwise.
functional
representation of the output buffer is shown below. The output driver impedance RON is defined by the value of the external reference resistor RZQ
The individual pull-up and pull-down
resistors RON(PU) and
as follows:
RON(PD) are defined as follows:
• RON,x = RZQ/y (with RZQ = 240Ω x Ω or 40Ω with y = 7 or 6, respectively)
• RON(PU) = (VDDQ - VOUT)/|IOUT|, when RON(PD) is
The individual pull-up and pull-down resistors RON(PU) and RON(PD) are defined as folturned off
lows:
• RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off
• RON(PU) = (VDDQ - VOUT)/|IOUT|, when RON(PD) is turned off
• RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off
Figure 10: Output Driver
6: Output Driver
Chip in drive mode
Output driver
VDDQ
IPU
To
other
circuitry
such as
RCV, . . .
RON(PU)
DQ
RON(PD)
IPD
IOUT
VOUT
VSSQ
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
22
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
34 Ohm Output Driver Impedance
The 34Ω driver (MR1[5, 1] = 01) is the default driver. Unless
otherwise stated, all timings and specifications listed herein
apply to the 34Ω driver only. Its impedance RON is defined
by the value of the external reference resistor RZQ as follows:
RON34 = RZQ/7 (with nominal RZQ = 240Ω ±1%) and is
actually 34.3Ω ±1%.
Table 18: DDR3L 34 Ohm Driver Impedance Characteristics
Gray-shaded cells are DDR3L unique values; All other values are the same for both DDR3L and DDR3.
MR1 [5, 1]
RTT
Resistor
RON,34PD
0, 1
34.3Ω
RON,34PU
Pull-up/pull-down mismatch (MMPUPD)
VOUT
Min
Nom
Max
Units
0.2 × VDDQ
0.6
1.0
1.15
RZQ/7
0.5 × VDDQ
0.9
1.0
1.15
RZQ/7
0.8 × VDDQ
0.9
1.0
1.45
RZQ/7
0.2 × VDDQ
0.9
1.0
1.45
RZQ/7
0.5 × VDDQ
0.9
1.0
1.15
RZQ/7
0.8 × VDDQ
0.6
1.0
1.15
RZQ/7
VIL(AC) to VIH(AC)
-10
NA
10
%
Notes:
1. Tolerance limits assume RZQ of 240Ω ±1% and are applicable
after proper ZQ calibration has been performed at a stable
temperature and voltage: VDDQ = VDD; VSSQ = VSS).
2. Measurement definition for mismatch between pull-up and
pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at
0.5 × VDDQ:
MMPUPD =
RON(PU) - RON(PD)
RON,nom
x 100
3. For IT and AT (1Gb only) devices, the minimum values are
derated by 6% when the device operates between –40°C and
0°C (TC). A larger maximum limit will result in slightly lower
minimum currents.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
23
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 19: DDR3L-1600 Speed Bins
-1251
DDR3L-1600 Speed Bin
CL-tRCD-tRP
Units
11-11-11
Parameter
Notes
Symbol
Min
Max
tAA
13.75
–
ns
tRCD
13.75
–
ns
PRECHARGE command period
tRP
13.75
–
ns
ACTIVATE-to-ACTIVATE or REFRESH command period
tRC
48.75
–
ns
ACTIVATE-to-PRECHARGE command period
tRAS
35
9 x tREFI
ns
2
3.0
3.3
ns
3
ns
4
ns
3
Internal READ command to first data
ACTIVATE to internal READ or WRITE delay time
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
CWL = 5
tCK
(AVG)
CWL = 6, 7, 8
tCK
(AVG)
CWL = 5
tCK
(AVG)
CWL = 6
tCK
(AVG)
Reserved
ns
4
CWL = 7, 8
tCK
(AVG)
Reserved
ns
4
CWL = 5
tCK
(AVG)
Reserved
ns
4
CWL = 6
tCK
(AVG)
ns
3
CWL = 7
tCK
(AVG)
Reserved
ns
4
CWL = 8
tCK
(AVG)
Reserved
ns
4
CWL = 5
tCK
(AVG)
Reserved
ns
4
CWL = 6
tCK
(AVG)
ns
3
CWL = 7
tCK
(AVG)
Reserved
ns
4
CWL = 8
tCK
(AVG)
Reserved
ns
4
CWL = 5, 6
tCK
(AVG)
Reserved
ns
4
CWL = 7
tCK
(AVG)
ns
3
CWL = 8
tCK
(AVG)
Reserved
ns
4
CWL = 5, 6
tCK
(AVG)
Reserved
ns
4
CWL = 7
tCK
(AVG)
ns
3
CWL = 8
tCK
(AVG)
Reserved
ns
4
CWL = 5, 6, 7
tCK
(AVG)
Reserved
ns
4
CWL = 8
tCK
(AVG)
ns
3
Reserved
2.5
3.3
1.875
<2.5
1.875
<2.5
1.5
<1.875
1.5
<1.875
1.25
Supported CL settings
Supported CWL settings
<1.5
5, 6, 7, 8, 9, 10
CK
5, 6, 7, 8
CK
Notes:
making a selection of tCK, both CL and CWL requirement
settings need to be fulfilled.
4. Reserved settings are not allowed.
1. The -125 speed grade is backward compatible with 1333, CL
= 9 (-15E) and 1066, CL = 7 (-187E).
2. tREFI depends on TOPER.
3. The CL and CWL settings result in tCK requirements. When
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
24
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Electrical Characteristics and AC Operating Conditions
Table 20: Electrical Characteristics and AC Operating Conditions
Note 1 below applies to base timing specifications; for additional specifications see the DDR3 Electrical Characteristics and AC
Operating Condition Tables and Notes.
Parameter
DDR3L-1600
Symbol
Units
Min
Max
N/A
–
ps
N/A
–
ps
25
–
ps
160
–
ps
55
–
ps
145
–
ps
N/A
–
ps
N/A
–
ps
N/A
–
ps
N/A
–
ps
60
–
ps
220
–
ps
185
–
ps
320
–
ps
N/A
–
ps
N/A
–
ps
130
–
ps
220
–
ps
DQ Input Timing
Data setup time to DQS, DQS#
Data setup time to DQS, DQS#
Data hold time from DQS, DQS#
Data setup time to DQS, DQS#
Data hold time from DQS, DQS#
Base (specification)
tDS
(AC160)
VREF @ 1 V/ns
Base (specification)
tDS
(AC135)
VREF @ 1 V/ns
Base (specification)
tDH
(DC90)
VREF @ 1 V/ns
Base (specification)
tDS
(AC130)
VREF @ 2 V/ns
Base (specification)
tDH
(DC90)
VREF @ 2 V/ns
Command and Address Timing
CTRL, CMD, ADDR setup to CK, CK#
CTRL, CMD, ADDR setup to CK, CK#
CTRL, CMD, ADDR setup to CK, CK#
CTRL, CMD, ADDR hold from CK, CK#
Base (specification)
tIS
(AC160)
VREF @ 1 V/ns
Base (specification)
tIS
(AC135)
VREF @ 1 V/ns
Base (specification)
tIS
(AC125)
VREF @ 1 V/ns
Base (specification)
tIH
(DC90)
VREF @ 1 V/ns
Notes:
1. When two VIH(AC) values (and two corresponding VIL(AC)
values) are listed for a specific speed bin, the user may choose
either value for the nput AC level. Whichever value is used,
the associated setup time for that AC level must also be
used. Additionally, one VIH(AC) value may be used for address/
command inputs and the other VIH(AC) value may be used for
data inputs. For example, for DDR3-800, two input AC levels
are defined: VIH(AC160),min and VIH(AC135),min (corresponding
VIL(AC160),min and VIL(AC135),min). For DDR3-800, the
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
address/command inputs must use either VIH(AC160),min
with tIS(AC160) of 215ps or VIH(AC135),min with tIS(AC135)
of 365ps; independently, the data inputs must use either
VIH(AC160),min with tDS(AC160) of 90ps or VIH(AC135),min with
tDS(AC135) of 140ps.
2. When DQ single-ended slew rate is 1V/ns, the DQS differential
slew rate is 2V/ns; when DQ single-ended slew rate is 2V/ns,
the DQS differential slew rate is 4V/ns.
25
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 21: Electrical Characteristics and AC Operating Conditions
Notes 1-8 apply to the entire table.
Parameter
DDR3L-1600
Symbol
Units
Notes
7800
ns
9, 42
3900
ns
42
ns
10, 11
Min
Max
8
8
Clock Timing
TC ≤ 85°C
Clock period average:
DLL disable mode
TC = >85°C to 95°C
tCK
(DLL_DIS)
Clock period average: DLL enable mode
tCK
(AVG)
High pulse width average
tCH
(AVG)
0.47
0.53
CK
12
Low pulse width average
tCL
(AVG)
0.47
0.53
CK
12
Clock period jitter
See Table 19 on page 24 for tCK range allowed
DLL locked
tJITper
–70
70
ps
13
DLL locking
tJITper,lck
–60
60
ps
13
ps
Clock absolute period
tCK
(ABS)
MIN = tCK (AVG) MIN + tJITper MIN
MAX = tCK (AVG) MAX + tJITper MAX
Clock absolute high pulse width
tCH
(ABS)
0.43
–
tCK
(AVG)
14
Clock absolute low pulse width
tCL
(ABS)
0.43
–
tCK
(AVG)
15
Cycle-to-cycle jitter
Cumulative error
across
DLL locked
tJITcc
140
ps
16
DLL locking
tJITcc,lck
120
ps
16
2 cycles
tERR2per
–103
103
ps
17
3 cycles
tERR3per
–122
122
ps
17
4 cycles
tERR4per
–136
136
ps
17
5 cycles
tERR5per
–147
147
ps
17
6 cycles
tERR6per
–155
155
ps
17
7 cycles
tERR7per
–163
163
ps
17
8 cycles
tERR8per
–169
169
ps
17
9 cycles
tERR9per
–175
175
ps
17
10 cycles
tERR10per
–180
180
ps
17
11 cycles
tERR11per
–184
184
ps
17
12 cycles
tERR12per
–188
188
ps
17
ps
17
n = 13, 14 . . . 49, 50 cycles
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
tERRnper
tERRnper
tERRnper
MIN = (1 + 0.68ln[n]) × tJITper MIN;
MAX = (1 + 0.68ln[n]) × tJITper MAX
26
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Parameter
DDR3L-1600
Symbol
Units
Notes
–
ps
18, 19, 44
–
–
ps
19, 20
10
–
ps
18, 19, 44
160
–
ps
19, 20
–
–
ps
18, 19
–
–
ps
19, 20
45
–
ps
18, 19
145
–
ps
19, 20
360
–
ps
41
tDQSQ
–
100
ps
tQH
0.38
–
DQ Low-Z time from CK, CK#
tLZDQ
–450
225
ps
22, 23
DQ High-Z time from CK, CK#
tHZDQ
–
225
ps
22, 23
25
Min
Max
–
DQ Input Timing
Data setup time to
DQS, DQS#
Base (specification)
Data setup time to
DQS, DQS#
Base (specification)
Data setup time to
DQS, DQS#
Base (specification)
Data hold time from
DQS, DQS#
Base (specification)
VREF @ 1 V/ns
VREF @ 1 V/ns
VREF @ 1 V/ns
VREF @ 1 V/ns
Minimum data pulse width
tDS
(AC175)
tDS
(AC150)
tDS
(AC135)
tDH
(DC100)
tDIPW
DQ Output Timing
DQS, DQS# to DQ skew, per access
DQ output hold time from DQS, DQS#
tCK
(AVG)
21
DQ Strobe Input Timing
DQS, DQS# rising to CK, CK# rising
tDQSS
–0.27
0.27
CK
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
CK
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
CK
DQS, DQS# falling setup to CK, CK# rising
tDSS
0.18
–
CK
25
DQS, DQS# falling hold from CK, CK# rising
tDSH
0.18
–
CK
25
DQS, DQS# differential WRITE preamble
tWPRE
0.9
–
CK
DQS, DQS# differential WRITE postamble
tWPST
0.3
–
CK
–225
225
ps
23
1
10
ns
26
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK#
DQS, DQS# rising to/from rising CK, CK# when DLL
is disabled
tDQSCK
tDQSCK
(DLL_DIS)
DQS, DQS# differential output high time
tQSH
0.40
–
CK
21
DQS, DQS# differential output low time
tQSL
0.40
–
CK
21
DQS, DQS# Low-Z time (RL - 1)
tLZDQS
–450
225
ps
22, 23
DQS, DQS# High-Z time (RL + BL/2)
tHZDQS
–
225
ps
22, 23
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
27
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Parameter
DDR3L-1600
Symbol
Min
Max
Units
Notes
DQ Strobe Output Timing (continued)
DQS, DQS# differential READ preamble
tRPRE
0.9
Note 24
CK
23, 24
DQS, DQS# differential READ postamble
tRPST
0.3
Note 27
CK
23, 27
DQS, DQS# differential output low time
tQSL
0.40
–
CK
21
DQS, DQS# Low-Z time (RL - 1)
tLZDQS
–450
225
ps
22, 23
DQS, DQS# High-Z time (RL + BL/2)
tHZDQS
–
225
ps
22, 23
DQS, DQS# differential READ preamble
tRPRE
0.9
Note 24
CK
23, 24
DQS, DQS# differential READ postamble
tRPST
0.3
Note 27
CK
23, 27
512
–
CK
28
45
–
ps
29, 30, 44
220
–
ps
20, 30
170
–
ps
29, 30, 44
320
–
ps
20, 30
120
–
ps
29, 30
220
–
ps
20, 30
560
–
ps
41
Command and Address Timing
tDLLK
DLL locking time
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
CTRL, CMD, ADDR
hold from CK,CK#
Base (specification)
tIS
(AC175)
VREF @ 1 V/ns
tIS
(AC150)
VREF @ 1 V/ns
tIH
(DC100)
VREF @ 1 V/ns
Minimum CTRL, CMD, ADDR pulse width
tIPW
ACTIVATE to internal READ or WRITE delay
tRCD
See Speed Bin Tables (page 24) for tRCD
ns
31
tRP
See Speed Bin Tables (page 24) for tRP
ns
31
ACTIVATE-to-PRECHARGE command period
tRAS
See Speed Bin Tables (page 24) for tRAS
ns
31, 32
ACTIVATE-to-ACTIVATE command period
tRC
See Speed Bin Tables (page 24) for tRC
ns
31, 43
MIN = greater of 4CK or 6ns
CK
31
CK
31
PRECHARGE command period
ACTIVATE-toACTIVATE minimum
command period
x4/x8 (1KB page size)
Four ACTIVATE
windows
x4/x8 (1KB page size)
x16 (2KB page size)
x16 (2KB page size)
tRRD
tFAW
30
–
ns
31
40
–
ns
31
Write recovery time
tWR
MIN = 15ns; MAX = N/A
ns
31, 32,
33,34
Delay from start of internal WRITE transaction to
internal READ command
tWTR
MIN = greater of 4CK or 7.5ns; MAX = N/A
CK
31, 34
READ-to-PRECHARGE time
tRTP
MIN = greater of 4CK or 7.5ns; MAX = N/A
CK
31, 32
CAS#-to-CAS# command delay
tCCD
MIN = 4CK; MAX = N/A
CK
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
28
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Parameter
DDR3L-1600
Symbol
Min
Max
Units
Notes
Command and Address Timing (continued)
Auto precharge write recovery + precharge time
tDAL
MIN = WR + tRP/tCK (AVG); MAX = N/A
CK
MODE REGISTER SET command cycle time
tMRD
MIN = 4CK; MAX = N/A
CK
MODE REGISTER SET command update delay
tMOD
MIN = greater of 12CK or 15ns; MAX = N/A
CK
MULTIPURPOSE REGISTER READ burst end to mode
register set for multipurpose register exit
tMPRR
MIN = 1CK; MAX = N/A
CK
CAS#-to-CAS# command delay
tCCD
MIN = 4CK; MAX = N/A
CK
Auto precharge write recovery + precharge time
tDAL
MIN = WR + tRP/tCK (AVG); MAX = N/A
CK
MODE REGISTER SET command cycle time
tMRD
MIN = 4CK; MAX = N/A
CK
MODE REGISTER SET command update delay
tMOD
MIN = greater of 12CK or 15ns; MAX = N/A
CK
MULTIPURPOSE REGISTER READ burst end to mode
register set for multipurpose register exit
tMPRR
MIN = 1CK; MAX = N/A
CK
Calibration Timing
POWER-UP and RE- SET
ZQCL command: Long operation
calibration time
Normal operation
ZQCS command: Short calibration time
tZQinit
512
–
CK
tZQoper
256
–
CK
tZQCS
64
–
CK
Initialization and Reset Timing
tXPR
MIN = greater of 5CK or tRFC + 10ns; MAX = N/A
CK
tVDDPR
MIN = N/A; MAX = 200
ms
RESET# LOW to power supplies stable
tRPS
MIN = 0; MAX = 200
ms
RESET# LOW to I/O and RTT High-Z
tIOZ
MIN = N/A; MAX = 20
ns
Exit reset from CKE HIGH to a valid command
Begin power supply ramp to power supplies stable
35
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH
command period
tRFC
– 1Gb
MIN = 110; MAX = 70,200
ns
tRFC
– 2Gb
MIN = 160; MAX = 70,200
ns
tRFC
– 4Gb
MIN = 260; MAX = 70,200
ns
tRFC
– 8Gb
MIN = 350; MAX = 70,200
ns
Self Refresh Timing
Exit self refresh to commands not requiring a locked
DLL
tXS
MIN = greater of 5CK or tRFC + 10ns; MAX = N/A
CK
Exit self refresh to commands requiring a locked DLL
tXSDLL
MIN = tDLLK (MIN); MAX = N/A
CK
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
28
29
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Parameter
DDR3L-1600
Symbol
Min
Max
Units
Notes
Self Refresh Timing (continued)
Minimum CKE low pulse width for self re-fresh entry
to self refresh exit timing
tCKESR
MIN = tCKE (MIN) + CK; MAX = N/A
CK
Valid clocks after self refresh entry or power- down
entry
tCKSRE
MIN = greater of 5CK or 10ns; MAX = N/A
CK
Valid clocks before self refresh exit, power-down exit,
or reset exit
tCKSRX
MIN = greater of 5CK or 10ns; MAX = N/A
CK
Power-Down Timing
tCKE
CKE MIN pulse width
Greater of 3CK or 5ns
CK
tCPDED
MIN = 1; MAX = N/A
CK
tPD
MIN = tCKE (MIN); MAX = 9 × tREFI
CK
tANPD
WL - 1CK
CK
Power-down entry period: ODT either synchronous or
asynchronous
PDE
Greater of tANPD or tRFC - REFRESH command to CKE LOW time
CK
Power-down exit period: ODT either synchronous or
asynchronous
PDX
Command pass disable delay
Power-down entry to power-down exit timing
Begin power-down period prior to CKE registered
HIGH
(MIN)
tANPD
+ tXPDLL
CK
Power-Down Entry Minimum Timing
tACTPDEN
MIN = 1
CK
PRECHARGE/PRECHARGE ALL command to powerdown entry
tPRPDEN
MIN = 1
CK
REFRESH command to power-down entry
tREFPDEN
MIN = 1
CK
MRS command to power-down entry
tMRSPDEN
MIN = tMOD (MIN)
CK
tRDPDEN
MIN = RL + 4 + 1
CK
ACTIVATE command to power-down entry
READ/READ with auto precharge command to powerdown entry
WRITE command to
power-down entry
BL8 (OTF, MRS) BC4OTF
tWRPDEN
MIN = WL + 4 + tWR/tCK (AVG)
CK
BC4MRS
tWRPDEN
MIN = WL + 2 + tWR/tCK (AVG)
CK
WRITE with auto
precharge command
to power-down entry
BL8 (OTF, MRS) BC4OTF
tWRAP-
DEN
MIN = WL + 4 + WR + 1
CK
BC4MRS
tWRAP-
DEN
MIN = WL + 2 + WR + 1
CK
tXP
MIN = greater of 3CK or 6ns; MAX = N/A
CK
tXPDLL
MIN = greater of 10CK or 24ns; MAX = N/A
CK
37
Power-Down Exit Timing
DLL on, any valid command, or DLL off to commands
not requiring locked DLL
Precharge power-down with DLL off to commands
requiring a locked DLL
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
28
30
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Parameter
DDR3L-1600
Symbol
Min
Max
Units
Notes
ODT Timing
RTT synchronous turn-on delay
ODTLon
CWL + AL - 2CK
CK
38
RTT synchronous turn-off delay
ODTLoff
CWL + AL - 2CK
CK
40
RTT turn-on from ODTL on reference
tAON
–225
225
ps
23, 38
RTT turn-off from ODTL off reference
tAOF
0.3
0.7
CK
39, 40
Asynchronous RTT turn-on delay (power-down with
DLL off)
tAONPD
MIN = 2; MAX = 8.5
ns
38
Asynchronous RTT turn-off delay (power-down with
DLL off)
tAOFPD
MIN = 2; MAX = 8.5
ns
40
ODT HIGH time with WRITE command and BL8
ODTH8
MIN = 6; MAX = N/A
CK
ODT HIGH time without WRITE command or with
WRITE command and BC4
ODTH4
MIN = 4; MAX = N/A
CK
Dynamic ODT Timing
RTT,nom-to-RTT(WR) change skew
ODTLcnw
WL - 2CK
CK
RTT(WR)-to-RTT,nom change skew - BC4
ODTLcwn4
4CK + ODTLoff
CK
RTT(WR)-to-RTT,nom change skew - BL8
ODTLcwn8
6CK + ODTLoff
CK
RTT dynamic change skew
tADC
0.3
0.7
CK
39
Write Leveling Timing
tWLMRD
40
–
CK
tWLDQSEN
25
–
CK
Write leveling setup from rising CK, CK# crossing to
rising DQS, DQS# crossing
tWLS
165
–
ps
Write leveling hold from rising DQS, DQS# crossing
to rising CK, CK# crossing
tWLH
165
–
ps
Write leveling output delay
tWLO
0
7.5
ns
Write leveling output error
tWLOE
0
2
ns
First DQS, DQS# rising edge
DQS, DQS# delay
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
31
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 21: Electrical Characteristics and AC Operating Conditions (continued)
Notes:
however, the spread spectrum may not use a clock rate below
tCK (AVG) MIN.
1. AC timing parameters are valid from specified TC MIN to TC
MAX values.
12. The clock’s tCH (AVG) and tCL (AVG) are the average half
clock period over any 200 consecutive clocks and is the
smallest clock half period allowed, with the exception of
a deviation due to clock jitter. Input clock jitter is allowed
provided it does not exceed values specified and must be of a
random Gaussian distribution in nature.
2. All voltages are referenced to VSS.
3. Output timings are only valid for RON34 output buffer selection.
4. The unit tCK (AVG) represents the actual tCK (AVG) of the input
clock under operation. The unit CK represents one clock cycle
of the input clock, counting the actual clock edges.
13. The period jitter (tJITper) is the maximum deviation in the clock
period from the average or nominal clock. It is allowed in either
the positive or negative direction.
5. AC timing and IDD tests may use a VIL-to-VIH swing of up
to 900mV in the test environment, but input timing is still
referenced to VREF (except tIS, tIH, tDS, and tDH use the
AC/DC trip points and CK, CK# and DQS, DQS# use their
crossing points). The minimum slew rate for the input signals
used to test the device is 1 V/ns for single-ended inputs and
2 V/ns for differential inputs in the range between VIL(AC) and
VIH(AC).
14. tCH (ABS) is the absolute instantaneous clock high pulse width
as measured from one rising edge to the following falling edge.
15. tCL (ABS) is the absolute instantaneous clock low pulse width
as measured from one falling edge to the following rising edge.
16. The cycle-to-cycle jitter tJITcc is the amount the clock period
can deviate from one cycle to the next. It is important to keep
cycle-to-cycle jitter at a minimum during the DLL locking time.
6. All timings that use time-based values (ns, μs, ms) should
use tCK (AVG) to determine the correct number of clocks
(see Table 21 on page 26) uses CK or tCK [AVG]
interchangeably). In the case of noninteger results, all minimum
limits are to be rounded up to the nearest whole integer, and
all maximum limits are to be rounded down to the nearest
whole integer.
17. The cumulative jitter error tERRnper, where n is the number of
clocks between 2 and 50, is the amount of clock time allowed
to accumulate consecutively away from the average clock over
n number of clock cycles.
18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns
slew rate DQs and 2 V/ns slew rate differential DQS, DQS#.
7. Strobe or DQSdiff refers to the DQS and DQS# differential
crossing point when DQS is the rising edge. Clock or CK
refers to the CK and CK# differential crossing point when CK
is the rising edge.
19. These parameters are measured from a data signal (DM, DQ0,
DQ1, and so forth) transition edge to its respective data strobe
signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base
specification values (to which derating tables apply) to VREF
when the slew rate is 1 V/ns. These values, with a slew rate of
1 V/ns, are for reference only.
8. This output load is used for all AC timing (except ODT
reference timing) and slew rates. The actual test load may be
different. The output signal voltage reference point is VDDQ/2
for single-ended signals and the crossing point for differential
signals.
21. When the device is operated with input clock jitter, this
parameter needs to be derated by the actual tJITper (larger
of tJITper (MIN) or tJITper (MAX) of the input clock (output
deratings are relative to the SDRAM input clock).
9. When operating in DLL disable mode, Micron does not
warrant compliance with normal mode timings or functionality.
10. The clock’s tCK (AVG) is the average clock over any 200
consecutive clocks and tCK (AVG) MIN is the smallest
clock rate allowed, with the exception of a deviation due to
clock jitter. Input clock jitter is allowed provided it does not
exceed values specified and must be of a random Gaussian
distribution in nature.
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average
clock. Most output parameters must be derated by the
actual jitter error when input clock jitter is present, even when
within specification. This results in each parameter becoming
larger. The following parameters are required to be derated
by subtracting tERR10per (MAX): tDQSCK (MIN), tLZDQS
(MIN), tLZDQ (MIN), and tAON (MIN). The following parameters
are required to be derated by subtracting tERR10per (MIN):
11. Spread spectrum is not included in the jitter specification
values. However, the input clock can accommodate spreadspectrum at a sweep rate in the range of 20–60 kHz with an
additional 1% of tCK (AVG) as a long-term jitter component;
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
32
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 21: Electrical Characteristics and AC Operating Conditions (continued)
tDQSCK
(MAX), tHZ (MAX), tLZDQS (MAX), tLZDQ MAX,
and tAON (MAX). The parameter tRPRE (MIN) is derated by
subtracting tJITper (MAX), while tRPRE (MAX) is derated by
subtracting tJITper (MIN).
ƒƒ For BL8 (fixed by MRS or OTF): Rising clock edge four
clock cycles after WL
ƒƒ For BC4 (OTF): Rising clock edge four clock cycles
after WL
ƒƒ For BC4 (fixed by MRS): Rising clock edge two clock
cycles after WL
35. RESET# should be LOW as soon as power starts to ramp
to ensure the outputs are in High-Z. Until RESET# is LOW,
the outputs are at risk of driving and could result in excessive
current, depending on bus activity.
24. The maximum preamble is bound by tLZDQS (MAX).
25. These parameters are measured from a data strobe signal
(DQS, DQS#) crossing to its respective clock signal (CK, CK#)
crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock
signal crossing. These parameters should be met whether
clock jitter is present.
36. The refresh period is 64ms when TC is less than or equal to
85°C. This equates to an average refresh rate of 7.8125μs.
However, nine REFRESH commands should be asserted at
least once every 70.3μs. When TC is greater than 85°C, the
refresh period is 32ms.
tDQSCK
26. The
(DLL_DIS) parameter begins CL + AL - 1 cycles
after the READ command.
27. The maximum postamble is bound by tHZDQS (MAX).
28. Commands requiring a locked DLL are: READ (and RDAP)
and synchronous ODT commands. In addition, after any
change of latency tXPDLL, timing must be met.
37. Although CKE is allowed to be registered LOW after a
REFRESH command when tREFPDEN (MIN) is satisfied,
there are cases where additional time such as tXPDLL (MIN) is
required.
29. tIS (base) and tIH (base) values are for a single-ended
1 V/ns control/command/address slew rate and 2 V/ns CK,
CK# differential slew rate.
38. ODT turn-on time MIN is when the device leaves High-Z and
ODT resistance begins to turn on. ODT turn-on time maximum
is when the ODT resistance is fully on. Designs that were
created prior to JEDEC tightening the maximum limit from 9ns
to 8.5ns will be allowed to have a 9ns maximum.
30. These parameters are measured from a command/address
signal transition edge to its respective clock (CK, CK#) signal
crossing. The specification values are not affected by the
amount of clock jitter applied as the setup and hold times are
relative to the clock signal crossing that latches the command/
address. These parameters should be met whether clock jitter
is present.
39. Half-clock output parameters must be derated by the actual
tERR10per and tJITdty when input clock jitter is present. This
results in each parameter becoming larger. The parameters
tADC (MIN) and tAOF (MIN) are each required to be derated
by subtracting both tERR10per (MAX) and tJITdty (MAX). The
parameters tADC (MAX) and tAOF (MAX) are required to be
derated by subtracting both tERR10per (MAX) and tJITdty
(MAX).
31. For these parameters, the DDR3 SDRAM device supports
tnPARAM (nCK) = RU(tPARAM [ns]/tCK[AVG] [ns]), assuming
all input clock jitter specifications are satisfied. For example,
the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all
input clock jitter specifications are met. This means that for
DDR3-800 6-6-6, of which tRP = 5ns, the device will support
tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter
specifications are met. That is, the PRECHARGE command at
T0 and the ACTIVATE command at T0 + 6 are valid even if six
clocks are less than 15ns due to input clock jitter.
40. ODT turn-off time minimum is when the device starts to turn
off ODT resistance. ODT turn-off time maximum is when the
DRAM buffer is in High-Z.
41. Pulse width of a input signal is defined as the width between
the first crossing of VREF(DC) and the consecutive crossing of
VREF(DC).
32. During READs and WRITEs with auto precharge, the DDR3
SDRAM will hold off the internal PRECHARGE command until
tRAS (MIN) has been satisfied.
42. Should the clock rate be larger than tRFC (MIN), an AUTO
REFRESH command should have at least one NOP command
between it and another AUTO REFRESH command.
Additionally, if the clock rate is slower than 40ns (25 MHz), all
REFRESH commands should be followed by a PRECHARGE
ALL command.
33. When operating in DLL disable mode, the greater of 4CK or
15ns is satisfied for tWR.
34. The start of the write recovery time is defined as follows:
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
33
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 21: Electrical Characteristics and AC Operating Conditions (continued)
43. DRAM devices should be evenly addressed when being
accessed. Disproportionate accesses to a particular row
address may result in a reduction of REFRESH characteristics
or product lifetime.
44. When two VIH(AC) values (and two corresponding VIL(AC)
values) are listed for a specific speed bin, the user may choose
either value for the input AC level. Whichever value is used,
the associated setup time for that AC level must also be
used. Additionally, one VIH(AC) value may be used for address/
command inputs and the other VIH(AC) value may be used for
data inputs. For example, for DDR3-800, two input AC levels
are defined: VIH(AC175),min and VIH(AC150),min (corresponding
VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/
command inputs must use either VIH(AC175),min with
tIS(AC175) of 200ps or VIH(AC150),min with tIS(AC150) of 350ps;
independently, the data inputs must use either VIH(AC175),min
with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of
125ps.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
34
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Commands - Truth Tables
Table 22: Truth Table - Command
Notes 1-5 apply to the entire table.
CKE
Symbol
Prev.
Cycle
Next
Cycle
CS#
RAS#
CAS#
WE#
BA
[2:0]
MODE REGISTER SET
MRS
H
H
L
L
L
L
BA
REFRESH
REF
H
H
L
L
L
H
V
V
V
V
V
Self refresh entry
SRE
H
L
L
L
L
H
V
V
V
V
V
6
Self refresh exit
SRX
L
H
H
V
V
V
L
H
H
H
V
V
V
V
V
6, 7
Single-bank PRECHARGE
PRE
H
H
L
L
H
L
BA
V
V
L
V
PRECHARGE all banks
PREA
H
H
L
L
H
L
V
V
H
V
Bank ACTIVATE
ACT
H
H
L
L
H
H
BA
WR
H
H
L
H
L
L
BA
RFU
V
L
CA
8
BC4OTF
WRS4
H
H
L
H
L
L
BA
RFU
L
L
CA
8
BL8OTF
WRS8
H
H
L
H
L
L
BA
RFU
H
L
CA
8
BL8MRS, BC4MRS
WRAP
H
H
L
H
L
L
BA
RFU
V
H
CA
8
BC4OTF
WRAPS4
H
H
L
H
L
L
BA
RFU
L
H
CA
8
BL8OTF
WRAPS8
H
H
L
H
L
L
BA
RFU
H
H
CA
8
RD
H
H
L
H
L
H
BA
RFU
V
L
CA
8
BC4OTF
RDS4
H
H
L
H
L
H
BA
RFU
L
L
CA
8
BL8OTF
RDS8
H
H
L
H
L
H
BA
RFU
H
L
CA
8
BL8MRS, BC4MRS
RDAP
H
H
L
H
L
H
BA
RFU
V
H
CA
8
BC4OTF
RDAPS4
H
H
L
H
L
H
BA
RFU
L
H
CA
8
BL8OTF
RDAPS8
H
H
L
H
L
H
BA
RFU
H
H
CA
8
NO OPERATION
NOP
H
H
H
H
H
V
V
V
V
V
9
Device DESELECTED
DES
H
H
H
X
X
X
X
X
X
X
X
10
Power-down entry
PDE
H
L
L
H
H
H
H
V
V
V
V
V
V
V
V
6
Power-down exit
PDX
L
H
L
H
H
H
H
V
V
V
V
V
V
V
V
6, 11
ZQ CALIBRATION LONG
ZQCL
H
H
L
H
H
L
X
X
X
H
X
12
ZQ CALIBRATION SHORT
ZQCS
H
H
L
H
H
L
X
X
X
L
X
Functions
BL8MRS, BC4MRS
WRITE
WRITE with auto
precharge
BL8MRS, BC4MRS
READ
READ with auto
precharge
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
An
A12
A[11,
9:0]
A10
Notes
OP code
Row address (RA)
35
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 22: Truth Table - Command (continued)
Notes:
1. Commands are defined by the states of CS#, RAS#, CAS#,
WE#, and CKE at the rising edge of the clock. The MSB
of BA, RA, and CA are device-, density-, and configuration
dependent.
2. RESET# is enabled LOW and used only for asynchronous
reset. Thus, RESET# must be held HIGH during any normal
operation.
3. The state of ODT does not affect the states described in this
table.
4. Operations apply to the bank defined by the bank address.
For MRS, BA selects one of four mode registers.
5. “V” means “H” or “L” (a defined logic level), and “X” means
“Don’t Care.”
6. See Table 23 (page 37) for additional information on CKE
transition.
7. Self refresh exit is asynchronous.
8. Burst READs or WRITEs cannot be terminated or interrupted.
MRS (fixed) and OTF BL/BC are defined in MR0.
9. The purpose of the NOP command is to prevent the DRAM
from registering any unwanted commands. A NOP will not
terminate an operation that is executing.
10. The DES and NOP commands perform similarly.
11. The power-down mode does not perform any REFRESH
operations.
12. ZQ CALIBRATION LONG is used for either ZQinit (first ZQCL
command during initialization) or ZQoper (ZQCL command
after initialization).
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
36
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 23: Truth Table - CKE
Notes 1 and 2 apply to the entire table.
CKE
Command5
(RAS#, CAS#, WE#, CS#)
Action5
L
“Don’t Care”
Maintain power-down
L
H
DES or NOP
Power-down exit
L
L
“Don’t Care”
Maintain self refresh
L
H
DES or NOP
Self refresh exit
Bank(s) active
H
L
DES or NOP
Active power-down entry
Reading
H
L
DES or NOP
Power-down entry
Writing
H
L
DES or NOP
Power-down entry
Precharging
H
L
DES or NOP
Power-down entry
Refreshing
H
L
DES or NOP
Precharge power-down entry
H
L
DES or NOP
Precharge power-down entry
H
L
REFRESH
Self refresh
Current State3
Power-down
Self-refresh
All banks idle
Previous Cycle4
(n - 1)
Present Cycle4
(n - 1)
L
Notes
6
Notes:
1. All states and sequences not shown are illegal or reserved
unless explicitly described elsewhere in this document.
2. tCKE (MIN) means CKE must be registered at multiple
consecutive positive clock edges. CKE must remain at the
valid input level the entire time it takes to achieve the required
number of registration clocks. Thus, after any CKE transition,
CKE may not transition from its valid level during the time
period of tIS + tCKE (MIN) + tIH.
3. Current state = The state of the DRAM immediately prior to
clock edge n.
4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1)
was the state of CKE at the previous clock edge.
5. COMMAND is the command registered at the clock edge
(must be a legal command as defined in Table 22 (page
35)). Action is a result of COMMAND. ODT does not affect
the states described in this table and is not listed.
6. Idle state = All banks are closed, no data bursts are in
progress, CKE is HIGH, and all timings from previous
operations are satisfied. All self refresh exit and power-down
exit parameters are also satisfied.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
37
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
ACTIVATE
Commands
The ACTIVATE command is used to open (or activate) a row
in a particular bank for a subsequent access. The value on the
BA[2:0] inputs selects the bank, and the address provided on
inputs A[n:0] selects the row. This row remains open (or active)
for accesses until a PRECHARGE command is issued to that
bank.
DESELECT
The DESELT (DES) command (CS# HIGH) prevents new
commands from being executed by the DRAM. Operations
already in progress are not affected.
NO OPERATION
A PRECHARGE command must be issued before opening a
different row in the same bank.
The NO OPERATION (NOP) command (CS# LOW) prevents
unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
ZQ CALIBRATION LONG
The ZQ CALIBRATION LONG (ZQCL) command is used to
perform the initial calibration during a power-up initialization and
reset sequence (see Figure 19 (page 54)). This command
may be issued at any time by the controller, depending
on the system environment. The ZQCL command triggers
the calibration engine inside the DRAM. After calibration
is achieved, the calibrated values are transferred from the
calibration engine to the DRAM I/O, which are reflected as
updated RON and ODT values.
The DRAM is allowed a timing window defined by either tZQinit
or tZQoper to perform a full calibration and transfer of values.
When ZQCL is issued during the initialization sequence, the
timing parameter tZQinit must be satisfied. When initialization
is complete, subsequent ZQCL commands require the timing
parameter tZQoper to be satisfied.
ZQ CALIBRATION SHORT
The ZQ CALIBRATION SHORT (ZQCS) command is used to
perform periodic calibrations to account for small voltage and
temperature variations. A shorter timing window is provided to
perform the reduced calibration and transfer of values as defined
by timing parameter tZQCS. A ZQCS command can effectively
correct a minimum of 0.5% RON and RTT impedance error
within 64 clock cycles, assuming the maximum sensitivities
specified in DDR3L 34 Ohm Output Driver Sensitivity.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
38
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
READ
The READ command is used to initiate a burst read access to
an active row. The address provided on inputs A[2:0] selects
the starting column address, depending on the burst length
and burst type selected (see Burst Order table for additional
information). The value on input A10 determines whether auto
precharge is used. If auto precharge is selected, the row being
accessed will be precharged at the end of the READ burst. If
auto precharge is not selected, the row will remain open for
subsequent accesses. The value on input A12 (if enabled in the
mode register) when the READ command is issued determines
whether BC4 (chop) or BL8 is used. After a READ command is
issued, the READ burst may not be interrupted.
Table 24: READ Command Summary
Functions
Symbol
BL8MRS, BC4MRS
READ
READ with auto
precharge
CKE
Prev. Cycle
Next Cycle
CS#
RAS#
CAS#
WE#
BA
[2:0]
An
RD
A12
A10
V
L
BC4OTF
RDS4
L
L
BL8OTF
RDS8
H
L
BL8MRS, BC4MRS
RDAP
V
H
H
L
H
L
H
BA
RFU
BC4OTF
RDAPS4
L
H
BL8OTF
RDAPS8
H
H
A[11,
9:0]
CA
WRITE
The WRITE command is used to initiate a burst write access to
an active row. The value on the BA[2:0] inputs selects the bank.
The value on input A10 determines whether auto precharge is
used. The value on input A12 (if enabled in the MR) when the
WRITE command is issued determines whether BC4 (chop) or
BL8 is used.
Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the
data. If a given DM signal is registered LOW, the corresponding
data will be written to memory. If the DM signal is registered
HIGH, the corresponding data inputs will be ignored and a
WRITE will not be executed to that byte/column location.
Table 25: WRITE Command Summary
Functions
Symbol
BL8MRS, BC4MRS
WRITE
WRITE with auto
precharge
CKE
Prev. Cycle
Next Cycle
CS#
RAS#
CAS#
WE#
BA
[2:0]
An
WR
A12
A10
V
L
BC4OTF
WRS4
L
L
BL8OTF
WRS8
H
L
BL8MRS, BC4MRS
WRAP
V
H
H
L
H
L
L
BA
RFU
BC4OTF
WRAPS4
L
H
BL8OTF
WRAPS8
H
H
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
A[11,
9:0]
CA
39
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
additional posting of REFRESH commands is allowed to
the extent that the maximum number of cumulative posted
REFRESH commands (both preand post-self refresh) does not
exceed eight REFRESH commands.
PRECHARGE
The PRECHARGE command is used to de-activate the
open row in a particular bank or in all banks. The bank(s) are
available for a subsequent row access a specified time (tRP)
after the PRECHARGE command is issued, except in the case
of concurrent auto precharge. A READ or WRITE command to
a different bank is allowed during a concurrent auto precharge
as long as it does not interrupt the data transfer in the current
bank and does not violate any other timing parameters. Input
A10 determines whether one or all banks are precharged. In
the case where only one bank is precharged, inputs BA[2:0]
select the bank; otherwise, BA[2:0] are treated as “Don’t Care.”
At any given time, a maximum of 16 REFRESH commands
can be issued within 2 x tREFI.
After a bank is precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being issued
to that bank. A PRECHARGE command is treated as a NOP if
there is no open row in that bank (idle state) or if the previously
open row is already in the process of precharging. However,
the precharge period is determined by the last PRECHARGE
command issued to the bank.
REFRESH
The REFRESH command is used during normal operation
of the DRAM and is analogous to CAS#-before-RAS# (CBR)
refresh or auto refresh. This command is nonpersistent, so it
must be issued each time a refresh is required. The addressing
is generated by the internal refresh controller. This makes the
address bits a “Don’t Care” during a REFRESH command.
The DRAM requires REFRESH cycles at an average interval
of 7.8μs (maximum when TC ≤ 85°C or 3.9μs maximum when
TC ≤ 95°C). The REFRESH period begins when the REFRESH
command is registered and ends tRFC (MIN) later.
To allow for improved efficiency in scheduling and switching
between tasks, some flexibility in the absolute refresh interval
is provided. A maximum of eight REFRESH commands can
be posted to any given DRAM, meaning that the maximum
absolute interval between any REFRESH command and the
next REFRESH command is nine times the maximum average
interval refresh rate. Self refresh may be entered with up to
eight REFRESH commands being posted. After exiting self
refresh (when entered with posted REFRESH commands),
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
40
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Commands
*Advanced information. Subject to change without notice.
Figure
11: Refresh
ModeMode
Figure
40: Refresh
T0
T2
T1
CK#
CK
tCK
T3
tCH
T4
Ta1
Valid 5
NOP1
PRE
Tb0
Tb1
Valid 5
Valid 5
NOP5
NOP5
Tb2
tCL
CKE
Command
Ta0
NOP1
NOP1
REF
NOP5
REF2
Address
ACT
RA
All banks
A10
RA
One bank
BA[2:0]
Bank(s)3
BA
DQS, DQS#4
DQ4
DM4
tRP
tRFC
(MIN)
tRFC2
Indicates break
in time scale
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other valid commands may be possibleofat
these times.
1. NOP commands are shown for ease
illustration;
otherCKE
validmust be active during the PRECHARGE, ACTIVATE, and REFRESH
commands,
but
may
commands may be possible at these times. CKE must be be inactive at other times (see Power-Down Mode (page 181)).
The second
active during the PRECHARGE,2.ACTIVATE,
and REFRESH
REFRESHis not required, but two back-to-back REFRESH commands are
shown.
commands, but may be inactive at other times (see Power3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one
Down Mode).
bank is active (must precharge all active banks).
2. The second REFRESH is not required, but two back-to-back
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
REFRESH commands are shown.
5. Only NOP and DES commands are allowed after a REFRESH command and until tRFC
3. “Don’t Care” if A10 is HIGH at this point;
A10 must
(MIN)however,
is satisfied.
be HIGH if more than one bank is active (must precharge all
activeREFRESH
banks).
SELF
Notes:
4. For operations shown, DM, DQ, and DQS signals are all “Don’t
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
Care”/High-Z.
system is powered down. When in self refresh mode, the DRAM retains data without ex-
5. Only NOP and DES commands are allowed after a REFRESH
ternal clocking. Self refresh mode is also a convenient method used to enable/disable
command and until tRFC (MIN) is satisfied.
the DLL as well as to change the clock frequency within the allowed synchronous operating range (see Input Clock Frequency Change (page 123)). All power supply inputs
(including V REFCA and V REFDQ) must be maintained at valid levels upon entry/exit and
during self refresh mode operation. V REFDQ may float or not drive V DDQ/2 while in self
refresh mode under the following conditions:
•
•
•
•
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
VSS < V REFDQ < V DD is maintained
VREFDQ is valid and stable prior to CKE going back HIGH
The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid
All other self refresh mode exit timing requirements are met
41
118
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
The ODT feature (including dynamic ODT) is not supported
during DLL disable mode. The ODT resistors must be disabled
by continuously registering the ODT ball LOW by programming
RTT,nom MR1[9, 6, 2] and RTT(WR) MR2[10, 9] to 0 while in the
DLL disable mode.
SELF REFRESH
The SELF REFRESH command is used to retain data in the
DRAM, even if the rest of the system is powered down. When
in self refresh mode, the DRAM retains data without external
clocking. Self refresh mode is also a convenient method used
to enable/disable the DLL as well as to change the clock
frequency within the allowed synchronous operating range
(see Input Clock Frequency Change). All power supply inputs
(including VREFCA and VREFDQ) must be maintained at valid
levels upon entry/exit and during self refresh mode operation.
VREFDQ may float or not drive VDDQ/2 while in self refresh mode
under the following conditions:
Specific steps must be followed to switch between the DLL
enable and DLL disable modes due to a gap in the allowed
clock rates between the two modes (tCK [AVG] MAX and tCK
[DLL_DIS] MIN, respectively). The only time the clock is allowed
to cross this clock rate gap is during self refresh mode. Thus,
the required procedure for switching from the DLL enable
mode to the DLL disable mode is to change frequency during
self refresh:
• VSS < VREFDQ < VDD is maintained
1.Starting from the idle state (all banks are precharged, all
timings are fulfilled, ODT is turned off, and RTT,nom and
RTT(WR) are High-Z), set MR1[0] to 1 to disable the DLL.
• VREFDQ is valid and stable prior to CKE going
back HIGH
• The first WRITE operation may not occur earlier than
512 clocks after VREFDQ is valid
2.Enter self refresh mode after tMOD has been satisfied.
3.After tCKSRE is satisfied, change the frequency to the
desired clock rate.
• All other self refresh mode exit timing requirements
are met
4.Self refresh may be exited when the clock is stable with
the new frequency for tCKSRX. After tXS is satisfied,
update the mode registers with appropriate values.
DLL Disable Mode
If the DLL is disabled by the mode register (MR1[0] can be
switched during initialization or later), the DRAM is targeted,
but not guaranteed, to operate similarly to the normal mode,
with a few notable exceptions:
5.The DRAM will be ready for its next command in the
DLL disable mode after the greater of tMRD or tMOD
has been satisfied. A ZQCL command should be issued
with appropriate timings met.
• The DRAM supports only one value of CAS latency (CL
= 6) and one value of CAS WRITE latency (CWL = 6).
• DLL disable mode affects the read data clock-to-data
strobe relationship (tDQSCK), but not the read data-todata strobe relationship (tDQSQ, tQH). Special attention
is required to line up the read data with the controller
time domain when the DLL is disabled.
• In normal operation (DLL on), tDQSCK starts from the
rising clock edge AL + CL
• cycles after the READ command. In DLL disable mode,
tDQSCK starts AL + CL - 1 cycles after the READ
command. Additionally, with the DLL disabled, the value
of tDQSCK could be larger than tCK.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
42
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Commands
*Advanced information. Subject to change without notice.
Figure 12: DLL Enable Mode to DLL Disable Mode
Figure 41: DLL Enable Mode to DLL Disable Mode
T0
CK#
CK
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
Valid1
CKE
Command
MRS2
6
NOP
tMOD
SRE3
SRX4
NOP
7
tCKSRE
tCKSRX8
NOP
tXS
MRS5
NOP
Valid1
tMOD
tCKESR
ODT9
Valid1
Notes:
Indicates break
in time scale
1. Any valid command.
Don’t Care
2. Disable DLL by setting MR1[0] to 1.
Notes: 1. Any valid command.
3. Enter SELF REFRESH.
2. Disable DLL by setting MR1[0] to 1.
4. Exit SELF REFRESH.
3. Enter SELF REFRESH.
5. Update the mode registers with the DLL disable
4. Exit SELF REFRESH.
parameters setting.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, RTT is in the High-Z state.
6. Starting with the idle state, RTT is in the High-Z state.
7. Change frequency.
7. Change frequency.
8. Clock must be stable tCKSRX. 8. Clock must be stable tCKSRX.
9. Static LOW in the case that RTT,nom
or RTT(WR)
9. Static
LOWisinenabled;
the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH.
otherwise, static LOW or HIGH.
A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 42 (page 121)).
A similar procedure is required for
switchingfrom
fromthe
theidle
DLL
5.The
DRAM
will be readyallfortimings
its nextare
command
the
1. Starting
state (all
banks
are precharged,
fulfilled,inODT
t
t
disable mode back to the DLL enableismode.
This
also
requires
DLL enable
mode after
theself
greater
of mode.
MRD or MOD has
turned
off,
and
RTT,nom and RTT(WR)
are High-Z),
enter
refresh
tCKSRE is satisfied, change
changing the frequency during self2.refresh
been
satisfied. However,
before
applying
Aftermode.
the frequency
to the new
clock
rate. any command
tDLLK
function
a locked
DLL,frequency
a delay of for
3. Self refresh may be exited whenor
the
clock isrequiring
stable with
the new
1.Starting from the idle state (all banks
are precharged,
all
tCKSRX.
after DLL
RESETregisters
must bewith
satisfied.
A ZQCL command
After tXS is satisfied,
update
the mode
the appropriate
valtimings are fulfilled, ODT is turned
off,Atand
RTT,nom and
tMRD, then set MR0[8]
ues.
a minimum,
set MR1[0] to
0
to
enable
the
DLL.
Wait
should be issued with the appropriate timings met.
RTT(WR) are High-Z), enter self refresh
to 1 tomode.
enable DLL RESET.
4. After
another tMRD
2.After tCKSRE is satisfied, change
the frequency
to thedelay is satisfied, update the remaining mode registers with
the
appropriate
values.
new clock rate.
5. The DRAM will be ready for its next command in the DLL enable mode after the
tMRD
tMOD has been satisfied. However, before applying any com3.Self refresh may be exited when greater
the clock
stable
of is
orwith
the new frequency for tCKSRX. After
tXS
satisfied,requiring a locked DLL, a delay of tDLLK after DLL RESET must
mand
or isfunction
update the mode registers with the
appropriate
values.command should be issued with the appropriate timings met.
be satisfied.
A ZQCL
At a minimum, set MR1[0] to 0 to enable the DLL. Wait
tMRD, then set MR0[8] to 1 to enable DLL RESET.
4.After another tMRD delay is satisfied, update the
remaining mode registers with the appropriate values.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
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2Gb_DDR3L.pdf - Rev. K 9/13 EN
43
120
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology,Form
Inc. All
reserved.
#: rights
CSI-D-685
Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Commands
*Advanced information. Subject to change without notice.
Figure 13: DLL Disable Mode to DLL Enable Mode
Figure 42: DLL Disable Mode to DLL Enable Mode
T0
CK#
CK
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf0
Th0
Tg0
CKE
Valid
tDLLK
Command
NOP
SRE1
7
SRX2
NOP
tCKSRE
8
tCKSRX9
MRS3
tXS
MRS4
tMRD
MRS5
Valid 6
tMRD
ODTLoff + 1 × tCK
tCKESR
ODT10
Indicates break
in time scale
Notes:
Don’t Care
1. Enter SELF REFRESH.
2. Exit SELF REFRESH. Notes:
3.
4.
5.
6.
7.
8.
9.
10.
1. Enter SELF REFRESH.
2. enable
Exit SELF
Wait tXS, then set MR1[0] to 0 to
DLL.REFRESH.
tXS, then set MR1[0] to 0 to enable DLL.
3.
Wait
Wait tMRD, then set MR0[8] to 1 to begin DLL RESET.
4. Wait tMRD, then set MR0[8] to 1 to begin DLL RESET.
Wait tMRD, update registers (CL, CWL, and
write recovery
5. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary).
may be necessary).
6. Wait tMOD, any valid command.
Wait tMOD, any valid command.
7. Starting with the idle state.
Starting with the idle state.
8. Change frequency.
Change frequency.
9. Clock must be stable at least tCKSRX.
t
Clock must be stable at least 10.
CKSRX.
Static LOW in the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH.
Static LOW in the case that RTT,nom or RTT(WR) is enabled;
The clock frequency range for the DLL disable mode is specified by the parameter tCK
otherwise, static LOW or HIGH.
(DLL_DIS). Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are
supported.
t
DLL
disable
affectis the read
data
clock to function
data strobe
relationship
DQSCK)
The clock frequency range for
the
DLL mode
disablewill
mode
WRITE
operations
similarly
between( the
DLL enable
tDQSQ, tQH). Special attention is needed to
but
not
the
data
strobe
to
data
relationship
(
specified by the parameter tCK (DLL_DIS). Due to latency
and DLL disable modes; however, ODT functionality is not
line up read data to the controller time domain.
counter and timing restrictions, only CL = 6 and CWL = 6 are
allowed with DLL disable mode.
Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL
supported.
cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles
DLL disable mode will affect after
the read
data command.
clock to data
the READ
strobe relationship (tDQSCK) but not the data strobe to data
WRITE operations function similarly between the DLL enable and DLL disable modes;
relationship (tDQSQ, tQH). Special attention is needed to line
however, ODT functionality is not allowed with DLL disable mode.
up read data to the controller time domain.
Compared to the DLL on mode where tDQSCK starts from the
rising clock edge AL + CL cycles after the READ command,
the DLL disable mode tDQSCK starts AL + CL - 1 cycles after
the READ command.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
44
121
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology,Form
Inc. All
reserved.
#:rights
CSI-D-685
Document 009
2Gb SDRAM-DDR3L
2Gb: MYX4DDR3L128M16JT*
x4, x8, x16 DDR3L SDRAM
Commands
*Advanced information. Subject to change without notice.
tDQSCK
tDQSCK
Figure
Disable
Figure
14: 43:
DLL DLL
Disable
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
Valid
CK#
CK
RL = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DQS, DQS# DLL on
DI
b
DQ BL8 DLL on
RL (DLL_DIS) = AL + (CL - 1) = 5
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
tDQSCK (DLL_DIS) MIN
DQS, DQS# DLL off
DI
b
DQ BL8 DLL disable
DI
b+1
tDQSCK
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
DI
b+3
DI
b+4
DI
b+5
DI
b+6
(DLL_DIS) MAX
DQS, DQS# DLL off
DI
b
DQ BL8 DLL disable
DI
b+1
DI
b+2
DI
b+7
Transitioning Data
Don’t Care
Table 26: READ Electrical Characteristics, DLL Disable Mode
Table 73: READ Electrical Characteristics, DLL Disable Mode
Parameter
Symbol
Parameter
tDQSCK (DLL_DIS)
Access window of DQS from CK, CK#
Access window of DQS from CK, CK#
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
Min
Symbol
tDQSCK 1(DLL_DIS)
Max
Min
10
1
Max
10
Unit
Unit
ns
ns
45
122
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Input Clock Frequency Change
When the DDR3 SDRAM is initialized, the clock must be
stable during most normal states of operation. This means
that after the clock frequency has been set to the stable state,
the clock period is not allowed to deviate, except for what is
allowed by the clock jitter and spread spectrum clocking (SSC)
specifications.
The input clock frequency can be changed from one stable
clock rate to another under two conditions: self refresh mode
and precharge power-down mode. It is illegal to change the
clock frequency outside of those two modes. For the self
refresh mode condition, when the DDR3 SDRAM has been
successfully placed into self refresh mode and tCKSRE has
been satisfied, the state of the clock becomes a “Don’t Care.”
When the clock becomes a “Don’t Care,” changing the clock
frequency is permissible if the new clock frequency is stable
prior to tCKSRX. When entering and exiting self refresh mode
for the sole purpose of changing the clock frequency, the self
refresh entry and exit specifications must still be met.
The precharge power-down mode condition is when the
DDR3 SDRAM is in precharge power-down mode (either fast
exit mode or slow exit mode). Either ODT must be at a logic
LOW or RTT,nom and RTT(WR) must be disabled via MR1 and
MR2. This ensures RTT,nom and RTT(WR) are in an off state prior
to entering precharge power-down mode, and CKE must be
at a logic LOW. A minimum of tCKSRE must occur after CKE
goes LOW before the clock frequency can change. The DDR3
SDRAM input clock frequency is allowed to change only within
the minimum and maximum operating frequency specified
for the particular speed grade (tCK [AVG] MIN to tCK [AVG]
MAX). During the input clock frequency change, CKE must be
held at a stable LOW level. When the input clock frequency
is changed, a stable clock must be provided to the DRAM
tCKSRX before precharge power-down may be exited. After
precharge power-down is exited and tXP has been satisfied,
the DLL must be reset via the MRS. Depending on the new
clock frequency, additional MRS commands may need to be
issued. During the DLL lock time, RTT,nom and RTT(WR) must
remain in an off state. After the DLL lock time, the DRAM is
ready to operate with a new clock frequency.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
46
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Input
Clock
Frequency
Change
*Advanced
information.
Subject to change
without notice.
Figure 15: Change Frequency During Precharge Power-Down
Figure 44: Change Frequency During Precharge Power-Down
Previous clock frequency
T0
T1
T2
New clock frequency
Ta0
Tb0
Tc1
Tc0
Td0
Td1
Te0
Te1
CK#
CK
tCH
tCH
b
tCL
tCK
tCKSRE
tIS
tIH
tCH
b
tCL
b
tCH
b
tCK
b
tCL
b
tCK
b
tCKSRX
tCKE
tIH
CKE
tIS
tCPDED
Command
tCL
b
tCK
b
NOP
NOP
NOP
NOP
NOP
Address
MRS
NOP
Valid
DLL RESET
tAOFPD/tAOF
tXP
Valid
tIH
tIS
ODT
DQS, DQS#
High-Z
DQ
High-Z
DM
tDLLK
Enter precharge
power-down mode
Frequency
change
Exit precharge
power-down mode
Indicates break
in time scale
Notes:
Don’t Care
1. Applicable for both SLOW-EXIT
and FAST-EXIT precharge
Notes: 1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.
power-down modes.
2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina2. tAOFPD and tAOF must be satisfied
outputs
High-Z
tionand
(ODT)
(page
191)prior
for exact requirements).
to T1 (see “On-Die Termination
page feature
108 for exact
3. (ODT)”
If theon
RTT,nom
was enabled in the mode register prior to entering precharge
requirements).
power-down mode, the ODT signal must be continuously registered LOW, ensuring RTT
is in
inthe
an mode
off state.
If the
RTT,nom feature was disabled in the mode register prior to enter3. If the RTT,nom feature was enabled
register
prior
ingmode,
precharge
power-down
mode, RTT will remain in the off state. The ODT signal can
to entering precharge power-down
the ODT
signal
be registered
HIGH
must be continuously registered LOW,
ensuring LOW
R is or
in an
off in this case.
TT
state. If the RTT,nom feature was disabled in the mode register
prior to entering precharge power-down mode, RTT will remain
in the off state. The ODT signal can be registered LOW or
HIGH in this case.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
47
124
Micron Technology, Inc. reserves the right to change products or specifications
notice. Document 009
Formwithout
#: CSI-D-685
© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4,
x8, x16
DDR3L SDRAM
2Gb
SDRAM-DDR3L
Write Leveling
MYX4DDR3L128M16JT*
Write Leveling
*Advanced information. Subject to change without notice.
For better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme
for the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK relationship
at the
DRAM
with a simple
feature provided
theleveling
DRAM.procedure
Write lev-must
For better signal integrity, DDR3
SDRAM
memory
modules
Thefeedback
memory controller
using theby
write
eling is generally used as part of the initialization process, if required. For normal
have adopted fly-by topology for the commands, addresses,
have adjustable delay settings on its DQS strobe to align the
DRAM operation, this feature must be disabled. This is the only DRAM operation where
control signals, and clocks. Write leveling is a scheme for the
rising edge of DQS to the clock at the DRAM pins. This is
the DQS functions as an input (to capture the incoming clock) and the DQ function as
memory controller to adjust or de-skew
the
DQS
strobe
(DQS,
when
the DRAM ODT
asynchronously
feeds
outputs (to report the state of theaccomplished
clock). Note that
nonstandard
schemes are
re- back
DQS#) to CK relationship at the quired.
DRAM with a simple feedback
the CK status via the DQ bus and samples with the rising
feature provided by the DRAM. Write leveling is generally used
edge of DQS. The controller repeatedly delays the DQS strobe
The
memory
controller
using
the
write
leveling
procedure
adjustable
as part of the initialization process, if required. For normal
until
a CK
transition
from 0must
to 1 have
is detected.
The delay
DQS delay
settings on its DQS strobe to align the rising edge of DQS to the clock at the
DRAMt pins.
t
DRAM operation, this feature must be disabled. This is the
established by this procedure helps ensure DQSS, DSS, and
This is accomplished when the DRAM
asynchronously feeds back the CK status via the
tDSH specifications in systems that use fly-by topology by deonly DRAM operation where the DQS functions as an input (to
DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the
capture the incoming clock) and
thestrobe
DQ function
trace
length The
mismatch.
A conceptual
timing
DQS
until a as
CKoutputs
transition skewing
from 0 tothe
1 is
detected.
DQS delay
established
byof this
(to report the state of the clock).
Note
that nonstandard
ODTtDQSS,
procedure
is shown
the figure below.
tDSS, and
tDSH in
this
procedure
helps ensure
specifications
in systems that use
schemes are required.
fly-by topology by de-skewing the trace length mismatch. A conceptual timing of this
procedure is shown in Figure 45.
Write Leveling
Figure 16: Write Leveling Concept
Figure 45: Write Leveling Concept
T0
T1
T2
T3
T4
T5
T6
T7
CK#
Source
CK
Differential DQS
CK#
Tn
T0
T1
T2
T3
T4
T5
T6
T4
T5
T6
CK
Destination
Differential DQS
0
DQ
Destination
CK#
Tn
T0
T1
0
T2
T3
CK
Push DQS to capture
0–1 transition
Differential DQS
DQ
1
1
Don’t Care
PDF: 09005aef83ed2952
MYX4DDR3L128M16JT*
2Gb_DDR3L.pdf - Rev. K 9/13 EN
Revision 1.5 - 10/30/14
125
48
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Write Leveling (continued)
When write leveling is enabled, the rising edge of DQS samples
CK, and the prime DQ outputs the sampled CK’s status. The
prime DQ for a x4 or x8 configuration is DQ0 with all other DQ
(DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is
DQ0 for the lower byte and DQ8 for the upper byte. It outputs
the status of CK sampled by LDQS and UDQS. All other DQ
(DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a
x16 enable each byte lane to be leveled independently.
Besides using MR1[7] to disable/enable write leveling, MR1[12]
must be used to enable/disable the output buffers. The ODT
value, burst length, and so forth need to be selected as well.
This interaction is shown in the table below. It should also be
noted that when the outputs are enabled during write leveling
mode, the DQS buffers are set as inputs, and the DQ are set
as outputs. Additionally, during write leveling mode, only the
DQS strobe terminations are activated and deactivated via the
ODT ball. The DQ remain disabled and are not affected by the
ODT ball.
The write leveling mode register interacts with other mode
registers to correctly configure the write leveling functionality.
Table 27: Write Leveling Matrix
MR1[7]
MR1[12]
MR1[2, 6, 9]
Write
Leveling
Output
Buffers
RTT,nom
Value
Disabled
DRAM ODT
Ball
DRAM RTT,nom
DQS
DRAM State
DQ
See normal operations
Disabled (1)
Enabled (1)
Case
Write leveling not enabled
0
NA
Low
Off
DQS not receiving: not terminated Prime DQ
High-Z: not terminated Other DQ
High-Z: not terminated
1
20Ω, 30Ω,
40Ω, 60Ω or
120Ω
High
On
DQS not receiving: terminated by RTT Prime
DQ High-Z: not terminated Other DQ High-Z: not terminated
2
NA
Low
Off
DQS receiving: not terminated
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
3
40Ω, 60Ω or
120Ω
High
On
DQS receiving: terminated by RTT
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
4
Off
Enabled (0)
Notes
2
3
Notes:
3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS
captures the input strobe, and only some RTT,nom values are
allowed. This simulates a normal write state to DQS.
1. Expected usage if used during write leveling: Case 1 may be
used when DRAM are on a dual-rank module and on the rank
not being leveled or on any rank of a module not being leveled
on a multislot system. Case 2 may be used when DRAM
are on any rank of a module not being leveled on a multislot
system. Case 3 is generally not used. Case 4 is generally used
when DRAM are on the rank that is being leveled.
2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS
ignores the input strobe, and all RTT,nom values are allowed.
This simulates a normal standby state to DQS.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
49
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Write Leveling Procedure
A memory controller initiates the DRAM write leveling mode by
setting MR1[7] to 1, assuming the other programable features
(MR0, MR1, MR2, and MR3) are first set and the DLL is fully
reset and locked. The DQ balls enter the write leveling mode
going from a High-Z state to an undefined driving state, so
the DQ bus should not be driven. During write leveling mode,
only the NOP or DES commands are allowed. The memory
controller should attempt to level only one rank at a time;
thus, the outputs of other ranks should be disabled by setting
MR1[12] to 1 in the other ranks. The memory controller may
assert ODT after a tMOD delay, as the DRAM will be ready to
process the ODT transition. ODT should be turned on prior to
DQS being driven LOW by at least ODTLon delay (WL - 2 tCK),
provided it does not violate the aforementioned tMOD delay
requirement.
The memory controller will most likely sample each applicable
prime DQ state and determine whether to increment or
decrement its DQS delay setting. After the memory controller
performs enough DQS toggles to detect the CK’s 0-to-1
transition, the memory controller should lock the DQS delay
setting for that DRAM. After locking the DQS setting is locked,
leveling for the rank will have been achieved, and the write
leveling mode for the rank should be disabled or reprogrammed
(if write leveling of another rank follows).
The memory controller may drive DQS LOW and DQS# HIGH
after tWLDQSEN has been satisfied. The controller may
begin to toggle DQS after tWLMRD (one DQS toggle is DQS
transitioning from a LOW state to a HIGH state with DQS#
transitioning from a HIGH state to a LOW state, then both
transition back to their original states). At a minimum, ODTLon
and tAON must be satisfied at least one clock prior to DQS
toggling.
After tWLMRD and a DQS LOW preamble (tWPRE) have been
satisfied, the memory controller may provide either a single
DQS toggle or multiple DQS toggles to sample CK for a given
DQS-to-CK skew. Each DQS toggle must not violate tDQSL
(MIN) and tDQSH (MIN) specifications. tDQSL (MAX) and
tDQSH (MAX) specifications are not applicable during write
leveling mode. The DQS must be able to distinguish the CK’s
rising edge within tWLS and tWLH. The prime DQ will output
the CK’s status asynchronously from the associated DQS rising
edge CK capture within tWLO. The remaining DQ that always
drive LOW when DQS is toggling must be LOW within tWLOE
after the first tWLO is satisfied (the prime DQ going LOW). As
previously noted, DQS is an input and not an output during
this process. Figure 17 (page 51) depicts the basic timing
parameters for the overall write leveling procedure.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
50
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
2Gb: x4,
x8, x16 DDR3L SDRAM
MYX4DDR3L128M16JT*
Write Leveling
*Advanced information. Subject to change without notice.
Figure 46: Write Leveling Sequence
Figure 17: Write Leveling Sequence
T1
CK#
CK
Command
T2
tWLS
tWLH
MRS1
NOP2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tMOD
ODT
tWLDQSEN
tDQSL3
tDQSH3
tDQSL3
tDQSH3
Differential DQS4
tWLMRD
tWLO
tWLO
Prime DQ5
tWLO
tWLOE
Early remaining DQ
tWLO
Late remaining DQ
Indicates break
in time scale
Undefined Driving Mode
Don’t Care
Notes:
Notes: 1. MRS: Load MR1 to enter write leveling mode.
1. MRS: Load MR1 to enter write2.leveling
NOP:mode.
NOP or DES.
3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and tDQSL
(MIN)
as width
defined
for regular writes. The maximum pulse width is system-dependent.
3. DQS, DQS# needs to fulfill minimum
pulse
requirements
DQS is
the differential data strobe (DQS, DQS#). Timing reference points are
tDQSH (MIN) and tDQSL (MIN)4.
as Differential
defined for regular
writes.
the zero crossings. The solid line represents DQS; the dotted line represents DQS#.
The maximum pulse width is system-dependent.
5. data
DRAM
drives
leveling
4. Differential DQS is the differential
strobe
(DQS,
DQS#).feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ
are driven LOW and remain in this state throughout the leveling procedure.
Timing reference points are the zero crossings. The solid line
represents DQS; the dotted line represents DQS#.
2. NOP: NOP or DES.
5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4
and x8). The remaining DQ are driven LOW and remain in this
state throughout the leveling procedure.
MYX4DDR3L128M16JT*
Revision
1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
51
128
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb: x4, x8, x16 DDR3L SDRAM
2Gb SDRAM-DDR3L
Write Leveling
MYX4DDR3L128M16JT*
Write Leveling Mode Exit Procedure
After the DRAM are leveled, they must exit from write
leveling
mode Subject
beforetothe
normal
*Advanced
information.
change
without notice.
mode can be used. Figure 47 depicts a general procedure for exiting write leveling
mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop
Write Leveling Mode Exit Procedure
driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memoAfter the DRAM are leveled, they
must exittofrom
write the
leveling
ODTprime
inputDQ
should
LOW
such
that ODTLoff
ry controller
capture
applicable
statebe
(atde-asserted
~Tb0). The DQ
balls
become
t
mode before the normal mode
can be used.
Figure
(MIN) expires
after
theremain
DQS isundefined
no longer driving
LOW. When
undefined
when
DQS18
nodepicts
longer remains
LOW, and
they
until MOD
after
theleveling
MRS command
(at the
Te1). ODT LOW satisfies tIS, ODT must be kept LOW (at ~Tb0)
a general procedure for exiting
write
mode. After
last rising DQS (capturing a The
1 atODT
T0), input
the memory
untilLOW
the DRAM
is ready
for either
another
tothe
be leveled
shouldcontroller
be de-asserted
such that
ODTLoff
(MIN)
expiresrank
after
tWLO (MAX) delay
should stop driving the DQSDQS
signals
after
or
until
the
normal
mode
can
be
used.
After
DQS
termination
is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at
plus enough delay to enable ~Tb0)
the memory
controller
is switched
off,rank
writetolevel
mode should
until the
DRAMtoiscapture
ready for either
another
be leveled
or untilbe
thedisabled
normal via the
tMOD
the applicable prime DQ statemode
(at ~Tb0).
Theused.
DQ balls
MRS command
(at Tc2).
Afterlevel
is satisfied
can be
Afterbecome
DQS termination
is switched
off, write
mode
should(at
beTe1), any
undefined when DQS no longer
remainsvia
LOW,
remain (atvalid
mayis be
registered
by the
DRAM.
disabled
the and
MRSthey
command
Tc2).command
After tMOD
satisfied
(at Te1),
any
valid Some
com- MRS
tMRD
mand
may
be registered
by The
the DRAM.
Some MRS
may
be issued
after tMRD
undefined until tMOD after the
MRS
command
(at Te1).
commands
may commands
be issued after
(at Td1).
(at Td1).
Figure
Write
Leveling
Exit Procedure
Figure18:
47:
Write
Leveling
Exit Procedure
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
CK#
CK
Command
Td0
Td1
Te0
Te1
NOP
Valid
NOP
Valid
tMRD
Address
MR1
tIS
Valid
Valid
tMOD
ODT
t
ODTLoff AOF (MIN)
RTT,nom
RTT DQS, RTT DQS#
t
DQS, DQS#
RTT(DQ)
DQ
tWLO
AOF (MAX)
+ tWLOE
CK = 1
Indicates break
in time scale
Undefined Driving Mode
Transitioning
Don’t Care
Note:
Note: 1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
1. The DQ result, = 1, between Ta0CK
andHIGH
Tc0, is
a result
theT0 state.
just
afterofthe
DQS, DQS# signals capturing CK HIGH just after the T0 state.
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
129
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
52
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Initialization
The following sequence is required for power-up and
initialization, as shown in Figure 19 (page 54):
2. Until stable power, maintain RESET# LOW to ensure
the outputs remain disabled (High-Z). After the power
is stable, RESET# must be LOW for at least 200μs to
begin the initialization process. ODT will remain in the
High-Z state while RESET# is LOW and until CKE is
registered HIGH.
1. Apply power. RESET# is recommended to be below
0.2 × VDDQ during power ramp to ensure the outputs
remain disabled (High-Z) and ODT off (RTT is also
High-Z). All other inputs, including ODT, may be
undefined.
3. CKE must be LOW 10ns prior to RESET# transitioning
HIGH.
During power-up, either of the following conditions may
exist and must be met:
4. After RESET# transitions HIGH, wait 500μs (minus one
clock) with CKE LOW.
• Condition A:
5. After the CKE LOW time, CKE may be brought HIGH
(synchronously) and only NOP or DES commands
may be issued. The clock must be present and valid
for at least 10ns (and a minimum of five clocks) and
ODT must be driven LOW at least tIS prior to CKE
being registered HIGH. When CKE is registered HIGH,
it must be continuously registered HIGH until the full
initialization process is complete.
ƒƒ VDD and VDDQ are driven from a single-power
converter output and are ramped with a
maximum delta voltage between them of ΔV
≤ 300mV. Slope reversal of any power supply
signal is allowed. The voltage levels on all balls
other than VDD, VDDQ, VSS, VSSQ must be less
than or equal to VDDQ and VDD on one side, and
must be greater than or equal to VSSQ and VSS
on the other side.
6. After CKE is registered HIGH and after tXPR has
been satisfied, MRS commands may be issued. Issue
an MRS (LOAD MODE) command to MR2 with the
applicable settings (provide LOW to BA2 and BA0 and
HIGH to BA1).
ƒƒ Both VDD and VDDQ power supplies ramp to
VDD,min and VDDQ,min within tVDDPR = 200ms.
ƒƒ VREFDQ tracks VDD × 0.5, VREFCA tracks VDD ×
0.5.
7. Issue an MRS command to MR3 with the applicable
settings.
ƒƒ VTT is limited to 0.95V when the power ramp
is complete and is not applied directly to the
device; however, tVTD should be greater than or
equal to 0 to avoid device latchup.
8. Issue an MRS command to MR1 with the applicable
settings, including enabling the DLL and configuring
ODT.
9. Issue an MRS command to MR0 with the applicable
settings, including a DLL RESET command. tDLLK
(512) cycles of clock input are required to lock the DLL.
• Condition B:
ƒƒ VDD may be applied before or at the same time
as VDDQ.
10. Issue a ZQCL command to calibrate RTT and RON
values for the process voltage temperature (PVT). Prior
to normal operation, tZQinit must be satisfied.
ƒƒ VDDQ may be applied before or at the same time
as VTT, VREFDQ, and VREFCA.
ƒƒ No slope reversals are allowed in the power
supply ramp for this condition.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
11. When tDLLK and tZQinit have been satisfied, the DDR3
SDRAM will be ready for normal operation.
53
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Initialization
*Advanced information. Subject to change without notice.
Figure 48:
19: Initialization
Sequence
Figure
Initialization
Sequence
T (MAX) = 200ms
VDD
VDDQ
VTT
See power-up
conditions
in the
initialization
sequence text,
set up 1
VREF
Power-up
ramp
tVTD
Stable and
valid clock
T0
T1
tCK
Tc0
Tb0
Ta0
Td0
CK#
CK
tCKSRX
tIOZ
tCL
tCL
= 20ns
RESET#
tIS
T (MIN) = 10ns
Valid
CKE
Valid
ODT
tIS
Command
NOP
MRS
MRS
MRS
MRS
Address
Code
Code
Code
Code
A10
Code
Code
Code
Code
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
ZQCL
Valid
DM
BA[2:0]
Valid
Valid
A10 = H
Valid
DQS
DQ
RTT
T = 200μs (MIN)
T = 500μs (MIN)
tXPR
MR2
All voltage
supplies valid
and stable
tMRD
tMRD
MR3
tMRD
MR1 with
DLL enable
tMOD
MR0 with
DLL reset
tZQinit
ZQ calibration
tDLLK
DRAM ready for
external commands
Normal
operation
Indicates break
in time scale
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
Don’t Care
54
131
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Voltage Initialization / Change
If the SDRAM is powered up and initialized for the 1.35V
operating voltage range, voltage can be increased to the 1.5V
operating range provided the following conditions are met (see
Figure 20 (page 56)):
• Just prior to increasing the 1.35V operating voltages,
no further commands are issued, other than NOPs or
COMMAND INHIBITs, and all banks are in the precharge
state.
• The 1.5V operating voltages are stable prior to issuing
new commands, other than NOPs or COMMAND
INHIBITs.
• The DLL is reset and relocked after the 1.5V operating
voltages are stable and prior to any READ command.
• The ZQ calibration is performed. tZQinit must be
satisfied after the 1.5V operating voltages are stable and
prior to any READ command.
If the SDRAM is powered up and initialized for the 1.5V
operating voltage range, voltage can be reduced to the 1.35V
operation range provided the following conditions are met (see
Figure 20 (page 56)):
• Just prior to reducing the 1.5V operating voltages,
no further commands are issued, other than NOPs or
COMMAND INHIBITs, and all banks are in the precharge
state.
• The 1.35V operating voltages are stable prior to issuing
new commands, other than NOPs or COMMAND
INHIBITs.
• The DLL is reset and relocked after the 1.35V operating
voltages are stable and prior to any READ command.
• The ZQ calibration is performed. tZQinit must be
satisfied after the 1.35V operating voltages are stable
and prior to any READ command.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
55
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Voltage
/ Change
*Advanced Initialization
information. Subject to change
without notice.
VV
Switching
DD Voltage
DD Voltage Switching
After the DDR3L DRAM is powered
and DRAM
initialized,
the
After the up
DDR3L
is powered
up and initialized, the power supply can be altered
power supply can be altered between
between the
the DDR3L
DDR3Land
andDDR3
DDR3 levels, provided the sequence in Figure 49 is mainlevels, provided the sequence tained.
in Figure 20 is maintained.
Figure 49: VDD Voltage Switching
Figure
20: VDD Voltage Switching
Tb
Ta
((
))
((
))
CK, CK#
Tc
Te
Td
((
))
((
))
((
))
((
))
Tf
Ti
Th
Tg
Tj
Tk
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Valid
((
))
((
))
Valid
((
))
((
))
((
))
((
))
Valid
((
))
((
))
((
))
((
))
((
))
((
))
tCKSRX
TMIN = 10ns
VDD, VDDQ (DDR3)
((
))
((
))
((
))
((
))
VDD, VDDQ (DDR3L)
TMIN = 10ns
TMIN = 200μs
T = 500μs
RESET#
CKE
((
))
((
))
((
))
((
))
tIS
TMIN = 10ns
((
))
tDLLK
tMRD
tXPR
tIS
((
))
((
))
MRS
((
))
((
))
MRS
((
))
((
))
((
))
((
))
MR2
((
))
((
))
MR3
((
))
((
))
Command
((
))
((
))
((
))
((
))
BA
((
))
((
))
((
))
((
))
ODT
((
))
((
))
((
))
((
))
((
))
((
))
RTT
((
))
((
))
((
))
Note 1
tMRD
tMRD
MRS
MR1
tMOD
((
))
((
))
MRS
((
))
((
))
((
))
((
))
MR0
((
))
((
))
tZQinit
ZQCL
((
))
((
))
Note 1
tIS
tIS
((
((
((
((
))
))
))
))
Static LOW in case RTT,nom is enabled at time Tg, otherwise static HIGH or LOW
((
((
((
((
))
))
))
))
((
))
((
))
((
))
((
))
((
))
Time break
((
))
Note:
Valid
Don’t Care
1. From time point Td until Tk, NOP or DES commands must be
Note: 1. From time point Td until Tk, NOP or DES commands must be applied between MRS and
applied between MRS and ZQCL commands.
ZQCL commands.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
56
133
Form without
#: CSI-D-685
Micron Technology, Inc. reserves the right to change products or specifications
notice. Document 009
© 2010 Micron Technology, Inc. All rights reserved.
ode
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Mode Registers
2Gb: x4, x8, x16 DDR3L SDRAM
Mode Registers
Mode registers (MR0–MR3) are used to define various
The MRS command can only be issued (or re-issued) when
modes
of
programmable
operations
of
the
DDR3
SDRAM.
all banks are idle and in the precharged state (tRP is satisfied
Registers
A mode register is programmed via the mode register set
and no data bursts are in progress). After an MRS command
Mode registers (MR0–MR3) are used to define various modes of programmable opera(MRS) command during initialization, and it retains the stored
has been issued, two parameters must be satisfied: tMRD
tions of the DDR3 SDRAM. A mode register is programmed
via the mode register set
information (except for MR0[8], which is self-clearing) until it is
and tMOD. The controller must wait tMRD before initiating any
(MRS) command during initialization, and it retains the stored information (except for
reprogrammed,MR0[8],
RESET#which
goes LOW,
the device loses
subsequent
MRS commands.
is self-clearing)
until power.
it is reprogrammed,
RESET#
goes LOW, the device
loses power.
Contents of a mode register can be altered by re-executing
Contents
of ifa mode
register
altered
the MRS command.
Even
the user
wantscan
to be
modify
onlyby re-executing the MRS command. Even if
the user
wants
to modify
only a subset
of the mode register’s variables, all variables
a subset of the
mode
register’s
variables,
all variables
must bewhen
programmed
the MRS
command is issued. Reprogramming the mode
must be programmed
the MRSwhen
command
is issued.
register
will
not
alter
the
contents
of
the
array, provided it is performed corReprogramming the mode register will not alter the contentsmemory
of
rectly.
the memory array, provided it is performed correctly.
The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (tRP is satisfied and no data bursts are in progress). After an MRS command has been issued, two parameters must be satisfied: tMRD and tMOD. The controller must wait tMRD before initiating any subsequent MRS commands.
Figure 21: MRS to MRS Command Timing (tMRD)
ure 50: MRS to MRS Command Timing (tMRD)
CK#
T0
T1
T2
Ta0
Ta1
Ta2
MRS1
NOP
NOP
NOP
NOP
MRS2
CK
Command
tMRD
Address
Valid
Valid
CKE3
Indicates break
in time scale
Don’t Care
Notes:
tRP (MIN)
Notes: 1. Prior to issuing the MRS command, all banks must be idle and precharged,
1. Prior to issuing the MRS command, all banks must be idle and
The controller must also wait tMOD before initiating any non-MRS
must be satisfied, and no data bursts can be in progress.
precharged, tRP (MIN)
must be satisfied, and no data bursts
commands (excluding NOP and DES). The DRAM requires tMOD
2. tMRD specifies the MRS to MRS command minimum cycle time.
can be in progress.
in order to update the requested features, with the exception of
3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see Pow- t
DLL RESET, which requires additional time. Until MOD has been
2. tMRD specifies the
MRS
to
MRS
command
minimum
cycle
er-Down Mode (page 181)).
satisfied, the updated features are to be assumed unavailable.
time.
4. For a CAS latency change, tXPDLL timing must be met before any non-MRS command.
3. CKE must be registered HIGH from the MRS command
until
controller must also wait tMOD before initiating any non-MRS commands (excludtMRSPDENThe
(MIN)
t
ing NOP and DES). The DRAM requires MOD in order to update the requested features,
4. For a CAS latency change, tXPDLL timing must be met before
with the exception of DLL RESET, which requires additional time. Until tMOD has been
any non-MRS command.
satisfied, the updated features are to be assumed unavailable.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
57
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
*Advanced
information.
Subject to change without notice.
Mode
Register
0 (MR0)
22:nonMRS
MRS to nonMRS
Command
Timing
(tMOD)
ure 51: Figure
MRS to
Command
Timing
(tMOD)
T0
T1
T2
Ta0
Ta1
Ta2
MRS
NOP
NOP
NOP
NOP
non
MRS
CK#
CK
Command
tMOD
Address
Valid
Valid
Valid
CKE
Old
setting
New
setting
Updating setting
Indicates break
in time scale
Don’t Care
Notes:
Notes: 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP
1. Prior to issuing themust
MRSbe
command,
banks
idle can be in progress).
at T0 so that ODTL is satisfied prior to Ta1. ODT must also be
satisfied,alland
nomust
databe
bursts
(they must be precharged, tRP must be
satisfied, and no data
registered LOW at each rising CK edge from T0 until tMODmin
t
2. Prior to Ta2 when MOD (MIN) is being satisfied, no commands (except NOP/DES) may be
bursts can be in progress).
is satisfied at Ta2.
issued.
tMOD (MIN) is being satisfied, no
2. Prior to Ta2 when
4. CKELOW
must at
be T0
registered
the MRS command until
3. If
RTT was previously enabled, ODT must be registered
so thatHIGH
ODTLfrom
is satiscommands (except
NOP/DES)
issued.
(MIN),CK
atedge
whichfrom
time power-down
may occur (see
fied
prior tomay
Ta1.be
ODT
must also be registered LOWtMRSPDEN
at each rising
T0 until
tMODmin is satisfied at Ta2.
“Power-Down Mode” on page 99).
3. If RTT was previously
enabled, ODT must be registered LOW
4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which
time power-down may occur (see Power-Down Mode (page 181)).
ode Register 0 (MR0)
rst
Mode Register 0 (MR0)
The base register, mode register 0 (MR0), is used to define various DDR3 SDRAM modes
of operation.
These
definitions
include
the selection
of a burstcommand,
length, burst
CASthen BC4 mode is
The base register,
mode register
0 (MR0),
is used
to define
READ/WRITE
if type,
A12=0,
latency,modes
operating
mode, DLL
RESET,
write recovery,
andIfprecharge
power-down
various DDR3 SDRAM
of operation.
These
definitions
selected.
A12=1, then
BL8 mode ismode
selected. Specific timing
(see
Figure
52
(page
136)).
include the selection of a burst length, burst type, CAS latency,
diagrams, and turnaround between READ/WRITE, are shown
operating mode, DLL RESET, write recovery, and precharge
in the READ/WRITE sections of this document.
Length
power-down mode (see Figure 23 (page 59)).
When a READ or WRITE command is issued, a block of columns
Burst length is defined by MR0[1:0]. Read and write accesses to the DDR3 SDRAM are
equal to the burst
length is
effectively
selected. All accesses for
to 4 (chop)
mode,
8 (fixed)
Burst Length burst-oriented, with the burst length being programmable
that
burst
take
place
within
this
block,
meaning that the burst
mode, or selectable using A12 during a READ/WRITE command (on-the-fly). The burst
will
wrap
within
the
block
if
a
boundary
is
reached. The block is
Burst length is defined
MR0[1:0]. the
Read
and writenumber
accessesof column locations that can be accessed for
length by
determines
maximum
uniquely
selected
by
A[i:2]
when
the
burst
to the DDR3 SDRAM
areREAD
burst-oriented,
the burst
lengthMR0[1:0] is set to 01 during a READ/WRITE length is set to 4 and
a given
or WRITE with
command.
When
byIfA[i:3]
the burst
lengthisisselected.
set to 8, where Ai is the most
command,
if A12 =mode,
0, then
mode
is selected.
A12 when
= 1, then
BL8 mode
being programmable
to 4 (chop)
8 BC4
(fixed)
mode,
or
timing
diagrams, andcommand
turnaround
READ/WRITE,
are shown
in the
significant
column address
bit for
a given configuration. The
selectable usingSpecific
A12 during
a READ/WRITE
(on-between
READ/WRITE
sections
of
this
document.
remaining
(least
significant)
address
bit(s) is (are) used to select
the-fly). The burst length determines the maximum number
the
starting
location
within
the
block.
of column locations
that
can beoraccessed
for a givenis READ
When
a READ
WRITE command
issued, a block of columns equal to the burst The programmed burst
length
applies
to both
READthis
andblock,
WRITE bursts.
or WRITE command.
MR0[1:0]
is set to
during for
a that
lengthWhen
is effectively
selected.
All01
accesses
burst
take place
within
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A[i:2] when the burst length is set to 4 and by A[i:3] when the burst
length is set to 8, where Ai is the most significant column address bit for a given configuration. The remaining (least significant) address bit(s) is (are) used to select the startMYX4DDR3L128M16JT*
58
Revision 1.5 - 10/30/14
9005aef83ed2952
DR3L.pdf - Rev. K 9/13 EN
135
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb: x4, 2Gb
x8, x16
DDR3L SDRAM
SDRAM-DDR3L
Mode Register 0 (MR0)
MYX4DDR3L128M16JT*
ing location within the block. The programmed burst length applies to both READ and
WRITE bursts.
*Advanced information. Subject to change without notice.
Figure 23: Mode Register 0 (MR0) Definitions
Figure 52: Mode Register 0 (MR0) Definitions
M15 M14
BA2 BA1 BA0 A[15:13] A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
18 17 16 15–13 12 11 10
PD
01 0 0
01
WR
Mode register 0 (MR0)
9
8 7 6 5 4 3 2
DLL 01 CAS# latency BT CL
1 0
BL
0
Mode register 0 (MR0)
0
1
Mode register 1 (MR1)
M12
Precharge PD
1
0
Mode register 2 (MR2)
0
DLL off (slow exit)
0
1
1
Mode register 3 (MR3)
1
DLL on (fast exit)
1
0
0
Fixed BL8
0
1
4 or 8 (on-the-fly via A12)
No
1
0
Fixed BC4 (chop)
Yes
1
1
Reserved
M8 DLL Reset
CAS Latency
M3
0
0
0
16
0
0
0
0
Reserved
0
Sequential (nibble)
0
0
1
5
0
0
1
0
5
1
Interleaved
0
1
0
6
0
1
0
0
6
0
1
1
7
0
1
1
0
7
1
0
0
8
1
0
0
0
8
1
0
1
10
1
0
1
0
9
1
1
0
12
1
1
0
0
10
1
1
1
14
1
1
1
0
11
0
0
0
1
12
0
0
1
1
13
0
1
0
1
14
M11 M10 M9 Write Recovery
Note:
Burst Length
M1 M0
Mode Register
0
M6 M5 M4 M2
READ Burst Type
Note:
1. MR0[18, 15:13, 7] are reserved
for future use and must be
programmed to 0.
1. MR0[18, 15:13, 7] are reserved for future use and must be programmed to 0.
Burst Type
Burst Type
Accesses
within a given burst can be programmed to either a
sequential or an interleaved order.
The burst
type
selected
Accesses
within
a is
given
burstviacan be programmed to either a sequential or an interMR0[3] (see Figure 23 (pageleaved
59)). The
ordering
of accesses
order.
The burst
type is selected via MR0[3] (see Figure 52 (page 136)). The orderwithin a burst is determineding
by ofthe
burst length,
burstis determined by the burst length, the burst type, and the
accesses
within the
a burst
starting
column
DDR3 only supports 4-bit burst chop and 8-bit burst access
type, and the starting column
address.
DDR3address.
only supports
modes.
Full
interleave
address ordering is supported for READs, while WRITEs are re4-bit burst chop and 8-bit burst
access
modes.
Full interleave
stricted
to
nibble
(BC4)
or word
address ordering is supported for READs, while WRITEs
are (BL8) boundaries.
restricted to nibble (BC4) or word (BL8) boundaries.
PDF: 09005aef83ed2952
MYX4DDR3L128M16JT*
2Gb_DDR3L.pdf - Rev. K 9/13 EN
Revision 1.5 - 10/30/14
136
59
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 28: Burst Order
Burst Length
READ/ WRITE
Starting Column
Address (A[2, 1, 0])
Burst Type =
Sequential (Decimal)
Burst Type =
Interleaved (Decimal)
Notes
000
0, 1, 2, 3, Z, Z, Z, Z
0, 1, 2, 3, Z, Z, Z, Z
1, 2
001
1, 2, 3, 0, Z, Z, Z, Z
1, 0, 3, 2, Z, Z, Z, Z
1, 2
010
2, 3, 0, 1, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
1, 2
011
3, 0, 1, 2, Z, Z, Z, Z
3, 2, 1, 0, Z, Z, Z, Z
1, 2
100
4, 5, 6, 7, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
1, 2
101
5, 6, 7, 4, Z, Z, Z, Z
5, 4, 7, 6, Z, Z, Z, Z
1, 2
110
6, 7, 4, 5, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
1, 2
111
7, 4, 5, 6, Z, Z, Z, Z
7, 6, 5, 4, Z, Z, Z, Z
1, 2
0VV
0, 1, 2, 3, X, X, X, X
0, 1, 2, 3, X, X, X, X
1, 3, 4
1VV
4, 5, 6, 7, X, X, X, X
4, 5, 6, 7, X, X, X, X
1, 3, 4
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
1
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
1
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
1
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
1
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
1
VVV
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1, 3
READ
4 (chop)
WRITE
8 (fixed)
READ
WRITE
Notes:
1. Internal READ and WRITE operations start at the same point in
time for BC4 as they do for BL8.
2. Z = Data and strobe output drivers are in tri-state.
3. V = A valid logic level (0 or 1), but the respective input buffer
ignores level-on input pins.
4. X = “Don’t Care.”
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
60
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
DLL RESET
CAS Latency (CL)
DLL RESET is defined by MR0[8] (see Figure 23 (page 59)).
Programming MR0[8] to 1 activates the DLL RESET function.
MR0[8] is self-clearing, meaning it returns to a value of 0 after
the DLL RESET function has been initiated.
CAS latency (CL) is defined by MR0[6:4], as shown in (see
Figure 23 (page 59)). CAS latency is the delay, in clock cycles,
between the internal READ command and the availability of the
first bit of output data. CL can be set to 5 through 14. DDR3
SDRAM do not support half-clock latencies.
Anytime the DLL RESET function is initiated, CKE must be
HIGH and the clock held stable for 512 (tDLLK) clock cycles
before a READ command can be issued. This is to allow time
for the internal clock to be synchronized with the external
clock. Failing to wait for synchronization can result in invalid
output timing specifications, such as tDQSCK timings.
Examples of CL = 6 and CL = 8 are shown below. If an
internal READ command is registered at clock edge n, and the
CAS latency is m clocks, the data will be available nominally
coincident with clock edge n + m. See Speed Bin Tables for
the CLs supported at various operating frequencies.
Write Recovery
WRITE recovery time is defined by MR0[11:9] (see Figure 23
(page 59)). Write recovery values of 5, 6, 7, 8, 10, or 12 can
be used by programming MR0[11:9]. The user is required to
program the correct value of write recovery, which is calculated
by dividing tWR (ns) by tCK (ns) and rounding up a noninteger
value to the next integer: WR (cycles) = roundup (tWR (ns)/tCK
(ns)).
Precharge Power-Down (Precharge PD)
The precharge power-down (precharge PD) bit applies only
when precharge powerdown mode is being used. When
MR0[12] is set to 0, the DLL is off during precharge powerdown, providing a lower standby current mode; however,
tXPDLL must be satisfied when exiting. When MR0[12] is set
to 1, the DLL continues to run during precharge power-down
mode to enable a faster exit of precharge power-down mode;
however, tXP must be satisfied when exiting (see “Power-Down
Mode” on page 99).
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
61
Form #: CSI-D-685 Document 009
CAS Latency (CL)
CAS latency (CL) is defined by MR0[6:4], as shown in Figure 52 (page 136). CAS latency
is the delay, in clock cycles, between the internal READ command and the availability of
the first bit of output data. CL can be set to 5 through 14. DDR3 SDRAM do not support
half-clock latencies.
2Gb SDRAM-DDR3L
Examples of CL = 6 and CL = 8 are shown below. If anMYX4DDR3L128M16JT*
internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m. See Speed*Advanced
Bin Tables
for theSubject
CLs supported
at notice.
information.
to change without
various operating frequencies.
Figure 24: READ Latency
Figure 53: READ Latency
T0
T1
T2
T3
T4
T5
T6
T7
T8
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
AL = 0, CL = 6
DQS, DQS#
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
T0
T1
T2
T3
T4
T5
T6
T7
T8
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
AL = 0, CL = 8
DQS, DQS#
DI
n
DQ
Transitioning Data
Don’t Care
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal tDQSCK and nominal tDSDQ.
1. For illustration purposes, only CL = 6 and CL = 8 are shown.
Other CL values are possible.
Notes:
Notes:
2. Shown with nominal tDQSCK and nominal tDSDQ.
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
138
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
62
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb: x4, x8, x16 DDR3L SDRAM
2Gb
SDRAM-DDR3L
Mode
Register 1 (MR1)
MYX4DDR3L128M16JT*
Mode Register 1 (MR1)
*Advanced information. Subject to change without notice.
The mode register 1 (MR1) controls additional functions and features not available in
other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration
Mode Register 1the(MR1)
only), DLL ENABLE/DLL DISABLE, RTT,nom value (ODT), WRITE LEVELING, POSTED
The mode register 1 (MR1)
additional
functions
or until
the device
loses power.
Reprogramming
thecontrolMR1
CAS controls
ADDITIVE
latency,
and and
OUTPUT
DRIVE
STRENGTH.
These
functions are
features not available led
in the
other
mode
registers:
Q
OFF
register
will
not
alter
the
contents
of
the
memory
array,
provided
via the bits shown in Figure 54 (page 139). The MR1 register is programmed via the
(OUTPUT DISABLE), TDQS (for the x8 configuration only),
it is performed correctly.
MRS command and retains the stored
information until it is reprogrammed, until REDLL ENABLE/DLL DISABLE, RTT,nom value (ODT), WRITE
SET# goes LOW, or until the deviceThe
loses
power.
Reprogramming
the MR1
register
will
MR1
register
must be loaded when
all banks
are idle
LEVELING, POSTED CAS ADDITIVE latency, and OUTPUT
not
alter
the
contents
of
the
memory
array,
provided
it
is
performed
correctly.
and
no
bursts
are
in
progress.
The
controller
must
satisfy
the
DRIVE STRENGTH. These functions are controlled via the
specified timing parameters tMRD and tMOD before initiating a
bits shown in Figure The
25 (page
The must
MR1 register
is when
MR1 63).
register
be loaded
all banks are idle and no bursts are in progress.
subsequent operation.
programmed via the MRS
command
and
retains
the
stored
The controller must satisfy the specified timing parameters tMRD and tMOD before iniinformation until it is reprogrammed,
until RESET#operation.
goes LOW,
tiating a subsequent
Figure
25: Mode
Register11 (MR1)
(MR1) Definition
igure 54:
Mode
Register
Definition
DLL
BA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
A1 A0
Address bus
18 17 16 15 14 13 12 11 10 9 8 7 6 5
01 0 1 01 01 01 Q Off TDQS 01 RTT 01 WL RTT ODS
4 3 2
1 0
AL RTT ODS DLL
Mode register 1 (MR1)
Mode Register
M17 M16
0
0
Mode register set 0 (MR0)
M12
Q Off
M11
TDQS
0
1
Mode register set 1 (MR1)
0
Enabled
0
Disabled
1
0
Mode register set 2 (MR2)
1
Disabled
1
Enabled
1
1
Mode register set 3 (MR3)
R TT,nom
(ODT) 2
M0
DLL Enable
0
Enable (normal)
1
Disable
M5 M1 Output Drive St rength
R TT,nom
(ODT) 3
M7 Write Levelization
M9 M6 M2
Non- Writes
Writes
0
Disable (normal)
0 0 0
R TT,nom disabled
R TT,nom disabled
1
Enable
0 0 1
RZQ/4 (60Ω [NOM])
RZQ/4 (60Ω [NOM])
0
0
RZQ/6 (40Ω [NOM])
0
1
RZQ/7 (34Ω [NOM])
1
0
Reserved
1
1
Reserved
0 1 0 RZQ/2 (120Ω [NOM]) RZQ/2 (120Ω [NOM])
0 1 1
RZQ/6 (40Ω [NOM])
RZQ/6 (40Ω [NOM])
M4 M3 Additive Latency (AL)
1 0 0 RZQ/12 (20Ω [NOM])
n/a
0
0
Disabled (AL = 0)
1 0 1
RZQ/8 (30Ω [NOM])
n/a
0
1
AL = CL - 1
1 1 0
Reserved
Reserved
1
0
AL = CL - 2
1 1 1
Reserved
Reserved
1
1
Reserved
1. MR1[18, 15:13, 10, 8] are reserved for future use and must be programmed to 0.
2. During write leveling, if MR1[7] and MR1[12] are 1, then all RTT,nom values are available
1. MR1[18, 15:13, 10, 8] are reserved for future use and must be
for use.
programmed to 0.
3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only RTT,nom write values
2. During write leveling, if MR1[7] and MR1[12] are 1, then all
are available for use.
R
values are available for use.
Notes:
Notes:
TT,nom
3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then
Enable/DLL
only RTT,nom Disable
write values are available for use.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE
command, as shown in Figure 54 (page 139). The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to nor63
mal operation after having disabled
the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using the approForm #: CSI-D-685 Document 009
priate LOAD MODE command.
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
The output impedance is set during initialization. Additional
impedance calibration updates do not affect device operation,
and all data sheet timings and current specifications are met
during an update.
DLL Enable/DLL Disable
The DLL may be enabled or disabled by programming MR1[0]
during the LOAD MODE command, as shown in Figure 25
(page 63). The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization and upon
returning to normal operation after having disabled the DLL
for the purpose of debugging or evaluation. Enabling the DLL
should always be followed by resetting the DLL using the
appropriate LOAD MODE command.
To meet the 34Ω specification, the output drive strength must
be set to 34Ω during initialization. To obtain a calibrated output
driver impedance after power-up, the DDR3 SDRAM needs a
calibration command that is part of the initialization and reset
procedure.
OUTPUT ENABLE/DISABLE
If the DLL is enabled prior to entering self refresh mode, the
DLL is automatically disabled when entering SELF REFRESH
operation and is automatically reenabled and reset upon exit
of SELF REFRESH operation. If the DLL is disabled prior to
entering self refresh mode, the DLL remains disabled even
upon exit of SELF REFRESH operation until it is reenabled and
reset.
The OUTPUT ENABLE function is defined by MR1[12], as
shown in Figure 25 (page 63). When enabled (MR1[12] = 0),
all outputs (DQ, DQS, DQS#) function when in the normal mode
of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM
outputs (DQ and DQS, DQS#) are tri-stated. The output disable
feature is intended to be used during IDD characterization of the
READ current and during tDQSS margining (write leveling) only.
The DRAM is not tested to check—nor does Micron warrant
compliance with—normal mode timings or functionality when
the DLL is disabled. An attempt has been made to have the
DRAM operate in the normal mode where reasonably possible
when the DLL has been disabled; however, by industry
standard, a few known exceptions are defined:
TDQS Enable
Termination data strobe (TDQS) is a feature of the x8 DDR3
SDRAM configuration that provides termination resistance
(RTT) and may be useful in some system configurations. TDQS
is not supported in x4 or x16 configurations. When enabled via
the mode register (MR1[11]), the RTT that is applied to DQS and
DQS# is also applied to TDQS and TDQS#. In contrast to the
RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the
termination resistance RTT only. The OUTPUT DATA STROBE
function of RDQS is not provided by TDQS; thus, RON does
not apply to TDQS and TDQS#. The TDQS and DM functions
share the same ball. When the TDQS function is enabled via
the mode register, the DM function is not supported. When the
TDQS function is disabled, the DM function is provided, and
the TDQS# ball is not used. The TDQS function is available in
the x8 DDR3 SDRAM configuration only and must be disabled
via the mode register for the x4 and x16 configurations.
• ODT is not allowed to be used
• The output data is no longer edge-aligned to the clock
• CL and CWL can only be six clocks
When the DLL is disabled, timing and functionality can vary
from the normal operation specifications when the DLL is
enabled (see “DLL Disable Mode” on page 42). Disabling
the DLL also implies the need to change the clock frequency
(see “Input Clock Frequency Change” on page 46).
Output Drive Strength
The DDR3 SDRAM uses a programmable impedance output
buffer. The drive strength mode register setting is defined by
MR1[5, 1]. RZQ/7 (34Ω [NOM]) is the primary output driver
impedance setting for DDR3 SDRAM devices. To calibrate the
output driver impedance, an external precision resistor (RZQ)
is connected between the ZQ ball and VSSQ. The value of the
resistor must be 240Ω ±1%.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
64
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
On-Die Termination
POSTED CAS ADDITIVE Latency
ODT resistance RTT,nom is defined by MR1[9, 6, 2] (see Figure
25 on page 63). The RTT termination value applies to the DQ,
DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3 supports
multiple RTT termination values based on RZQ/n where n can
be 2, 4, 6, 8, or 12 and RZQ is 240Ω
POSTED CAS ADDITIVE latency (AL) is supported to make the
command and data bus efficient for sustainable bandwidths in
DDR3 SDRAM. MR1[4, 3] define the value of AL, as shown in
Figure 26 (page 66). MR1[4, 3] enable the user to program
the DDR3 SDRAM with AL = 0, CL - 1, or CL - 2.
Unlike DDR2, DDR3 ODT must be turned off prior to reading
data out and must remain off during a READ burst. RTT,nom
termination is allowed any time after the DRAM is initialized,
calibrated, and not performing read access, or when it is not
in self refresh mode. Additionally, write accesses with dynamic
ODT enabled (RTT(WR)) temporarily replaces RTT,nom with
RTT(WR).
With this feature, the DDR3 SDRAM enables a READ or WRITE
command to be issued after the ACTIVATE command for that
bank prior to tRCD (MIN). The only restriction is ACTIVATE
to READ or WRITE + AL ≥ tRCD (MIN) must be satisfied.
Assuming tRCD (MIN) = CL, a typical application using this
feature sets AL = CL - 1tCK = tRCD (MIN) - 1 tCK. The READ
or WRITE command is held for the time of the AL before it is
released internally to the DDR3 SDRAM device. READ latency
(RL) is controlled by the sum of the AL and CAS latency (CL),
RL = AL + CL. WRITE latency (WL) is the sum of CAS WRITE
latency and AL, WL = AL + CWL (see “Mode Register 2 (MR2)”
on page 66). Examples of READ and WRITE latencies are
shown in Figure 26 (page 66) and Figure 28 (page 67).
The actual effective termination, RTT(EFF), may be different
from the RTT targeted due to nonlinearity of the termination.
For RTT(EFF) values and calculations (see “On-Die Termination
(ODT)” on page 108).
The ODT feature is designed to improve signal integrity of the
memory channel by enabling the DDR3 SDRAM controller
to independently turn on/off ODT for any or all devices. The
ODT input control pin is used to determine when RTT is turned
on (ODTL on) and off (ODTL off), assuming ODT has been
enabled via MR1[9, 6, 2]. Timings for ODT are detailed in “OnDie Termination (ODT)” on page 108.
WRITE LEVELING
The WRITE LEVELING function is enabled by MR1[7], as
shown in Figure 25 (page 63). Write leveling is used (during
initialization) to deskew the DQS strobe to clock offset as a
result of fly-by topology designs. For better signal integrity,
DDR3 SDRAM memory modules adopted fly-by topology for
the commands, addresses, control signals, and clocks.
The fly-by topology benefits from a reduced number of stubs
and their lengths. However, fly-by topology induces flight
time skews between the clock and DQS strobe (and DQ) at
each DRAM on the DIMM. Controllers will have a difficult time
maintaining tDQSS, tDSS, and tDSH specifications without
supporting write leveling in systems which use fly-by topologybased modules. Write leveling timing and detailed operation
information is provided in “Write Leveling” on page 48.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
65
Form #: CSI-D-685 Document 009
2Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 2 (MR2)
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS
WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 142)). Examples of READ and WRITE latencies are shown in Figure 55 (page 142) and Figure 57
(page 143).
*Advanced information. Subject to change without notice.
Figure
READ
Latency
==
5, 6)
CL = 6)
Figure
26:55:
READ
Latency
(AL =(AL
5, CL
BC4
CK#
T0
T1
ACTIVE n
READ n
T2
T6
T11
T12
T13
T14
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
tRCD
(MIN)
DQS, DQS#
AL = 5
CL = 6
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
RL = AL + CL = 11
Indicates break
in time scale
Transitioning Data
Don’t Care
Mode Register 2 (MR2)
Mode Register 2 (MR2)
The mode register 2 (MR2) controls
additional
functions
until
it is programmed
or until the
loses
The mode
register
2 (MR2)and
controls
additional
functionsagain
and features
notdevice
available
in power.
features not available in thethe
other
mode
registers.
Reprogramming
theare
MR2
register
not alter
the contents
other
mode
registers.These
These additional
functions
CAS
WRITEwill
latency
(CWL),
AUadditional functions are CAS WRITE
latency
(CWL), AUTO
of the memory
array, provided
is performed
correctly.
TO SELF
REFRESH
(ASR),SELF
SELF REFRESH
TEMPERATURE
(SRT),it and
DYNAMIC
ODT The
REFRESH (ASR), SELF REFRESH
(SRT),
MR2 register
loaded
when all
are idle
(RTT(WR)TEMPERATURE
). These functions
are controlled
via themust
bits be
shown
in Figure
56.banks
The MR2
is and no
via are
the controlled
MRS command
will
retain
the
stored
information
until
it
is wait the
and DYNAMIC ODT (RTT(WR)).programmed
These functions
dataand
bursts
are
in
progress,
and
the
controller
must
2Gb: x4, x8, x16 DDR3L SDRAM
t
t
programmed
again
or
until
the
device
loses
power.
Reprogramming
the
MR2
register
via the bits shown in Figure 27. The MR2 is programmed
specified time MRD and
MOD before
initiating2a (MR2)
subsequent
Mode
Register
willretain
not alter
the contents
of the memory
array, provided it is performed correctly. The
via the MRS command and will
the stored
information
operation.
MR2 register must be loaded when all banks are idle and no data bursts are in progress,
Figure 56: Mode Register 2 (MR2)
and theDefinition
controller must wait the specified time tMRD and tMOD before initiating a subBA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
Figure 27: Mode Register 2 sequent operation.
(MR2) Definition
18 17 16 15 14 13 12 11 10 9 8 7 6
0 01 01 01 01 01 RTT(WR) 01 SRT ASR
5
01 1
M17 M16
Mode Register
1
0
M5 M4 M3
Mode register 2 (MR2)
CAS Write Latency (CWL)
5 CK (tCK ≥ 2.5ns)
6 CK (2.5ns > tCK ≥ 1.875ns)
Mode register set 0 (MR0)
0 Normal (0°C to 85°C)
0
0
0
0
1
Mode register set 1 (MR1)
1 Extended (≥85°C to 95°C)
0
0
1
1
0
Mode register set 2 (MR2)
0
1
0
7 CK (1.875ns > tCK ≥ 1.5ns)
1
1
Mode register set 3 (MR3)
0
1
1
1
0
0
8 CK (1.5ns > tCK ≥ 1.25ns)
9 CK (1.25ns > tCK ≥ 1.071ns)
1
0
1 10 CK (1.071ns > t CK ≥ 0.938ns)
1
1
0
Reserved
1
1
1
Reserved
M10 M9
Dynamic ODT
(R TT(WR) )
M6
Auto Self Refresh
(Optional)
0
Disabled: Manual
RTT(WR) disabled
0
0
0
1
RZQ/4 (60 [NOM])
1
0
RZQ/2 (120 [NOM])
1
1
1 Enabled: Automatic
Reserved
Micron Technology, Inc. reserves the right to change products or specifications without notice.
142
© 2010 Micron Technology, Inc. All rights reserved.
1. MR2[18, 15:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
MYX4DDR3L128M16JT*
CAS Write
Latency (CWL)
Revision 1.5 - 10/30/14
2
01 01 01
0
1. MR2[18, 15:11, 8, and
2:0] are reserved for
future use and must all be
programmed to 0.
Note:
3
0
Note:
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
M7 Self Refresh Temperature
4
CWL
66
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
#: CSI-D-685
internal write to the latching of the first data in. CWL must be correctly set toForm
the
corre-Document 009
0
Mode register set 0 (MR0)
0 Normal (0°C to 85°C)
0
0
0
0
1
Mode register set 1 (MR1)
1 Extended (≥85°C to 95°C)
0
0
1
1
0
Mode register set 2 (MR2)
0
1
0
7 CK (1.875ns > tCK ≥ 1.5ns)
1
1
Mode register set 3 (MR3)
0
1
1
1
0
0
8 CK (1.5ns > tCK ≥ 1.25ns)
9 CK (1.25ns > tCK ≥ 1.071ns)
1
0
M10 M9
CAS Write Latency (CWL)
Note:
5 CK (tCK ≥ 2.5ns)
6 CK (2.5ns > tCK ≥ 1.875ns)
0
Dynamic ODT
(R TT(WR) )
RTT(WR) disabled
0
0
0
1
RZQ/4 (60 [NOM])
1
0
RZQ/2 (120 [NOM])
1
1
M6
Auto Self Refresh
(Optional)
0
Disabled: Manual
1 Enabled: Automatic
1 10 CK (1.071ns > t CK ≥ 0.938ns)
2Gb
SDRAM-DDR3L
1 1 0
Reserved
1 1 1
Reserved
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Reserved
1. MR2[18, 15:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
CWL
defined by
MR2[5:3] (CWL)
and is the delay, in clock cycles,
CASis Write
Latency
from the releasing of the internal write to the latching of the
CWL isset
defined
MR2[5:3] and is the delay, in clock cycles, from the releasing of the
first data in. CWL must be correctly
to theby
corresponding
internal
write
to
the
of the first data in. CWL must be correctly set to the correoperating clock frequency (see Figure 27 (page latching
66)). The
sponding operating clock frequency (see Figure 56 (page 143)). The overall WRITE laoverall WRITE latency (WL) is equal to CWL + AL (Figure 25
tency (WL) is equal to CWL + AL (Figure 54 (page 139)).
(page 63)).
Figure
CAS
Write
Latency
Figure
28:57:
CAS
Write
Latency
CK#
T0
T1
ACTIVE n
WRITE n
T2
T6
T11
T12
T13
T14
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
tRCD
(MIN)
DQS, DQS#
AL = 5
CWL = 6
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
WL = AL + CWL = 11
Indicates break
in time scale
AUTO
SELF
REFRESH
AUTO
SELF
REFRESH
(ASR) (ASR)
Transitioning Data
Don’t Care
SELF REFRESH TEMPERATURE (SRT)
Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,
Mode register MR2[6] is used
to disable/enable
ASR rateMode
register
MR2[7]
used 85°C
to disable/enable
the self
refresh mode’sthe
refresh
is assumed
to be
at theisnormal
limit (some- the SRT
function. When ASR is disabled,
the referred
self refresh
refreshrate).function.
When SRT
is disabled,
the selfthe
refresh
times
to mode’s
as 1x refresh
In the disabled
mode,
ASR requires
usermode’s
to en- refresh
rate is assumed to be at the normal 85°C limit (sometimes
rate is assumed to be at the normal 85°C limit (sometimes
referred to as 1x refresh rate). In the disabled mode, ASR
referred to as 1x refresh rate). In the disabled mode, SRT
requires the user to ensure the DRAM never exceeds a TC
requires the user to ensure the DRAM never exceeds a TC of
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
143
2Gb_DDR3L.pdf
Rev.
K
9/13
EN
© 2010
Micron Technology,
Inc. All
rights reserved.
of 85°C while in self refresh unless the user enables the SRT
85°C while in self refresh mode
unless
the user
enables
ASR.
feature listed below when the TC is between 85°C and 95°C.
When SRT is enabled, the DRAM self refresh is changed
Enabling ASR assumes the DRAM self refresh rate is changed
internally from 1x to 2x, regardless of the case temperature.
automatically from 1x to 2x when the case temperature
This enables the user to operate the DRAM beyond the
exceeds 85°C. This enables the user to operate the DRAM
standard 85°C limit up to the optional extended temperature
beyond the standard 85°C limit up to the optional extended
range of 95°C while in self refresh mode. The standard self
temperature range of 95°C while in self refresh mode.
refresh current test specifies test conditions to normal case
temperature (85°C) only, meaning if SRT is enabled, the
The standard self refresh current test specifies test conditions
standard self refresh current specifications do not apply (see
to normal case temperature (85°C) only, meaning if ASR is
“Extended Temperature Usage” on page 98).
enabled, the standard self refresh current specifications do not
apply (see “Extended Temperature Usage” on page 98).
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
67
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Dynamic ODT is only applicable during WRITE cycles. If ODT
(RTT,nom) is disabled, dynamic ODT (RTT(WR)) is still permitted.
RTT,nom and RTT(WR) can be used independent of one other.
Dynamic ODT is not available during write leveling mode,
regardless of the state of ODT (RTT,nom). For details on dynamic
ODT operation, refer to “Dynamic ODT” on page 111.
SRT vs. ASR
If the normal case temperature limit of 85°C is not exceeded,
then neither SRT nor ASR is required, and both can be disabled
throughout operation. However, if the extended temperature
option of 95°C is needed, the user is required to provide a 2x
refresh rate during (manual) refresh and to enable either the
SRT or the ASR to ensure self refresh is performed at the 2x
rate.
SRT forces the DRAM to switch the internal self refresh rate
from 1x to 2x. Self refresh is performed at the 2x refresh rate
regardless of the case temperature.
ASR automatically switches the DRAM’s internal self refresh
rate from 1x to 2x. However, while in self refresh mode, ASR
enables the refresh rate to automatically adjust between
1x to 2x over the supported temperature range. One other
disadvantage with ASR is the DRAM cannot always switch
from a 1x to a 2x refresh rate at an exact case temperature of
85°C. Although the DRAM will support data integrity when it
switches from a 1x to a 2x refresh rate, it may switch at a lower
temperature than 85°C.
Since only one mode is necessary, SRT and ASR cannot be
enabled at the same time.
DYNAMIC ODT
The dynamic ODT (RTT(WR)) feature is defined by MR2[10, 9].
Dynamic ODT is enabled when a value is selected. This new
DDR3 SDRAM feature enables the ODT termination value
to change without issuing an MRS command, essentially
changing the ODT termination on-the-fly.
With dynamic ODT (RTT(WR)) enabled, the DRAM switches
from normal ODT (RTT,nom) to dynamic ODT (RTT(WR)) when
beginning a WRITE burst and subsequently switches back to
ODT (RTT,nom) at the completion of the WRITE burst. If RTT,nom
is disabled, the RTT,nom value will be High-Z. Special timing
parameters must be adhered to when dynamic ODT (RTT(WR))
is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4,
ODTH8, and tADC.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
68
Form #: CSI-D-685 Document 009
namic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8,
and tADC.
Dynamic ODT is only applicable during WRITE cycles. If ODT (R TT,nom) is disabled, dynamic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent of
one other. Dynamic ODT is not available during write leveling
mode,
regardless of the
2Gb
SDRAM-DDR3L
state of ODT (RTT,nom). For details on dynamic ODT operation,
refer to Dynamic ODT
MYX4DDR3L128M16JT*
(page 193).
*Advanced information. Subject to change without notice.
e Register 3 (MR3)
Mode Register 3 (MR3)
The mode register 3 (MR3) controls additional functions and features not available in
The mode register
(MR3)mode
controlsregisters.
additional Currently
functions anddefined
will not
alter MULTIPURPOSE
the contents of the memory
array, provided
the3other
is the
REGISTER
(MPR).it is
features not available
in
the
other
mode
registers.
Currently
performed
correctly.
The
MR3
register
must
be
loaded
when
This function is controlled via the bits shown in Figure 58 (page 145). The MR3 is prodefined is the MULTIPURPOSE REGISTER (MPR). This function
all banks are idle and no data bursts are in progress, and the
grammed via the LOAD MODE command
and retains the stored information until it is
is controlled via the bits shown in Figure 29 (page 69). The
controller must wait the specified time tMRD and tMOD before
programmed again or until the device loses power. Reprogramming the MR3 register
MR3 is programmed via the LOAD MODE command and
initiating a subsequent operation.
will not alter the contents of the memory array, provided it is performed correctly. The
retains the stored information until it is programmed again or
register
must be loaded
all banks are idle and no data bursts are in progress,
until the device MR3
loses power.
Reprogramming
the MR3when
register
and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation.
Figure 29: Mode Register 3 (MR3) Definition
58: Mode Register 3 (MR3) Definition
BA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8
18 17 16
01 1 1
A7 A6 A5
A4 A3
A2
A1 A0
15 14 13 12 11 10 9
8 7
6
5
4
3
2
1 0
01 01 01 01 01 01 01 01 01 01 01 01 01 MPR MPR_RF
Address bus
Mode register 3 (MR3)
M2
MPR Enable
0
0
Mode register set (MR0)
0
Normal DRAM operations2
0
0
MPR READ Function
Predefined pattern3
0
1
Mode register set 1 (MR1)
1
Dataflow from MPR
0
1
Reserved
1
0
Mode register set 2 (MR2)
1
0
Reserved
1
1
Mode register set 3 (MR3)
1
1
Reserved
M17 M16
Mode Register
M1 M0
1. MR3[18 and 15:3] are reserved for future use and must all be programmed to 0.
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
1. MR3[18 and 15:3]
are reserved to
for be
future
use and
all be
3. Intended
used
formust
READ
synchronization.
Notes:
Notes:
programmed to 0.
2. When MPR control is set for normal DRAM operation, MR3[1,
0] will be ignored.
IPURPOSE REGISTER (MPR)
3. Intended toThe
be used
for READ synchronization.
MULTIPURPOSE
REGISTER
function is used to output a predefined system timing
calibration bit sequence. Bit 2 is the master bit that enables or disables access to the
MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic
concept of the multipurpose register is shown in Figure 59 (page 146).
If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normal
mode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read data
but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to 00, then a predefined read pattern for system calibration is selected.
To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks are precharged,
83ed2952
f - Rev. K 9/13MYX4DDR3L128M16JT*
EN
Revision 1.5 - 10/30/14
145
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
69
Form #: CSI-D-685 Document 009
2Gb: x4, x8, x16
Mode Re
and tRP is met). When the MPR is enabled, any subsequent READ or
are redirected to the multipurpose register. The resulting operation w
or a RDAP command is issued, is defined by MR3[1:0] when the MPR
Table 77 (page 147)). When the MPR is enabled, only READ or RDAP
lowed until a subsequent MRS command is issued with the MPR dis
Power-down mode,
self refresh,
and
anytoother
nonREAD/RDAP
com
*Advanced
information.
Subject
change
without notice.
lowed during MPR enable mode. The RESET function is supported d
mode.
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
Figure 30: Multipurpose Register (MPR) Block Diagram
MULTIPURPOSE REGISTER (MPR)
Figure 59: Multipurpose Register (MPR) Block Diagram
The MULTIPURPOSE REGISTER function is used to output a
predefined system timing calibration bit sequence. Bit 2 is the
master bit that enables or disables access to the MPR register,
Memory core
and bits 1 and 0 determine which mode the MPR is placed
in. The basic concept of the multipurpose register is shown in
Figure 30 (page 70).
If MR3[2] is a 0, then the MPR access is disabled, and the
DRAM operates in normal mode. However, if MR3[2] is a 1,
then the DRAM no longer outputs normal read data but outputs
MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to
00, then a predefined read pattern for system calibration is
selected.
MR3[2] = 0 (MPR off)
Multipurpose register
predefined data for READs
MR3[2] = 1 (MPR on)
To enable the MPR, the MRS command is issued to MR3, and
DQ, DM, DQS, DQS#
MR3[2] = 1. Prior to issuing the MRS command, all banks must
be in the idle state (all banks are precharged, and tRP is met).
Notes: 1. A predefined data pattern can be read out of the MPR with an exte
When the MPR is enabled, any subsequent READ or RDAP
mand.
Notes:
commands are redirected to the multipurpose register. The
2. MR3[2] defines whether the data flow comes from the memory cor
1. A predefined data pattern can be read out of the MPR with an
the data flow is defined, the MPR contents can be read out continu
resulting operation when either a READ or a RDAP command
external
READ
orREAD
RDAPcommand.
command.
is issued, is defined by MR3[1:0] when the MPR is enabled
2. MR3[2] defines whether the data flow comes from the memory
(see Table 30 on page 71). When the MPR is enabled, only
core or the MPR. When the data flow is defined, the MPR
Table
76:a MPR
Functional Description of MR3 Bits
READ or RDAP commands are allowed
until
subsequent
contents can be read out continuously with a regular READ or
MRS command is issued with the MPR disabled (MR3[2] =
MR3[2]
MR3[1:0] RDAP command.
0). Power-down mode, self refresh, and any other nonREAD/
READ Function
Function
RDAP commands are not allowed during MPR
MPR enable MPR
mode.
0 enable mode.“Don’t Care”
Normal operation, no MPR transactio
The RESET function is supported during MPR
All subsequent READs come from the DRAM me
All subsequent WRITEs go to the DRAM mem
1
Table 29: MPR Functional Description of MR3 Bits
A[1:0]
(see Table 77 (page 147))
MPR Functional Description
MR3[2]
MR3[1:0]
MPR
MPR READ Function
0
“Don’t Care”
1
A[1:0] (see Table 30 on
page 71)
Function
The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4
DQ0 = lower byte and DQ8 = upper byte) to output the MPR data wit
operation,
no MPR
transaction
DQs Normal
driven
LOW, or
for all
DQs to output the MPR data . The MPR re
All subsequent
READs
come and
from the
DRAMburst
memory
array (MRS and OTF via A12/BC#)
fixed READ
burst
READ
chop
Alllatencies
subsequentand
WRITEs
to the DRAM
memory array
ACgotimings
applicable,
provided the DLL is locked as r
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2
146
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
Enable MPR mode, subsequent READ/RDAP commands d
2
Micron Technology, Inc. reserves the right to change pr
© 2010 Mic
70
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
MPR Functional Description
• Burst order bit 0 (the first bit) is assigned to LSB,
and burst order bit 7 (the last bit) is assigned to MSB
The MPR JEDEC definition enables either a prime DQ (DQ0 on
a x4 and a x8; on a x16, DQ0 = lower byte and DQ8 = upper
byte) to output the MPR data with the remaining DQs driven
LOW, or for all DQs to output the MPR data . The MPR readout
supports fixed READ burst and READ burst chop (MRS and
OTF via A12/BC#) with regular READ latencies and AC timings
applicable, provided the DLL is locked as required.
• A[9:3] are a “Don’t Care”
MPR addressing for a valid MPR read is as follows:
• BA[2:0] are a “Don’t Care”
• A10 is a “Don’t Care”
• A11 is a “Don’t Care”
• A12: Selects burst chop mode on-the-fly, if enabled
within MR0
• A13 is a “Don’t Care”
• A[1:0] must be set to 00 as the burst order is fixed
per nibble
MPR Register Address Definitions and Bursting Order
• A2 selects the burst order:
The MPR currently supports a single data format. This data
format is a predefined read pattern for system calibration.
The predefined pattern is always a repeating 0–1 bit pattern.
Examples of the different types of predefined READ pattern
bursts are shown in the following figures.
ƒƒ BL8, A2 is set to 0, and the burst order is fixed
to 0, 1, 2, 3, 4, 5, 6, 7
• For burst chop 4 cases, the burst order is switched
on the nibble base along with the following:
ƒƒ A2 = 0; burst order = 0, 1, 2, 3
ƒƒ A2 = 1; burst order = 4, 5, 6, 7
Table 30: MPR Readouts and Burst Order Bit Mapping
MR3[2]
MR3[1:0]
Function
Burst Read
Length A[2:0]
BL8
1
0
1
1
1
10
1
11
READ predefined pattern for system calibration
RFU
0
BC4
Burst Order and Data Pattern
Burst order: 0, 1, 2, 3, 4, 5, 6, 7; Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1
Burst order: 0, 1, 2, 3; Predefined pattern: 0, 1, 0, 1
BC4
100
Burst order: 4, 5, 6, 7; Predefined pattern: 0, 1, 0, 1
N/A
N/A
N/A
Note:
1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is
assigned to MSB of the selected MPR agent.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
71
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
MPR Read Predefined Pattern
MODE REGISTER SET (MRS) Command
The predetermined read calibration pattern is a fixed pattern
of 0, 1, 0, 1, 0, 1, 0, 1. The following is an example of using
the read out predetermined read calibration pattern. The
example is to perform multiple reads from the multipurpose
register to do system level read timing calibration based on the
predetermined and standardized pattern.
The mode registers are loaded via inputs BA[2:0], A[13:0].
BA[2:0] determine which mode register is programmed:
• BA2 = 0, BA1 = 0, BA0 = 0 for MR0
• BA2 = 0, BA1 = 0, BA0 = 1 for MR1
• BA2 = 0, BA1 = 1, BA0 = 0 for MR2
The following protocol outlines the steps used to perform the
read calibration:
• BA2 = 0, BA1 = 1, BA0 = 1 for MR3
The MRS command can only be issued (or re-issued) when all
banks are idle and in the precharged state (tRP is satisfied and
no data bursts are in progress). The controller must wait the
specified time tMRD before initiating a subsequent operation
such as an ACTIVATE command (see Figure 21 on page 57).
There is also a restriction after issuing an MRS command with
regard to when the updated functions become available.
This parameter is specified by tMOD. Both tMRD and tMOD
parameters are shown in Figure 21 (page 57) and Figure 22
(page 58). Violating either of these requirements will result in
unspecified operation.
1. Precharge all banks
2. After tRP is satisfied, set MRS, MR3[2] = 1 and
MR3[1:0] = 00. This redirects all subsequent reads and
loads the predefined pattern into the MPR. As soon as
tMRD and tMOD are satisfied, the MPR is available
3. Data WRITE operations are not allowed until the MPR
returns to the normal DRAM state
4. Issue a read with burst order information (all other
address pins are “Don’t Care”):
• A[1:0] = 00 (data burst order is fixed starting at
nibble)
• A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4,
5, 6, 7)
• A12 = 1 (use BL8)
5. After RL = AL + CL, the DRAM bursts out the
predefined read calibration pattern
(0, 1, 0, 1, 0, 1, 0, 1)
6. The memory controller repeats the calibration reads
until read data capture at memory controller is
optimized
7. After the last MPR READ burst and after tMPRR
has been satisfied, issue MRS, MR3[2] = 0, and
MR3[1:0] = “Don’t Care” to the normal DRAM state.
All subsequent read and write accesses will be regular
reads and writes from/to the DRAM array
8. When tMRD and tMOD are satisfied from the last
MRS, the regular DRAM commands (such as activate
a memory bank for regular read or write access) are
permitted
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
72
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
2Gb: x4,MYX4DDR3L128M16JT*
x8, x16 DDR3L SDRAM
ZQ CALIBRATION Operation
*Advanced information. Subject to change without notice.
ZQ CALIBRATION Operation
The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON)
ZQ CALIBRATION Operation
and ODT values (RTT) over process, voltage, and temperature, provided a dedicated
240Ω (±1%)
external
resistor isthe
connected
the DRAM’s
ZQ issuing
ball to Vanother
The ZQ CALIBRATION command
is used
to calibrate
other from
activities
(other than
ZQCL or ZQCS
SSQ.
DRAM output drivers (RON) and
ODT
values
(R
)
over
process,
command)
can
be
performed
on
the
DRAM
channel by the
TT
DDR3 SDRAM require
a longer time to calibrate RON and ODT at power-up initialization
t
t
voltage, and temperature, provided
a dedicated
240Ω
(±1%)
controller
for the
duration periodic
of ZQinitcalibrations.
or ZQoper. The quiet time
and self refresh
exit, and
a relatively
shorter
time
to perform
external resistor is connected
from
the
DRAM’s
ZQ
ball
to
on
the
DRAM
channel
helps
accurately
calibrate
RON and ODT.
DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS.
An example
VSSQ.
After
DRAM
calibration
is
achieved,
the
DRAM
should
disable
of ZQ calibration timing is shown below.
the
ZQ
ball’s
current
consumption
path
to
reduce
power.
All banks
be precharged
and tRP must be met before ZQCL or ZQCS commands
DDR3 SDRAM require a longer
time tomust
calibrate
RON and ODT
canself
berefresh
issued exit,
to the
DRAM.
No otherZQ
activities
(other than
issuingcan
another
ZQCL
at power-up initialization and
and
a relatively
CALIBRATION
commands
be issued
in or
parallel to DLL
ZQCS
command)
can
be
performed
on
the
DRAM
channel
by
the
controller
for
the
dushorter time to perform periodic calibrations.
DDR3
SDRAM
RESET
and
locking
time.
Upon
self
refresh
exit,
an explicit
ration of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately calidefines two ZQ CALIBRATION commands: ZQCL and ZQCS.
ZQCL is required if ZQ calibration is desired.
brate R and ODT. After DRAM calibration is achieved, the DRAM should disable the
An example of ZQ calibration timingON
is shown below.
ZQ ball’s current consumption path to
power.
In reduce
dual-rank
systems that share the ZQ resistor between
t
All banks must be precharged
and
RP
must
be
met
before
devices,
the
controller
must
not enable
overlap
of tZQinit,
ZQ CALIBRATION commands can be issued in parallel to DLL
RESET
and locking
time.
t
t
ZQCL or ZQCS commandsUpon
can be
issued
to
the
DRAM.
No
ZQoper,
or
ZQCS
between
ranks.
self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must not
enable overlap of tZQinit, tZQoper, or tZQCS between ranks.
Figure 31: ZQ CALIBRATION Timing (ZQCL and ZQCS)
Figure 64: ZQ CALIBRATION Timing (ZQCL and ZQCS)
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
ZQCL
NOP
NOP
NOP
Valid
Valid
ZQCS
NOP
NOP
NOP
Valid
Address
Valid
Valid
Valid
A10
Valid
Valid
Valid
CK#
CK
Command
CKE
1
Valid
Valid
1
Valid
ODT
2
Valid
Valid
2
Valid
DQ
3
Activities
3
High-Z
tZQinit
or tZQoper
High-Z
Activities
tZQCS
Indicates break
in time scale
Notes:
Don’t Care
1. CKE must be continuously registered HIGH during the
Notes: 1. CKE must be continuously registered HIGH during the calibration procedure.
calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during
the calibration procedure. 3. All devices connected to the DQ bus should be High-Z during calibration.
3. All devices connected to the DQ bus should be High-Z during
calibration.
MYX4DDR3L128M16JT*
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© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
ACTIVATE Operation
Before any READ or WRITE commands can be issued to a
bank within the DRAM, a row in that bank must be opened
(activated). This is accomplished via the ACTIVATE command,
which selects both the bank and the row to be activated.
After a row is opened with an ACTIVATE command, a READ
or WRITE command may be issued to that row, subject to
the tRCD specification. However, if the additive latency is
programmed correctly, a READ or WRITE command may be
issued prior to tRCD (MIN). In this operation, the DRAM enables
a READ or WRITE command to be issued after the ACTIVATE
command for that bank, but prior to tRCD (MIN) with the
requirement that (ACTIVATE-to-READ/WRITE) + AL ≥ tRCD
(MIN) (see Posted CAS Additive Latency). tRCD (MIN) should
be divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after the
ACTIVATE command on which a READ or WRITE command
can be entered. The same procedure is used to convert other
specification limits from time units to clock cycles.
When at least one bank is open, any READ-to-READ command
delay or WRITE-to-WRITE command delay is restricted to
tCCD (MIN).
A subsequent ACTIVATE command to a different row in the
same bank can only be issued after the previous active row
has been closed (precharged). The minimum time interval
between successive ACTIVATE commands to the same
bank is defined by tRC. A subsequent ACTIVATE command
to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access
overhead. The minimum time interval between successive
ACTIVATE commands to different banks is defined by tRRD.
No more than four bank ACTIVATE commands may be issued
in a given tFAW (MIN) period, and the tRRD (MIN) restriction still
applies. The tFAW (MIN) parameter applies, regardless of the
number of banks already opened or closed.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
74
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
2Gb: MYX4DDR3L128M16JT*
x4, x8, x16 DDR3L SDRAM
READ Operation
*Advanced information. Subject to change without notice.
READ Operation
READ Operation
READ bursts are initiated with a READ command. The starting column and bank adare provided
the READ
command
auto precharge
is either
enabled
or
READ bursts are initiated with adresses
READ command.
Thewith
starting
clocks
later. RLand
is defined
as the sum
of posted
CAS additive
disabled for that burst access. If auto precharge is enabled, the row being accessed is
column and bank addresses are provided with the READ
latency (AL) and CAS latency (CL) (RL = AL + CL). The value
automatically precharged at the completion of the burst. If auto precharge is disabled,
command and auto precharge is either enabled or disabled for
of AL and CL is programmable in the mode register via the
the row will be left open after the completion of the burst.
that burst access. If auto precharge is enabled, the row being
MRS command. Each subsequent data-out element is valid
DuringatREAD
bursts, theofvalid
element
frompositive
the starting
column
address
is is, at
accessed is automatically precharged
the completion
the data-out
nominally
at the next
or negative
clock
edge (that
available
is defined
theCK#).
sumFigure
of posted
CAS additive
burst. If auto precharge is disabled,
the READ
row willlatency
be left (RL)
openclocks
thelater.
next RL
crossing
of CKas
and
32 shows
an example
latency (AL) and CAS latency (CL)of(RL
AL + CL).
value of
andanCL
programmaafter the completion of the burst.
RL=based
on a The
CL setting
of AL
8 and
ALissetting
of 0.
ble in the mode register via the MRS command. Each subsequent data-out element is
valid
nominally
at the
nextthe
positive or negative clock edge (that is, at the next crossing
During READ bursts, the valid
data-out
element
from
CK and READ
CK#). Figure
shows an example of RL based on a CL setting of 8 and an AL
starting column address is of
available
latency67(RL)
setting of 0.
Figure
32: 67:
READ
Latency
Figure
READ
Latency
CK#
T0
T7
T8
T9
T10
T11
T12
T12
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
Address
Bank a,
Col n
CL = 8, AL = 0
DQS, DQS#
DQ
DO
n
Notes:
Indicates break
in time scale
1. DO n = data-out from column n.
Transitioning Data
Don’t Care
2. Subsequent elements of data-out appear in the programmed
order following DO n.Notes: 1. DO n = data-out from column n.
2. Subsequent elements of data-out appear in the programmed order following DO n.
DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on
DQS, DQS# is driven by the DRAM
with the
output
Data from
anyREAD
READpreamble
burst may(tRPRE).
be concatenated
with data
DQSalong
and HIGH
state
on data.
DQS# is known
as the
The LOW state
The initial LOW state on DQSon
and
HIGH
on DQS#
from acoincident
subsequent
READ
command
to provide
a is
continuous
DQS
andstate
the HIGH
stateison DQS#,
with
the last
data-out
element,
known as the READ preamble (tknown
RPRE). as
Thethe
LOW
state
on DQS (tRPST).
flow ofUpon
data.completion
The first data
element
from thenonew
burst
READ
postamble
of a burst,
assuming
other
tDQSQ
and the HIGH state on DQS#,commands
coincident with
lastinitiated,
data- the
follows
the last
element
of a completed
burst.of
The
new READ
havethe
been
DQ goes
High-Z.
A detailed
explanation
tQH (data-out window hold), and the valid
(validpostamble
data-out skew),
window
arefirst
de-READ
out element, is known as the READ
(tRPST).
Upon
command should be issued tCCDdata
cycles
after the
tDQSCK (DQS transition skew
picted
in
Figure
78
(page
165).
A
detailed
explanation
of
completion of a burst, assuming no other commands have
command. This is shown for BL8 in Figure 33 (page 77).
to CK)Aisdetailed
also depicted
in Figure
(pageis165).
been initiated, the DQ goes High-Z.
explanation
of 78
If BC4
enabled, tCCD must still be met, which will cause a
tDQSQ (valid data-out skew), tQH (data-out window hold), and
gap
in
the
data with
output,
shown
in Figure 34
(page 77).
Data from any READ burst may be concatenated
dataasfrom
a subsequent
READ
the valid data window are depicted
in Figure
43 (page
83). A
Nonconsecutive
READ
reflected
in Figure
35 (page
command
to provide
a continuous
flow of data. The
firstdata
data is
element
from
the new
detailed explanation of tDQSCKburst
(DQSfollows
transition
to CK) is of a78).
DDR3 SDRAM
does
notREAD
allow command
interruptingshould
or truncating
theskew
last element
completed
burst. The
new
be
command.
also depicted in Figure 43 (pageissued
83). tCCD cycles after the first READ
any READ
burst. This is shown for BL8 in Figure 68
(page 159). If BC4 is enabled, tCCD must still be met, which will cause a gap in the data
output, as shown in Figure 69 (page 159). Nonconsecutive READ data is reflected in
MYX4DDR3L128M16JT*
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75
157
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
READ Operation (continued)
Data from any READ burst must be completed before a
subsequent WRITE burst is allowed. An example of a READ
burst followed by a WRITE burst for BL8 is shown in Figure
36 (page 78) (BC4 is shown in Figure 37 (page 79)). To
ensure the READ data is completed before the WRITE data is
on the bus, the minimum READ-to-WRITE timing is RL + tCCD
- WL + 2tCK.
A READ burst may be followed by a PRECHARGE command
to the same bank, provided auto precharge is not activated.
The minimum READ-to-PRECHARGE command spacing to
the same bank is four clocks and must also satisfy a minimum
analog time from the READ command. This time is called tRTP
(READ-to-PRECHARGE). tRTP starts AL cycles later than the
READ command. Examples for BL8 are shown in Figure 38
(page 79) and BC4 in Figure 39 (page 80). Following the
PRECHARGE command, a subsequent command to the same
bank cannot be issued until tRP is met. The PRECHARGE
command followed by another PRECHARGE command to the
same bank is allowed. However, the precharge period will be
determined by the last PRECHARGE command issued to the
bank.
If A10 is HIGH when a READ command is issued, the READ
with auto precharge function is engaged. The DRAM starts
an auto precharge operation on the rising edge, which is AL
+ tRTP cycles after the READ command. DRAM support a
tRAS lockout feature (see Figure 41 on page 80). If tRAS
(MIN) is not satisfied at the edge, the starting point of the
auto precharge operation will be delayed until tRAS (MIN) is
satisfied. If tRTP (MIN) is not satisfied at the edge, the starting
point of the auto precharge operation is delayed until tRTP
(MIN) is satisfied. In case the internal precharge is pushed out
by tRTP, tRP starts at the point at which the internal precharge
happens (not at the next rising clock edge after this event). The
time from READ with auto precharge to the next ACTIVATE
command to the same bank is AL + (tRTP + tRP)*, where *
means rounded up to the next integer. In any event, internal
precharge does not start earlier than four clocks after the last
8n-bit prefetch.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
76
Form #: CSI-D-685 Document 009
2Gb_DDR3L.pdf
2Gb_DDR3L.pdf
- Rev. K 9/13
- Rev.
EN K 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
PDF: 09005aef83ed2952
Bank,
Col b
Col b
READ
Bank,
tRPRE
tRPRE
NOP
DO
n+1
DO
n+1
DO
n
DO
n
NOP
T6
NOP
DO
n+3
DO
n+3
RL = 5
DO
n+2
RL = 5
DO
n+2
DO
n+4
DO
n+4
NOP
T7
NOP
DO
n+5
DO
n+5
NOP
T8
NOP
T8
DO
n+6
DO
n+6
DO
n+7
DO
n+7
NOP
T9
NOP
T9
DO
b
DO
b
DO
b+1
DO
b+1
NOP
T10
NOP
T10
DO
b+2
DO
b+2
DO
b+3
DO
b+3
NOP
T11
NOP
T11
DO
b+4
DO
b+4
DO
b+5
DO
b+5
NOP
T12
NOP
T12
DO
b+6
DO
b+6
DO
b+7
DO
b+7
tRPST
tRPST
NOP
T13
NOP
T13
NOP
T14
NOP
T14
159 159
4.
3.
2.
1.
Bank,
Col n
Notes:
tCCD
RL = 5
RL = 5
NOP
T3
NOP
Bank,
Col b
Bank,
Col b
READ
T4
READ
tRPRE
tRPRE
NOP
T5
NOP
T5
DO
n
DO
n
DO
n+1
DO
n+1
NOP
T6
NOP
T6
RL = 5
DO
n+2
RL = 5
DO
n+2
DO
n+3
DO
n+3
tRPST
tRPST
NOP
T7
NOP
T7
NOP
T8
NOP
T8
tRPRE
tRPRE
NOP
T9
NOP
T9
DO
b
DO
b
DO
b+1
DO
b+1
NOP
T10
NOP
T10
DO
b+2
DO
b+2
DO
b+3
DO
b+3
tRPST
tRPST
NOP
T11
NOP
T11
NOP
T13
NOP
T13
Transitioning Data
NOP
T12
NOP
T12
Don’t Care
NOP
T14
NOP
T14
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
Transitioning Data
Don’t Care
2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0
NOP commandsNotes:
are shown
of illustration;
other commands
be valid other
at these
times. may be valid at these times.
andease
T4.
1. for
NOP
commands
are shown
for ease of may
illustration;
commands
3. by
DOeither
nBC4
(or setting
b) = data-out
column
(orand
column
The BC4 setting is activated
MR0[1:0]
10 from
or MR0[1:0]
=n01
A12
=b).
0or
during
READ= command
at=T0
and T4.READ command at T0
2.
The
is =
activated
by
either
MR0[1:0]
= 10
MR0[1:0]
01 and A12
0 during
and
4. column
BC4,T4.
RLn=(or
5 (CL
= 5, b).
AL = 0).
DO n (or b) = data-out from
column
3. DO n (or b) = data-out from column n (or column b).
BC4, RL = 5 (CL = 5, AL = 0).
4. BC4, RL = 5 (CL = 5, AL = 0).
Notes:
DQ3
DQ3
DQS, DQS#
Address2
DQS, DQS#
NOP
NOP
Bank,
Col n
READ
T2
NOP
Command1
Address2
T1
NOP
tCCD
T0
READ
CK
Command1
CK#
CK
T0
T1
T2
T3
T4
Figure
69:
Consecutive
READ
Bursts
(BC4)
CK#
Figure 34: Consecutive READ Bursts (BC4)
Figure 69: Consecutive READ Bursts (BC4)
3. DO n (or b) = data-out from column n (or column b).
Notes:
and T4.
1. NOP
commands are shown for ease of illustration; other commands may be valid at these times.
3. The
DO nBL8
(orsetting
b) = data-out
fromby
column
(or column
b).or MR0[1:0] = 01 and A12 = 1 during READ command at T0
2.
is activated
eithernMR0[1:0]
= 00
4. BL8, RL = 5 (CL = 5, AL =4.0).and
BL8, T4.
RL = 5 (CL = 5, AL = 0).
3. DO n (or b) = data-out from column n (or column b).
4. BL8, RL = 5 (CL = 5, AL = 0).
2. by
The
BL8 MR0[1:0]
setting is =
activated
by either
MR0[1:0]
==
001or
MR0[1:0]
01 and A12
1 and
during
2. The BL8 setting is activated
either
00 or MR0[1:0]
= 01
and A12
during
READ= command
at =T0
T4.READ command at T0
Don’t Care
RL = 5
RL = 5
NOP
T5
NOP
T7
1. NOP commandsNotes:
are shown
ease
of illustration;
other commands
be valid other
at these
times. may be valid at these times.
1. for
NOP
commands
are shown
for ease of may
illustration;
commands
Transitioning Data
tCCD
T4
READ
T6
Don’t Care
Bank,
Col n
NOP
T3
NOP
T5
Transitioning Data
Notes:
DQ3
DQ3
DQS, DQS#
Address2
DQS, DQS#
Col n
READ
Bank,
NOP
T2
NOP
Command21
Address
T1
NOP
tCCD
T0
READ
CK
Command1
CK#
CK
T1
T2
T3
T4
Figure
68:T0 Consecutive
READ
Bursts
(BL8)
CK#
Figure 33: Consecutive READ Bursts (BL8)
Figure 68: Consecutive READ Bursts (BL8)
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb:2Gb:
x4, x8,
x4, x16
x8, x16
DDR3L
DDR3L
SDRAM
SDRAM
READ
READ
Operation
Operation
*Advanced information. Subject to change without notice.
Micron Technology,
Micron Technology,
Inc. reserves
Inc.the
reserves
right to
the
change
right to
products
changeor
products
specifications
or specifications
without notice.
without notice.
© 2010 Micron
© 2010
Technology,
Micron Technology,
Inc. All rights
Inc.reserved.
All rights reserved.
77
Form #: CSI-D-685 Document 009
T0
T1
T2
T3
T4
T5
2Gb_DDR3L.pdf - Rev.
2Gb_DDR3L.pdf
K 9/13 EN - Rev. K 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
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NOP
Notes:
NOP
CL = 8
READ
Bank a,
Col b
1. AL = 0, RL = 8.
NOP
NOP
T6
NOP
T6
NOP
T7
NOP
T7
NOP
T8
NOP
T8
DO
n
DO
n
CL = 8
NOP
CL = 8
T9
NOP
T9
NOP
T10
NOP
T10
NOP
T11
NOP
T11
NOP
T12
NOP
T12
NOP
T13
NOP
T13
DO
b
DO
b
NOP
T14
NOP
T14
160
T0
T1
T2
T3
NOP
T4
Bank,
Col n
Col n
READ
Bank,
T1
T0
T2
NOP
T3
NOP
T4
T5
NOP
NOP
NOP
NOP
Notes:
RL = 5
RL = 5
READ-to-WRITE command delay = RL + tCCD
NOP
tRPRE
tRPRE
+ 2tCK -
WL
NOP
READ-to-WRITE command delay = RL + tCCD + 2tCK - WL
NOP
READ
T5
DO
DO
n
DO
DO
DO
DOBank,
n + Col
1 bn + 2
Col b
WRITE
Bank,
T6
WRITE
T6
DO
DO
n+3
DO
DO
n+4
NOP
T7
NOP
T7
DO
DO
n+5
DO
NOP
T9
NOP
T9
DO
tRPST
DO
n+7
tRPST
WL = 5
DO
n+6
NOP
T8
NOP
T8
NOP
T10
NOP
T10
tWPRE
tWPRE
DI
DI
n
NOP
T11
NOP
T11
DI
DI
n+1
tBL
tBL
DI
DI
DI
DI
n+2 n+3
NOP
T12
NOP
T12
DI
n+5
DI
DI
NOP
T16
NOP
T16
DI
n+6
NOP
T14
NOP
DI
DI
Don’t Care
tWPST
DI
n+7
tWR
tWPST t
WR
NOP
tWR
tWR
T15
NOP
T15
Transitioning Data
Transitioning Data
T14
Transitioning Data
DI
n+4
= 4 clocks
NOP
= 4 clocks
T13
NOP
T13
NOP
T15
NOP
T15
Don’t Care
Don’t Care
NOP
T17
NOP
T17
n+4 n+5 n+6 n+7
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
n+1 n+2 n+3
n
1. NOP commands are shown
for ease of illustration; other commands may
be
valid at these
times.
WL = 5
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at
Transitioning Data
Don’t Care
T0, and the WRITE command at T6.
Notes:
3. DO n = data-out from column, DI b = data-in for column b.
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
= 5 (AL = 0,other
CL = commands
5), WL = 5 (AL
0, valid
CWL at
= 5).
1. NOP commands are shown 4.
for BL8,
ease RL
of illustration;
may=be
these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at
2. The BL8 setting is activated by either
MR0[1:0]
=
00
or
MR0[1:0]
=
01
and
A12
=
1
during
the READ command at T0, and the WRITE command at T6.
T0, and the WRITE command at T6.
3. DO n = data-out from column,
b=
data-in
for column
b.
3. DI
DO
n=
data-out
from column,
DI b = data-in for column b.
BL8,
= 5= (AL
= 0, CL
= 5), WL = 5 (AL = 0, CWL = 5).
4. BL8, RL = 5 (AL = 0, CL = 5),4.WL
= 5RL(AL
0, CWL
= 5).
DQ3
DQS, DQS#
2
Address
DQ3
DQS, DQS#
1
Command
Address2
CK
CK#
Command
Figure
71: READ (BL8) to WRITE (BL8)
1
CK
Figure 36: READ (BL8) to WRITE (BL8)
CK#
Seven subsequent
elements of data-out appear in the programmed order following DO b.
4. Seven subsequent Notes:
elements4.
of data-out
appear
1.
AL = 0, RL
= 8. in the programmed order following DO b.
2. DO n (or b) = data-out from column n (or column b).
3. Seven
subsequent elements of data-out appear in the programmed order following DO n.
Figure 71: READ (BL8) to WRITE
(BL8)
4. Seven subsequent elements of data-out appear in the programmed order following DO b.
Seven subsequent
elements
of data-out
inDO
then.programmed order following DO n.
3. Seven subsequent elements3.
of data-out
appear in the
programmed
order appear
following
2. DO n (or b) = data-out from column
(or column
b).
2. DO nn (or
b) = data-out
from column n (or column b).
1. DQ
AL = 0, RL = 8.
Notes:
DQS, DQS#
DQ
READ
Bank a,
Col n
NOP
Address
Command
DQS, DQS#
T4
T5
T3
CL = 8
T2
T0
T1
Bank a,
Col b
Bank a,
Col n
CK
CK#
Address
Command
READ
NOP
NOP
NOP
NOP
READ
Figure
70:
Nonconsecutive
READ Bursts
CK
CK#
Figure 35: Nonconsecutive READ Bursts
Figure 70: Nonconsecutive READ Bursts
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4,
2Gb:
x8, x4,
x16x8,
DDR3L
x16 DDR3L
SDRAMSDRAM
READ
Operation
READ
Operation
*Advanced information. Subject to change without
notice.
Micron Technology,Micron
Inc. reserves
Technology,
the right
Inc.to
reserves
changethe
products
right toorchange
specifications
products
without
or specifications
notice. without notice.
160
© 2010 Micron Technology,
© 2010 Micron
Inc. AllTechnology,
rights reserved.
Inc. All rights reserved.
78
Form #: CSI-D-685 Document 009
T0
T1
T2
T3
T4
2Gb_DDR3L.pdf
2Gb_DDR3L.pdf
- Rev. K 9/13-EN
Rev. K 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
T1
NOP
T2
NOP
T3
NOP
T4
WRITE
Bank,
Col n
Notes:
RL = 5
RL = 5
tRPRE
Bank,
Col b
tRPRE
Bank,
Bank,
command delay = RL + tCCD/2 + 2tCK - WLCol b
ColREAD-to-WRITE
n
READ-to-WRITE command delay = RL + tCCD/2 + 2tCK - WL
READ
NOP
NOP
NOP
WRITE
T0
READ
NOP
T5
NOP
T5
DO
n
DO
n
DO
n+ 1
DO
n+ 1
DO
n+3
tRPST
DO
n+3
WL = 5
DO
n+ 2
NOP
T7
NOP
T7
tRPST
WL = 5
DO
n+ 2
NOP
T6
NOP
T6
NOP
T8
NOP
T8
tWPRE
tWPRE
DI
n
DI
n
NOP
T9
NOP
T9
DI
n+ 1
DI
n+ 1
DI
n+2
DI
n+2
NOP
T10
NOP
T10
= 4 clocks
= 4 clocks
NOP
DI
n+ 3
t
DI WPST
n+ 3
tWPST
tBL
tBL
T11
NOP
T11
NOP
T12
NOP
T12
tWR
Don’t Care
NOP
T15
NOP
T15
PDF: 09005aef83ed2952
PDF: 09005aef83ed2952
161
T0
T1
T2
T3
T4
READ
Bank a,
Col n
Command
DQ
DQS, DQS#
DQ
CK
DQS,
DQS#
Address
T0
READ
Bank a,
Col n
CK#
Address
Command
tRTP
tRTP
tRAS
tRAS
NOP
T2
T1
NOP
NOP
NOP
NOP
T3
NOP
NOP
T4
NOP
CK
Figure
73: READ to PRECHARGE (BL8)
CK#
Figure 38: READ to PRECHARGE (BL8)
Bank a,
(or all)
PRE
T5
Bank a,
(or all)
PRE
T5
NOP
T6
NOP
T6
NOP
T7
NOP
T7
NOP
T8
NOP
T8
DO
n
DO
n
DO
n+1
DO
n+2
DO tRP DO
n+1
n+2
NOP
tRP
T9
NOP
T9
DO
n+3
DO
n+3
DO
n+4
DO
n+4
NOP
T10
NOP
T10
DO
n+5
DO
n+5
DO
n+6
DO
n+6
NOP
T11
NOP
T11
4. BC4,
T4. RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
3. DO n = data-out from column n; DI n = data-in from column b.
4. BC4, (BL8)
RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Figure 73: READ to PRECHARGE
DO
n+7
DO
n+7
NOP
T12
NOP
T12
Bank a,
Row b
ACT
T13
Bank a,
Row b
ACT
T13
NOP
T14
NOP
T14
NOP
T15
NOP
T15
Transitioning Data
Transitioning Data
NOP
T16
NOP
T16
Don’t Care
Don’t Care
NOP
T17
NOP
T17
DO
from =
column
n; DI n = data-in from column b.
4. BC4, RL = 5 (AL - 0, CL =3.
WLnBC4
==5data-out
(AL
0, CWL
5).
2.5),The
OTF=setting
is activated
by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at
T4.
3. DO n = data-outNotes:
from column
n; DIcommands
n = data-inare
from
column
1. NOP
shown
forb.ease of illustration; other commands may be valid at these times.
Transitioning Data
Don’t Care
2. The BC4 OTF setting is activated
by MR0[1:0]
and is
A12
= 0 during
READ command
and WRITE
2. The BC4
OTF setting
activated
by MR0[1:0]
and A12at=T0
0 during
READcommand
commandatatT4.
T0 and WRITE command at
tWTR
tWR
NOPtWTR
T14
NOP
T14
Transitioning Data
NOP
T13
NOP
T13
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
Notes:
DQ3
DQS, DQS#
DQ3
2
Address
DQS,
DQS#
Address2
Command1
CK
CK#1
Command
Figure
72: READ (BC4) to WRITE (BC4) OTF
CK
CK#
Figure 37: READ (BC4) to WRITE (BC4) OTF
Figure 72: READ (BC4) to WRITE (BC4) OTF
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb:2Gb:
x4, x8,
x4,x16
x8, DDR3L
x16 DDR3L
SDRAM
SDRAM
READ
READ
Operation
Operation
*Advanced information. Subject to change without notice.
Micron Technology,
Inc. reserves Inc.
the reserves
right to the
change
rightproducts
to change
or specifications
products or specifications
without notice.
without notice.
161 Micron Technology,
© 2010 Micron
© 2010
Technology,
Micron Technology,
Inc. All rightsInc.
reserved.
All rights reserved.
79
Form #: CSI-D-685 Document 009
2Gb_DDR3L.pdf
2Gb_DDR3L.pdf
2Gb_DDR3L.pdf
- Rev.- K
-Rev.
Rev.
9/13
KKEN
9/13
9/13EN
EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
NOP
NOP
Bank
READa,
Col n
READ
Bank a,
Bank
Col na,
Col n
T1
T1
NOP
T0
T0
READ
tRTP
tRTP
tRTP
tRAS
tRAS
tRAS
NOP
NOP
T2
T2
NOP
NOP
NOP
T3
T3
NOP
NOP
NOP
T4
T4
NOP
Bank a,
Bank
a,
(or all)
(or all)
Bank
PREa,
(or
all)
PRE
T5
T5
PRE
T5
NOP
NOP
T6
T6
NOP
T6
PDF: PDF:
09005aef83ed2952
PDF:09005aef83ed2952
09005aef83ed2952
162
162
162
DQ
DQ
DQS, DQS#
DQS, DQS#
DQ
Address
Address
DQS, DQS#
Command
Address
Command
CK
CK#
CK#
Command
CK
CK
CK#
Bank a,
Bank
Col na,
Col n
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ
READa,
Bank
READ
Col n
Bank a,
Bank
Col na,
Col n
T1
T1
T0
T0
t
tRAS
RAS
(MIN)
(MIN)
(MIN)
tRAS
t
tRAS
RAS
(MIN)
(MIN)
t
tRTP
RTP
NOP
NOP
NOP
T6
T6
AL = 4
AL = 4
NOP
NOP
NOP
T5
T5
(MIN)
NOP
NOP
NOP
T4
T4
tRTP
NOP
NOP
NOP
T3
T3
AL = 4
NOP
NOP
NOP
T2
T2
T7
NOP
NOP
NOP
T7
T7
DO
DO
n
n
DO
n
CL = 6
CL = 6
CL = 6
NOP
NOP
NOP
T7
T7
T7
tRTP
tRTP
tRAS
T6
T6
T6
tRTP
NOP
NOP
NOP
T5
T5
NOP
NOP
AL = 5
AL = 5
NOP
NOP
NOP
T4
T4
NOP
NOP
T8
T8
NOP
T8
AL = 5
NOP
NOP
NOP
NOP
READ
Bank
READa,
READ
Col n
NOP
NOP
T3
T3
T2
T2
T1
T1
T0
T0
T7
T7
T7
NOP
Figure 76: READ with Auto Precharge (AL = 4, CL = 6)
Figure 41:
READ
Precharge
(AL (AL
= 4,=CL
=
Figure
76:
READ
with
Auto
Precharge
4,
CL
Figure
76:
READT1with
withAuto
Auto
Precharge
CL6)=
= 6)
6)
T0
T2
T3
T4 (AL = 4,
T5
T6
DQ
DQ
DQS, DQS#
DQS, DQS#
DQ
DQS, DQS#
Address
Address
CK
CK#
CK#
Command
CK
CK
Command
Address
Command
CK#
Figure 75: READ to PRECHARGE (AL = 5, CL = 6)
Figure 40: READ
to PRECHARGE
(AL(AL
= 5,
CL = 6)
Figure
READ
= 5, CL = 6)
Figure 75:
75:
READT1 to
to PRECHARGE
PRECHARGE
T0
T2
T3 (AL =T45, CL =T56)
DQ
DQ
DQS, DQS#
DQ
DQS, DQS#
DQS, DQS#
Address
Address
CK
CK#
CK#
Command
CK
CK
Command
Address
Command
CK#
Figure 39: READ to PRECHARGE (BC4)
Figure 74: READ to PRECHARGE (BC4)
Figure 74:
74:
READ
to PRECHARGE
(BC4)
Figure
READ
to
PRECHARGE
(BC4)
T0
T1
T2
T3
T4
T8
T8
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T9
T9
T9
NOP
NOP
NOP
T10
T10
T10
NOP
PRE
PREa,
Bank
PRE
(or
all)
Bank a,
Bank
a,
(or all)
(or all)
T10
T10
T10
NOP
NOP
T11
T11
NOP
T11
T9
T9
T9
NOP
NOP
DO
nDO
+3
n+3
CL = 6
CL = 6
T10
T10
T10
NOP
DO
n+3
CL = 6
DO
nDO
+2
n+2
DO
n+2
NOP
T8
T8
T8
NOP
NOP
NOP
DO
nDO
+1
n+1
DO
n+1
t
tRP
RP
tRP
NOP
NOP
T9
T9
NOP
T9
DO
DO
n
n
DO
n
T11
T11
T11
DO
nDO
+1
n+1
NOP
NOP
NOP
DO
n
DO
DO
n
n
DO
nDO
+2
n+2
DO
n+2
T11
T11
T11
NOP
NOP
NOP
DO
n+1
NOP
NOP
T12
T12
NOP
T12
DO
nDO
+3
n+3
DO
n+3
DO
nDO
+1
n+1
DO
n+1
Bank a,
Bank
a,
Row b
Row b
Bank
ACTa,
Row
ACTb
T13
T13
ACT
T13
T12
DO
nDO
+2
n+2
DO
n+2
DO
nDO
+3
n+3
DO
n+3
T13
NOP
NOP
NOP
T13
T13
T13
NOP
NOP
NOP
T13
T13
Indicates break
in time scale
Indicates break
Indicates break
in time scale
in time scale
NOP
NOP
NOP
T12
T12
T12
tRP
tRP
tRP
NOP
NOP
NOP
T12
T12
NOP
NOP
T14
T14
NOP
T14
Ta0
Ta0
Don’t Care
Don’t Care
Don’t Care
Bank a,
Bank
a,
Row b
Row b
ACTa,
Bank
ACTb
Row
ACT
Transitioning Data
Transitioning Data
t
tRP
RP
tRP
NOP
NOP
NOP
Don’t Care
Don’t Care
Ta0
Don’t Care
Transitioning Data
Transitioning Data
Bank a,
Bank
a,
Row b
Row b
Bank
ACTa,
ACTb
Row
ACT
T15
T15
T15
Don’t Care
Don’t Care
Don’t Care
NOP
NOP
T17
T17
NOP
T17
Transitioning Data
NOP
NOP
NOP
T14
T14
T14
Transitioning Data
Transitioning Data
Transitioning Data
NOP
NOP
T16
T16
NOP
T16
Transitioning Data
NOP
NOP
T15
T15
NOP
T15
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb:
2Gb:
2Gb:
x4,
x4,
x4,
x8,
x8,
x8,
x16
x16
x16
DDR3L
DDR3L
DDR3L
SDRAM
SDRAM
SDRAM
READ
READ
READ
Operation
Operation
Operation
*Advanced information. Subject to change without notice.
Micron
Micron
Micron
Technology,
Technology,
Technology,
Inc. reserves
Inc.
Inc.reserves
reserves
the right
the
theright
to
right
change
totochange
change
products
products
products
or specifications
ororspecifications
specifications
without
without
without
notice.
notice.
notice.
© 2010
©©2010
Micron
2010Micron
Micron
Technology,
Technology,
Technology,
Inc. All
Inc.
Inc.
rights
All
Allrights
rights
reserved.
reserved.
reserved.
80
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
READ Operation (continued)
DQS to DQ output timing is shown in Figure 42 (page 82).
The DQ transitions between valid data outputs must be within
tDQSQ of the crossing point of DQS, DQS#. DQS must also
maintain a minimum HIGH and LOW time of tQSH and tQSL.
Prior to the READ preamble, the DQ balls will either be floating
or terminated, depending on the status of the ODT signal.
Figure 43 (page 83) shows the strobe-to-clock timing during
a READ. The crossing point DQS, DQS# must transition within
±tDQSCK of the clock crossing point. The data out has no
timing relationship to CK, only to DQS, as shown in Figure 43
(page 83).
Figure 43 (page 83) also shows the READ preamble and
postamble. Typically, both DQS and DQS# are High-Z to save
power (VDDQ). Prior to data output from the DRAM, DQS is
driven LOW and DQS# is HIGH for tRPRE. This is known as
the READ preamble.
The READ postamble, tRPST, is one half clock from the last
DQS, DQS# transition. During the READ postamble, DQS is
driven LOW and DQS# is HIGH. When complete, the DQ is
disabled or continues terminating, depending on the state of
the ODT signal. Figure 46 (page 85) demonstrates how to
measure tRPST.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
81
Form #: CSI-D-685 Document 009
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
NOP
T2
RL = AL + CL
NOP
T3
tRPRE
(MAX)
tLZDQ (MIN)
tDQSQ
NOP
T4
NOP
T6
tDQSQ
(MAX)
NOP
T7
NOP
T8
tRPST
NOP
T9
DO
n+1
DO
n+2
Data valid
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
tQH
DO
DO
DO
DO
DO
DO
DO
n+1
n+2
n+3
n+4
n+5
n+6
n+7
DO
DO
DO
DO
DO
DO
DO
n+3
n+1
n+2
n+4
n+5
n+6
n+7
Data valid
DO
n
DO
n
tQH
DO
n
NOP
T5
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
NOP
T1
tHZDQ
Don’t Care
(MAX)
NOP
T10
164
7. Early data transitions may not always happen at the same DQ. Data transitions
of a DQ can be early or late within a burst.
6. tDQSQ defines the skew between DQS, DQS# to data and does not define
DQS, DQS# to CK.
a burst.
5. Output timings are referenced to
VDDQ/2 and DLL on and locked.
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within
4. BL8, RL = 5 (AL = 0, CL = 5).
DDQ
tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK.
3. DO n = data-out from column
6. n.
2. The BL8 setting is activated4.byBL8,
either
MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and
RL = 5 (AL = 0, CL = 5).
A12 = 1 during READ command
at
T0.
5. Output timings are referenced to V
/2 and DLL on and locked.
3. DO n = data-out from column n.
BL8
is activated
by either may
MR0[1,
1. NOP commands are shown2.forThe
ease
ofsetting
illustration;
other commands
be 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at
T0.
valid at these times.
Notes:
All DQ collectively
DQ3 (first data no longer valid)
DQ3 (last data valid)
Notes:
Bank,
Col n
Address2
DQS, DQS#
READ
T0
Command1
CK
CK#
Figure 77: Data Output Timing – tDQSQ and Data Valid Window
Figure 42: Data Output Timing – tDQSQ and Data Valid Window
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Operation
*Advanced information. Subject to changeREAD
without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice
© 2010 Micron Technology, Inc. All rights reserved
82
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
tHZ
and tLZ transitions occur in the same access time as valid
data transitions. These parameters are referenced to a specific
voltage level that specifies when the device output is no longer
2Gb: x4, x8, x16 DDR3L SDRAM
driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ.
READ Operation
Figure 44 (page 84) shows a method of calculating the point
when the device is no longert driving tHZDQS
and tHZDQ, or
tLZ transitions occur in the same access time as valid data transitions. These
HZ
and
t
t
begins driving LZDQS, LZDQ, by measuring the signal at two
parameters are referenced to a specific voltage level that specifies when the device outdifferent voltages. The actual voltage measurement t points
put is no longer driving HZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ. Figare not critical as long as the calculation is consistent. The
ure 79 (page 166) shows a method of calculating the point when the device is no longer
parameters tLZDQS, tLZDQ, tdriving
HZDQS,tHZDQS
and tHZDQ
defined
tHZDQ,
andare
or begins driving tLZDQS, tLZDQ, by measuring the signal
as single-ended.
at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent. The parameters tLZDQS, tLZDQ, tHZDQS, and tHZDQ
are defined as single-ended.
Figure
78:
Data
Strobe
Timing
– READs
Figure
43:
Data
Strobe
Timing
– READs
RL measured
to this point
T0
CK
T1
T2
T3
T4
T5
T6
CK#
tDQSCK
tLZDQS
tDQSCK
(MIN)
(MIN)
tQSH
tDQSCK
(MIN)
tQSL
tQSH
tDQSCK
(MIN)
tHZDQS
(MIN)
(MIN)
tQSL
DQS, DQS#
early strobe
tRPST
tRPRE
Bit 0
tLZDQS
Bit 1
tDQSCK
(MAX)
Bit 2
Bit 3
tDQSCK
(MAX)
Bit 4
Bit 5
tDQSCK
(MAX)
Bit 6
Bit 7
tDQSCK
(MAX)
tHZDQS
(MAX)
(MAX)
tRPST
DQS, DQS#
late strobe
tRPRE
tQSH
Bit 0
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
tQSL
Bit 1
tQSH
Bit 2
tQSL
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
83
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
2Gb: x4, x8, x16 DDR3L SDRAM
MYX4DDR3L128M16JT*
2Gb: x4,
x8, x16 DDR3L
SDRAM
READ Operation
READ Operation
*Advanced information. Subject to change without notice.
tLZ and tHZ
Figure 79: Method for Calculating
tLZ and tHZ
Figure
79:Method
Method
Calculating
tLZ and
tHZ
Figure 44:
forfor
Calculating
VOH - xmV
VOH - xmV
VTT + 2xmV
VTT + 2xmV
VOH - 2xmV
VOH - 2xmV
VTT + xmV
VTT + xmV
tLZDQS, tLZDQ
tLZDQS, tLZDQ
tHZDQS, tHZDQ
tHZDQS, tHZDQ
T2
T1
T2
T1
tHZDQS, tHZDQ end point
tHZDQS, tHZDQ end point = 2
VOL + 2xmV
VOL + 2xmV
VTT - xmV
VTT - xmV
VOL + xmV
VOL + xmV
VTT - 2xmV
VTT - 2xmV
T1
T1
T2
T2
tLZDQS, tLZDQ begin point = 2 × T1 - T2
tLZDQS, tLZDQ begin point = 2 × T1 - T2
= 2 × T1 - T2
× T1 - T2
Notes: 1. Within a burst, the rising strobe edge is not necessarily fixedtat tDQSCK (MIN) tor tDQSCK
a burst,
the the
rising
strobe
edge
is not
necessarily
fixedtDQSCK
at DQSCK
(MIN)
DQSCK
tDQSCK
Notes: 1. Within
(MAX).
Instead,
rising
strobe
edge
can
vary between
(MIN)
andor
tDQSCK (MIN) and tDQSCK
(MAX).
Instead,
the
rising
strobe
edge
can
vary
between
t
t
1. Within a burst, the rising strobe edge
is not necessarily fixed
(MAX).
case), and LZDQS (MAX) and HZDQS (MAX) are not tied to
(MAX).
tDQSCK
at tDQSCK (MIN) or tDQSCK (MAX).
Instead,
the rising
strobe
(MAX)
(late
however,
theyistend
to track
2. The
DQS HIGH
pulse
width is defined
by tQSH,
and
thestrobe
DQS case);
LOW pulse
width
defined
tQSH, and the DQS LOW pulse
2.
The
DQS
HIGH
pulse
width
is
defined
by
width is
defined
t
t
t
t
t
by QSL.
Likewise,
LZDQS (MIN) andone
HZDQS
(MIN) are not tied to tDQSCK
(MIN)
(early
edge can vary between DQSCK (MIN)
and
DQSCK
(MAX).
another.
tLZDQS
tHZDQS
by tstrobe
QSL. Likewise,
(MIN) andand
(MIN)
are not
tied
to tDQSCK
(MIN)
(early(late
t
tHZDQS
tDQSCK
case),and
and
(MAX)
are
notoftied
(MAX)
2. The DQS HIGH pulse width is defined
by tQSH,
theLZDQS
DQS (MAX)3.
The
minimum
pulse
width
thetto
READ
preamble
is defined
tLZDQS
tHZDQS
strobe
case),
and
(MAX)
and
(MAX)
are
not
tied
to
DQSCK
(MAX) (late
strobe
case);
however,
they
tend
to
track
one
another.
tLZDQS (MIN)
tRPRE (MIN). The minimum pulse width of the READ
LOW pulse width is defined by tstrobe
QSL. Likewise,
by
case); however, they tend to track one another.
3.
The minimum
pulse
width of the READ
preamble
is defined
by t(MIN).
RPRE (MIN). The minitRPST
and tHZDQS (MIN) are not tied
to tDQSCK
(MIN) (early
strobe
postamble
isisdefined
by by
tRPRE
3. The
minimum
the READ
preamble
defined
(MIN). The minimum pulse pulse
widthwidth
of theofREAD
postamble
is defined
by tRPST
(MIN).
mum pulse width of the READ postamble is defined by tRPST (MIN).
Notes:
Figure 80: tRPRE Timing
Figure 80: tRPRE Timing
CK
Figure 45: tRPRE Timing
CK
VTT
CK#
VTT
CK#
tA
tA
tB
DQS
DQS
Single-ended signal provided
Single-ended
signal information
provided
as background
as background information
tC
tB
VTT
tC
tD
DQS#
DQS#
Single-ended signal provided
Single-ended
signal information
provided
as background
as background information
VTT
tD
VTT
VTT
T1
tRPRE
T1 begins
tRPRE begins
DQS - DQS#
DQS - DQS#
tRPRE
tRPRE
T2
ends
tRPRE ends
Resulting differential
Resulting
signaldifferential
relevant for
tRPRE
signal
relevant
for
specification
tRPRE specification
MYX4DDR3L128M16JT*
Revision
1.5 - 10/30/14
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2Gb_DDR3L.pdf - Rev. K 9/13 EN
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2Gb_DDR3L.pdf - Rev. K 9/13 EN
0V
0V
tT2
RPRE
84
166
166
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010
Micron
All rights
reserved.
Micron Technology, Inc. reserves the right to change
products
or Technology,
specificationsInc.
without
notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
2Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
Figure 46: tRPST Timing
Figure 81: tRPST Timing
CK
VTT
CK#
tA
DQS
Single-ended signal, provided
as background information
t
tC
VTT
B
tD
DQS#
VTT
Single-ended signal, provided
as background information
tRPST
DQS - DQS#
Resulting differential
signal relevant for
tRPST specification
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
T1
begins
tRPST
0V
T2
ends
tRPST
85
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
of a completed burst. Figure 50 (page 89) and Figure 51
(page 89) show concatenated bursts. An example of
nonconsecutive WRITEs is shown in Figure 52 (page 90).
WRITE Operation
WRITE bursts are initiated with a WRITE command. The
starting column and bank addresses are provided with the
WRITE command, and auto precharge is either enabled or
disabled for that access. If auto precharge is selected, the
row being accessed is precharged at the end of the WRITE
burst. If auto precharge is not selected, the row will remain
open for subsequent accesses. After a WRITE command has
been issued, the WRITE burst may not be interrupted. For
the generic WRITE commands used in Figure 49 (page 88)
through Figure 57 (page 93), auto precharge is disabled.
Data for any WRITE burst may be followed by a subsequent
READ command after tWTR has been met (see Figure 53 (page
90), Figure 54 (page 91), and Figure 55 (page 92)).
Data for any WRITE burst may be followed by a subsequent
PRECHARGE command, providing tWR has been met, as
shown in Figure 56 (page 93) and Figure 57 (page 93).
Both tWTR and tWR starting time may vary, depending on the
mode register settings (fixed BC4, BL8 versus OTF).
During WRITE bursts, the first valid data-in element is registered
on a rising edge of DQS following the WRITE latency (WL)
clocks later and subsequent data elements will be registered
on successive edges of DQS. WRITE latency (WL) is defined as
the sum of posted CAS additive latency (AL) and CAS WRITE
latency (CWL): WL = AL + CWL. The values of AL and CWL are
programmed in the MR0 and MR2 registers, respectively. Prior
to the first valid DQS edge, a full cycle is needed (including a
dummy crossover of DQS, DQS#) and specified as the WRITE
preamble shown in Figure 49 (page 88). The half cycle on
DQS following the last data-in element is known as the WRITE
postamble.
The time between the WRITE command and the first valid
edge of DQS is WL clocks ±tDQSS. Figure 50 (page 89)
through Figure 57 (page 93) show the nominal case where
tDQSS = 0ns; however, Figure 49 (page 88) includes tDQSS
(MIN) and tDQSS (MAX) cases.
Data may be masked from completing a WRITE using data
mask. The data mask occurs on the DM ball aligned to the
WRITE data. If DM is LOW, the WRITE completes normally. If
DM is HIGH, that bit of data is masked.
Upon completion of a burst, assuming no other commands
have been initiated, the DQ will remain High-Z, and any
additional input data will be ignored.
Data for any WRITE burst may be concatenated with a
subsequent WRITE command to provide a continuous
flow of input data. The new WRITE command can be tCCD
clocks following the previous WRITE command. The first data
element from the new burst is applied after the last element
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
86
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4,*Advanced
x8, x16
DDR3L SDRAM
information. Subject to change without notice.
WRITE Operation
Figure 47: tWPRE Timing
Figure 82: tWPRE Timing
2Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
CK
Figure 82: tWPRE Timing
VTT
CK#CK
VTT
CK#
T1
tWPRE begins
DQS - DQS#
Figure 83: tWPST Timing
0V
tWPRE
T1
ResultingtWPRE
differential
begins
signal relevant for
tWPRE specification
DQS
- DQS#
T2
tWPRE
ends
0V
tWPRE
T2
Resulting differential
signal relevant for
CK tWPRE specification
tWPRE
ends
Figure 48: tWPST Timing
Figure 83: tWPST Timing
VTT
CK#CK
VTT
CK#
DQS - DQS#
Resulting differential
signal relevant for
tWPST specification
DQS - DQS#
Resulting differential
signal relevant for
tWPST specification
tWPST
T1
begins
tWPST
tWPST
0V
T2
ends
tWPST
T1
begins
0V
tWPST
T2
ends
tWPST
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
87
Form #: CSI-D-685 Document 009
PDF: 09005aef83ed2952
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
*Advanced information. Subject to change without notice.
Figure 49: WRITE Burst
Figure 84: WRITE Burst
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command1
WL = AL + CWL
Address2
Bank,
Col n
tDQSS
tWPRE
(MIN)
tDQSS tDSH
tDSH
tDSH
tDSH tWPST
DQS, DQS#
tDQSH
tDQSL
tDQSH
DI
n
DQ3
tDQSS
DI
n+1
tWPRE
(NOM)
tDQSL
tDQSH
DI
n+2
tDQSL
DI
n+3
tDSH
tDQSH
DI
n+4
tDQSL
DI
n+5
tDSH
tDQSH
DI
n+6
tDQSL
DI
n+7
tDSH
tDSH
tWPST
tDQSH
tDQSL
DQS, DQS#
tDQSH
tDQSL
tDQSH
tDSS
tDQSH
tDSS
DI
n
DQ3
tDQSL
DI
n+1
tDQSL
tDQSH
tDQSL
tDSS
DI
n+2
DI
n+3
tDSS
DI
n+4
DI
n+5
tDSS
DI
n+6
DI
n+7
tDQSS
tDQSS
tWPRE
(MAX)
tWPST
DQS, DQS#
tDQSH
tDQSL
tDQSH
tDSS
DI
n
DQ3
tDQSL
tDQSH
tDSS
DI
n+1
tDQSL
tDQSH
tDSS
DI
n+2
DI
n+3
tDQSL
tDQSH
tDSS
DI
n+4
DI
n+5
tDQSL
tDSS
DI
n+6
DI
n+7
Transitioning Data
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2.
The
settingother
is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
NOP commands are shown for ease
of BL8
illustration;
the WRITE command at T0.
commands may be valid at these times.
3. DI n = data-in for column n.
The BL8 setting is activated by either MR0[1:0] = 00 or
4. BL8, WL = 5 (AL = 0, CWL = 5).
MR0[1:0] = 01 and A12 = 1 duringtthe WRITE command at
5. DQSS must be met at each rising clock edge.
T0.
6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST acDI n = data-in for column n.
tually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
BL8, WL = 5 (AL = 0, CWL = 5).
Notes:
1.
2.
3.
4.
Don’t Care
Notes:
5. tDQSS must be met at each rising clock edge.
6. tWPST is usually depicted as ending at the crossing of DQS,
DQS#; however, tWPST actually ends when DQS no longer
drives LOW and DQS# no longer drives HIGH.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
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2Gb_DDR3L.pdf - Rev. K 9/13 EN
88
170
Micron Technology, Inc. reserves the right to change products or specifications without notice.
#:rights
CSI-D-685
Document 009
© 2010 Micron Technology,Form
Inc. All
reserved.
2Gb_DDR3L.pdf
2Gb_DDR3L.pdf
- Rev. K 9/13
- Rev.
ENK 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
PDF: 09005aef83ed2952
Valid
Valid
Address2
NOP
T1
NOP
T2
NOP
tCCD
NOP
tCCD
WL = 5
WL = 5
NOP
T3
NOP
Valid
Valid
WRITE
T4
WRITE
tWPRE
tWPRE
DI
n
DI
n
NOP
T5
NOP
DI
n+1
DI
n+1
DI
n+2
DI
n+2
NOP
T6
NOP
T6
DI
n+4
WL = 5
WL
DI = 5 DI
n+3
n+4
DI
n+3
NOP
T7
NOP
T7
DI
n+5
DI
n+5
DI
n+6
DI
n+6
NOP
T8
NOP
T8
DI
n+7
DI
n+7
DI
b
DI
b
NOP
T9
NOP
T9
DI
b+1
DI
b+1
DI
b+2
DI
b+2
NOP
T10
NOP
T10
tBL
tBL
DI
b+3
DI
b+3
DI
b+4
DI
b+4
= 4 clocks
NOP
= 4 clocks
T11
NOP
T11
DI
b+5
DI
b+5
DI
b+6
DI
b+6
NOP
T12
NOP
T12
DI
b+7
Transitioning Data
tWPST
DI
b+7
tWPST
NOP
T13
NOP
T13
T14
NOP
NOP
Don’t Care
Don’t Care
tWTR
tWR
tWTR
tWR
T14
171 171
Valid
Address2
DQS, DQS#
T2
NOP
Notes:
tCCD
NOP
tCCD
WL = 5
WL = 5
NOP
T3
NOP
Valid
Valid
WRITE
T4
WRITE
DI
n
DI
n+1
DI
n+2
WL = 5
WL
DI = 5
n+3
tWPRE
tWPST
DI
n+3
DI
n+2
tWPRE
NOP
T8
NOP
tWPRE
NOP
T7
NOP
tWPST
DI
n+1
NOP
T6
NOP
T8
tWPRE
DI
n
NOP
T5
NOP
5. If set via MRS (fixed) tWR and tWTR would start T11 (2 cycles earlier).
4.
3.
2.
1.
Notes:
DQ3
DQS, DQS#
NOP
T1
NOP
T7
DI
b
DI
b
NOP
T9
NOP
T9
DI
b+1
DI
b+1
DI
b+2
DI
b+2
NOP
T10
NOP
T10
tBL
tWPST
DI
b+3
tWPST
DI
b+3
= 4 clocks
= 4 clocks
NOP
tBL
T11
NOP
T11
NOP
T12
NOP
T12
Transitioning Data
NOP
T13
NOP
T13
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.Transitioning Data
2. BC4, WL = 5 (AL = 0, CWL = 5).
NOP commandsNotes:
are shown
of
other
commands
may
be b).
valid at
these
times. may be valid at these times.
1.
NOP
commands
are shown
for ease
illustration;
other
commands
3. for
DI ease
n (or
b) illustration;
= data-in
for
column
n (orofcolumn
2.
BC4,
WL
=
5
(AL
=
0,
CWL
=
5).
BC4, WL = 5 (AL = 0, CWL
5). BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
4. =The
tWR
3.
(or
b)
= data-in
column
n (orwould
column
b). T11 (2 cycles earlier).
5. DI
If set
via
MRS
(fixed)
and tWTR
start
DI n (or b) = data-in for column
nn(or
column
b). for
4. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
The BC4 setting is activated by MR0[1:0] = 01 and tA12 = 0 during
the WRITE command at T0 and T4.
5. If set via MRS (fixed) WR and tWTR would start T11 (2 cycles earlier).
Valid
DQ3
WRITE
Address2
T0
WRITE
Command1
CK
Command1
CK#
CK
T0
T1
T2
T3
T4
T5
Figure
86:
Consecutive
WRITE
(BC4)
to WRITE
(BC4)
via T6
OTF
CK#
Figure 51: Consecutive WRITE (BC4) to WRITE (BC4) via OTF
Figure 86: Consecutive WRITE (BC4) to WRITE (BC4) via OTF
T14
NOP
NOP
Don’t Care
Don’t Care
tWTR
tWR
tWTR
tWR
T14
2. by
The
BL8 MR0[1:0]
setting is =activated
by either
MR0[1:0]
MR0[1:0]
= 01 and
A12 = 1 at
during
the
WRITE commands at
2. The BL8 setting is activated
either
00 or MR0[1:0]
= 01
and A12= =001 or
during
the WRITE
commands
T0 and
T4.
commands
are shown for ease of illustration; other commands may be valid at these times.
Notes: 1. NOP
T0 and
T4.
3. DI n (or b) = data-in for column
n (or column
b).
2.
setting
is activated
by either
MR0[1:0]b).= 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at
3. The
DI n BL8
(or b)
= data-in
for column
n (or column
T0
4. BL8, WL = 5 (AL = 0, CWL
5).and
4.=BL8,
WLT4.
= 5 (AL = 0, CWL = 5).
3. DI n (or b) = data-in for column n (or column b).
4. BL8, WL = 5 (AL = 0, CWL = 5).
1. for
NOP
commands
are shown
for ease ofmay
illustration;
other
commands
Transitioning Data
1. NOP commandsNotes:
are shown
ease
of illustration;
other commands
be valid at
these
times. may be valid at these times.
Notes:
DQ3
DQS, DQS#
DQ3
DQS, DQS#
WRITE
Address2
T0
WRITE
Command1
CK
Command1
CK#
CK
T0
T1
T2
T3
T4
T5
Figure
85:
Consecutive
WRITE
(BL8)
to WRITE
(BL8)
CK#
Figure 50: Consecutive WRITE (BL8) to WRITE (BL8)
Figure 85: Consecutive WRITE (BL8) to WRITE (BL8)
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb:
2Gb:
x4, x8,
x4, x16
x8, x16
DDR3L
DDR3L
SDRAM
SDRAM
WRITE
WRITE
Operation
Operation
*Advanced information. Subject to change without notice.
Micron Technology,
Micron Technology,
Inc. reserves
Inc.the
reserves
right to
thechange
right to
products
change or
products
specifications
or specifications
without notice.
without notice.
© 2010 Micron
© 2010
Technology,
Micron Technology,
Inc. All rights
Inc. All
reserved.
rights reserved.
89
Form #: CSI-D-685 Document 009
T0
T1
T2
T3
T4
T5
Valid
2Gb_DDR3L.pdf
2Gb_DDR3L.pdf
- Rev. K 9/13 EN- Rev. K 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
PDF: 09005aef83ed2952
NOP
T1
NOP
T2
T4
WL = CWL + AL = 7
WL = CWL + AL = 7
NOP
NOP
T3
Valid
WRITE
Valid
T5
NOP
T6
NOP
T6
DI
n
DI
n
NOP
T7
NOP
T7
T9
NOP
T9
NOP
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
DI
DI
DI
n + 1 WL
n +=2CWL
n+
+ 3AL n
=+
74
NOP
WL = CWL + AL = 7
T8
NOP
T8
DI
n+5
DI
n+5
DI
n+6
DI
n+6
NOP
T10
NOP
T10
DI
n+7
DI
n+7
NOP
T11
NOP
T11
DI
b
DI
b
NOP
T12
NOP
T12
DI
b+1
DI
b+1
DI
b+2
DI
b+2
NOP
T13
NOP
T13
DI
b+3
DI
b+3
DI
b+4
DI
b+4
NOP
T14
NOP
T14
DI
b+5
DI
b+5
T1
T2
T3
172
5.
4.
3.
2.
1.
Notes:
DQ4
DQS, DQS#
DQ4
Notes:
NOP
T1
NOP
NOP
T2
NOP
WL = 5
WL = 5
NOP
T3
NOP
NOP
T4
NOP
T4
tWPRE
tWPRE
DI
n
DI
n
NOP
T5
NOP
T5
DI
n+1
DI
n+1
DI
n+2
DI
n+2
NOP
T6
NOP
T6
DI
n+3
DI
n+3
DI
n+4
DI
n+4
NOP
T7
NOP
T7
DI
n+5
DI
n+5
DI
n+6
DI
n+6
NOP
T8
NOP
T8
DI
n+7
t
DI WPST
n+7
tWPST
NOP
T10
NOP
T10
Indicates break
in time scale
NOP
T9
NOP
T9
Data
NOP
T11
NOP
T11
Transitioning Data
Transitioning Data
tWTR2
tWTR2
DI
b+7
NOP
T16
NOP
T16
Transitioning
DI
DI
b+6 b+7
DI
b+6
NOP
T15
NOP
T15
Don’t Care
Valid
READ
Valid
Ta0
READ
Ta0
Don't Care
Don't Care
NOP
T17
NOP
T17
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
Indicates break
Transitioning Data
Don’t Care
timefirst
scale rising clock edge after the last
2. tWTR controls the WRITE-to-READ delay to the same device and starts with inthe
write data shown at T9.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
commands
are
shown for
ease ofMR0[1:0]
illustration;
commands
valid at
times.
Notes: 1.
3. NOP
The BL8
setting is
activated
by either
= 00other
or MR0[1:0]
= 01may
and be
MR0[12]
= these
1 during
the WRITE command
tWTR controls the WRITE-to-READ
delayREAD
to the
thecommand
same
device
andcan
starts
with
firstordevice
rising
edge after
the
data
shown
atafter
T9.
2. tat
WTR
WRITE-to-READ
delay
thethe
same
and starts
with
thelast
firstwrite
rising
clock
edge
the last
T0. controls
The
at Ta0
be to
either
BC4
BL8, clock
depending
on MR0[1:0]
and
the
A12
status
at Ta0.
write
data
shown
at
T9.
The BL8 setting is activated
by
either
MR0[1:0]
=
00
or
MR0[1:0]
=
01
and
MR0[12]
=
1
during
the
WRITE
command
at
T0.
The
READ
command
at
4. DI n = data-in for column n.
3.
The
BL8
setting
is
activated
by
either
MR0[1:0]
=
00
or
MR0[1:0]
=
01
and
MR0[12]
=
1
during
the
WRITE
command
Ta0 can be either BC4 or BL8,
depending
on
MR0[1:0]
and
the
A12
status
at
Ta0.
5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
DI n = data-in for column n. at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.
4. DI n = data-in for column n.
RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Valid
Address3
DQS, DQS#
WRITE
Valid
T0
WRITE
Command13
Address
CK
Command1
CK#
CK#
Figure
53:
WRITE (BL8) to READ (BL8)
CK
Figure
88: WRITE (BL8) to READ (BL8)
T0
2. Seven subsequent elements of data-in are applied in the programmed order following DO n.
2. Seven subsequent elements of data-in are applied in the programmed order following DO n.
3. Each WRITE command may be to any bank.
3. Each WRITE command
to(or
any
1.
DI
n
b)bank.
=WL
data-in
for column
n 0).
(or column b).
Notes: may
4. be
Shown
for
= 7 (CWL
= 7, AL =
2.
Seven
subsequent
elements
of
data-in
are applied in the programmed order following DO n.
4. Shown for WL = 7 (CWL = 7, AL = 0).
3. Each WRITE command may be to any bank.
Figure 88: WRITE (BL8) to 4.
READ
(BL8)
Shown
for WL = 7 (CWL = 7, AL = 0).
DM
1. DInn(or
(orcolumn
b) = data-in
Notes:
1. DI n (or b) = data-in
for column
b). for column n (or column b).
DQ
Notes:
DQS, DQS#
DM
DQ
WRITE
Command
Valid
T0
DQS, DQS#
Address
CK
Address
CK#
Figure
87:
Nonconsecutive
WRITE NOP
to WRITE
Command
WRITE
NOP
NOP
NOP
WRITE
CK
CK#
Figure 52: Nonconsecutive WRITE to WRITE
Figure 87: Nonconsecutive WRITE to WRITE
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4,
2Gb:
x8,
x4,
x16
x8,DDR3L
x16 DDR3L
SDRAM
SDRAM
WRITE
WRITE
Operation
Operation
*Advanced information. Subject to change without notice.
Micron
Inc.
Technology,
reserves the
Inc.
right
reserves
to change
the right
products
to change
or specifications
products orwithout
specifications
notice.without notice.
172Micron Technology,
© 2010 Micron©Technology,
2010 Micron
Inc.
Technology,
All rights reserved.
Inc. All rights reserved.
90
Form #: CSI-D-685 Document 009
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
Valid
Address3
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
Notes:
NOP
T1
NOP
T2
WL = 5
NOP
T3
NOP
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
DI
n+3
tWPST
NOP
T7
Indicates break
in time scale
NOP
T8
Transitioning Data
tWTR2
NOP
T9
Don’t Care
Valid
READ
Ta0
173
5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).
4. DI n = data-in for column n.
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last
1. NOP commands are shown for
easedata
of illustration;
write
shown at other
T7. commands may be valid at these times.
t
2. WTR controls the WRITE-to-READ
delay
to the
same
andbystarts
with the
first
rising the
clock
3. The fixed
BC4
setting
is device
activated
MR0[1:0]
= 10
during
WRITE command at T0 and the READ command at
Ta0. at T7.
edge after the last write data shown
4. DI n by
= data-in
for=column
n. the WRITE command at T0 and the
3. The fixed BC4 setting is activated
MR0[1:0]
10 during
READ command at Ta0. 5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).
DQ4
DQS, DQS#
WRITE
T0
Command1
CK
CK#
Figure 89: WRITE to READ (BC4 Mode Register Setting)
Figure 54: WRITE to READ (BC4 Mode Register Setting)
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDR
WRITE Operat
*Advanced information. Subject to change without notice.
Micron Technology, Inc. reserves the right to change products or specifications witho
© 2010 Micron Technology, Inc. All rights
91
Form #: CSI-D-685 Document 009
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
Valid
Address3
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
Notes:
NOP
T1
NOP
T2
WL = 5
NOP
T3
NOP
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
NOP
= 4 clocks
DI
n+3
tWPST
tBL
T7
NOP
T8
NOP
T9
Indicates break
in time scale
tWTR2
NOP
T10
Transitioning Data
NOP
T11
RL = 5
Don’t Care
Valid
READ
Tn
174
5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
4. DI n = data-in for column n.
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts after tBL.
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ
2. tWTR controls the WRITE-to-READ
delayattoTn.
the same device and starts after tBL.
command
3. The BC4 OTF setting is activated
MR0[1:0]
01 and A12
4. DI nby
= data-in
for= column
n. = 0 during the WRITE command at
T0 and the READ command
Tn.RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
5. at
BC4,
DQ4
DQS, DQS#
WRITE
T0
Command1
CK
CK#
Figure 90: WRITE (BC4 OTF) to READ (BC4 OTF)
Figure 55: WRITE (BC4 OTF) to READ (BC4 OTF)
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L
WRITE Op
*Advanced information. Subject to change without notice.
Micron Technology, Inc. reserves the right to change products or specificati
© 2010 Micron Technology, Inc.
92
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
2Gb:MYX4DDR3L128M16JT*
x4, x8, x16 DDR3L SDRAM
WRITE Operation
2Gb: x4, x8, x16 DDR3L SDRAM
*Advanced information.WRITE
Subject to change
without notice.
Operation
Figure
91: WRITE
to PRECHARGE
Figure
56: WRITE
(BL8)(BL8)
to PRECHARGE
Figure 91: WRITE (BL8) to PRECHARGE
CK#
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Command
CK
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Command
Address
WRITE
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Valid
Address
Valid
CK#
DQS, DQS#
WL = AL + CWL
tWR
WL = AL + CWL
tWR
DQ
BL8
DQS,
DQS#
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DQ BL8
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
DI
n+6 n+7
Indicates break
in time scale
Notes:
Valid
DI
n+7
Transitioning Data
Don’t Care
Indicates break
1. DI n = data-in from column n.
Transitioning Data
Don’t Care
in time scale
Notes: 1. DI n = data-in from column n.
2. Seven subsequent elements of data-in are applied in the
2. Seven subsequent elements of data-in are applied in the programmed order following
programmed order following
= data-in from column n.
Notes: DO1.n.DI
DOnn.
Seven
elements
of data-in
3. Shown for WL = 7 (AL = 0, CWL2.
=
7).
3. Shownsubsequent
for WL = 7 (AL
= 0, CWL
= 7). are applied in the programmed order following
DO n.
3. Shown for WL = 7 (AL = 0, CWL = 7).
Figure 92: WRITE (BC4 Mode Register Setting) to PRECHARGE
Figure
92: WRITE
Register
to PRECHARGE
Figure
57: WRITE
(BC4 (BC4
ModeMode
Register
Setting) Setting)
to PRECHARGE
CK#
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Command
CK
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Command
Address
WRITE
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Valid
Address
Valid
CK#
DQS, DQS#
WL = AL + CWL
tWR
WL = AL + CWL
tWR
DQ
BC4
DQS,
DQS#
DI
n
DI
n+1
DI
n+2
DI
n+3
DQ BC4
DI
n
DI
n+1
DI
n+2
DI
n+3
Notes:
1.
2.
3.
4.
Indicates break
in time scale
Indicates break
Valid
Transitioning Data
Don’t Care
Transitioning Data
Don’t Care
in time scale
commands may be valid at
Notes: 1. NOP commands are shown for ease of illustration; other
NOP commands are shown for ease
of
illustration;
other
these times.
1.
NOP
commands
aretime
shown
for isease
of illustration;
other
beafter
validthe
at last
Notes:
commands may be valid
at these
2. times.
The write
recovery
(tWR)
referenced
from the
firstcommands
rising clockmay
edge
these
times.is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGE
t
write
data
The write recovery time ( WR) is referenced from the first
2. The write recovery
time
(tWR)
referenced
canat
beT7.
issued
theissame
bank. from the first rising clock edge after the last
tWR to
rising clock edge after the last writecommand
data is shown
tWR specifies the last burst WRITE cycle until the PRECHARGE
write
data
is
shown
at
T7.
3. The
BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
specifies the last burst WRITE cycle
untilfixed
the PRECHARGE
command can be issued to the same bank.
4.
DI
n
=
data-in
for column n.
command can be issued to the same bank.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
5. by
BC4 (fixed),=WL
= 5, RLthe
= 5.
The fixed BC4 setting is activated
during
4. DIMR0[1:0]
n = data-in10for
column n.
WRITE command at T0.
5. BC4 (fixed), WL = 5, RL = 5.
DI n = data-in for column n.
5. BC4 (fixed), WL = 5, RL = 5.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
93
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
175
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
175
Form #: CSI-D-685 Document 009
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
*Advanced information. Subject to change without notice.
Figure
58: WRITE (BC4 OTF) to PRECHARGE
Figure 93: WRITE (BC4 OTF) to PRECHARGE
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
CK
Command1
tWR2
Address3
Bank,
Col n
Valid
tWPRE
tWPST
DQS, DQS#
DI
n
DQ4
DI
n+1
DI
n+2
DI
n+3
WL = 5
Indicates break
in time scale
Notes:
Transitioning Data
Don’t Care
1. NOP commands are shown for ease of illustration; other
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
commands may be valid at these times.
these times.
2. The write recovery time (tWR) is2.referenced
from
the rising
The write
recovery
time (tWR) is referenced from the rising clock edge at T9. tWR speciclock edge at T9. tWR specifies thefies
lastthe
burst
WRITE
cycle
last burst WRITE cycle until the PRECHARGE command can be issued to the same
until the PRECHARGE command can
be issued to the same
bank.
bank.
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command
at T0. = 01 and A12 = 0
3. The BC4 setting is activated by MR0[1:0]
during the WRITE command at 4.
T0.DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
4. DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
DQ Input Timing
DQ Input Timing
Figure 84 (page 170) shows the strobe-to-clock timing during a WRITE burst. DQS,
DQS# must transition within 0.25tCK of the clock transitions, as limited by tDQSS. All
data and data mask setup and hold timings are measured relative to the DQS, DQS#
crossing, not the clock crossing.
The WRITE preamble and postamble are also shown in Figure 84 (page 170). One clock
Figure 49 (page 88) shows theprior
strobe-to-clock
timing
during
hold times
are also
shown
in Figure
49for
(page
to data input
to the
DRAM, Data
DQS setup
must and
be HIGH
and DQS#
must
be LOW.
Then
t
a WRITE burst. DQS, DQS# must
transition
withinis0.25
CK LOW
of
88). Allissetup
andHIGH)
hold times
arethe
measured
from the crossing
a half
clock, DQS
driven
(DQS#
driven
during
WRITE preamble,
the clock transitions, as limitedtWPRE.
by tDQSS.
All data
andmust
databe kept
points
of DQS
and
DQS#. These
anddata
holdisvalues
pertain
Likewise,
DQS
LOW
by the
controller
aftersetup
the last
written
mask setup and hold timings to
are
relativethe
toWRITE
the postamble,
to data inputtWPST.
and data mask input. Additionally, the half period
themeasured
DRAM during
DQS, DQS# crossing, not the clock crossing.
of the data input strobe is specified by tDQSH and tDQSL.
Data setup and hold times are also shown in Figure 84 (page 170). All setup and hold
times are
are also
measured
the crossing points of DQS and DQS#. These setup and hold
The WRITE preamble and postamble
shownfrom
in Figure
values pertain to data input and data mask input.
49 (page 88). One clock prior to data input to the DRAM,
the
halffor
period
DQS must be HIGH and DQS#Additionally,
must be LOW.
Then
a halfof the data input strobe is specified by tDQSH and tDQSL.
clock, DQS is driven LOW (DQS# is driven HIGH) during the
WRITE preamble, tWPRE. Likewise, DQS must be kept LOW
by the controller after the last data is written to the DRAM
during the WRITE postamble, tWPST.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
94
176
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology,Form
Inc. All
reserved.
#: rights
CSI-D-685
Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
*Advanced
information.
Subject to change without notice.
WRITE
Operation
Figure 59: Data Input Timing
Input Timing
DQS, DQS#
tWPRE
DQ
tDQSH
tWPST
tDQSL
DI
b
DM
tDS
tDH
tDS
tDH
Transitioning Data
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
Don’t Care
95
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
After the DRAM has entered self refresh mode, all external
control signals, except CKE and RESET#, are “Don’t Care.”
The DRAM initiates a minimum of one REFRESH command
internally within the tCKE period when it enters self refresh
mode.
PRECHARGE Operation
Input A10 determines whether one bank or all banks are to
be precharged and, in the case where only one bank is to be
precharged, inputs BA[2:0] select the bank.
The requirements for entering and exiting self refresh mode
depend on the state of the clock during self refresh mode.
First and foremost, the clock must be stable (meeting tCK
specifications) when self refresh mode is entered. If the clock
remains stable and the frequency is not altered while in self
refresh mode, then the DRAM is allowed to exit self refresh
mode after tCKESR is satisfied (CKE is allowed to transition
HIGH tCKESR later than when CKE was registered LOW). Since
the clock remains stable in self refresh mode (no frequency
change), tCKSRE and tCKSRX are not required. However, if
the clock is altered during self refresh mode (if it is turned-off
or its frequency changes), then tCKSRE and tCKSRX must be
satisfied. When entering self refresh mode, tCKSRE must be
satisfied prior to altering the clock's frequency. Prior to exiting
self refresh mode, tCKSRX must be satisfied prior to registering
CKE HIGH.
When all banks are to be precharged, inputs BA[2:0] are
treated as “Don’t Care.” After a bank is precharged, it is in the
idle state and must be activated prior to any READ or WRITE
commands being issued.
SELF REFRESH Operation
The SELF REFRESH operation is initiated like a REFRESH
command except CKE is LOW. The DLL is automatically
disabled upon entering SELF REFRESH and is automatically
enabled and reset upon exiting SELF REFRESH.
All power supply inputs (including VREFCA and VREFDQ) must
be maintained at valid levels upon entry/exit and during self
refresh mode operation. VREFDQ may float or not drive VDDQ/2
while in self refresh mode under certain conditions:
When CKE is HIGH during self refresh exit, NOP or DES must
be issued for tXS time. tXS is required for the completion of
any internal refresh already in progress and must be satisfied
before a valid command not requiring a locked DLL can be
issued to the device. tXS is also the earliest time self refresh
re-entry may occur. Before a command requiring a locked DLL
can be applied, a ZQCL command must be issued, tZQOPER
timing must be met, and tXSDLL must be satisfied. ODT must
be off during tXSDLL.
• VSS < VREFDQ < VDD is maintained.
• VREFDQ is valid and stable prior to CKE going
back HIGH.
• The first WRITE operation may not occur earlier than
512 clocks after VREFDQ is valid.
• All other self refresh mode exit timing requirements
are met.
The DRAM must be idle with all banks in the precharge state
(tRP is satisfied and no bursts are in progress) before a self
refresh entry command can be issued. ODT must also be
turned off before self refresh entry by registering the ODT ball
LOW prior to the self refresh entry command (see “On-Die
Termination (ODT)” on page 108 for timing requirements). If
RTT,nom and RTT(WR) are disabled in the mode registers, ODT
can be a “Don’t Care.” After the self refresh entry command is
registered, CKE must be held LOW to keep the DRAM in self
refresh mode.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
96
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb:
x4, x8, x16 DDR3L SDRAM
*Advanced information. Subject to change without notice.
SELF REFRESH Operation
Figure 60: Self Refresh Entry/Exit Timing
Figure 95: Self Refresh Entry/Exit Timing
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Te0
Tf0
Valid
Valid
CK#
CK
tCKSRX1
tCKSRE1
tIS
tIH
tCPDED
tIS
CKE
tCKESR
(MIN)1
tIS
ODT2
Valid
ODTL
RESET#2
Command
NOP
SRE (REF)3
NOP4
SRX (NOP)
NOP5
Address
tRP8
Valid 6
Valid 7
Valid
Valid
tXS6, 9
tXSDLL7, 9
Enter self refresh mode
(synchronous)
Exit self refresh mode
(asynchronous)
Indicates break
in time scale
Don’t Care
1. The clock must be valid and stable, meeting tCK specifications at least tCKSRE after entering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the
clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and
Notes:
unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not
tCK specifications
tCKESR must be5.
1. The clock must be valid and stable,apply;
meeting
NOP orprior
DES to
commands
areSRX.
required prior to exiting self
however,
satisfied
exiting at
at least tCKSRE after entering self
refresh
mode,
and
at
refresh
mode
until
state
Te0.
2. ODT must be disabled and RTT off prior to entering self refresh at state T1. If both
least tCKSRX prior to exiting self refresh
mode,
clock
tXS mode
RTT,nom
andifRthe
are disabled6.
in the
registers,
can be a “Don’t
Care.”a
is required
before ODT
any commands
not requiring
TT(WR)
is stopped or altered between states
Ta0
and
Tb0.
If
the
3. Self refresh entry (SRE) is synchronous
via DLL.
a REFRESH command with CKE LOW.
locked
clock remains valid and unchanged
and command
during
4. Afrom
NOPentry
or DES
is required
at T2 after
the SRE
command
is issuedrequiring
prior toa the
7. tXSDLL
is required
before
any commands
tCKSRX
self refresh mode, then tCKSRE and
do not apply;
inputs
becoming
“Don’t Care.”
locked DLL.
however, tCKESR must be satisfied
prioror
to DES
exiting
at SRX. are required prior to exiting self refresh mode until state Te0.
5. NOP
commands
8. The device must be in the all banks idle state prior to entering
t
2. ODT must be disabled and RTT6.
off prior
entering self
refresh
XS istorequired
before
any commands
requiring
locked
DLL.all banks must be precharged,
selfnot
refresh
mode. a
For
example,
tXSDLL
at state T1. If both RTT,nom and 7.
RTT(WR)
are is
disabled
in the
required
before any commands
requiring
a
locked
DLL.
tRP must
be met, and no data bursts can be in progress.
mode registers, ODT can be a “Don’t
Care.”
8. The
device must be in the all banks
idlerefresh
state prior
entering self
refreshtXS
mode.
9. Self
exit is to
asynchronous;
however,
and tFor
XSDLL
example,
all banks must be precharged, tRP must be met, and no data bursts can be in
3. Self refresh entry (SRE) is synchronous
via a REFRESH
timings start at the first rising clock edge where CKE HIGH
progress.
command with CKE LOW.
tCKSRX timing is also measured so that
satisfies ttISXR at Tc1.
9. Self
exitSRE
is asynchronous; however,
XS and tXSDLL timings start at the first rising
4. A NOP or DES command is required
at refresh
T2 after the
tISXR is satisfied at Tc1.
clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that
command is issued prior to the inputs
becoming “Don’t Care.”
tISXR
is satisfied at Tc1.
Notes:
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
97
Form #: CSI-D-685 Document 009
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Extended Temperature Usage
Micross’ DDR3 SDRAM support the optional extended case
temperature (TC) range of 0°C to 95°C. Thus, the SRT and
ASR options must be used at a minimum.
from 64ms to 32ms. However, self refresh mode requires either
ASR or SRT to support the extended temperature. Thus, either
ASR or SRT must be enabled when TC is above 85°C or self
refresh cannot be used until TC is at or below 85°C. Table 31
summarizes the two extended temperature options and Table
32 summarizes how the two extended temperature options
relate to one another.
The extended temperature range DRAM must be refreshed
externally at 2x (double refresh) anytime the case temperature is
above 85°C (and does not exceed 95°C). The external refresh
requirement is accomplished by reducing the refresh period
Table 31: Self Refresh Temperature and Auto Self Refresh Description
Field
MR2
Bits
Description
Self Refresh Temperature (SRT)
SRT
7
If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh:
• MR2[7] = 0: Normal operating temperature range (0°C to 85°C)
• MR2[7] = 1: Extended operating temperature range (0°C to 95°C)
If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is supported
• MR2[7] = 0: SRT is disabled
Auto Self Refresh (ASR)
ASR
6
When ASR is enabled, the DRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating
temperature values).
• MR2[6] = 1: ASR is enabled (M7 must = 0)
When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESH operation.
• MR2[6] = 0: ASR is disabled; must use manual self refresh temperature (SRT)
Table 32: Self Refresh Mode Summary
MR2[6]
(ASR)
MR2[7]
(SRT)
SELF REFRESH Operation
0
0
Self refresh mode is supported in the normal temperature range
Normal (0°C to 85°C)
0
1
Self refresh mode is supported in normal and extended
temperature ranges; When SRT is enabled, it increases self
refresh power consumption
Normal and extended (0°C to 95°C)
1
0
Self refresh mode is supported in normal and extended
temperature ranges; Self refresh power consumption may be
temperature-dependent
Normal and extended (0°C to 95°C)
1
1
Illegal
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
Permitted Operating Temperature Range for Self Refresh Mode
98
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Power-Down Mode
Power-down is synchronously entered when CKE is registered
LOW coincident with a NOP or DES command. CKE is not
allowed to go LOW while an MRS, MPR, ZQCAL, READ,
or WRITE operation is in progress. CKE is allowed to go
LOW while any of the other legal operations (such as ROW
ACTIVATION, PRECHARGE, auto precharge, or REFRESH)
are in progress. However, the power-down IDD specifications
are not applicable until such operations have completed.
Depending on the previous DRAM state and the command
issued prior to CKE going LOW, certain timing constraints must
be satisfied (as noted in Table 33). Timing diagrams detailing
the different power-down mode entry and exits are shown in
Figure 61 (page 101) through Figure 70 (page 105).
Table 33: Command to Power-Down Entry Parameters
DRAM Status
Last Command Prior to CKE LOW1
Parameter (Min)
Parameter Value
Figure
Idle or active
ACTIVATE
tACTPDEN
1tCK
Figure 68 (page 104)
Idle or active
PRECHARGE
tPRPDEN
1tCK
Figure 69 (page 105)
Active
READ or READAP
tRDPDEN
RL + 4tCK + 1tCK
Figure 64 (page 102)
Active
WRITE: BL8OTF, BL8MRS, BC4OTF
WL + 4tCK + tWR/tCK
Figure 65 (page 103)
Active
WRITE: BC4MRS
WL + 2tCK + tWR/tCK
Figure 65 (page 103)
Active
WRITEAP: BL8OTF, BL8MRS, BC4OTF
WL + 4tCK + WR + 1tCK
Figure 66 (page 103)
Active
WRITEAP: BC4MRS
WL + 2tCK + WR + 1tCK
Figure 66 (page 103)
Idle
REFRESH
tREFPDEN
1tCK
Figure 67 (page 104)
Power-down
REFRESH
tXPDLL
Greater of 10tCK or 24ns
Figure 71 (page 106)
Idle
MODE REGISTER SET
tMRSPDEN
tMOD
Figure 70 (page 105)
tWRPDEN
tWRAPDEN
Notes:
1. If slow-exit mode precharge power-down is enabled and
entered, ODT becomes asynchronous tANPD prior to CKE
going LOW and remains asynchronous until tANPD + tXPDLL
after CKE goes HIGH.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
99
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Power-Down Mode (continued)
Entering power-down disables the input and output buffers,
excluding CK, CK#, ODT, CKE, and RESET#. NOP or DES
commands are required until tCPDED has been satisfied, at
which time all specified input/output buffers are disabled. The
DLL should be in a locked state when power-down is entered
for the fastest power-down exit timing. If the DLL is not locked
during power-down entry, the DLL must be reset after exiting
power-down mode for proper READ operation as well as
synchronous ODT operation.
ODT must be in a valid state but all other input signals are
“Don’t Care.” If RESET# goes LOW during power-down, the
DRAM will switch out of power-down mode and go into the
reset state. After CKE is registered LOW, CKE must remain
LOW until tPD (MIN) has been satisfied. The maximum time
allowed for powerdown duration is tPD (MAX) (9 × tREFI).
The power-down states are synchronously exited when CKE
is registered HIGH (with a required NOP or DES command).
CKE must be maintained HIGH until tCKE has been satisfied. A
valid, executable command may be applied after power-down
exit latency, tXP, and tXPDLL have been satisfied. A summary
of the power-down modes is listed below.
During power-down entry, if any bank remains open after all inprogress commands are complete, the DRAM will be in active
power-down mode. If all banks are closed after all in-progress
commands are complete, the DRAM will be in precharge
power-down mode. Precharge power-down mode must be
programmed to exit with either a slow exit mode or a fast exit
mode. When entering precharge power-do n mode, the DLL is
turned off in slow exit mode or kept on in fast exit mode.
For specific CKE-intensive operations, such as repeating a
power-down-exit-to-refreshto-power-down-entry sequence,
the number of clock cycles between power-down exit and
power-down entry may not be sufficient to keep the DLL
properly updated. In addition to meeting tPD when the
REFRESH command is used between power-down exit and
power-down entry, two other conditions must be met. First,
tXP must be satisfied before issuing the REFRESH command.
Second, tXPDLL must be satisfied before the next powerdown may be entered. An example is shown in Figure 71 (page
106).
The DLL also remains on when entering active power-down.
ODT has special timing constraints when slow exit mode
precharge power-down is enabled and entered. Refer to
“Asynchronous ODT Mode” on page 119 for detailed ODT
usage requirements in slow exit mode precharge power-down.
A summary of the two power-down modes is listed in Table 34
(page 100).
While in either power-down state, CKE is held LOW, RESET#
is held HIGH, and a stable clock signal must be maintained.
Table 34: Power-Down Modes
DRAM State
Active (any bank open)
Precharged
(all banks precharged)
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
MR0[12]
DLL State
Power-Down Exit
Relevant Parameters
“Don’t Care”
On
Fast
tXP
to any other valid command
1
On
Fast
tXP
to any other valid command
0
Off
Slow
tXPDLL
to commands that require the DLL to be locked (READ, RDAP, or ODT
on); tXP to any other valid command
100
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
2Gb: x4, x8, Power-Down
x16 DDR3L SDRAM
Mode
*Advanced information.
Subject to change without
notice.
Power-Down
Mode
Figure 61: Active Power-Down Entry and Exit
Figure 96: Active Power-Down Entry and Exit
Figure 96: Active Power-Down Entry and Exit
CK#
CK#
CK
CK
Command
Command
T0
T0
T1
T1
tCK
T2
T2
tCH
tCK
Address
Address
Ta2
Ta2
Ta3
Ta3
Ta4
Ta4
NOP
NOP
NOP
NOP
NOP
NOP
Valid
Valid
tCL
NOP
NOP
tPD
tPD
tIS
CKE
CKE
Ta1
Ta1
tCL
tCH
NOP
NOP
Valid
Valid
Ta0
Ta0
tIS
tIH
tIH
tIH
tCKE
tIS
tIH
tCKE
tIS
(MIN)
(MIN)
Valid
Valid
Valid
Valid
tXP
tCPDED
tXP
tCPDED
Enter power-down
Enter power-down
mode
mode
Exit power-down
Exit power-down
mode
mode
Indicates break
in time scale
Indicates
break
in time scale
Don’t Care
Don’t Care
Figure
97: Precharge
Power-Down
(Fast-Exit
Mode)
Entry and Exit
Figure
62: Precharge
Power-Down
(Fast-Exit
Mode) Entry
and Exit
Figure 97: Precharge Power-Down (Fast-Exit Mode) Entry and Exit
CK#
CK#
CK
CK
T0
T0
T1
T1
t
t
CK
CK
T2
T2
t
t
t
t
CH
CH
Command
Command
NOP
NOP
T3
T3
t
NOP
NOP
NOP
NOP
t
CPDED
CPDED
t
t
t
CKE
CKE
T5
T5
IS
IS
t
t
IH
IH
t
t
t
IS
IS
PD
PD
t
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf
- Rev. K 9/13 EN
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
Ta1
Ta1
NOP
NOP
Valid
Valid
CKE (MIN)
CKE (MIN)
t
t
Enter power-down
Enter power-down
mode
mode
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
Ta0
Ta0
CL
CL
NOP
NOP
t
T4
T4
Exit power-down
Exit power-down
mode
mode
XP
XP
Indicates break
in
time scale
Indicates
break
in time scale
Don’t Care
Don’t Care
101
183
183
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron
Technology,
Inc. All
reserved.
Form
#: rights
CSI-D-685
Document 009
Micron Technology, Inc. reserves the right to©change
products
or specifications
without
notice.
© 2010 Micron Technology, Inc. All rights reserved.
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Mode
2Gb: x4, x8, Power-Down
x16 DDR3L SDRAM
*Advanced information.
Subject to change without
notice.
Power-Down
Mode
Figure
63: Precharge
Power-Down
(Slow-Exit
Mode) Entry
and Exit
Figure
98: Precharge
Power-Down
(Slow-Exit
Mode)
Entry and Exit
Figure 98: Precharge Power-Down (Slow-Exit Mode) Entry and Exit
CK#
T0
T1
T2
T3
T4
Ta
Ta1
Tb
T0
T1
T2
T3
T4
Ta
Ta1
Tb
NOP
NOP
NOP
Valid 1
Valid 2
NOP
NOP
NOP
Valid 1
Valid 2
CK
CK#
CK
Command
PRE
Command
PRE
tCK
tCH
tCL
tCK
tCH
tCL
NOP
NOP
CKE
tCPDED
tCKE
(MIN)
tCPDED
tCKE
(MIN)
tIS
tIH
tIS
tIH
tXP
CKE
tPD
tPD
Enter power-down
mode
Enter power-down
mode
Notes:
tXP
tIS
tXPDLL
tIS
tXPDLL
Exit power-down
mode
Exit power-down
mode
Indicates break
in time scale
Indicates break
in time scale
1. Any valid command not requiring a locked DLL.
AnyDLL.
valid command not requiring a locked DLL.
Notes: a 1.
2. Any valid command requiring
locked
2.
Any
valid command requiring
a locked
DLL.DLL.
not requiring
a locked
Notes: 1.
Don’t Care
Don’t Care
2. Any valid command requiring a locked DLL.
Figure
99: Power-Down
Entry
After
READwith
or READ
with Auto
Precharge (RDAP)
Figure
64: Power-Down
Entry After
READ
or READ
Auto Precharge
(RDAP)
Figure 99:
Power-Down
Entry
After
READ
or READ
with
Auto
Precharge
(RDAP)
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
CK#
CK
CK#
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
CK
Command
READ/
RDAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
READ/
RDAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CKE
Ta7
Ta8
NOP
Ta11
Ta12
Ta10
Ta11
Ta12
NOP
tIS
tCPDED
tIS
tCPDED
NOP
Ta9
Ta10
NOP
CKE
Address
Valid
Address
Valid
DQS, DQS#
RL = AL + CL
tPD
RL = AL + CL
tPD
DQS, DQS#
DQ BL8
DI
n
DI
DI
n+1 n+2
DI
n+3
DI
n+4
DI
n+ 5
DI
n+6
DI
n+7
DQ BL8
DI
n
DI
n
DI
DI
DI
n+1 n+2 n+3
DI
DI
DI
n+1 n+2 n+3
DI
n+4
DI
n+ 5
DI
n+6
DI
n+7
DQ BC4
DQ BC4
DI
tDI
RDPDEN
n
n+1
DI
DI
n+2 n+3
tRDPDEN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
Power-down or
self refresh entry
Power-down or
self refresh entry
Indicates break
in time scale
Indicates break
in time scale
Transitioning Data
Don’t Care
Transitioning Data
Don’t Care
102
184
184
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
2Gb SDRAM-DDR3L
2Gb:MYX4DDR3L128M16JT*
x4, x8, x16 DDR3L SDRAM
2Gb: x4, x8, Power-Down
x16 DDR3L SDRAM
Mode
Power-Down Mode
*Advanced information. Subject to change without notice.
Figure
100: Power-Down
Entry
After WRITE
Figure
65: Power-Down
Entry After
WRITE
Figure 100: Power-Down Entry After WRITE
CK#
CK#
CK
T0
T0
T1
T1
Ta0
Ta0
Ta1
Ta1
Ta2
Ta2
Ta3
Ta3
Ta4
Ta4
Ta5
Ta5
Ta6
Ta6
Ta7
Ta7
Tb0
Tb0
WRITE
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tb1
Tb1
Tb2
Tb2
NOP
NOP
NOP
Tb3
Tb3
Tb4
Tb4
CK
Command
Command
tISNOP tCPDED
tIS
tCPDED
CKE
CKE
Address
Address
Valid
Valid
WL = AL + CWL
WL = AL + CWL
tWR
tPD
tWR
tPD
DQS, DQS#
DQS, DQS#
DQ BL8
DQ BL8
DI
n
DI
n
DI
DI
n+1 n+2
DI
DI
n+1 n+2
DQ BC4
DQ BC4
DI
n
DI
n
DI
n+1
DI
n+1
DI
n+3
DI
n+3
DI
n+4
DI
n+4
DI
DI
n+5 n+6
DI
DI
n+5 n+6
DI
n+7
DI
n+7
DI
DI
n+2 n+3
DI
DI
n+2 n+3
tWRPDEN
tWRPDEN
Power-down or
self
refresh entry
Power-down
or 1
self refresh entry1
Note:
1. CKE can go LOW 2tCK earlier if BC4MRS.
Note:
Note:
Indicates break
in
time scale
Indicates
break
in time scale
Transitioning Data
Transitioning Data
Don’t Care
Don’t Care
1. CKE can go LOW 2ttCK earlier if BC4MRS.
1. CKE can go LOW 2 CK earlier if BC4MRS.
Figure 66: Power-Down Entry After WRITE with Auto Precharge (WRAP)
Figure 101: Power-Down Entry After WRITE with Auto Precharge (WRAP)
Figure 101: Power-Down Entry After WRITE with Auto Precharge (WRAP)
CK#
CK#
CK
T0
T0
T1
T1
Ta0
Ta0
Ta1
Ta1
Ta2
Ta2
Ta3
Ta3
Ta4
Ta4
Ta5
Ta5
Ta6
Ta6
Ta7
Ta7
Tb0
Tb0
Tb1
Tb1
Tb2
Tb2
WRAP
WRAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tb3
Tb3
Tb4
Tb4
CK
Command
Command
tIS
tIS
tCPDED
tCPDED
CKE
CKE
Address
Address
Valid
Valid
A10
A10
WR1
WR1
WL = AL + CWL
WL = AL + CWL
DQS, DQS#
DQS, DQS#
DQ BL8
DQ BL8
DI
n
DI
n
DI
n+1
DI
n+1
DI
DI
DI
n+2 n+3 n+4
DI
DI
DI
n+2 n+3 n+4
DQ BC4
DQ BC4
DI
n
DI
n
DI
n+1
DI
n+1
DI
DI
n+2 n+3
DI
DI
n+2 n+3
tWRAPDEN
tWRAPDEN
DI
n+5
DI
n+5
Notes:
DI
n+6
DI
n+6
tPD
DI
n+7
DI
n+7
Start internal
precharge
Start
internal
precharge
1. tWR is programmed through MR0[11:9] and represents
tWRmin (ns)/tCK rounded up to the next integer tCK.
tPD
Power-down or
self
refresh entry
Power-down
or 2
self refresh entry2
Indicates break
in time scale
Indicates
break
in time scale
Transitioning Data
Transitioning Data
Don’t Care
Don’t Care
2. CKE can go LOW 2tCK earlier if BC4MRS.
Notes: 1. ttWR is programmed through MR0[11:9] and represents ttWRmin (ns)/ttCK rounded up to
WRnext
is programmed
Notes: 1. the
integer tCK.through MR0[11:9] and represents WRmin (ns)/ CK rounded up to
the next integer tCK.
2. CKE can go LOW 2ttCK earlier if BC4MRS.
2. CKE can go LOW 2 CK earlier if BC4MRS.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf
- Rev. K 9/13 EN
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2Gb_DDR3L.pdf - Rev. K 9/13 EN
103
185
185
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron
Technology,
Inc. All rights
reserved.
Micron Technology, Inc. reserves the right to©change
products
or specifications
without
notice.
© 2010 Micron Technology,Form
Inc. All
reserved.
#: rights
CSI-D-685
Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
2Gb:
x4,information.
x8, x16Subject
DDR3L
SDRAM
*Advanced
to change
without notice.
Power-Down Mode
Figure
67: REFRESH to Power-Down Entry
Figure 102: REFRESH to Power-Down Entry
Figure 102: REFRESH
to Power-Down
Entry
T0
T1
T2
CK#
CK
CK#
T0
CK
Command
T1
tCK
tCH
tCL
tCK
tCH
REFRESH
tCL
Command
REFRESH
T3
Ta0
Ta1
Ta2
Tb0
T2
T3
Ta0
Ta1
Ta2
Tb0
NOP
NOP
NOP
NOP
NOP
NOP
tIS
tCPDED
tPD
tCPDED
NOP
(MIN)
Valid
tCKE
tCKE
tREFPDEN
CKE
Valid
(MIN)
tPD
tIS
CKE
NOP
tREFPDEN
Note:
tRFC
(MIN)1
tRFC
(MIN)1
tXP
(MIN)
tXP
(MIN)
Indicates break
in time scale
1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.
Don’t Care
Indicates break
Don’t Care
in time scale
until tRFC is satisfied.
Note:
1. After CKE goes HIGH during tRFC, CKE must remain HIGH
Note:
1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.
Figure 103: ACTIVATE to Power-Down Entry
Figure 68: ACTIVATE
to Power-Down
Entry
T0
T1
T2 Entry
Figure 103: ACTIVATE to Power-Down
CK#
CK
CK#
T0
CK
Command
Command
T1
tCK
tCH
tCL
tCK
tCH
ACTIVE
tCL
ACTIVE
Address
Valid
Address
Valid
CKE
T4
T5
T6
T7
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
tCPDED
tIS
CKE
T3
tCPDED
tPD
tIS
tPD
tACTPDEN
tACTPDEN
Don’t Care
Don’t Care
MYX4DDR3L128M16JT*
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© 2010 Micron Technology,Form
Inc. All
reserved.
#: rights
CSI-D-685
Document 009
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
*Advanced information. Subject to change without notice.
Figure
69: PRECHARGE
to Power-Down
Entry
Figure
104: PRECHARGE
to Power-Down
Entry
T0
T1
T2
T3
T4
NOP
NOP
T5
T6
T7
CK#
CK
tCK
Command
tCH
tCL
PRE
All/single
bank
Address
tCPDED
tIS
tPD
CKE
tPREPDEN
Don’t Care
Figure
70: MRS Command to Power-Down Entry
Figure 105: MRS Command to Power-Down Entry
CK#
T0
CK
T1
tCK
Command
MRS
Address
Valid
T2
tCH
NOP
Ta0
Ta1
Ta2
Ta3
Ta4
tCPDED
tCL
NOP
NOP
NOP
tMRSPDEN
NOP
tPD
tIS
CKE
Indicates break
in time scale
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
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Don’t Care
105
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
*Advanced information. Subject to change without notice.
Figure
71: Power-Down Exit to Refresh to Power-Down Entry
Figure 106: Power-Down Exit to Refresh to Power-Down Entry
T0
T1
T2
T3
T4
Ta0
NOP
REFRESH
Ta1
Tb0
CK#
CK
Command
tCK
NOP
tCH
tCL
NOP
NOP
tCPDED
NOP
NOP
tXP1
tIH
tIS
CKE
tIS
tPD
tXPDLL2
Enter power-down
mode
Enter power-down
mode
Exit power-down
mode
Notes:
Indicates break
in time scale
1. tXP must be satisfied before issuing the command.
Don’t Care
2. tXPDLL must be satisfied (referenced
to the registration of
Notes: 1. tXP must be satisfied before issuing the command.
power-down exit) before the next power-down
can be entered.
2. tXPDLL must be satisfied (referenced to the registration of power-down exit) before the
next power-down can be entered.
RESET Operation
The RESET signal (RESET#) is an asynchronous reset signal
that triggers any time it drops LOW, and there are no restrictions
about when it can go LOW. After RESET# goes LOW, it must
remain LOW for 100ns. During this time, the outputs are
disabled, ODT (RTT) turns off (High-Z), and the DRAM resets
itself. CKE should be driven LOW prior to RESET# being
driven HIGH. After RESET# goes HIGH, the DRAM must be
re-initialized as though a normal power-up was executed. All
refresh counters on the DRAM are reset, and data stored in
the DRAM is assumed unknown after RESET# has gone LOW.
MYX4DDR3L128M16JT*
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106
188
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology,Form
Inc. All
reserved.
#: rights
CSI-D-685
Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
RESET Operation
*Advanced information. Subject to change without notice.
Figure 72: RESET Sequence
Figure 107: RESET Sequence
System RESET
(warm boot)
Stable and
valid clock
T0
T1
tCK
Tc0
Tb0
Ta0
Td0
CK#
CK
tCL
tCL
t CKSRX1
T = 100ns (MIN)
RESET#
tIOZ
= 20ns
T = 10ns (MIN)
tIS
Valid
CKE
tIS
tIS
Static LOW in case RTT_Nom is enabled at time Ta0, otherwise static HIGH or LOW
ODT
Valid
tIS
MRS
MRS
MRS
MRS
Address
Code
Code
Code
Code
A10
Code
Code
Code
Code
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
Command
NOP
Valid
ZQCL
DM
BA[2:0]
DQS
DQ
RTT
Valid
Valid
A10 = H
Valid
High-Z
High-Z
High-Z
T = 500μs (MIN)
MR2
All voltage
supplies valid
and stable
tMRD
tMRD
tXPR
MR3
DRAM ready
for external
commands
tMRD
MR1 with
DLL ENABLE
tMOD
MR0 with
DLL RESET
ZQCAL
tZQinit
tDLLK
Normal
operation
Note:
1. The minimum time required is the longer of 10ns or 5 clocks.
Note:
MYX4DDR3L128M16JT*
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Indicates break
in time scale
Don’t Care
1. The minimum time required is the longer of 10ns or 5 clocks.
107
190
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology,Form
Inc. All
reserved.
#: rights
CSI-D-685
Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
On-Die Termination (ODT)
2Gb: x4, x8, x16 DDR3L SDRAM
On-Die Termination (ODT)
On-die termination (ODT) is a feature that enables the DRAM to
enable/disable and turn on/off termination resistance for each
mination
(ODT)
DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for
On-die
termination (ODT) is a feature that enables the DRAM to enable/disable and
the
x16 configuration.
turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8
configurations
(and
TDQS, TDQS#
the x8ofconfiguration,
ODT
is designed
to improve
signal for
integrity
the memory when enabled). ODT is applied to each
DQ, UDQS,
UDQS#,
LDQS, LDQS#,
UDM, and LDM signal for the x16 conchannel
by enabling
the DRAM
controller
to independently
figuration.
turn
on/off the DRAM’s internal termination resistance for any
grouping
of DRAMtodevices.
ODT
is not
supported
during
DLL channel by enabling the
ODT is designed
improve
signal
integrity
of the
memory
disable
(simple
functional representation
shown
below). internal termination resistDRAM mode
controller
to independently
turn on/off
the DRAM’s
The
is enabled
internal
ODT control
which
anceswitch
for any
groupingbyofthe
DRAM
devices.
ODT islogic,
not supported
during DLL disable
modethe
(simple
functional
representation
below). The switch is enabled by the inuses
external
ODT ball and
other controlshown
information.
ternal ODT control logic, which uses the external ODT ball and other control information.
Figure 73: Figure 108: On-Die Termination
Die Termination
ODT
To other
circuitry
such as
RCV,
...
RTT
VDDQ/2
Switch
DQ, DQS, DQS#,
DM, TDQS, TDQS#
epresentation of ODT
The value ofRepresentation
RTT (ODT termination
by the
settings of
Functional
of ODT resistance value) is determined
Nominal
ODT
several mode register bits (see Table 87 (page 195)). The ODT ball is ignored while in
The
value mode
of RTT(must
(ODTbetermination
resistance
ODT
is the base termination resistance for each
self refresh
turned off prior
to self value)
refreshisentry)
or if(NOM)
mode registers
MR1 and MR2
are settings
programmed
to disable
ODT. ODT
comprised
of nominal
and or disabled via MR1[9, 6, 2] (see
determined
by the
of several
mode register
bits is(see
applicable
ball; it ODT
is enabled
dynamic
ODT
modes
can function
or asynchronous
Table
40 on
page
113).and
Theeither
ODT of
ballthese
is ignored
while in in
selfsynchronous
Mode Register
1 (MR1) Definition), and it is turned on or off via
mode (when
the DLL
off during
precharge
power-down
the ball.
DLL is synchrorefresh
mode (must
be is
turned
off prior
to self refresh
entry) or or when
the ODT
nizing).
Nominal
ODT
is
the
base
termination
and
is
used
in
any
allowable
ODT state.
if mode registers MR1 and MR2 are programmed to disable
Dynamic
ODT
is
applied
only
during
writes
and
provides
OTF
switching
from
no RTT or
ODT. ODT is comprised of nominal ODT and dynamic ODT
RTT,nom to RTT(WR).
modes and either of these can function in synchronous or
The actual effective
RTT(EFF)
may beprecharge
different from RTT targeted due to
asynchronous
mode termination,
(when the DLL
is off , during
nonlinearity
of
the
termination.
For
R
values
and
calculations, see Table 32
power-down or when the DLL is synchronizing).
ODT
TT(EFF) Nominal
(page
56).
is the base termination and is used in any allowable ODT state.
Dynamic ODT is applied only during writes and provides OTF
switching from no RTT or RTT,nom to RTT(WR).
ODT (NOM) is the base termination resistance for each applicable ball; it is enabled or
The actual effective termination, RTT(EFF), may be different from
disabled via MR1[9, 6, 2] (see Mode Register 1 (MR1) Definition), and it is turned on or
R
targeted
dueball.
to nonlinearity of the termination. For RTT(EFF)
TTvia
off
the ODT
values and calculations, see Table 17 (page 20).
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
108
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 35: Truth Table – ODT (Nominal)
Note 1 applies to the entire table.
MR1[9, 6, 2]
ODT Pin
DRAM Termination State
DRAM State
Notes
0
0
RTT,nom disabled, ODT off
Any valid
2
0
1
RTT,nom disabled, ODT on
Any valid except self refresh, read
3
000–101
0
RTT,nom enabled, ODT off
Any valid
2
000–101
1
RTT,nom enabled, ODT on
Any valid except self refresh, read
3
110 and 111
X
RTT,nom reserved, ODT on or off
Illegal
Notes:
1. Assumes dynamic ODT is disabled (see “Dynamic ODT” on
page 111 when enabled).
2. ODT is enabled and active during most writes for proper
termination, but it is not illegal for it to be off during writes.
3. ODT must be disabled during reads. The RTT,nom value is
restricted during writes. Dynamic ODT is applicable if enabled.
Nominal ODT resistance RTT,nom is defined by MR1[9, 6, 2],
as shown in Mode Register 1 (MR1) Definition. The RTT,nom
termination value applies to the output pins previously
mentioned. DDR3 SDRAM supports multiple RTT,nom values
based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is
240Ω. RTT,nom termination is allowed any time after the DRAM
is initialized, calibrated, and not performing read access, or
when it is not in self refresh mode.
Write accesses use RTT,nom if dynamic ODT (RTT(WR)) is
disabled. If RTT,nom is used during writes, only RZQ/2, RZQ/4,
and RZQ/6 are allowed (see Table 39 on page 112). ODT
timings are summarized in Table 36 (page 110), as well as
listed in the Electrical Characteristics and AC Operating
Conditions table.
Examples of nominal ODT timing are shown in conjunction
with the synchronous mode of operation in “Synchronous ODT
Mode” on page 117.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
109
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 36: ODT Parameters
Description
Begins at
Defined to
Definition for All
DDR3L Speed Bins
Unit
ODTLon
ODT synchronous turn-on delay
ODT registered HIGH
RTT(ON) ±tAON
CWL + AL - 2
tCK
ODTLoff
ODT synchronous turn-off delay
ODT registered HIGH
RTT(OFF) ±tAOF
CWL + AL - 2
tCK
tAONPD
ODT asynchronous turn-on delay
ODT registered HIGH
RTT(ON)
2–8.5
ns
tAOFPD
ODT asynchronous turn-off delay
ODT registered HIGH
RTT(OFF)
2–8.5
ns
ODTH4
ODT minimum HIGH time after ODT
assertion or write (BC4)
ODT registered HIGH or write
registration with ODT HIGH
ODT registered LOW
4tCK
tCK
ODTH8
ODT minimum HIGH time after write (BL8)
Write registration with ODT HIGH
ODT registered LOW
6tCK
tCK
tAON
ODT turn-on relative to ODTLon completion
Completion of ODTLon
RTT(ON)
See Electrical Characteristics and
AC Operating Conditions table
ps
tAOF
ODT turn-off relative to ODTLoff completion
Completion of ODTLoff
RTT(OFF)
0.5tCK ± 0.2tCK
tCK
Symbol
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
110
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
When enabling this special use case, some standard ODT spec
conditions may be violated: ODT is sometimes suppose to be
held low. Such ODT spec violation (ODT not LOW) is allowed
under this special use case. Most notably, if Write Leveling is
used, this would appear to be a problem since RTT(WR) can not
be used (should be disabled) and RTT(NOM) should be used.
For Write leveling during this special use case, with the DLL
locked, then RTT(NOM) maybe enabled when entering Write
Leveling mode and disabled when exiting Write Leveling mode.
More so, RTT(NOM) must be enabled when enabling Write
Leveling, via same MR1 load, and disabled when disabling
Write Leveling, via same MR1 load if RTT(NOM) is to be used.
Dynamic ODT
In certain application cases, and to further enhance signal
integrity on the data bus, it is desirable that the termination
strength of the DDR3 SDRAM can be changed without issuing
an MRS command, essentially changing the ODT termination
on the fly. With dynamic ODT RTT(WR) enabled, the DRAM
switches from nominal ODT RTT,nom to dynamic ODT RTT(WR)
when beginning a WRITE burst and subsequently switches
back to nominal ODT RTT,nom at the completion of the WRITE
burst. This requirement is supported by the dynamic ODT
feature, as described below.
ODT will turn-on within a delay of ODTLon + tAON + tMOD +
1CK (enabling via MR1) or turn-off within a delay of ODTLoff
+ tAOF + tMOD + 1CK. As seen in the table below, between
the Load Mode of MR1 and the previously specified delay, the
value of ODT is uncertain. this means the DQ ODT termination
could turn-on and then turn-off again during the period of
stated uncertainty.
Dynamic ODT Special Use Case
When DDR3 devices are architect as a single rank memory
array, dynamic ODT offers a special use case: the ODT ball can
be wired high (via a current limiting resistor preferred) by having
RTT,nom disabled via MR1 and RTT(WR) enabled via MR2. This
will allow the ODT signal not to have to be routed yet the DRAM
can provide ODT coverage during write accesses.
Table 37: Automatic Table Numbering
Begin RTT,nom Uncertainty
End RTT,nom Uncertainty
MR1 load mode command:
Enable Write Leveling and RTT(NOM)
ODTLon + tAON + tMOD + 1CK
MR1 load mode command:
Disable Write Leveling and RTT(NOM)
ODTLoff + tAOFF + tMOD + 1CK
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
I/Os
RTT,nom Final State
DQS, DQS#
Drive RTT,nom value
DQs
No RTT,nom
DQS, DQS#
No RTT,nom
DQs
No RTT,nom
111
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Functional Description
The dynamic ODT mode is enabled if either MR2[9] or MR2[10]
is set to 1. Dynamic ODT is not supported during DLL disable
mode so RTT(WR) must be disabled. The dynamic ODT function
is described below:
is enabled, the ODT termination is controlled.
• A latency of ODTLcnw after the WRITE command:
termination strength RTT,nom switches to RTT(WR)
• A latency of ODTLcwn8 (for BL8, fixed or OTF) or
ODTLcwn4 (for BC4, fixed or OTF) after the WRITE
command: termination strength RTT(WR) switches
back to RTT,nom.
• Two RTT values are available—RTT,nom and RTT(WR).
• The value for RTT,nom is preselected via
MR1[9, 6, 2].
• On/off termination timing is controlled via the ODT
ball and determined by ODTLon, ODTLoff, ODTH4,
and ODTH8.
• The value for RTT(WR) is preselected via MR2[10, 9].
• During DRAM operation without READ or WRITE
commands, the termination is controlled.
• During the tADC transition window, the value of RTT
is undefined.
• Nominal termination strength RTT,nom is used.
• Termination on/off timing is controlled via the ODT
ball and latencies ODTLon and ODTLoff.
ODT is constrained during writes and when dynamic ODT is
enabled (see Table 38 on page 112). ODT timings listed in
Table 35 (page 109) also apply to dynamic ODT mode.
• When a WRITE command (WR, WRAP, WRS4, WRS8,
WRAPS4, WRAPS8) is registered, and if dynamic ODT
Table 38: Dynamic ODT Specific Parameters
Symbol
Description
Begins at
Defined to
Definition for All DDR3L
Speed Bins
Unit
ODTLcnw
Change from RTT,nom to RTT(WR)
Write registration
RTT switched from RTT,nom to RTT(WR)
WL - 2
tCK
ODTLcwn4
Change from RTT(WR) to RTT,nom (BC4)
Write registration
RTT switched from RTT(WR) to RTT,nom
4tCK + ODTL off
tCK
ODTLcwn8
Change from RTT(WR) to RTT,nom (BL8)
Write registration
RTT switched from RTT(WR) to RTT,nom
6tCK + ODTL off
tCK
tADC
RTT change skew
ODTLcnw completed
RTT transition complete
0.5tCK ± 0.2tCK
tCK
Table 39: Mode Registers for RTT,nom
MR1 (RTT,nom)
RTT,nom (RZQ)
RTT,nom (Ohm)
RTT,nom Mode
Restriction
0
Off
Off
n/a
0
1
RZQ/4
60
Self refresh
0
1
0
RZQ/2
120
0
1
1
RZQ/6
40
1
0
0
RZQ/12
20
1
0
1
RZQ/8
30
1
1
0
Reserved
Reserved
n/a
1
1
1
Reserved
Reserved
n/a
M9
M6
M2
0
0
0
Self refresh, write
Note: 1. RZQ = 240Ω. If RTT,nom is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
112
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 40: Mode Registers for RTT(WR)
MR2 (RTT(WR))
RTT(WR) (RZQ)
RTT(WR) (Ohm)
M10
M9
0
0
Dynamic ODT off: WRITE does not affect RTT,nom
0
1
RZQ/4
60
1
0
RZQ/2
120
1
1
Reserved
Reserved
Table 41: Timing Diagrams for Dynamic ODT
Figure and Page
Title
Figure 74 (page 114)
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Figure 75 (page 114)
Dynamic ODT: Without WRITE Command
Figure 76 (page 115)
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Figure 77 (page 116)
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Figure 78 (page 116)
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
113
Form #: CSI-D-685 Document 009
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
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2Gb_DDR3L.pdf
2Gb_DDR3L.pdf
- Rev. K -9/13
Rev.EN
K 9/13 EN
T1
NOP
NOP
T0
NOP
NOP
T3
NOP
ODTH4
NOP
ODTH4
ODTLon
ODTLon
NOP
T2
NOP
(MIN)
tAON
ODTH4
ODTH4
NOP
T6
NOP
RTT,nom
ODTLcnw
(MAX)
ODTLcnw
RTT,nom
tAON
tAON
(MIN)
(MAX)
tAON
NOP
Valid
WRS4
Valid
T5
NOP
T4
WRS4
WL
WL
NOP
T8
NOP
tADC
(MAX)
ADC(MIN)
(MAX)
tADC
t
tADC (MIN)
ODTLcwn4
ODTLcwn4
NOP
T7
NOP
DI
n
DI
n
NOP
T9
NOP
DI
n+ 1
DI
n+ 1
RTT(WR)
RTT(WR)
DI
n+ 2
DI
n+ 2
NOP
T10
NOP
DI
n+ 3
DI
n+ 3
NOP
T11
NOP
(MIN)
tADC
(MAX)
ADC(MIN)
(MAX)
tADC
t
tADC
NOP
T12
NOP
T12
NOP
T13
NOP
T13
T15
NOP
T15
RTT,nom
NOP
T16
NOP
T16
Transitioning
ODTLoff
NOP
ODTLoff
RTT,nom
NOP
T14
NOP
T14
(MIN)
(MAX)
Don’t Care
tAOF
ttAOF
AOF(MIN)
(MAX)
tAOF
NOP
T17
NOP
T17
196 196
T2
T3
Valid
tAON
(MIN)
tAON (MAX)
tAON
(MIN)
Valid
ODTH4
ODTLon
ODTH4
ODTLon
tAON (MAX)
Valid
Valid
T4
Valid
Valid
T5
Valid
Valid
Valid
Valid
T6
T6
RTT,nom
RTT,nom
Valid
Valid
T7
T7
T9
T9
Valid
Valid
T10
T10
(MAX)
Transitioning
Transitioning
tAOF
tAOF (MIN)
tAOF (MAX)
tAOF
ODTLoff
(MIN)
Valid
Valid
ODTLoff
Valid
Valid
T8
T8
Don’t Care
Don’t Care
Valid
Valid
T11
T11
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Notes: 1. AL = 0, CWL = 5. RTT,nom is enabled and RTT(WR) is either enabled or disabled.
2. ODTH4
defined
fromenabled
ODT registered
HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT reg1. AL = 0, CWL = 5. RTT,nom is enabled
and is
RTT(WR)
is either
or disabled.
= 5. RTT,nom is enabled and RTT(WR) is either enabled or disabled.
Notes: 1. AL = 0, CWL
istered
LOW
at
T5
is
also
legal.
2. ODTH4 is defined from ODT registered
HIGH
to ODTfrom
registered
in this HIGH
example,
ODTH4
is satisfied.
ODTinregistered
LOW at
T5
2. ODTH4
is defined
ODT LOW;
registered
to ODT
registered
LOW;
this example,
ODTH4
is satisfied. ODT regis also legal.
istered LOW at T5 is also legal.
Notes:
DQ
DQS, DQS#
DQ
RTT
DQS, DQS#
ODT
RTT
ODT
Address
Valid
Address
Command
Valid
T1
Valid
T0
Valid
CK#
CK
CK#
Command
CK
Figure
Dynamic
ODT:T2Without
WRITET4Command
Figure
75:110:
Dynamic
ODT:
WRITET3Command
T0
T1 Without
T5
Figure 110: Dynamic ODT: Without WRITE Command
Transitioning
Don’t Care
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled.
1. Via MRS or OTF. AL = 0, CWL2.= ODTH4
5. RTT,nom
and
R
are
enabled.
TT(WR)
applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled.
is satisfied
goes LOW of
atthe
T8 WRITE
(four clocks
afterInthe
command).
2. ODTH4 applies to first registeringODTH4
ODT HIGH
and theniftoODT
the registration
command.
thisWRITE
example,
ODTH4 is satisfied if ODT
2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
goes LOW at T8 (four clocks after the WRITE command).
ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
Notes:
DQ
DQ
DQS, DQS#
DQS, DQS#
RTT
RTT
ODT
ODT
Address
Command
CK#
CK
Address
Command
CK
T0
T1
T2 ODT:
T3 ODT T4
T5
T6
T7
T8
T9 WRITE,
T10
T11
Figure
109:
Dynamic
Asserted
Before
and
After
the
BC4
CK#
Figure
74: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Figure 109: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
2Gb:
2Gb:
x4,x4,
x8,x8,
x16x16
DDR3L
DDR3L
SDRAM
SDRAM
Dynamic
Dynamic
ODT
ODT
Micron Technology,
Micron Technology,
Inc. reserves
Inc. reserves
the right
the
toright
change
to change
productsproducts
or specifications
or specifications
withoutwithout
notice. notice.
© 2010 Micron
© 2010 Technology,
Micron Technology,
Inc. All rights
Inc. Allreserved.
rights reserved.
114
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197
NOP
T0
Valid
WRS8
T1
NOP
T2
ODTLon
ODTLcnw
NOP
T3
WL
ODTH8
NOP
T4
tAON
(MAX)
(MIN)
tADC
NOP
T5
ODTLcwn8
DI
b
NOP
T6
DI
b+1
DI
b+2
RTT(WR)
NOP
T7
DI
b+3
DI
b+ 4
NOP
T8
DI
b+5
ODTLoff
DI
b+6
NOP
T9
DI
b+ 7
(MAX)
tAOF
Transitioning
tAOF
NOP
T10
(MIN)
Don’t Care
NOP
T11
this example,
2. In this example, ODTH8 = 62.is In
satisfied
exactly. ODTH8 = 6 is satisfied exactly.
1. Via
or OTF;can
ALbe
= 0,
CWLenabled
= 5. If Ror
can beODT
either
orRdisabled,
ODT can be HIGH. RTT(WR) is enabled.
Notes:
1. Via MRS or OTF; AL
= 0, CWL
= 5.MRS
If RTT,nom
either
disabled,
canenabled
be HIGH.
TT,nom
TT(WR) is enabled.
Notes:
DQ
DQS, DQS#
RTT
ODT
Address
Command
CK
CK#
Figure 111: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Figure 76: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Dynamic
2Gb: x4, x8, x16 DDR3L SDR
Micron Technology, Inc. reserves the right to change products or specifications wit
© 2010 Micron Technology, Inc. All righ
115
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
2Gb:
x4,
2Gb:MYX4DDR3L128M16JT*
x4, x8,
x8, x16
x16 DDR3L
DDR3L SDRAM
SDRAM
Dynamic ODT
Dynamic ODT
*Advanced information. Subject to change without notice.
Figure
Figure 112:
112: Dynamic
Dynamic ODT:
ODT: ODT
ODT Pin
Pin Asserted
Asserted with
with WRITE
WRITE Command
Command for
for 6
6 Clock
Clock Cycles,
Cycles, BC4
BC4
Figure 77: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
CK#
CK#
CK
CK
Command
Command
T0
T0
T1
T1
NOP
NOP
WRS4
WRS4
Address
Address
Valid
Valid
ODT
ODT
T2
T2
T3
T3
NOP
NOP
NOP
NOP
ODTLcnw
ODTLcnw
T4
T4
T5
T5
T6
T6
T7
T7
T8
T8
T9
T9
T10
T10
T11
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTH4
ODTH4
ODTLoff
ODTLoff
ODTLon
ODTLon
tADC
tADC
RTT
RTT
(MAX)
(MAX)
tAON
tAON
(MIN)
(MIN)
ODTLcwn4
ODTLcwn4
tAOF
tAOF
tADC
tADC
(MIN)
(MIN)
RTT,nom
RTT,nom
tADC (MAX)
tADC (MAX)
RTT(WR)
RTT(WR)
tAOF
tAOF
(MIN)
(MIN)
(MAX)
(MAX)
DQS, DQS#
DQS, DQS#
DQ
DQ
DI
n
DI
n
WL
WL
DI
n DI
+1
n+1
DI
n DI
+2
n+2
DI
n DI
+3
n+3
Transitioning
Transitioning
Notes:
Don’t Care
Don’t Care
Via
MRSand
or OTF.
AL are
= 0, CWL = 5. RTT,nom and RTT(WR) are enabled.
1. Via MRS or OTF. AL =Notes:
0, CWL =1.
RTT,nom
RTT(WR)
1.5.Via
MRS or OTF.
AL = 0,enabled.
CWL = 5. RTT,nom and RTT(WR) are enabled.
Notes:
2. ODTH4
is to
defined
from ODT
registered
HIGH to ODT registered LOW, so in this example,
2. ODTH4 is defined from ODT registered
HIGH
ODT registered
LOW,
so in
2. ODTH4
is defined
from ODT
registered
HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
ODTH4
is satisfied.
this example, ODTH4 is satisfied. ODT
registered
LOW atODT
T5 isregistered
also legal. LOW at T5 is also legal.
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
Figure
78: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
CK#
CK#
CK
CK
Command
Command
T0
T0
T1
T1
NOP
NOP
WRS4
WRS4
Address
Address
Valid
Valid
T2
T2
T3
T3
NOP
NOP
NOP
NOP
ODTLcnw
ODTLcnw
T4
T4
T5
T5
T6
T6
T7
T7
T8
T8
T9
T9
T10
T10
T11
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLoff
ODTLoff
ODTH4
ODTH4
ODT
ODT
tADC
tADC
ODTLon
ODTLon
RTT
RTT
tAOF
tAOF
(MAX)
(MAX)
tAON
tAON
(MIN)
(MIN)
ODTLcwn4
ODTLcwn4
RTT(WR)
RTT(WR)
(MIN)
(MIN)
tAOF
tAOF
(MAX)
(MAX)
DQS, DQS#
DQS, DQS#
WL
WL
Notes:
DI
n
DI
n
DQ
DQ
DI
n DI
+1
n+1
DI
n DI
+2
n+2
DI
n DI
+3
n+3
Transitioning
Transitioning
Don’t Care
Don’t Care
1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom can be either enabled or
1. ViaHIGH.
MRS or
OTF. is
AL = 0, CWL = 5. RTT,nom can be either enabled or disabled. If disabled,
Notes:
disabled. If disabled, ODT
can remain
RTT(WR)
1. Via MRS or
OTF. ALenabled.
= 0, CWL = 5. RTT,nom can be either enabled or disabled. If disabled,
Notes:
ODT can remain HIGH. RTT(WR) is enabled.
ODTexactly.
can remain HIGH. RTT(WR) is enabled.
2. In this example ODTH4 = 4 is satisfied
2. In this example ODTH4 = 4 is satisfied exactly.
2. In this example ODTH4 = 4 is satisfied exactly.
MYX4DDR3L128M16JT*
Revision
1.5 - 10/30/14
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2Gb_DDR3L.pdf - Rev. K 9/13 EN
116
198
198
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Micron Technology, Inc. reserves the right to©change
products
or specifications
without
notice.
2010 Micron
Technology,
Inc. All rights
reserved.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
register (MR1[4, 3]) also applies to the ODT signal. The device’s
internal ODT signal is delayed a number of clock cycles defined
by the AL relative to the external ODT signal. Thus, ODTLon =
CWL + AL - 2 and ODTLoff = CWL + AL - 2.
Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is
turned on and locked and when either RTT,nom or RTT(WR)
is enabled. Based on the power-down definition, these
modes are:
Timing Parameters
ODT Latency and Posted ODT
Synchronous ODT mode uses the following timing parameters:
ODTLon, ODTLoff, ODTH4, ODTH8, tAON, and tAOF. The
minimum RTT turn-on time (tAON [MIN]) is the point at which
the device leaves High-Z and ODT resistance begins to turn
on. Maximum RTT turn-on time (tAON [MAX]) is the point at
which ODT resistance is fully on. Both are measured relative
to ODTLon. The minimum RTT turn-off time (tAOF [MIN]) is the
point at which the device starts to turn off ODT resistance. The
maximum RTT turn off time (tAOF [MAX]) is the point at which
ODT has reached High-Z. Both are measured from ODTLoff.
In synchronous ODT mode, RTT turns on ODTLon clock cycles
after ODT is sampled HIGH by a rising clock edge and turns off
ODTLoff clock cycles after ODT is registered LOW by a rising
clock edge. The actual on/off times varies by tAON and tAOF
around each clock edge (see Table 42 on page 117). The
ODT latency is tied to the WRITE latency (WL) by ODTLon =
WL - 2 and ODTLoff = WL - 2.
When ODT is asserted, it must remain HIGH until ODTH4 is
satisfied. If a WRITE command is registered by the DRAM
with ODT HIGH, then ODT must remain HIGH until ODTH4
(BC4) or ODTH8 (BL8) after the WRITE command (see Figure
80 on page 118). ODTH4 and ODTH8 are measured from
ODT registered HIGH to ODT registered LOW or from the
registration of a WRITE command until ODT is registered LOW.
• Any bank active with CKE HIGH
• Refresh mode with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR0[12])
• Precharge power-down mode if DLL is enabled by
MR0[12] during precharge powerdown
Since write latency is made up of CAS WRITE latency (CWL)
and additive latency (AL), the AL programmed into the mode
Table 42: Synchronous ODT Parameters
Symbol
Description
Begins at
Defined to
Definition for All
DDR3L Speed Bins
Unit
ODTLon
ODT synchronous turn-on delay
ODT registered HIGH
RTT(ON) ±tAON
CWL + AL - 2
tCK
ODTLoff
ODT synchronous turn-off delay
ODT registered HIGH
RTT(OFF) ±tAOF
CWL +AL - 2
tCK
ODTH4
ODT minimum HIGH time after
ODT assertion or WRITE (BC4)
ODT registered HIGH or write
registration with ODT HIGH
ODT registered LOW
4tCK
tCK
ODTH8
ODT minimum HIGH time after WRITE (BL8)
Write registration with ODT HIGH
ODT registered LOW
6tCK
tCK
tAON
ODT turn-on relative to ODTLon completion
Completion of ODTLon
RTT(ON)
See Electrical Characteristics and
AC Operating Conditions table
ps
tAOF
ODT turn-off relative to ODTLoff completion
Completion of ODTLoff
RTT(OFF)
0.5tCK ± 0.2tCK
tCK
MYX4DDR3L128M16JT*
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MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
T0
T1
T2
T5
ODTLon = CWL + AL - 2
ODTH4 (MIN)
AL = 3
T3
T6
T7
(MAX)
(MIN)
tAON
tAON
T8
Completion of ODTLoff
T9
AL = 3
T11
T12
RTT,nom
ODTLoff = CWL + AL - 2
T10
RTT(OFF)
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without notice.
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2Gb_DDR3L.pdf
- Rev. K 9/13 EN
NOP
T0
NOP
T1
NOP
T2
NOP
T4
ODTLon = WL - 2
ODTH4
NOP
T3
NOP
T5
NOP
T6
ODTH4 (MIN)
NOP
T8
(MAX)
(MIN)
tAON
tAON
ODTH4
NOP
T9
RTT,nom
tAOF
ODTLon = WL - 2
ODTLoff = WL - 2
WRS4
T7
tAOF
(MIN)
NOP
T10
(MAX)
tAON
NOP
T11
(MIN)
tAON
(MAX)
NOP
T12
NOP
RTT,nom
ODTLoff = WL - 2
NOP
T13
T14
t
T15
NOP
(MAX)
Don’t Care
(MAX)
(MIN)
tAOF
tAOF
NOP
T17
Don’t Care
tAOF
AOF (MIN)
T16
Transitioning
NOP
T15
Transitioning
T13
0.5tCK ± 0.2tCK
tCK
*Advanced information. Subject to change without notice.
1. WL = 7. RTT,nom is enabled. RTT(WR) is disabled.
7. RTT,nom
is enabled.
RTT(WR) is disabled.
Notes:
2. ODT must be held
HIGH for1.atWL
least= ODTH4
after
assertion (T1).
2.
ODT
must
be
held
HIGH
for
ODTH4
after (T7).
assertion (T1).
3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) afterat
theleast
WRITE
command
3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7).
4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE
4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the
command with ODT HIGH to ODT registered LOW.
WRITE command with ODT HIGH to ODT registered LOW.
5. Although ODTH4 is satisfied
ODT registered
at T6, from
ODT must
go LOWHIGH
beforeatT11
ODTH4
alsoLOW
be before T11 as ODTH4 must
5.from
Although
ODTH4 HIGH
is satisfied
ODT not
registered
T6,as
ODT
mustmust
not go
satisfied from the registration ofalso
the be
WRITE
command
at
T7.
satisfied from the registration of the WRITE command at T7.
Notes:
RTT
ODT
Command
CKE
CK#
CK
Figure 80:
Synchronous
ODTODT
(BC4)(BC4)
Figure
115:
Synchronous
T14
CWL - 2
1. AL = 3; CWL = 5; ODTLon = WL = 6.0; ODTLoff = WL - 2 = 6. RTT,nom is enabled.
Note: 1. AL = 3; CWL = 5; ODTLon = WL = 6.0; ODTLoff = WL - 2 = 6. RTT,nom is enabled.
Note:
RTT
ODT
CKE
CK#
CK
T4
ODT turn-off relative to ODTLoff
completion
Figure 79:
Synchronous
ODTODT
Figure
114:
Synchronous
tAOF
2Gb: x4, x8, x16 DDR3L SDRAM
Synchronous ODT Mode
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
201
2Gb
Micron Technology, In
118
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
ODT Off During READs
Because the device cannot terminate and drive at the same
time, RTT must be disabled at least one-half clock cycle before
the READ preamble by driving the ODT ball LOW (if either
RTT,nom or RTT(WR) is enabled). RTT may not be enabled until
the end of the postamble, as shown in the following example.
Note: ODT may be disabled earlier and enabled later than shown in
Figure 81 (page 120).
Asynchronous ODT Mode
Asynchronous ODT mode is available when the DRAM runs in
DLL on mode and when either RTT,nom or RTT(WR) is enabled;
however, the DLL is temporarily turned off in precharged
power-down standby (via MR0[12]). Additionally, ODT operates
asynchronously when the DLL is synchronizing after being
reset. See “Power-Down Mode” on page 99 for definition
and guidance over power-down details.
In asynchronous ODT timing mode, the internal ODT command
is not delayed by AL relative to the external ODT command. In
asynchronous ODT mode, ODT controls RTT by analog time.
The timing parameters tAONPD and tAOFPD replace ODTLon/
tAON and ODTLoff/tAOF, respectively, when ODT operates
asynchronously.
The minimum RTT turn-on time (tAONPD [MIN]) is the point
at which the device termination circuit leaves High-Z and
ODT resistance begins to turn on. Maximum RTT turnon time
(tAONPD [MAX]) is the point at which ODT resistance is fully
on. tAONPD (MIN) and tAONPD (MAX) are measured from
ODT being sampled HIGH.
The minimum RTT turn-off time (tAOFPD [MIN]) is the point
at which the device termination circuit starts to turn off ODT
resistance. Maximum RTT turn-off time (tAOFPD [MAX]) is the
point at which ODT has reached High-Z. tAOFPD (MIN) and
tAOFPD (MAX) are measured from ODT being sampled LOW.
MYX4DDR3L128M16JT*
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119
Form #: CSI-D-685 Document 009
2Gb_DDR3L.pdf - Rev. K 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
Valid
Address
NOP
T1
NOP
T2
NOP
T3
NOP
T5
NOP
T6
RL = AL + CL
RTT,nom
ODTLoff = CWL + AL - 2
NOP
T4
NOP
T7
NOP
T8
NOP
T9
(MAX)
(MIN)
tAOF
tAOF
NOP
T11
DI
b
DI
b+1
DI
b+2
NOP
T12
ODTLon = CWL + AL - 2
NOP
T10
DI
b+3
DI
b+4
NOP
T13
DI
b+5
DI
b+6
NOP
T14
tAON
NOP
T17
Don’t Care
(MAX)
RTT,nom
NOP
T16
Transitioning
DI
b+7
NOP
T15
PDF: 09005aef83ed2952
203
T0
T1
Note:
T2
tIS
T4
(MIN)
tAONPD
tAONPD
T5
1. AL is ignored.
tIH
T3
(MAX)
T6
T7
T8
T9
Description
Asynchronous RTT turn-on delay (power-down with DLL off)
Asynchronous RTT turn-off delay (power-down with DLL off)
Symbol
tAONPD
tAOFPD
Table 90: Asynchronous ODT Timing Parameters for All Speed Bins
1. AL is ignored.
Note:
RTT
ODT
CKE
CK#
CK
Figure 82:
ODT
Timing
withwith
Fast Fast
ODT Transition
Figure
117:Asynchronous
Asynchronous
ODT
Timing
ODT Transition
RTT,nom
T10
tIH
T11
tIS
T12
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2
2
Min
T14
(MAX)
(MIN)
tAOFPD
tAOFPD
T13
Max
8.5
8.5
T16
Transitioning
T15
ns
ns
Unit
Don’t Care
T17
1. ODT during
must be
disabled
externally
READs
by driving
For example, CL = 6; AL = CL - 1 = 5; RL = AL
Note: externally
1. ODT must be disabled
READs
by driving
ODTduring
LOW. For
example,
CL = ODT
6; ALLOW.
=
+ CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8. RTT,nom is enabled. RTT(WR) is a “Don’t
CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2
Care.”
= 8. RTT,nom is enabled. RTT(WR) is a “Don’t Care.”
Note:
DQ
DQS, DQS#
RTT
ODT
READ
T0
Command
CK#
CK
Figure
116:ODT
ODTDuring
During
READs
Figure 81:
READs
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
*Advanced information.
Subject to change
notice.
Synchronous
ODT without
Mode
205
120
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 43: Asynchronous ODT Timing Parameters for All Speed Bins
Symbol
Description
tAONPD
Asynchronous RTT turn-on delay (power-down with DLL off)
tAOFPD
Asynchronous RTT turn-off delay (power-down with DLL off)
Min
Max
Unit
2
8.5
ns
Synchronous to Asynchronous ODT Mode Transition
(Power-Down Entry)
There is a transition period around power-down entry (PDE)
where the DRAM’s ODT may exhibit either synchronous or
asynchronous behavior. This transition period occurs if the DLL
is selected to be off when in precharge power-down mode
by the setting MR0[12] = 0. Power-down entry begins tANPD
prior to CKE first being registered LOW, and ends when CKE is
first registered LOW. tANPD is equal to the greater of ODTLoff
+ 1tCK or ODTLon + 1tCK. If a REFRESH command has been
issued, and it is in progress when CKE goes LOW, powerdown entry ends tRFC after the REFRESH command, rather
than when CKE is first registered LOW. Power-down entry
then becomes the greater of tANPD and tRFC - REFRESH
command to CKE registered LOW.
If AL has a large value, the uncertainty of the state of RTT
becomes quite large. This is because ODTLon and ODTLoff
are derived from the WL; and WL is equal to CWL + AL. Figure
83 (page 123) shows three different cases:
• ODT_A: Synchronous behavior before tANPD.
• ODT_B: ODT state changes during the transition period
with tAONPD (MIN) < ODTLon × tCK + tAON (MIN) and
tAONPD (MAX) > ODTLon × tCK + tAON (MAX).
• ODT_C: ODT state changes after the transition period
with asynchronous behavior.
ODT assertion during power-down entry results in an RTT
change as early as the lesser of tAONPD (MIN) and ODTLon ×
tCK + tAON (MIN), or as late as the greater of tAONPD (MAX)
and ODTLon × tCK + tAON (MAX). ODT de-assertion during
power-down entry can result in an RTT change as early as the
lesser of tAOFPD (MIN) and ODTLoff × tCK + tAOF (MIN), or as
late as the greater of tAOFPD (MAX) and ODTLoff × tCK + tAOF
(MAX). Table 44 (page 122) summarizes these parameters.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
121
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 44: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period
Description
Min
Max
Greater of: tANPD or tRFC - refresh to CKE LOW
Power-down entry transition period (power-down entry)
tANPD
Power-down exit transition period (power-down exit)
+ tXPDLL
ODT to RTT turn-on delay (ODTLon = WL - 2)
Lesser of: tAONPD (MIN) (2ns) or
ODTLon × tCK + tAON (MIN)
Greater of: tAONPD (MAX) (8.5ns) or
ODTLon × tCK + tAON (MAX)
ODT to RTT turn-off delay (ODTLoff = WL - 2)
Lesser of: tAOFPD (MIN) (2ns) or
ODTLoff × tCK + tAOF (MIN)
Greater of: tAOFPD (MAX) (8.5ns) or
ODTLoff × tCK + tAOF (MAX)
tANPD
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
WL - 1 (greater of ODTLoff + 1 or ODTLon + 1)
122
Form #: CSI-D-685 Document 009
DF: 09005aef83ed2952
Gb_DDR3L.pdf - Rev. K 9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
WL - 1 (greater of ODTLoff + 1 or ODTLon + 1)
207
NOP
T0
REF
T1
Note:
NOP
T2
RTT,nom
T5
tANPD
NOP
ODTLoff
NOP
T4
NOP
T6
NOP
T8
NOP
T9
RTT,nom
(MAX)
PDE transition period
(MIN)
(MIN)
tAOF
tAOF
tRFC
NOP
T7
1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3.
RTT,nom
NOP
T3
1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3.
Note:
DRAM RTT C
asynchronous
ODT C
asynchronous
DRAM RTT B
asynchronous
or synchronous
ODT B
asynchronous
or synchronous
DRAM RTT A
synchronous
ODT A
synchronous
Command
CKE
CK#
CK
NOP
T11
(MIN)
(MAX)
NOP
T12
ODTLoff + tAOFPD (MAX)
tAOFPD
tAOFPD
ODTLoff + tAOFPD (MIN)
NOP
T10
NOP
Ta0
Indicates break
in time scale
NOP
T13
Figure 118: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry
Figure 83: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry
tANPD
tAOFPD
NOP
Ta3
Don’t Care
(MAX)
(MIN)
NOP
Ta2
tAOFPD
Transitioning
NOP
Ta1
Greater of: tAOFPD (MAX) (8.5ns) or
ODTLoff × tCK + tAOF (MAX)
Lesser of: tAOFPD (MIN) (2ns) or
ODTLoff × tCK + tAOF (MIN)
ODT to RTT turn-off delay
(ODTLoff = WL - 2)
+ tXPDLL
Max
Greater of: tAONPD (MAX) (8.5ns) or
ODTLon × tCK + tAON (MAX)
tANPD
Greater of: tANPD or tRFC - refresh to CKE LOW
Lesser of: tAONPD (MIN) (2ns) or
ODTLon × tCK + tAON (MIN)
Min
ODT to RTT turn-on delay
(ODTLon = WL - 2)
Power-down exit transition period
(power-down exit)
Power-down entry transition period
(power-down entry)
Description
Table 91: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous ODT Mode
*Advanced information. Subject to change without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
123
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Asynchronous to Synchronous ODT Mode Transition
(Short CKE Pulse)
Asynchronous to Synchronous ODT Mode
Transition (Power-Down Exit)
If the time in the precharge power-down or idle states is very
short (short CKE LOW pulse), the power-down entry and
power-down exit transition periods overlap. When overlap
occurs, the response of the DRAM’s RTT to a change in the
ODT state can be synchronous or asynchronous from the
start of the power-down entry transition period to the end of
the power-down exit transition period, even if the entry period
ends later than the exit period.
The DRAM’s ODT can exhibit either asynchronous or
synchronous behavior during power-down exit (PDX). This
transition period occurs if the DLL is selected to be off when in
precharge power-down mode by setting MR0[12] to 0. Powerdown exit begins tANPD prior to CKE first being registered
HIGH, and ends tXPDLL after CKE is first registered HIGH.
tANPD is equal to the greater of ODTLoff + 1tCK or ODTLon +
1tCK. The transition period is tANPD + tXPDLL.
If the time in the idle state is very short (short CKE HIGH
pulse), the power-down exit and power-down entry transition
periods overlap. When this overlap occurs, the response of the
DRAM’s RTT to a change in the ODT state may be synchronous
or asynchronous from the start of power-down exit transition
period to the end of the powerdown entry transition period.
ODT assertion during power-down exit results in an RTT
change as early as the lesser of tAONPD (MIN) and ODTLon ×
tCK + tAON (MIN), or as late as the greater of tAONPD (MAX)
and ODTLon × tCK + tAON (MAX). ODT de-assertion during
power-down exit may result in an RTT change as early as the
lesser of tAOFPD (MIN) and ODTLoff × tCK + tAOF (MIN), or as
late as the greater of tAOFPD (MAX) and ODTLoff × tCK + tAOF
(MAX). Table 44 (page 122) summarizes these parameters.
If AL has a large value, the uncertainty of the RTT state becomes
quite large. This is because ODTLon and ODTLoff are derived
from WL, and WL is equal to CWL + AL. Figure 84 (page 125)
shows three different cases:
• ODT C: Asynchronous behavior before tANPD.
• ODT B: ODT state changes during the transition period,
with tAOFPD (MIN) < ODTLoff × tCK + tAOF (MIN), and
ODTLoff × tCK + tAOF (MAX) > tAOFPD (MAX).
• ODT A: ODT state changes after the transition period
with synchronous response.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
124
Form #: CSI-D-685 Document 009
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
209
T0
RTT,nom
T1
(MIN)
tANPD
Ta0
NOP
Ta1
NOP
Ta2
tAOFPD
NOP
Ta3
NOP
Ta5
(MIN)
tXPDLL
NOP
Ta6
(MAX)
RTT,nom
ODTLoff + tAOF (MAX)
tAOFPD
ODTLoff + tAOF (MIN)
PDX transition period
NOP
Ta4
1. CL = 6; AL = CL - 1; CWL = 5; ODTLoff = WL - 2 = 8.
RTT,nom
(MAX)
Note:
tAOFPD
tAOFPD
T2
1. CL = 6; AL = CL - 1; CWL = 5; ODTLoff = WL - 2 = 8.
Note:
DRAM RTT C
synchronous
ODT C
synchronous
ODT B
asynchronous
or synchronous
RTT B
asynchronous
or synchronous
DRAM RTT A
asynchronous
ODT A
asynchronous
COMMAND
CKE
CK#
CK
NOP
Tb0
NOP
Tb1
NOP
Tb2
Figure 84: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit
Tc1
NOP
Indicates break
in time scale
NOP
Tc0
Figure 119: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit
Transitioning
ODTLoff
NOP
Tc2
(MIN)
(MAX)
NOP
Td1
Don’t Care
tAOF
tAOF
NOP
Td0
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDR
Asynchronous to Synchronous ODT Mode Transition (Pow
Down E
*Advanced information. Subject to change without notice.
Micron Technology, Inc. reserves the right to change products or specifications with
© 2010 Micron Technology, Inc. All right
125
Form #: CSI-D-685 Document 009
NOP
REF
NOP
T1
T0
REF
T1
T0
NOP
NOP
T2
T2
NOP
NOP
T5
T5
NOP
NOP
T7
T7
T8
T8
NOP
NOP
tANPD
PDX transition period
(MIN) PDX transition period
tANPD
(MIN)
tRFC
NOP
NOP
T9
T9
tRFC
PDE transition period
PDE transition period
NOP
NOP
T6
T6
tANPD
Short CKE low transition period (R TT change asynchronous or synchronous)
Short CKE low transition period (R TT change asynchronous or synchronous)
NOP
NOP
T4
T4
1. AL = 0, WL = 5,
= 4.
1. AL = 0, WL = 5, tANPD = 4.
tANPD
tANPD
NOP
NOP
T3
T3
tXPDLL
tXPDLL
NOP
NOP
Ta1
Ta1
Indicates break
in time scale
Indicates break
in time scale
NOP
NOP
Ta0
Ta0
NOP
NOP
NOP
Command
Note:
Note:
NOP
NOP
T7
tXPDLL
tANPD
NOP
NOP
T6
tXPDLL
NOP
NOP
T5
tANPD
NOP
NOP
T4
tANPD
NOP
NOP
T3
NOP
NOP
T8
1. AL = 0, WL = 5,
= 4.
1. AL = 0, WL = 5, tANPD = 4.
tANPD
Short CKE HIGH transition period (RTT change asynchronous or synchonous)
tANPD
Short CKE HIGH transition period (RTT change asynchronous or synchonous)
NOP
NOP
T2
1. AL = 0, WL = 5, tANPD = 4.
Note:
NOP
T1
T0
CK#
CK
CK#
CK
Command
NOP
NOP
T9
Ta1
NOP
NOP
Indicates break
in time scale
Indicates break
in time scale
NOP
NOP
Ta0
Figure
121:Transition
Transition
Period
for Short
CKE HIGH
withand
Entry
Exit
Period Overlapping
Figure 86:
Period
for Short
CKE HIGH
CyclesCycles
with Entry
Exitand
Period
Overlapping
Figure 121:
Transition
Period
for
Short
CKE
HIGH
Cycles
with
Entry
and
Exit
Period
Overlapping
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Ta0
Ta1
Note:
Note:
1. AL = 0, WL = 5, tANPD = 4.
Note:
CKE
EKC
211211
EKC
2Gb_DDR3L.pdf
2Gb_DDR3L.pdf
- Rev. -KRev.
9/13KEN
9/13 EN
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
PDF: 09005aef83ed2952
Command
CKE
CK#
CK
CK#
CK
Command
Figure 85: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping
Figure 120: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping
Figure 120: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping
Don’t Care
Don’t Care
NOP
NOP
Transitioning
NOP
NOP
Ta4
Ta4
Transitioning
NOP
NOP
Ta2
Ta3
Don’t Care
Ta2
Don’t Care
NOP
NOP
Ta4
Ta4
Transitioning
Ta3
NOP
NOP
Ta3
Ta3
Transitioning
NOP
NOP
Ta2
Ta2
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb:
2Gb:
x4,x4,
x8,x8,
x16
x16
DDR3L
DDR3L
SDRAM
SDRAM
Asynchronous
Asynchronous
toto
Synchronous
Synchronous
ODT
ODT
Mode
Mode
Transition
Transition
(Power(PowerDown
Down
Exit)
Exit)
*Advanced information. Subject to change without
notice.
Micron
Micron
Technology,
Technology,
Inc. reserves
Inc. reserves
the right
the to
right
change
to change
products
products
or specifications
or specifications
without
without
notice.notice.
© 2010
© Micron
2010 Micron
Technology,
Technology,
Inc. AllInc.
rights
All rights
reserved.
reserved.
126
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
2Gb:MYX4DDR3L128M16JT*
x4, x8, x16 DDR3L SDRAM
Package Dimensions
*Advanced information. Subject to change without notice.
Figure
11: 96-Ball
x16 (JT)
Figure
87: 96-Ball
FBGAFBGA
– x16 –(JT)
0.155
Seating plane
A
1.8 CTR
Nonconductive
overmold
96X Ø0.45
Dimensions apply
to solder balls postreflow on Ø0.35
SMD ball pads.
0.12 A
Ball A1 ID
9
8
7
3
2
Ball A1 ID
1
A
B
C
D
E
F
14 ±0.1
G
H
12 CTR
J
K
L
M
N
P
R
0.8 TYP
T
1.1 ±0.1
0.8 TYP
6.4 CTR
0.25 MIN
8 ±0.1
Notes:
1. All dimensions are in millimeters.
1. All dimensions are in millimeters.2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
Notes:
2. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
127
25
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Table 45: Ordering Information
Part Number
Data Rate (Mbps)
Device Grade
MYX4DDR3L128M16JT-125IT
1600
Industrial
MYX4DDR3L128M16JT-125
1600
Commercial
Please contact a Micross sales representative for IBIS or thermal models at [email protected].
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
128
Form #: CSI-D-685 Document 009
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Document Title
2GByte, 128M x 16, DDR3 SDRAM, 8mm x 14mm - 96-ball FBGA Package
Revision History
Revision #
History
Release Date
Status
1.0
Initial Release
July 2014
Preliminary
1.1
Page 1 (blue box at right): Changed "FPGA" to "FBGA"
October 3, 2014
Preliminary
Page 1 (blue box at right): Removed "-x16" after "(Sn63 / Pb37)
Page 1 (blue box at right): Changed "Marking" to "Code"
1.2
Changed speed grades -15 and -18 -to -15E and -187E
October 15, 2014
Preliminary
1.3
Added ECN #
October 20, 2014
Preliminary
1.4
Page 9 (Table 7): Changed 8-8-8 to 7-7-7 and 10-10-10 to 9-9-9.
October 22, 2014
Preliminary
1.5
Removed speed grades -15E and -187E
October 30, 2014
Preliminary
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
129
Form #: CSI-D-685 Document 009