Micross-RetailPlus-Datasheet-MYX4DDR264M16HW 2016-03 Rev1-4

1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
1Gb - 64M x 16 DDR2 SDRAM
Features
OptionsCode
• Tin-lead ball metallurgy
• VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
• Configuration
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
ƒƒ 64 Meg x 16
(8 Meg x 16 x 8 banks)
• Differential data strobe (DQS, DQS#) option
64M16
• 4n-bit prefetch architecture
• FBGA package (Sn63/Pb37)
• Duplicate output strobe
BG
• DLL to align DQ and DQS transitions with CK
ƒƒ 84-ball FBGA (8mm x 12.5mm) Die Rev: H
HR
• 8 internal banks for concurrent operation
ƒƒ 84-ball FBGA (8mm x 12.5mm) Die Rev :M
NF
• Programmable CAS latency (CL)
• Timing – cycle time
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1
ƒƒ 2.5ns @ CL = 5 (DDR2-800)
-25E
tCK
• Operating temperature
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
ƒƒ Industrial (–40°C ≤ TC ≤ +95°C;
–40°C ≤ TA ≤ +85°C)
IT
ƒƒ Military (–55°C ≤ TC ≤ +125°C)
XT
• Industrial temperature (IT) option
• Supports JEDEC clock jitter specification
• AEC-Q100 (MIL version)
• PPAP submission (MIL version)
Table 2: Addressing
• 8D response time
Table 1: Key Timing Parameters
Speed
Grade
-25E
Data Rate (MT/s)
tRC
CL=3
CL=4
CL=5
CL=6
CL=7
400
533
800
800
n/a
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
(ns)
55
Parameter
64 Meg x 16
Configuration
8 Meg x 16 x 8 banks
Refresh count
8K
Row address
A[12:0] (8K)
Bank address
BA[2:0] (8)
Column address
A[9:0] (1K)
1
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
Contents
1
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3
2
Ball Assignments and Descriptions . . . . . . . . . . . . . . . 4
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
5
3.1
Industrial Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Enhanced Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
9
Mode Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 28
9.1
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2
AC and DC Operating Conditions . . . . . . . . . . . . . . . . . 29
9.3
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . 29
9.4
Input Electrical Characteristics and
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.5
Output Electrical Characteristics and
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.6
Temperature and Thermal Impedance . . . . . . . . . . . . . 34
9.7
FBGA Package Capacitance . . . . . . . . . . . . . . . . . . . . 36
9.8
Electrical Specifications – IDD Parameters . . . . . . . . . . . 37
9.9
IDD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.10
AC Timing Operating Specifications . . . . . . . . . . . . . . . 39
4.1
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
DLL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5
Write Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10Package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11
4.7
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . 14
5.1
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2
Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
DQS# Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5
On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . 17
5.6
Off-Chip Driver (OCD) Impedance Calibration . . . . . . . . 17
5.7
Posted CAS Additive Latency (AL) . . . . . . . . . . . . . . . . 17
6
Extended Mode Register 2 (EMR2) . . . . . . . . . . . . . . . 18
7
Extended Mode Register 3 (EMR3) . . . . . . . . . . . . . . . 19
8Commands
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.1
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.2
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.3
NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.4
LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.5
ACTIVATE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.6
ACTIVATE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.7
READ COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.8
READ OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.9
WRITE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.10
WRITE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.11
PRECHARGE COMMAND . . . . . . . . . . . . . . . . . . . . . . . 26
8.12
PRECHARGE OPERATION . . . . . . . . . . . . . . . . . . . . . . . 27
8.13
REFRESH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.14
SELF REFRESH COMMAND . . . . . . . . . . . . . . . . . . . . . 27
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
2
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
1
Functional Block Diagram
The DDR2 SDRAM is a high-speed CMOS, dynamic random 1Gb:
accessx4,
memory.
is internally
x8, Itx16
DDR2configured
SDRAMas a
multibank DRAM.
Functional Block Diagrams
Figure
5: 64 Meg
x 16Diagram
Functional
Block
Diagram
Figure
1: Functional
Block
– 64 Meg
x 16
ODT
CKE
CK
CK#
Command
decode
CS#
RAS#
CAS#
WE#
Control
logic
13
Mode
registers
16
Refresh 13
counter
13
Rowaddress
MUX
Bank 7
Bank 7
Bank 6
Bank 6
Bank 5
Bank 5
Bank 4
Bank 4
Bank 3
Bank 3
Bank 2
Bank 2
Bank 1
Bank 1
Bank 0
Bank 0
rowMemory array
address
latch 8,192 (8,192 x 256 x 64)
and
decoder
16 Address
register
16
64
Read
latch
2
3
10
Bank
control
logic
Columnaddress
counter/
latch
16
16
DRVRS
MUX DATA
4
UDQS, UDQS#
Input LDQS, LDQS#
registers
2
2
64
8
2
WRITE
2
FIFO Mask
2
and
64
drivers
16
256
(x64)
8
sw1
16
DQS
generator
I/O gating
DM mask logic
Column
decoder
CK, CK#
2
COL0, COL1
CK out
CK in
VDDQ
ODT control
sw1 sw2 sw3
DLL
16
Sense amplifier
16,384
A0–A12,
BA0–BA2
CK, CK#
COL0, COL1
64 16
16
Data
16
2
2
2
2
sw2 sw3
R1
R2
R3
R1
R2
R3
sw1
sw2 sw3
R1
R2
R3
R1
R2
R3
sw1
sw2 sw3
DQ0–DQ15
UDQS, UDQS#
LDQS, LDQS#
RCVRS
16
16 16
16
R1
R2
R3
16
R1
R2
R3
UDM, LDM
4
VSSQ
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
3
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
2
Ball Assignments and Descriptions
Figure 2: 84-Ball FBGA – x16 Ball Assignments (Top View)
1
2
3
4
5
6
7
8
9
V DD
NC
V SS
DQ14
V SSQ
UDM
UDQS
V SSQ
DQ15
V DDQ
DQ9
V DDQ
V DDQ
DQ8
V DDQ
DQ12
V SSQ
DQ11
DQ10
V SSQ
DQ13
V DD
NC
V SS
DQ6
V SSQ
LDM
LDQS
V SSQ
DQ7
V DDQ
DQ1
V DDQ
V DDQ
DQ0
V DDQ
DQ4
V SSQ
DQ3
DQ2
V SSQ
DQ5
V DDL
V REF
V SS
V SSDL
CK
V DD
CKE
WE#
RAS#
CK#
ODT
BA0
BA1
CAS#
CS#
A10
A1
A2
A0
A3
A5
A6
A4
A7
A9
A11
A8
A12
RFU
RFU
RFU
A
V SSQ UDQS#/NU V DDQ
B
C
D
E
V SSQ LDQS#/NU V DDQ
F
G
H
J
K
L
BA2
M
V DD
N
V SS
P
V SS
R
V DD
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
4
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
Table 3: FBGA 84-Ball – x16 Descriptions
Symbol
Type
Description
A[12:0] (x16)
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10)
for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all
banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command.
BA[2:0]
Input
Bank address inputs: BA[2:0] define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
BA[2:0] define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM.
The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW
provides precharge power-down and SELF REFRESH operation (all banks idle), or ACTIVATE power-down (row active in any bank).
CKE is synchronous for power-down entry, power-down exit, output disable, and for self refresh entry. CKE is asynchronous for
SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding
CKE) are disabled during self refresh. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during
first power-up. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper SELF REFRESH operation, VREF must be maintained.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked
when CS# is registered high. CS# provides for external bank selection on systems with multiple ranks. CS# is considered part of
the command code.
LDM, UDM (DM)
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH
during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to
match that of DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for upper byte DQ[15:8].
ODT
Input
On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following balls: DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS,
DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input will be ignored if disabled via the LOAD
MODE command.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.
DQ[15:0] (x16)
I/O
Data input/output: Bidirectional data bus for 64 Meg x 16.
DQS, DQS#
I/O
Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, centeraligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.
LDQS, LDQS#
I/O
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
UDQS, UDQS#
I/O
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
VDD
Supply
Power supply: 1.8V ±0.1V
VDDQ
Supply
DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity.
VDDL
Supply
DLL power supply: 1.8V ±0.1V.
VREF
Supply
SSTL_18 reference voltage.
MYX4DDR264M16HW*
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Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
3
Symbol
Type
Description
VSS
Supply
Ground.
VSSDL
Supply
DLL ground: Isolated on the device from VSS and VSSQ.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
NC
-
No connect: These balls should be left unconnected.
NU
-
Not used
NU
-
Not used
RFU
-
Reserved for future use: Row address bits A13 (R8), A14 (R3), A15 (R7)
Functional Description
The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate
architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per
clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bitwide, onehalf-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during
WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering
has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#).
The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and
CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are
registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location
and continue for a programmed number of locations in a programmed sequence. Accesses begin with the
registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed.
The address bits registered coincident with the READ or WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write.
An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of
the burst access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent
operation, thereby providing high, effective bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
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Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18compatible.
3.1
Industrial Temperature
The industrial temperature (IT) option, if offered, has two simultaneous requirements: ambient temperature
surrounding the device cannot be less than -40°C or greater than 85°C, and the case temperature cannot be
less than -40°C or greater than 95°C. JEDEC specifications require the refresh rate to double when TC exceeds
85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance, input/
output impedance and IDD values must be derated when TC is < 0°C or > 85°C.
3.2
Enhanced Temperature
The Enhanced temperature (ET) option, has two simultaneous requirements: ambient temperature surrounding
the device cannot be less than –40°C or greater than +105°C, and the case temperature cannot be less than
–40°C or greater than +105°C. JEDEC specifications require the refresh rate to double when TC exceeds
+85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance, the
input/output impedance, and IDD values must be derated when TC is < 0°C or > +85°C.
3.3
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled
mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is
divided into 2 bytes: the lower byte and the upper byte. For the lower byte (DQ[7:0]), DM refers to LDM
and DQS refers to LDQS. For the upper byte (DQ[15:8]), DM refers to UDM and DQS refers to UDQS.
• A x16 device’s DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the
lower byte for data transfers and terminate the upper byte as noted:
ƒƒ Connect UDQS to ground via 1kΩ* resistor
ƒƒ Connect UDQS# to VDD via 1kΩ* resistor
ƒƒ Connect UDM to VDD via 1kΩ* resistor
ƒƒ Connect DQ[15:8] individually to either VSS or VDD via 1kΩ* resistors, or float DQ[15:8].
*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.
• Complete functionality is described throughout the document, and any page or diagram may have
been simplified to convey a topic and may not be inclusive of all requirements.
• Any specific requirement takes precedence over a general statement.
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
7
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
3.4
Initialization
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation. Figure 3 illustrates, and the notes outline, the sequence
Initialization
required for power-up and initialization.
Figure 43: DDR2 Power-Up and Initialization
Figure
3: DDR2 Power-Up and Initialization
DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Figure 43 illustrates, and the notes outline, the sequence required for power-up and initialization.
VDD
VDDL
VDDQ
tVTD1
VTT1
VREF
T0
tCK
CK#
CK
tCL
LVCMOS
CKE low level2
Ta0
Tb0
Tc0
Td0
Te0
Tf0
Tg0
Th0
Ti0
Tj0
Tk0
Tl0
Tm0
NOP3
PRE
LM5
LM6
LM7
LM8
PRE9
REF10
REF10
LM11
LM12
LM13
Valid14
A10 = 1
Code
Code
Code
Code
A10 = 1
Code
Code
Code
Valid
tCL
SSTL_18 2
low level
ODT
88
Command
15
DM
15
DQS
High-Z
15
High-Z
DQ
Rtt
High-Z
T = 200μs (MIN)3
Power-up:
VDD and stable
clock (CK, CK#)
T = 400ns (MIN)4
tMRD
tRPA
EMR(2)
tMRD
EMR(3)
tMRD
tMRD
tRPA
tRFC
tRFC
tMRD
tMRD
tMRD
EMR
MR without
DLL RESET
EMR with
OCD default
EMR with
OCD exit
200 cycles of CK are required before a READ command can be issued
Normal
operation
MR with
DLL RESET
Indicates a Break in
Time Scale
Don’t care
Notes:
2Gb: x4, x8, x16 DDR2 SDRAM
Initialization
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
16
Address
1. Applying power; if CKE is maintained below 0.2 × VDDQ, outputs remain disabled. To guarantee RTT (ODT
resistance) is off, VREF must be valid and a low level must be appliedto the ODT ball (all other inputs may
be undefined; I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DDR2 SDRAM
device latch-up). VTT is not applied directly to the device; however, tVTD should be ≥ 0 to avoid device
latch-up. At least one of the following two sets of conditions (A or B) must be met to obtain a stable
supply state (stable supply defined as VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and
maximum values as stated in Table 8 (page 29):
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
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Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
A. Single power source: The VDD voltage ramp from 300mV to VDD,min must take no longer than 200ms;
during the VDD voltage ramp, |VDD - VDDQ| ≤ 0.3V. Once supply voltage ramping is complete (when
VDDQ crosses VDD,min), Table 8 (page 29) specifications apply.
ƒƒ VDD, VDDL, and VDDQ are driven from a single power converter output
ƒƒ VTT is limited to 0.95V MAX
ƒƒ VREF tracks VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during supply ramp time;
does not need to be satisfied when ramping power down
ƒƒ VDDQ ≥ VREF at all times
B. Multiple power sources: VDD ≥ VDDL ≥ VDDQ must be maintained during supply voltage ramping, for
both AC and DC levels, until supply voltage ramping completes (VDDQ crosses VDD,min). Once supply
voltage ramping is complete, Table 8 (page 29) specifications apply.
ƒƒ Apply VDD and VDDL before or at the same time as VDDQ; VDD/VDDL voltage ramp time must be ≤
200ms from when VDD ramps from 300mV to VDD,min
ƒƒ Apply VDDQ before or at the same time as VTT; the VDDQ voltage ramp time from when VDD,min is
achieved to when VDDQ,min is achieved must be ≤ 500ms; while VDD is ramping, current can be
supplied from VDD through the device to VDDQ
ƒƒ VREF must track VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during supply ramp
time; VDDQ ≥ VREF must be met at all times; does not need to be satisfied when ramping power
down
ƒƒ Apply VTT; the VTT voltage ramp time from when VDDQ,min is achieved to when VTT,min is achieved
must be no greater than 500ms
2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device powerup prior to VREF being stable. After state T0, CKE is required to have SSTL_18 input levels. Once CKE
transitions to a high level, it must stay HIGH for the duration of the initialization sequence.
3. For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT commands,
then take CKE HIGH.
4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.
5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW to BA0, and
provide HIGH to BA1; set register E7 to “0” or “1” to select appropriate self refresh rate; remaining EMR(2)
bits must be “0” (see "Extended Mode Register 2 (EMR2)" on page 18 for all EMR(2) requirements).
6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide HIGH to BA0 and
BA1; remaining EMR(3) bits must be “0.” See "Extended Mode Register 3 (EMR3)" on page 19 for all
EMR(3) requirements.
7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command, provide
LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to “0” or “1;” Micross
recommends setting them to “0;” remaining EMR bits must be “0.” See "Extended Mode Register (EMR)"
on page 14 for all EMR requirements.
8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required to lock
the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0; CKE must be
MYX4DDR264M16HW*
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1Gb DDR2 SDRAM
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*Advanced information. Subject to change without notice.
HIGH the entire time the DLL is resetting; remaining MR bits must be “0.” See "Mode Register (MR)" on
page 10 for all MR requirements.
9. Issue PRECHARGE ALL command
10. Issue two or more REFRESH commands.
11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation (that is, to
program operating parameters without resetting the DLL). To access the MR, set BA0 and BA1 LOW;
remaining MR bits must be set to desired settings. See "Mode Register (MR)" on page 10 for all MR
requirements.
12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and E9 to “1,”
and then setting all other desired parameters. To access the EMR, set BA0 HIGH and BA1 LOW. See
"Extended Mode Register (EMR)" on page 14 for all EMR requirements.
13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to “0,” and
then setting all other desired parameters. To access the extended mode registers, EMR, set BA0 HIGH
and BA1 LOW for all EMR requirements.
14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the DLL RESET
at Tf0.
15. DM represents UDM and LDM; DQS represents UDQS, UDQS#, LDQS, LDQS#. DQ represents DQ[15:0].
16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are required to be
decoded).
4
Mode Register (MR)
The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition
includes the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, write recovery,
and power-down mode, as shown in Figure 4 (page 11). Contents of the mode register can be altered by
re-executing the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables,
all variables must be programmed when the command is issued.
The MR is programmed via the LM command and will retain the stored information until it is programmed again
or until the device loses power (except for bit M8, which is self-clearing). Reprogramming the mode register will
not alter the contents of the memory array, provided it is performed correctly.
The LM command can only be issued (or reissued) when all banks are in the precharged state (idle state) and
no bursts are in progress. The controller must wait the specified time tMRD before initiating any subsequent
operations such as an ACTIVATE command. Violating either of these requirements will result in an unspecified
operation.
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
10
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
2Gb:
x4, x8,
x16
DDR2
SDRAM
*Advanced
information.
Subject
to change
without
notice.
4.1
Mode Register (MR)
Burst Length
Burst Length
Burst length is defined
bylength
bits M0–M2,
as shown
in M0–M2,
Figure 4. as
Read
and write
accesses
to theand
DDR2
SDRAM
are
Burst
is defined
by bits
shown
in Figure
36. Read
write
accesses
burst-oriented, with
length
being
to either
fourburst
or eight.
Thebeing
burst programmable
length determines
to the
theburst
DDR2
SDRAM
areprogrammable
burst-oriented,
with the
length
to
either
four
or
eight.
The
burst
length
determines
the
maximum
number
of
column
locathe maximum number of column locations that can be accessed for a given READ or WRITE command.
tions that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
When a READ or WRITE command is issued, a block of columns equal to the burst
All accesses for that
burstis take
place within
this All
block,
meaning
burst
wrapwithin
within this
the block,
block if a
length
effectively
selected.
accesses
for that
that the
burst
takewill
place
boundary is reached.
The
block
is
uniquely
selected
by
A2–Ai
when
BL
=
4
and
by
A3–Ai
when
BL
=
8 block
(whereis
meaning that the burst will wrap within the block if a boundary is reached. The
uniquely
selected
by A2–Ai
= 4 and by A3–Ai
when BL(least
= 8 (where
Ai isaddress
the most
Ai is the most significant
column
address
bit for when
a givenBL
configuration).
The remaining
significant)
significant
bit forthe
a given
The
remaining
(least signifibit(s) is (are) used to
select thecolumn
starting address
location within
block.configuration).
The programmed
burst
length applies
to both
cant)
address
bit(s)
is
(are)
used
to
select
the
starting
location
within
the
block.
The proread and write bursts.
grammed burst length applies to both read and write bursts.
Figure
4: MR Definition
Figure 36:
MR Definition
1
2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
16 15 14 n 12 11 10
0
MR
WR
0 PD
Mode Register (Mx)
9
8
M12 PD Mode
0
Fast exit
(normal)
1
Slow exit
(low power)
M11 M10 M9
M15 M14
Notes:
7
6
5
4
3
2
1
0
DLL TM CAS# Latency BT Burst Length
M2 M1 M0 Burst Length
M7 Mode
0 Normal
0
0
0
Reserved
1
0
0
1
Reserved
0
1
0
4
0
1
1
8
Test
M8 DLL Reset
0
No
1
0
0
Reserved
1
Yes
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Write Recovery
0
0
0
Reserved
0
0
1
2
M3
0
1
0
3
0
Sequential
0
1
1
4
1
Interleaved
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
M6 M5 M4
Mode Register Definition
0
0
Mode register (MR)
0
1
Extended mode register (EMR)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
Burst Type
CAS Latency (CL)
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
1. M16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be
programmed to “0.”
1. M16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and must be programmed to “0.”
2. Mode bits (Mn) with corresponding address balls (An) greater than M12 (A12) are re2. Mode bits (Mn) with served
corresponding
address
balls
(An)
than M12
(A12) are reserved for future use
for future
use and
must
begreater
programmed
to “0.”
3.
Not
all
listed
WR
and
CL
options
are
supported
in
any
individual speed grade.
and must be programmed to “0.”
Notes:
3. Not all listed WR and CL options are supported in any individual speed grade.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
4.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is
selected via bit M3, as shown in Figure 4. The ordering of accesses within a burst is determined by the burst
length, the burst type, and the starting column address, as shown in Table 4. DDR2 SDRAM supports 4-bit
burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is supported;
however, sequential address ordering is nibble-based.
Table 4: Burst Definition
Burst Length
Order of Accesses Within a Burst
Starting Column Address
(A2, A1, A0)
Burst Type = Sequential
Burst Type = Interleaved
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
4
8
4.3
Operating Mode
The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to
the desired values, as shown in Figure 4 (page 11). When bit M7 is “1,” no other bits of the mode register are
programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the
manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is “1.”
MYX4DDR264M16HW*
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1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
4.4
DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 4 (page 11). Programming bit M8 to “1” will activate
the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET
function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued
to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization
to occur may result in a violation of the tAC or tDQSCK parameters.
4.5
Write Recovery
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 4 (page 11). The WR register is
used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge
operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks (programmed in bits
M9–M11) from the last data burst.
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The user is required to
program the value of WR, which is calculated by dividing tWR (in nanoseconds) by tCK (in nanoseconds) and
rounding up a noninteger value to the next integer; WR (cycles) = tWR (ns)/tCK (ns). Reserved states should not
be used as an unknown operation or incompatibility with future versions may result.
4.6
Power-Down Mode
Active power-down (PD) mode is defined by bit M12, as shown in Figure 4 (page 11). PD mode enables the
user to determine the active power-down mode, which determines performance versus power savings. PD
mode bit M12 does not apply to precharge PD mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled. The tXARD parameter
is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is enabled. The tXARDS
parameter is used for slow-exit active PD exit timing. The DLL can be enabled but “frozen” during active PD
mode because the exit-to-READ command timing is relaxed. The power difference expected between IDD3P
normal and IDD3P lowpower mode is defined in the DDR2 IDD Specifications and Conditions table.
4.7
CAS Latency (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 4 (page 11). CL is the delay, in clock
cycles, between the registration of a READ command and the availability of the first bit of output data. The CL
can be set to 3, 4, 5, 6, or 7 clocks, depending on the speed grade option being used.
MYX4DDR264M16HW*
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2Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
AS Latency (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 36 (page 78). CL is
the delay, in clock cycles, between the registration of a READ command and the availainformation.
Subject to change without notice.
bility of the first bit of output data. The CL can be set to 3, 4, 5,*Advanced
6, or 7 clocks,
depending
on
the
speed
grade
option
being
used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as an unknown
DDR2
SDRAM
does incompatibility
not support any
latencies.
Reserved states should not be
operation
otherwise
withhalf-clock
future versions
may result.
used as an unknown operation otherwise incompatibility with future versions may reDDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This feature allows the READ
sult.
tRCD (MIN) by delaying the internal command to the DDR2 SDRAM by AL
command
to be
issued
prior atofeature
DDR2
SDRAM
also
supports
called posted CAS additive latency (AL). This featRCD (MIN)
clocks.
Thethe
AL READ
featurecommand
is described
detail
in to
"Posted
CAS Additive
Latency
on page 17.
ture
allows
toinbefurther
issued
prior
by delaying
the(AL)"
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further
Examples
of CL CAS
= 3 and
CL = 4
are shown
Figure84).
5; both assume AL = 0. If a READ command is registered
detail
in Posted
Additive
Latency
(AL)in(page
at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n + m
Examples of CL = 3 and CL = 4 are shown in Figure 37; both assume AL = 0. If a READ
(this assumes AL = 0).
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).
Figure 5: CL
gure 37: CL
CK#
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
DQS, DQS#
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
CL = 3 (AL = 0)
CK#
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
DQS, DQS#
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
CL = 4 (AL = 0)
Notes:
Notes:
Transitioning data
Don’t care
1. BL = 4.
1. BL = 4.
2.2. Posted
additive latency
Posted CAS#
CAS# additive
latency (AL)
(AL) =
= 0.
0.
tAC,tDQSCK,
tDQSCK, and
3.3. Shown
Shownwith
withnominal
nominaltAC,
and ttDQSQ.
DQSQ.
5
Extended Mode Register (EMR)
The extended mode register controls functions beyond those controlled by the mode register; these
additional functions are DLL enable/disable, output drive strength, on-die termination (ODT), posted
AL, off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable,
and output disable/enable. These functions are controlled via the bits shown in Figure 6. The EMR is
programmed via the LM command and will retain the stored information until it is programmed again or the
: 09005aef824f87b6
b_DDR2.pdf – Rev. H 10/11 EN
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2006 Micron Technology, Inc. All rights reserved.
14
Form #: CSI-D-685 Document 005
2Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
The extended mode register controls functions beyond
those controlled by the mode
Extended Mode Register (EMR)
register; these additional functions are DLL enable/disable, output drive strength, ondie termination (ODT), posted AL, off-chip driver
impedance calibration (OCD), DQS#
*Advanced information. Subject to change without notice.
enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These funcdevice loses power.
thethe
EMR
not alter
the contents
the is
memory
array, provided
it is
tions Reprogramming
are controlled via
bitswill
shown
in Figure
38. Theof
EMR
programmed
via the LM
command
and
will
retain
the
stored
information
until
it
is
programmed
again
or
the
deperformed correctly.
vice loses power. Reprogramming the EMR will not alter the contents of the memory arprovided
it isallperformed
correctly.
The EMR must ray,
be loaded
when
banks are idle
and no bursts are in progress, and the controller must wait
t
the specified time
anywhen
subsequent
operation.
these
requirements
TheMRD
EMRbefore
mustinitiating
be loaded
all banks
are idleViolating
and no either
burstsofare
in progress,
andcould
the
t
result in an unspecified
operation.
controller must wait the specified time MRD before initiating any subsequent operation. Violating either of these requirements could result in an unspecified operation.
FigureDefinition
6: EMR Definition
Figure 38: EMR
1
2
BA2 BA1 BA0 An A12
16
0
A10 A9 A8 A7 A6 A5 A4 A3 A2
15 14 n 12 11 10 9 8 7 6 5 4 3 2
1 0
MRS 0 Out RDQS DQS# OCD Program RTT Posted CAS# RTT ODS DLL
Outputs
E0
DLL Enable
E6 E2 RTT (Nominal)
0
Enable (normal)
1
Disabled
0 0
RTT disabled
1
Disable (test/debug)
0 1
75
1 0
150
E1
1 1
50
0
Full
1
Reduced
E15 E14
0
No
1
Yes
Output Drive Strength
E5 E4 E3 Posted CAS# Additive Latency (AL)
0
Enable
0
0
0
0
1
Disable
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Reserved
4
0
0
0
OCD exit
0
0
1
Reserved
0
1
0
Reserved
1
0
0
Reserved
1
1
1
Enable OCD defaults
3
Mode Register Set
0
0
0
1
Extended mode register (EMR)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
Mode register (MR)
1. E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be programmed to “0.”
E16 (BA2) is only
applicable
for densities
≥1Gb, reserved
for future
use,greater
and must
beE12
programmed
to “0.”
2. Mode
bits (En)
with corresponding
address
balls (An)
than
(A12) are reserved
for
future
use
and
must
be
programmed
to
“0.”
Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved for future use
3. Not all listed AL options are supported in any individual speed grade.
and must be programmed
to “0.”
4. As detailed in the Initialization (page 88) section notes, during initialization of the
Not all listed AL options
are supported
in any
grade.
OCD operation,
all three
bitsindividual
must be speed
set to “1”
for the OCD default state, then set to
“0”
before
initialization
is
finished.
During initialization of the OCD operation, all three bits must be set to “1” for the OCD default state, then
Notes:
4.
register (Ex)
Enabled
E9 E8 E7 OCD Operation
3.
Extended mode
0
E10 DQS# Enable
2.
Address bus
E12
E11 RDQS Enable
1.
A1 A0
Notes:
set to “0” before initialization is finished.
82
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MYX4DDR264M16HW*
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2006 Micron Technology, Inc. All rights reserved.
15
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
5.1
DLL Enable/Disable
The DLL may be enabled or disabled by programming bit E0 during the LM command, as shown in Figure 6
(page 15). These specifications are applicable when the DLL is enabled for normal operation. DLL enable
is required during power-up initialization and upon returning to normal operation after having disabled the DLL
for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL
using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is automatically re-enabled
and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a READ command
can be issued to allow time for the internal clock to synchronize with the external clock. Failing to wait for
synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
Anytime the DLL is disabled and the device is operated below 25 MHz, any AUTO REFRESH command should
be followed by a PRECHARGE ALL command.
5.2
Output Drive Strength
The output drive strength is defined by bit E1, as shown in Figure 6 (page 15). The normal drive strength for
all outputs is specified to be SSTL_18. Programming bit E1 = 0 selects normal (full strength) drive strength for
all outputs. Selecting a reduced drive strength option (E1 = 1) will reduce all outputs to approximately 45 to
60 percent of the SSTL_18 drive strength. This option is intended for the support of lighter load and/or pointtopoint environments.
5.3
DQS# Enable/Disable
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the differential data strobe
pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a singleended mode and the DQS# ball is disabled.
When disabled, DQS# should be left floating; however, it may be tied to ground via a 20Ω to 10kΩ resistor. This
function is also used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0),
then both DQS# and RDQS# will be enabled. RDQS is not available on this device.
5.4
Output Enable/Disable
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 6 (page 15). When enabled (E12
= 0), all outputs (DQ, DQS, DQS#) function normally. When disabled (E12 = 1), all outputs (DQ, DQS, DQS#)
are disabled, thus removing output buffer current. The output disable feature is intended to be used during IDD
characterization of read current.
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5.5
On-Die Termination (ODT)
ODT effective resistance, RTT(EFF), is defined by bits E2 and E6 of the EMR, as shown in Figure 6 (page 15).
The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM
controller to independently turn on/off ODT for any or all devices. RTT effective resistance values of 50Ω, 75Ω
and 510Ω are selectable and apply to each DQ, DQS/DQS#, UDQS/UDQS#, LDQS/ LDQS#, DM, and UDM/
LDM signals. Bits (E6, E2) determine what ODT resistance is enabled by turning on/off “sw1,” “sw2,” or “sw3.”
The ODT effective resistance value is selected by enabling switch “sw1,” which enables all R1 values that are
150Ω each, enabling an effective resistance of 75OΩ(RTT2 [EFF] = R2/2). Similarly, if “sw2” is enabled, all R2
values that are 300Ω each, enable an effective ODT resistance of 150Ω (RTT2[EFF] = R2/2). Switch “sw3” enables
R1 values of 100Ω, enabling effective resistance of 50Ω. Reserved states should not be used, as an unknown
operation or incompatibility with future versions may result.
The ODT control ball is used to determine when RTT(EFF) is turned on and off, assuming ODT has been enabled
via bits E2 and E6 of the EMR. The ODT feature and ODT input ball are only used during active, active powerdown (both fast-exit and slow-exit modes), and precharge power-down modes of operation.
ODT must be turned off prior to entering self refresh mode. During power-up and initialization of the DDR2
SDRAM, ODT should be disabled until the EMR command is issued. This will enable the ODT feature, at which
point the ODT ball will determine the RTT(EFF) value. Anytime the EMR enables the ODT function, ODT may not
be driven HIGH until eight clocks after the EMR has been enabled.
5.6
Off-Chip Driver (OCD) Impedance Calibration
The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by Micross and thereby
must be set to the default state. Enabling OCD beyond the default settings will alter the I/O drive characteristics
and the timing and output I/O specifications will no longer be valid.
5.7
Posted CAS Additive Latency (AL)
Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in Figure 6 (page 15). Bits E3–E5
allow the user to program the DDR2 SDRAM with an AL of 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should
not be used as an unknown operation or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to tRCD (MIN) with
the requirement that AL ≤ tRCD (MIN). A typical application using this feature would set AL = tRCD (MIN) - 1
× tCK. The READ or WRITE command is held for the time of the AL before it is issued internally to the DDR2
SDRAM device. RL is controlled by the sum of AL and CL; RL = AL + CL. WRITE latency (WL) is equal to RL
minus one clock; WL = AL + CL - 1 × tCK.
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6
Extended Mode Register 2 (EMR2)
2Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register 2 (EMR2)
The extended mode register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently
Extended
Mode
Register
all bits in EMR2
are reserved,
except2for(EMR2)
E7, which is used in commercial or high-temperature operations, as
shown in Figure 7. TheThe
EMR2
is programmed
via the 2LM
command
and will
retain the
storedthose
information
until it by
extended
mode register
(EMR2)
controls
functions
beyond
controlled
theuntil
mode
register.
Currently
bits in EMR2 the
are EMR
reserved,
except
forcontents
E7, which
used
is programmed again or
the device
loses
power. all
Reprogramming
will not
alter the
of is
the
in itcommercial
high-temperature operations, as shown in Figure 41. The EMR2 is promemory array, provided
is performedorcorrectly.
grammed via the LM command and will retain the stored information until it is programmed again
or to
until
the device
loses
power.
the EMR
not alter
Bit E7 (A7) must be programmed
as “1”
provide
a faster
refresh
rate Reprogramming
on IT and AT devices
if TC will
exceeds
the
contents
of
the
memory
array,
provided
it
is
performed
correctly.
85°C.
Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT and AT deEMR2 must be loadedvices
whenif all
are85°C.
idle and no bursts are in progress, and the controller must wait the
T Cbanks
exceeds
t
specified time MRD before initiating any subsequent operation. Violating either of these requirements could
EMR2 must be loaded when all banks are idle and no bursts are in progress, and the
result in an unspecified operation.
controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in an unspecified operation.
Figure 7: EMR2 Definition
Figure 41: EMR2 Definition
1
2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
16
0
E15 E14
Notes:
15 14 n
MRS 0
12 11
0 0
10 9 8 7 6
0 0 SRT 0
0
5 4 3 2
0 0 0 0
A1 A0
1
0
0
0
Mode Register Set
E7
SRT Enable
Mode register (MR)
0
1X refresh rate (0°C to 85°C)
1
Extended mode register (EMR)
1
2X refresh rate (>85°C)
0
Extended mode register (EMR2)
1
Extended mode register (EMR3)
0
0
0
1
1
Address bus
Extended mode
register (Ex)
1. E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be programmed to “0.”
1. E16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and must be programmed to “0.”
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re2. Mode bits (En) with corresponding
address
balls
greater
than E12 (A12)
are reserved for future use
served for future
use
and(An)
must
be programmed
to “0.”
Notes:
and must be programmed to “0.”
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7
2Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register 3 (EMR3)
Extended Mode Register 3 (EMR3)
The extended
mode register
3 (EMR3)3controls
functions beyond those controlled by the mode register. Currently
Extended
Mode
Register
(EMR3)
all bits in EMR3 are reserved, as shown in Figure 8. The EMR3 is programmed via the LM command and will
The extended
registeragain
3 (EMR3)
controls
functions
beyond
those controlled
retain the stored information
until it ismode
programmed
or until
the device
loses power.
Reprogramming
theby
the mode register. Currently all bits in EMR3 are reserved, as shown in Figure 42. The
EMR will not alter the contents of the memory array, provided it is performed correctly.
EMR3 is programmed via the LM command and will retain the stored information until
it is programmed again or until the device loses power. Reprogramming the EMR will
EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the
not alter the contents of the memory array, provided it is performed correctly.
specified time tMRD before initiating any subsequent operation. Violating either of these requirements could
EMR3
must be loaded when all banks are idle and no bursts are in progress, and the
result in an unspecified
operation.
controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in an unspecified operation.
Figure 8: EMR3 Definition
Figure 42: EMR3 Definition
1
2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
16
15 14 n
0
MRS
E15 E14
0
12 11
10
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
A1 A0
1
0
0
0
Address bus
Extended mode
register (Ex)
Mode Register Set
0
0
0
1
Extended mode register (EMR)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
Mode register (MR)
1. E16 (BA2) is only applicable for densities ุ1Gb, is reserved for future use, and must be
programmed to “0.”
1. E16 (BA2) is only applicable
forbits
densities
≥1Gb,
is reserved address
for future
use,(An)
andgreater
must be
2. Mode
(En) with
corresponding
balls
than E12 (A12) are reserved for future use and must be programmed to “0.”
programmed to “0.”
Notes:
Notes:
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved
for future use and must be programmed to “0.”
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8
Commands
8.1
Truth Tables
The following tables provide a quick reference of available DDR2 SDRAM commands, including CKE powerdown modes and bank-to-bank commands.
Table 5: Truth Table - DDR2 Commands
Notes 1-3 apply to the entire table.
CKE
Function
Previous
Cycle
Current
Cycle
CS#
RAS#
CAS#
WE#
BA2–
BA0
An–A11
LOAD MODE
H
H
L
L
L
L
BA
OP code
REFRESH
H
H
L
L
L
H
X
X
X
X
SELF REFRESH entry
H
L
L
L
L
H
X
X
X
X
H
X
X
X
X
SELF REFRESH exit
L
H
X
X
X
4, 7
L
H
H
H
6
A10
A9–A0
Notes
4, 6
Single bank PRECHARGE
H
H
L
L
H
L
BA
X
L
X
All banks PRECHARGE
H
H
L
L
H
L
X
X
H
X
Bank ACTIVATE
H
H
L
L
H
H
BA
WRITE
H
H
L
H
L
L
BA
Column address
L
Column address
4, 5, 6, 8
WRITE with auto precharge
H
H
L
H
L
L
BA
Column address
H
Column address
4, 5, 6, 8
READ
H
H
L
H
L
H
BA
Column address
L
Column address
4, 5, 6, 8
READ with auto precharge
H
H
L
H
L
H
BA
Column address
H
Column address
4, 5, 6, 8
NO OPERATION
H
X
L
H
H
H
X
X
X
X
Device DESELECT
H
X
H
X
X
X
X
X
X
X
H
X
X
X
Power-down entry
H
L
X
X
X
X
L
H
H
H
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Row address
4
9
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CKE
Function
Previous
Cycle
Current
Cycle
Power-down exit
L
H
CS#
RAS#
CAS#
WE#
H
X
X
X
L
H
H
H
BA2–
BA0
An–A11
A10
A9–A0
Notes
X
X
X
X
9
Notes:
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising
edge of the clock.
2. The state of ODT does not affect the states described in this table. The ODT function is not available
during self refresh.
3. “X” means “H or L” (but a defined logic level) for valid IDD measurements.
4. BA2 is only applicable for densities ≥1Gb.
5. An n is the most significant address bit for a given density and configuration. Some larger address bits
may be “Don’t Care” during column addressing, depending on density and configuration.
6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD MODE command
selects which mode register is programmed.
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
9. The power-down mode does not perform any REFRESH operations. The duration of power-down is
limited by the refresh requirements outlined in the AC parametric section.
8.2
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM.
The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also
referred to as COMMAND INHIBIT.
8.3
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS#
is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
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8.4
LOAD MODE (LM)
The mode registers are loaded via bank address and address inputs. The bank address balls determine which
mode register will be programmed. See "Mode Register (MR)" on page 10. The LM command can only be
issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
8.5
ACTIVATE COMMAND
The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The
value on the bank address inputs determines the bank, and the address inputs select the row. This row remains
2Gb: x4, x8, x16 DDR2 SDRAM
active (or open) for accesses until a precharge command is issued to that bank. A prechargeACTIVATE
command must
be issued before opening a different row in the same bank.
ACTIVATE
8.6
ACTIVATEBefore
OPERATION
any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This
is accomplished
which
selectsSDRAM,
both thea bank
Before any READ
or WRITE
commands via
canthe
be ACTIVATE
issued to acommand,
bank within
the DDR2
row in that
and
the
row
to
be
activated.
bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVATE
command, which
the bank
the row to be
activated.a READ or WRITE command may
After selects
a row isboth
opened
withand
an ACTIVATE
command,
t
be issued to that row subject to the RCD specification. tRCD (MIN) should be divided
After a row isbyopened
withperiod
an ACTIVATE
command,
READ
WRITEnumber
command
may be issued
to that row
the clock
and rounded
up toathe
nextorwhole
to determine
the earliest
t
t
subject to theclock
RCDedge
specification.
RCD (MIN) should
be divided
by the
clock period
and command
rounded upcan
to the
after the ACTIVATE
command
on which
a READ
or WRITE
benext
entered.
The same
procedure
usedafter
to convert
other specification
time
whole number
to determine
the earliest
clockisedge
the ACTIVATE
command on limits
which from
a READ
or WRITE
tRCD (MIN) specification of 20ns with a 266 MHz
units
to clock The
cycles.
Forprocedure
example,isa used
command can
be entered.
same
to convert other specification limits from time units to
t
clock ( CK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown
in Figure 44,
clock cycles. For example, a tRCD (MIN) specification
of
20ns with a 266 MHz clock (tCK = 3.75ns) results in
which covers any case where 5 < tRCD (MIN)/tCK ื 6. Figure 44 also shows the case for
5.3 clocks, rounded
up to26.< tRRD (MIN)/tCK ื 3.
tRRD where
t
t
Figure 9:Meeting
Example: tMeeting
RRDand
(MIN)tRCD
and (MIN)
RCD (MIN)
Figure 44: Example:
RRD (MIN)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Command
ACT
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
RD/WR
Address
Row
CK#
CK
Bank address
Row
Bank x
Bank y
tRRD
Row
Col
Bank z
Bank y
tRRD
tRCD
Don’t Care
A subsequent ACTIVATE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVATE commands to the same bank is defined by tRC.
MYX4DDR264M16HW*
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A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini22
mum time interval between successive ACTIVATE commands to different banks is det
fined by RRD.
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DDR2 devices with 8 banks (1Gb or larger) have an additional requirement: tFAW. This
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
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A subsequent ACTIVATE command to a different row in the same bank can only be issued after the previous
active row has been closed (precharged). The minimum time interval between successive ACTIVATE commands
to the same bank is defined by tRC.
A subsequent ACTIVATE command to another bank can be issued while the first bank is being accessed,
which results in a reduction of total row-access overhead. The minimum time interval between successive
ACTIVATE commands to different banks is defined by tRRD.
DDR2 devices with 8 banks (1Gb or larger) have an additional requirement: tFAW. This requires no more than
four ACTIVATE commands may be issued in any given tFAW (MIN) period
8.7
READ COMMAND
The READ command is used to initiate a burst read access to an active row. The value on the bank address
inputs determine the bank, and the address provided on address inputs A0–Ai (where Ai is the most significant
column address bit for a given configuration) selects the starting column location. The value on input A10
determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed
will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for
subsequent accesses.
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior
to tRCD (MIN) by delaying the actual registration of the READ/WRITE command to the internal device by AL
clock cycles.
8.8
READ OPERATION
READ bursts are initiated with a READ command. The starting column and bank addresses are provided with
the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge
is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge
is disabled, the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address will be available READ
latency (RL) clocks later. RL is defined as the sum of AL and CL: RL = AL + CL. The value for AL and CL are
programmable via the MR and EMR commands, respectively. Each subsequent data-out element will be valid
nominally at the next positive or negative clock edge (at the next crossing of CK and CK#). Figure 10 (page
24) shows an example of RL based on different AL and CL settings.
DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state on DQS and the HIGH
state on DQS# are known as the read preamble (tRPRE). The LOW state on DQS and the HIGH state on DQS#
coincident with the last data-out element are known as the read postamble (tRPST).
Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z.
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Data from any READ burst may be concatenated with data from a subsequent READ command to provide
a continuous flow of data. The first data element from the new burst follows the last element of a completed
burst. The new READ command should be issued x cycles after the first READ command, where x equals
BL/2 cycles.
DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4 operations. Once
the BL = 4 READ command is registered, it must be allowed to complete the entire READ burst. However,
a READ (with auto precharge disabled) using BL = 8 operation may be interrupted and truncated only by
another READ burst as long as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture
of DDR2 SDRAM.
Data from any READ burst must be completed before a subsequent
burst DDR2
is allowed.
2Gb: x4,WRITE
x8, x16
SDRAM
READ
Figure 10: READ Latency
Figure 46: READ Latency
CK#
T0
T1
T2
T3
READ
NOP
NOP
NOP
T3n
T4
T4n
T5
CK
Command
Address
NOP
NOP
Bank a,
Col n
RL = 3 (AL = 0, CL = 3)
DQS, DQS#
DO
n
DQ
Notes:
CK#
T0
T1
T2
T3
T4
NOP
NOP
NOP
T4n
T5
T5n
1. DO n = data-out
from column n.
CK
2. BL =Command
4.
READ
NOP
NOP
3. ThreeAddress
subsequent
elements
of data-out appear in the programmed order following DO n.
Bank
a,
Col n
t
4. Shown with nominal tAC,
and tDQSQ.CL = 3
AL = DQSCK,
1
RL = 4 (AL = 1 + CL = 3)
8.9
DQS, DQS#
WRITE COMMAND
DO
n
DQ
The WRITE command is used to initiate a burst write access to an active row. The value on the bank select inputs
T0
T1
T2
T3
T3n
T4
T4n
T5
selects the bank,
and the address provided on inputs A0–Ai (where Ai is the most significant column address
CK#
bit for a givenCKconfiguration) selects the starting column location. The value on input A10 determines whether
Command
READ
NOP precharge
NOPis selected,
NOP
NOP accessed
NOP
or not auto
precharge
is used. If auto
the row being
will be precharged at the
end of theAddress
WRITE burst;
Bank a,if auto precharge is not selected, the row will remain open for subsequent accesses.
Col n
RL = 4 (AL = 0, CL = 4)
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior
DQS, DQS#
to tRCD (MIN) by delaying the actual registration of the READ/WRITE command to the internal device by AL
clock cycles.DQ
DO
n
Transitioning Data
MYX4DDR264M16HW* Notes:
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Don’t Care
1. DO n = data-out from column n.
24
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
Form #:
DO n.
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Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to
memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
8.10
WRITE OPERATION
WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL minus one clock
cycle (WL = RL - 1CK) (see "READ COMMAND" on page 23). The starting column and bank addresses are
provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the burst.
During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following
the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The
LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the
LOW state on DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ±tDQSS. Subsequent DQS
positive rising edges are timed, relative to the associated clock edge, as ±tDQSS. tDQSS is specified with a
relatively wide range (25% of one clock cycle). All of the WRITE diagrams show the nominal case, and where
the two extreme cases (tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included.
Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and
any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous
flow of input data. The first data element from the new burst is applied after the last element of a completed
burst. The new WRITE command should be issued x cycles after the first WRITE command, where x
equals BL/2.
DDR2 SDRAM supports concurrent auto precharge options, as shown in Table 6 (page 26).
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4 operation. Once the
BL = 4 WRITE command is registered, it must be allowed to complete the entire WRITE burst cycle. However,
a WRITE BL = 8 operation (with auto precharge disabled) might be interrupted and truncated only by another
WRITE burst as long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture of
DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated with any command except
another WRITE command.
Data for any WRITE burst may be followed by a subsequent READ command. The number of clock cycles
required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst may be followed
by a subsequent PRECHARGE command. tWR must be met. tWR starts at the end of the data burst, regardless
of the data mask condition.
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Table 6: WRITE Using Concurrent Auto Precharge
From Command (Bank n)
WRITE with auto precharge
To Command (Bank m)
Minimum Delay (with Concurrent Auto Precharge)
READ or READ with auto precharge
(CL - 1) + (BL/2) + tWTR
WRITE or WRITE with auto precharge
(BL/2)
Units
tCK
2Gb: x4, x8,
1 x16 DDR2 SDRAM
WRITE
PRECHARGE or ACTIVATE
Figure 58: Write Burst
Figure 11: Write Burst
T0
T1
T2
Command
WRITE
NOP
NOP
Address
Bank a,
Col b
CK#
T2n
T3
T3n
T4
CK
t DQSS (NOM)
NOP
WL ± tDQSS
NOP
5
DQS, DQS#
DI
b
DQ
DM
t DQSS (MIN)
tDQSS5
WL - tDQSS
Notes: DQS, DQS#
t
DQ rising DQS signals must alignDI
1. Subsequent
bto the clock within DQSS.
2. DI b = data-in
DM for column b.
3. Three subsequent elements of data-in are applied in the programmed order following DI b.
t DQSS (MAX)
WL + tDQSS
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
tDQSS5
DQS, DQS#
5. A10 is LOW with the WRITE command (auto precharge is disabled).
DI
b
DQ
8.11
DM
PRECHARGE COMMAND
Transitioning Data
Don’t Care
The PRECHARGE
command
is used
to deactivate
open
rowwithin
in a particular
bank or the open row in all
tDQSS.
1. Subsequent
rising DQS
signals
must alignthe
to the
clock
Notes:
banks. The
will be available
for b.
a subsequent row activation a specified time (tRP) after the PRECHARGE
2. bank(s)
DI b = data-in
for column
command
issued,
except inelements
the case of
of data-in
concurrent
auto precharge,
where a READ
orfollowing
WRITE command to
3. isThree
subsequent
are applied
in the programmed
order
DI
b.
a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not
4. other
Showntiming
with BL
= 4, AL = 0,After
CL = a3;bank
thus, has
WL =been
2. precharged, it is in the idle state and must be
violate any
parameters.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is
MYX4DDR264M16HW*
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1Gb DDR2 SDRAM
MYX4DDR264M16HW*
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allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of
precharging. However, the precharge period will be determined by the last PRECHARGE command issued to
the bank.
8.12
PRECHARGE OPERATION
Precharge can be initiated by either a manual PRECHARGE command or by an autoprecharge in conjunction
with either a READ or WRITE command. Precharge will deactivate the open row in a particular bank or the open
row in all banks. The PRECHARGE operation is shown in the previous READ and WRITE operation sections.
During a manual PRECHARGE command, the A10 input determines whether one or all banks are to be
precharged. In the case where only one bank is to be precharged, bank address inputs determine the bank
to be precharged. When all banks are to be precharged, the bank address inputs are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. When a single-bank PRECHARGE command is issued, tRP timing
applies. When the PRECHARGE (ALL) command is issued, tRPA timing applies, regardless of the number of
banks opened.
8.13
REFRESH COMMAND
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#-before-RAS#
(CBR) REFRESH. All banks must be in the idle mode prior to issuing a REFRESH command. This command is
nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal
refresh controller. This makes the address bits a “Don’t Care” during a REFRESH command.
The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average interval of 7.8125μs
(MAX) and all rows in all banks must be refreshed at least once every 64ms. The refresh period begins when the
REFRESH command is registered and ends tRFC (MIN) later. The average interval must be reduced to 3.9μs
(MAX) when TC exceeds 85°C.
8.14
SELF REFRESH COMMAND
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the DDR2 SDRAM retains data without external clocking.
All power supply inputs (including VREF) must be maintained at valid levels upon entry/exit and during SELF
REFRESH operation.
The SELF REFRESH command is initiated when CKE is LOW. The differential clock should remain stable and
meet tCKE specifications at least 1 × tCK after entering self refresh mode. The procedure for exiting self refresh
requires a sequence of commands. First, the differential clock must be stable and meet tCK specifications at
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1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
tCK
least 1 ×
prior to CKE going back to HIGH. Once CKE is HIGH (tCKE [MIN] has been satisfied with three
clock registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for tXSNR. A simple
algorithm for meeting both refresh and DLL requirements is used to apply NOP or DESELECT commands for
200 clock cycles before applying any other command.
9
Electrical Specifications
9.1
Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions outside those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Table 7: Absolute Maximum DC Ratings
Parameter
Symbol
Min
Max
Units
Notes
VDD supply voltage relative to VSS
VDD
-1.0
2.3
V
1
VDDQ supply voltage relative to VSSQ
VDDQ
-0.5
2.3
V
1, 2
VDDL supply voltage relative to VSSL
VDDL
-0.5
2.3
V
1
Voltage on any ball relative to VSS
VIN, VOUT
-0.5
2.3
V
3
Input leakage current; any input 0V ≤ VIN ≤ VDD; all other balls not under test = 0V)
II
-5
5
μA
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and ODT disabled
IOZ
-5
5
μA
VREF leakage current; VREF = valid VREF level
IVREF
-2
2
μA
Notes:
1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times; this is not required when power is
ramping down.
2. VREF ≤ 0.6 x VDDQ; however, VREF may be ≥ VDDQ provided that VREF ≤ 300mV.
3. Voltage on any I/O may not exceed voltage on VDDQ.
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1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
9.2
AC and DC Operating Conditions
Table 8: Recommended DC Operating Conditions (SSTL_18)
All voltages referenced to VSS.
Parameter
Symbol
Min
Nom
Max
Units
Notes
Supply voltage
VDD
1.7
1.8
1.9
V
1, 2
VDDL supply voltage
VDDL
1.7
1.8
1.9
V
2, 3
I/O supply voltage
VDDQ
1.7
1.8
1.9
V
2, 3
I/O reference voltage
VREF(DC)
0.49 × VDDQ
0.50 × VDDQ
0.51 × VDDQ
V
4
I/O termination voltage (system)
VTT
VREF(DC) - 40
VREF(DC)
VREF(DC) + 40
mV
5
Notes:
1. VDD and VDDQ must track each other. VDDQ must be ≤ VDD.
2. VSSQ = VSSL = VSS.
3. VDDQ tracks with VDD; VDDL tracks with VDD.
4. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the
same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±1 percent of the DC value.
Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF(DC). This measurement is to be taken
at the nearest VREF bypass capacitor.
5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected
to be set equal to VREF, and must track variations in the DC level of VREF.
9.3
ODT DC Electrical Characteristics
Table 9: ODT DC Electrical Characteristics
All voltages are referenced to VSS.
Parameter
Symbol
Min
Nom
Max
Units
Notes
RTT effective impedance value for 75Ω setting; EMR (A6, A2) = 0, 1
RTT1(EFF)
60
75
90
Ω
1, 2
RTT effective impedance value for 150Ω setting; EMR (A6, A2) = 1, 0
RTT2(EFF)
120
150
180
Ω
1, 2
RTT effective impedance value for 50Ω setting; EMR (A6, A2) = 1, 1
RTT3(EFF)
40
50
60
Ω
1, 2
ΔΔVM
–6
–
6
%
3
Deviation of VM with respect to VDDQ/2
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Notes:
1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL(DC) to the ball being tested, and
then measuring current, I(VIH[AC]), and I(VIL[AC]), respectively.
VIH(AC) - VIL(AC)
RTT1(EFF) =
I(VIH(AC)) - (VIL(AC))
2. Minimum IT and AT device values are derated by six percent less when the devices operate between
–40°C and 0°C (TC).
3. Measure voltage (VM) at tested ball with no load.
ΔVM =
9.4
(
2 x VM
VDDQ
)
- 1 x 100
Input Electrical Characteristics and Operating Conditions
Table 10: Input DC Logic Levels
All voltages are referenced to VSS.
Parameter
Symbol
Min
Max
Units
Input high (logic 1) voltage
VIH(DC)
VREF(DC) + 125
VDDQ1
mV
Input low (logic 0) voltage
VIL(DC)
–300
VREF(DC) - 125
mV
1. Note: 1. VDDQ + 300mV allowed provided 1.9V is not exceeded.
Table 11: Input AC Logic Levels
All voltages are referenced to VSS.
Parameter
Symbol
Min
Max
Units
Input high (logic 1) voltage (-187E/-25E/-25/-3E/-3)
VIH(AC)
VREF(DC) + 200
VDDQ
mV
Input low (logic 0) voltage (-187E/-25E/-25/-3E/-3)
VIL(AC)
–300
VREF(DC) - 200
mV
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Table 16: Input AC Logic Levels
All voltages are referenced to VSS
Parameter
Symbol
Min
Max
Units
1
Input high (logic 1) voltage (-37E/-5E)
VIH(AC)
VREF(DC) + 250
Input high (logic 1) voltage (-187E/-25E/-25/-3E/-3)
VIH(AC)
VREF(DC) + 200
Input low (logic 0) voltage (-37E/-5E)
VIL(AC)
1Gb DDR2
SDRAM
VDDQ1
mV
MYX4DDR264M16HW*
–300
VREF(DC) - 250
mV
Input low (logic 0) voltage (-187E/-25E/-25/-3E/-3)
VIL(AC)
–300
Note:
VDDQ
mV
VREF(DC) - 200
mV
*Advanced
Subject to change without notice.
1. Refer to AC Overshoot/Undershoot Specification
(page information.
55).
Figure 12: Single-Ended
Input
Signal Levels
Figure 13: Single-Ended
Input Signal
Levels
Note:
1,150mV
VIH(AC)
1,025mV
VIH(DC)
936mV
918mV
900mV
882mV
864mV
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
775mV
VIL(DC)
650mV
VIL(AC)
1. Numbers in diagram reflect nominal DDR2-400/DDR2-533 values.
Table 12: Differential Input Logic Levels
All voltages referenced to VSS.
Parameter
Symbol
Min
Max
Units
Notes
DC input signal voltage
VIN(DC)
–300
VDDQ
mV
1, 6
DC differential input voltage
VID(DC)
250
VDDQ
mV
2, 6
AC differential input voltage
VID(AC)
500
V
mV
3, 6
AC differential cross-point voltage
VIX(AC)
0.50 × VDDQ - 175
0.50 × VDDQ + 175
mV
4
Input midpoint voltage
VMP(DC)
850
950
mV
5
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
45
DDQ Inc. reserves the right to change products or specifications without notice.
Micron Technology,
© 2007 Micron Technology, Inc. All rights reserved.
Notes:
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK#, DQS,
DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.
2. VID(DC) specifies the input differential voltage |VTR - VCP| required for switching, where VTR is the true input
(such as CK, DQS, LDQS, UDQS) level and VCP is the complementary input (such as CK#, DQS#, LDQS#,
UDQS#) level. The minimum value is equal to VIH(DC) - VIL(DC). Differential input signal levels are shown in
Figure 13 (page 32).
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All voltages referenced to VSS
Parameter
Symbol
Min
Max
Units
Notes
DC input signal voltage
VIN(DC)
–300
VDDQ
mV
1, 6
DC differential input voltage
VID(DC)
250
VDDQ
mV
2, 6
AC differential input voltage
VID(AC)
500
AC differential cross-point voltage
VIX(AC)
0.50 × VDDQ - 175
Input midpoint voltage
VMP(DC)
850
mV
5
1Gb DDR2
mV SDRAM
3, 6
0.50
× VDDQ + 175
mV
4
MYX4DDR264M16HW*
VDDQ
950
information.
Subject topair
change
without
notice.
1. VIN(DC) specifies the allowable DC execution of*Advanced
each input
of differential
such
as CK,
CK#,
DQS,
DQS#,
LDQS,
LDQS#,
UDQS,
UDQS#,
and
RDQS,
RDQS#.
VID(AC) specifies the input differential voltage |VTR - VCP| required for switching, where VTR is the true input
2. VID(DC) specifies the input differential voltage |VTR - VCP| required for switching, where
(such as CK, DQS,
LDQS, UDQS, RDQS) level and VCP is the complementary input (such as CK#, DQS#,
VTR is the true input (such as CK, DQS, LDQS,
UDQS) level and VCP is the complementary
LDQS#, UDQS#,
RDQS#)
level.
The
minimum
value
is equal
to The
VIH(AC)
- VIL(AC),value
as shown
in to VIH(DC) input (such as
CK#,
DQS#,
LDQS#,
UDQS#)
level.
minimum
is equal
V
.
Differential
input
signal
levels
are
shown
in
Figure
14.
Table 11 (page 30).
IL(DC)
specifies
the input
voltage
- VCP
| required for
switching,
where
3.
V
ID(AC)
TR the
The typical value of VIX(AC)
is expected
to differential
be about 0.5
× VDDQ|Vof
transmitting
device
and VIX(AC)
is
VTR is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the compleexpected to track
variations
in
V
.
V
indicates
the
voltage
at
which
differential
input
signals
must
DDQas CK#,
IX(AC) DQS#, LDQS#, UDQS#, RDQS#) level. The minimum value is
mentary input (such
cross, as shown
in Figure
13. - VIL(AC), as shown in Table 16 (page 45).
equal
to VIH(AC)
is expected
to be about
× )/2
VDDQ
of the
device
4. The
of VIX(AC)
VMP(DC) specifies
thetypical
input value
differential
common
mode voltage
(VTR +0.5
VCP
where
VTRtransmitting
is the true input
(CK,
and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which
DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC) is expected to be approximately
differential input signals must cross, as shown in Figure 14.
0.5 × VDDQ.5. V
MP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is
true input
(CK,1.9V
DQS)islevel
and VCP is the complementary input (CK#, DQS#). VMP(DC)
VDDQ + 300mVthe
allowed
provided
not exceeded.
is expected to be approximately 0.5 × VDDQ.
6. VDDQ + 300mV allowed provided 1.9V is not exceeded.
Notes:
3.
4.
5.
6.
Figure 13: Differential Input Signal Levels
Figure 14: Differential Input Signal Levels
VIN(DC)max1
2.1V
VDDQ = 1.8V
CP2
1.075V
X
VMP(DC)3
0.9V
0.725V
VIX(AC)4
VID(DC)5
VID(AC)6
X
TR2
VIN(DC)min1
–0.30V
1. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
2. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,
RDQS#,
and UDQS#
TR and CP may
not beLDQS#,
more positive
than signals.
VDDQ + 0.3V or more negative than VSS - 0.3V.
3.
This
provides
a
minimum
of
to a maximum
ofrepresents
950mV andCK#,
is expected
be
TR represents the CK, DQS, RDQS, LDQS,850mV
and UDQS
signals; CP
DQS#, to
RDQS#,
VDDQ/2.
LDQS#, and UDQS# signals.
4. TR and CP must cross in this region.
This provides
minimum
of 850mV
maximum
of 950mV
and is
expected
to be
VDDQ/2.
when static
and
is centered
around
VMP(DC).
5. aTR
and CP must
meet to
at aleast
VID(DC)min
TR cross
and CP
have a minimum 500mV peak-to-peak swing.
TR and CP 6.
must
in must
this region.
Notes:
Notes:
1.
2.
3.
4.
5. TR and CP must meet at least VID(DC)min when static and is centered around VMP(DC).
Micron Technology,
products or specifications without notice.
6. TR and CP must have a minimum 500mV
swing.Inc. reserves the right to©change
46peak-to-peak
2007 Micron Technology, Inc. All rights reserved.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
7. Numbers in diagram reflect nominal values (VDDQ = 1.8V).
MYX4DDR264M16HW*
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1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
9.5
Output Electrical Characteristics and Operating Conditions
1Gb: x4, x8, x16 DDR2 SDRAM
Output Electrical Characteristics and Operating Conditions
Table 13: Differential AC Output Parameters
Output Electrical Characteristics and Operating Conditions
Parameter
Symbol
Min
Max
Units
Notes
AC differential cross-point voltage
VOX(AC)
0.50 × VDDQ - 125
0.50 × VDDQ + 125
mV
1
AC differential voltage swing
Vswing
1.0
–
mV
Table 18: Differential AC Output Parameters
Symbol
Min
Max
Units
Notes
AC Note:
differential cross-point voltage
Parameter
VOX(AC)
0.50 × VDDQ - 125
0.50 × VDDQ + 125
mV
1
AC differential voltage swing
Vswing
1.0
–
mV
1. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting device and VOX(AC) is
1. The
value indicates
of VOX(AC)the
is expected
be about
0.5 × Voutput
the transmitting deNote:
expected to track
variations
in Vtypical
voltage attowhich
differential
DDQ ofsignals
DDQ. VOX(AC)
vice
and
V
is
expected
to
track
variations
in
V
.
V
indicates
the voltage at
OX(AC)
DDQ
OX(AC)
must cross.
which differential output signals must cross.
Figure Output
15: Differential
Output Signal Levels
Figure 14: Differential
Signal Levels
VDDQ
VTR
Crossing point
Vswing
VOX
VCP
VSSQ
Table 14: Output DC Current Drive
Table 19: Output DC Current Drive
Parameter
Symbol
Value
Parameter
Output MIN source DC current
I
Output MIN source DC current OH
Output MIN sink DC current
IOL
Output MIN sink DC current
2.
3.
4.
13.4
Symbol
IOH
IOL
Units
mA
mA
Value
–13.4
13.4
Notes
Units
1, 2, 4
mA
2, 3, 4
mA
Notes
1, 2, 4
2, 3, 4
1. For IOH(DC); VDDQ = 1.7V, VOUT = 1,420mV. (VOUT - VDDQ)/IOH must be less than 21Ω for values of VOUT between VDDQ and VDDQ - 280mV.
; VDDQ(V=OUT
1.7V,
VOUT
= 280mV.
VOUT
must
befor
lessvalues
than 21Ω
for values of VOUT
2.
For=IOL(DC)
For IOH(DC); VDDQ = 1.7V, VOUT
1,420mV.
- VDDQ
)/IOH
must be
less/IOL
than
21Ω
of VOUT
between 0V and 280mV.
between VDDQ and VDDQ - 280mV.
3. The DC value of VREF applied to the receiving device is set to VTT.
For IOL(DC); VDDQ = 1.7V, 4.
VOUT
= values
280mV.ofVIOUT/IOLand
must
be less
21Ω
of VOUT
between
0V1and
IOL(DC)
arethan
based
on for
thevalues
conditions
given
in Notes
and 2. They
The
OH(DC)
280mV.
are used to test device drive current capability to ensure VIH,min plus a noise margin and
VIL,max
minus
a noise
margin
aretodelivered
to an SSTL_18 receiver. The actual current valThe DC value of VREF applied
to the
receiving
device
is set
VTT.
ues are derived by shifting the desired driver operating point (see output IV curves)
The values of IOH(DC) and IOL(DC)
area based
on line
the conditions
in Notes
1 and
2. They
used to
along
21Ω load
to define agiven
convenient
driver
current
forare
measurement.
Notes:
1.
–13.4
Notes:
test device drive current capability to ensure VIH,min plus a noise margin and VIL,max minus a noise margin
are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver
operating point (see output IV curves) along a 21Ω load line to define a convenient driver current for
measurement.
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Table 15: Output Characteristics
1Gb: x4, x8, x16 DDR2 SDRAM
Output Electrical Characteristics and Operating Conditions
Parameter
Min
Output impedance
Nom
Max
Units
See Output Driver Characteristics (page 50)
Table
20:pull-down
Output
Characteristics 0
Pull-up and
mismatch
Output slew rate
Parameter
–
1.5
Min
Output impedance
–
4
Nom
5
Ω
1, 2
Ω
1, 2, 3
V/ns
Max
See Output Driver Characteristics (page 50)
Notes: mismatch
Pull-up and pull-down
0
–
Notes
4
1. Absolute specifications: 0°C ≤ TC 1.5
≤ +85°C; VDDQ = 1.8V
Output slew rate
– ±0.1V, VDD = 1.8V5±0.1V.
Units
1, 4, 5, 6
Notes
Ω
1, 2
Ω
1, 2, 3
V/ns
1, 4, 5, 6
2. Impedance
for output
DC current: VDDQ
= 1.7V;
= 1420mV;
OUT
±0.1V,
VDDV=
1.8V
±0.1V. (VOUT 1. Absolute conditions
specifications:
0°C ≤ Tsource
Notes: measurement
C ≤ +85°C; VDDQ = 1.8V
VDDQ)/IOH must2.beImpedance
less than 23.4Ω
for values
of VOUT between
VDDQ
andDC
VDDQ
- 280mV.
impedance
= 1.7V;
VOUT =
measurement
conditions
for output
source
current:
VDDQThe
1420mV;
V
)/I
must
be
less
than
23.4Ω
for
values
of
V
between
V
measurement condition
for(Voutput
sink
DC
current:
V
=
1.7V;
V
=
280mV;
V
/I
must
be
lessand
OUT
DDQ OH
OUT OL
DDQ
DDQ
OUT
OUT
V
280mV.
The
impedance
measurement
condition
for
output
sink
DC
current:
VDDQ
DDQ
than 23.4Ω for values of VOUT between 0V and 280mV.
= 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V
3. Mismatch is an absolute
value between pull-up and pull-down; both are measured at the same
and 280mV.
temperature and
voltage.
3. Mismatch is an absolute value between pull-up and pull-down; both are measured at
same temperature
and is
voltage.
4. Output slew rate the
for falling
and rising edges
measured between VTT - 250mV and VTT + 250mV for
4. Output slew rate for falling and rising edges is measured between VTT - 250mV and VTT
single-ended signals. For differential signals (DQS, DQS#), output slew rate is measured between DQS
+ 250mV for single-ended signals. For differential signals (DQS, DQS#), output slew rate
- DQS# = –500mV
and DQS#between
- DQS =DQS
500mV.
Output
slew rate
guaranteed
designOutput
but is slew
not rate
is measured
- DQS#
= –500mV
andisDQS#
- DQS =by
500mV.
guaranteed
by design but is not necessarily tested on each device.
necessarily testedis on
each device.
The
ofmeasured
the slew rate
from VIL(DC)max to VIH(DC)min is equal to
5. The absolute 5.
value
ofabsolute
the slewvalue
rate as
fromasVmeasured
IL(DC)max to VIH(DC)min is equal to or greater than the
or greater than the slew rate as measured from VIL(AC)max to VIH(AC)min. This is guaranslew rate as measured
from
VIL(AC)max
to VIH(AC)min. This is guaranteed by design and characterization.
teed by
design
and characterization.
6. IT and ET devices
additional
0.4an
V/ns
in the MAX
– 40°C
and 0°C. –
6. ITrequire
and ATan
devices
require
additional
0.4 limit
V/ns when
in theTMAX
limit when
TC is between
C is between
40°C and 0°C.
Figure
15: Output
Slew Rate
LoadRate Load
Figure
16: Output
Slew
VTT = VDDQ/2
Output
(VOUT)
9.6
25Ω
Reference
point
Temperature and Thermal Impedance
It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in Table 16 (page 35),
be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet
specifications. An important step in maintaining the proper junction temperature is using the device’s thermal
impedances correctly. The thermal impedances are listed in Table 17 (page 36) for the applicable and
available die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08,
“Thermal Applications” prior to using the thermal impedances listed in Table 17 (page 36). For designs that
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are expected to last several years and require the flexibility to use several DRAM die shrinks, consider using
final target theta values (rather than existing values) to account for increased thermal impedances from the die
size reduction.
The DDR2 SDRAM device’s safe junction temperature range can be maintained when the TC specification is
not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat
sinks may be required in order to satisfy the case temperature specifications.
2Gb: x4, x8, x16 DDR2
Electrical Specifications – Absolute R
Table 16: Temperature Limits
Parameter
Storage
temperature
Table
6: Temperature
Operating temperature – commercial
Symbol
TSTG
Limits
TC
TC
Operating temperature – industrial
TA
Storage temperature
TC
Operating
temperature – commercial
Operating temperature
– automotive
TA
Parameter
Operating temperature – industrial
Min
Max
-55
0
-40
-40
-40
-40
150
85
Symbol
95
T85
STG
105
TC
105
Notes:
Units
Min
–55
0
TC
–40
TAMB
–40
°C
Notes
1
2, 3
Max 2, 3, 4
150 4, 5
85 2, 3, 4
4, 5
Units
°C
°C
95
°C
85
°C
Notes: 1. MAX storage case temperature TSTG is measured in the center of the package,
1. MAX storage case temperature TSTG is measured in the center of the
package, as shown in Figure 16.
in Figure 12. This case temperature limit is allowed to be exceeded briefly duri
This case temperature limit is allowed
to
be
exceeded
briefly
during
package
reflow,
as noted
in Micron
age reflow, as noted in Micron technical note
TN-00-15,
“Recommended
Solde
technical note TN-00-15, “Recommended
rameters.” Soldering Parameters.”
2. MAX
case
temperature
is measured
in theincenter
2. MAX operating case temperature
TCoperating
is measured
in the
center of theTCpackage,
as shown
Figure of
16.the package,
in
Figure
12.
3. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
3. Device functionality is not guaranteed if the device exceeds maximum TC durin
4. Both temperature specifications
must be satisfied.
tion.
5. Operating ambient temperature
surrounding
the package.
4. Both
temperature
specifications must be satisfied.
5. Operating ambient temperature surrounding the package.
Figure 16: Example Temperature Test Point Location
Figure 12: Example Temperature Test Point Location
Test point
Length (L)
0.5 (L)
0.5 (W)
Width (W)
Lmm x Wmm FBGA
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Table 17: Thermal Impedance
Die
Revision
Package
60-ball
H1
84-ball
60-ball
M1
84-ball
Substrate (pcb)
Θ JA (°C/W)
Airflow = 0m/s
Θ JA (°C/W)
Airflow = 1m/s
Θ JA (°C/W)
Airflow = 2m/s
2-layer
4-layer
2-layer
4-layer
Low Conductivity
High Conductivity
Low Conductivity
High Conductivity
72.5
54.5
68.8
51.3
85.4
63.2
80.8
59.7
55.5
45.7
52.0
42.7
70.6
56.1
67.0
53.3
49.5
42.3
46.5
39.6
64.5
52.8
61.6
50.7
Θ JB (°C/W)
Θ JC (°C/W)
35.6
35.2
32.5
32.3
5.7
5.6
42.8
11.7
44.7
11.7
Note:
1. Thermal resistance data is based on a number of samples from multiple lots and should be viewed as a
typical number.
9.7
FBGA Package Capacitance
Table 18: Input Capacitance
Parameter
Symbol
Min
Max
Units
Notes
Input capacitance: CK, CK#
CCK
1.0
2.0
pF
1
Delta input capacitance: CK, CK#
CDCK
–
0.25
pF
2, 3
Input capacitance: BA[2:0], A[14:0] (A[13:0] on x16), CS#, RAS#, CAS#, WE#, CKE, ODT
CI
1.0
2.0
pF
1, 4
Delta input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODT
CDI
–
0.25
pF
2, 3
Input/output capacitance: DQ, DQS, DM, NF
CIO
2.5
4.0
pF
1, 4
Delta input/output capacitance: DQ, DQS, DM, NF
CDIO
–
0.5
pF
2, 3
Notes:
1. This parameter is sampled. VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V, VREF = VSS, f = 100 MHz, TC = 25°C,
VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.1V. DM input is grouped with I/O balls, reflecting the fact that
they are matched in loading.
2. The capacitance per ball group will not differ by more than this maximum amount for any given device.
3. ΔC are not pass/fail parameters; they are targets.
4. Reduce MAX limit by 0.25pF for -25, -25E, and -187E speed devices.
5. Reduce MAX limit by 0.5pF for -3, -3E, -25, -25E, and -187E speed devices.
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9.8
Electrical Specifications – IDD Parameters
9.8.1
IDD Specifications and Conditions
Table 19: General IDD Parameters
IDD Parameters
-25E
CL (IDD)
5
tRCD
12.5
tRC
tRRD
tCK
(IDD)
(IDD)
57.5
(IDD) - x16 (2KB)
10
(IDD)
2.5
tRAS
MIN (IDD)
45
tRAS
MAX (IDD)
70,000
tRP
(IDD)
12.5
tRFC
(IDD - 256Mb)
75
tRFC
(IDD - 512Mb)
105
tRFC
(IDD - 1Gb)
127.5
tRFC
(IDD - 2Gb)
197.5
tFAW
(IDD) - x16 (2KB)
Defined by pattern in Table 20 (page 37)
9.8.2
IDD7 Conditions
The detailed timings are shown below for IDD7. Where general IDD parameters in Table 19 conflict with pattern
requirements of Table 20, then Table 20 requirements take precedence.
Table 20: IDD7 Timing Patterns (8-Bank Interleave READ Operation)
Speed Grade
IDD7 Timing Patterns
Timing patterns for 8-bank x16 devices
-25E
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
Notes:
1. A = active; RA = read auto precharge; D = deselect.
2. All banks are being interleaved at tRC (IDD) without violating tRRD (IDD) using a BL = 4.
3. Control and address bus inputs are stable during deselects.
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9.9
IDD Parameters
Table 21: IDD Parameters
Parameter/Condition
Symbol
-25E
Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching
IDD0
80
mA
Operating one bank active-read-precharge current: Iout = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRC = tRC (I ), tRAS = tRAS MIN (I ), tRCD = tRCD (I ); CKE is HIGH, CS# is HIGH between valid commands;
DD
DD
DD
Address bus inputs are switching; Data pattern is same as IDD4W
IDD1
95
mA
Precharge power-down current: All banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs
are stable; Data bus inputs are floating
IDD2P
7 (Rev H)
10 (Rev M)
mA
Precharge quiet standby current: All banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and
address bus inputs are stable; Data bus inputs are floating
IDD2Q
26
mA
Precharge standby current: All banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are switching; Data bus inputs are switching
IDD2N
30
mA
Active power-down current: All banks open;
stable; Data bus inputs are floating
tCK
=
tCK
(IDD); CKE is LOW; Other control and address bus inputs are
IDD3P(FAST)
IDD3P(SLOW)
20 (Rev H)
30 (Rev M)
10 (Rev H)
20 (Rev M)
35 (Rev H)
38 (Rev M)
mA
Active standby current: All banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is
HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching
IDD3N
Operating burst write current: All banks open, continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK
(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
IDD4W
160
mA
Operating burst read current: All banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (I ), tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, CS# is HIGH be- tween valid commands; Address
DD
DD
DD
bus inputs are switching; Data bus inputs are switching
IDD4R
150
mA
Burst refresh current: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching
IDD5
150 (Rev H)
160 (Rev M)
mA
IDD6
7
IDD6L
5
IDD7
260
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus
inputs are floating
Operating bank interleave read current: All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL =
tRCD (I ) - 1 x tCK (I ); tCK = tCK (IDD), tRC = tRC (I ), tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, CS# is
DD
DD
DD
DD
DD
HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching.
mA
mA
mA
Notes:
1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.
2. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
3. IDD parameters are specified with ODT disabled.
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4. Data bus consists of DQ, DM, DQS, DQS#, LDQS, LDQS#, UDQS, and UDQS#. IDD values must be met
with all combinations of EMR bits 10 and 11.
5. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
6. The following IDD values must be derated (IDD limits increase) on IT-option devices when operated outside
of the range 0°C ≤ TC ≤ +85°C:
• When TC ≤ 0°C
IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and
IDD7 must be derated by 7%.
• When TC ≥ 85°C
IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5W must be derated by 2%; IDD2P must
be derated by 20%; IDD3P slow must be derated by 30%; and IDD6 must be derated by 80% (IDD6 will
increase by this amount if TC < 85°C and the 2x refresh option is still enabled).
9.10
AC Timing Operating Specifications
Table 22: AC Operating Specifications and Conditions
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes 1-5 apply to the
entire table; VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics
Parameter
-25E
Symbol
Min
Max
Units
Notes
ns
6,7,8,9
Clock
CL = 6
tCK
(avg)
2.5
8.0
CL = 5
tCK
(avg)
2.5
8.0
CK high-level width
tCH
(avg)
0.48
0.52
tCK
CK low-level width
tCL
(avg)
0.48
0.52
tCK
Clock cycle time
Half clock period
Absolute tCK
tHP
tCK
MIN = lesser of tCH and tCL MAX = n/a
ps
(abs) MIN = tCK (AVG) MIN + tJITper (MIN); MAX = tCK (AVG) MAX + tJITper (MAX)
Absolute CK high-level width
tCH
(abs)
Absolute CK low-level width
tCL
(abs)
tCK
tCH
tJITdty
MIN =
(AVG) MIN ×
(AVG) MIN +
(MIN);
MAX = tCK (AVG) MAX × tCH (AVG) MAX + tJITdty (MAX)
MIN = tCK (AVG) MIN × tCL (AVG) MIN + tJITdty (MIN)
MAX = tCK (AVG) MAX × tCL (AVG) MAX + tJITdty (MAX)
10
11
ps
ps
ps
Clock Jitter
Period jitter
tJITper
-100
100
ps
12
Half period
tJITdty
-100
100
ps
13
Cycle to cycle
tJITcc
180
180
ps
14
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AC Characteristics
Parameter
-25E
Units
Notes
Symbol
Min
Max
Cumulative error, 2 cycles
tERR
2per
-150
150
ps
Cumulative error, 3 cycles
tERR
3per
-175
175
ps
Cumulative error, 4 cycles
tERR
4per
-200
200
ps
Cumulative error, 5 cycles
tERR
5per
tERR
6-
-200
200
ps
-300
300
ps
-450
450
ps
15
-350
350
ps
19
Cumulative error, 6–10 cycles
Cumulative error, 11–50 cycles
10per
tERR
1150per
15
15,16
Data Strobe Out
DQS output access time from CK/CK#
tDQSCK
DQS read preamble
tRPRE
MIN = 0.9 × tCK; MAX = 1.1 × tCK
tCK
17, 18, 19
DQS read postamble
tRPST
MIN = 0.4 × tCK; MAX = 0.6 × tCK
tCK
17,18,19,20
tLZ1
MIN = tAC (MIN); MAX = tAC (MAX)
ps
19, 21, 22
CK/CK# to DQS Low-Z
Data Strobe In
DQS rising edge to CK rising edge
tDQSS
MIN = –0.25 × tCK; MAX = 0.25 × tCK
tCK
DQS input-high pulse width
tDQSH
MIN = 0.35 × tCK; MAX = n/a
tCK
DQS input-low pulse width
tDQSL
MIN = 0.35 × tCK; MAX = n/a
tCK
DQS falling to CK rising: setup time
tDSS
MIN = 0.2 × tCK; MAX = n/a
tCK
DQS falling from CK rising: hold time
tDSH
MIN = 0.2 × tCK; MAX = n/a
tCK
tWPRES
MIN = 0; MAX = n/a
ps
23, 24
DQS write preamble
tWPRE
MIN = 0.35 × tCK; MAX = n/a
tCK
18
DQS write postamble
tWPST
MIN = 0.4 × tCK; MAX = 0.6 × tCK
tCK
18, 25
–
MIN = WL - tDQSS; MAX = WL + tDQSS
tCK
Write preamble setup time
WRITE command to first DQS transition
18
Data Out
DQ output access time from CK/CK#
tAC
DQS–DQ skew, DQS to last DQ valid, per group, per access tDQSQ
DQ hold from next DQS strobe
tQHS
-400
400
ps
19
–
200
ps
26, 27
–
300
ps
28
DQ–DQS hold, DQS to first DQ not valid
tQH
MIN = tHP - tQHS; MAX = n/a
ps
26, 27, 28
CK/CK# to DQ, DQS High-Z
tHZ
MIN = n/a; MAX = tAC (MAX)
ps
19, 21, 29
CK/CK# to DQ Low-Z
tLZ2
MIN = 2 × tAC (MIN); MAX = tAC (MAX)
ps
19, 21, 22
Data valid output window
DVW
MIN = tQH - tDQSQ; MAX = n/a
ns
26, 27
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AC Characteristics
-25E
Parameter
Symbol
Min
Max
Units
Notes
Data In
DQ and DM input setup time to DQS
tDSb
50
–
ps
DQ and DM input hold time to DQS
tDHb
125
–
ps
DQ and DM input setup time to DQS
tDSa
250
–
ps
DQ and DM input hold time to DQS
tDHa
250
–
ps
tDIPW
DQ and DM input pulse width
MIN = 0.35 × tCK; MAX = n/a
tCK
26, 30, 31
18, 32
Command and Address
Input setup time
tISb
175
–
ps
Input hold time
tIHb
250
–
ps
Input setup time
tISa
375
–
ps
Input hold time
tIHa
375
–
ps
Input pulse width
tIPW
0.6
–
tCK
18, 32
ACTIVATE-to- ACTIVATE delay, same bank
tRC
55
–
ns
18, 34, 51
ACTIVATE-to-READ or WRITE delay
tRCD
12.5
–
ns
18
ACTIVATE-to-PRECHARGE delay
tRAS
40
70k
ns
18, 34, 35
tRP
12.5
–
ns
<1Gb
tRPA
12.5
–
ns
≥1Gb
tRPA
15
–
ns
ACTIVATE-to-ACTIVATE delay different bank
tRRD
10
–
ns
18, 37
4-bank activate period (≥1Gb)
tFAW
45
–
ns
18, 38
Internal READ-to-PRECHARGE delay
tRTP
7.5
–
ns
18, 37, 39
CAS#-to-CAS# delay
tCCD
2
–
tCK
18
Write recovery time
tWR
15
–
ns
18, 37
Write AP recovery + precharge time
tDAL
–
ns
40
Internal WRITE-to-READ delay
tWTR
7.5
–
ns
18, 37
LOAD MODE cycle time
tMRD
2
-
tCK
18
PRECHARGE period
PRECHARGE ALL period <1Gb
tWR
+ tRP
31, 33
18, 36
Refresh
REFRESH- to- ACTIVATE or to -REFRESH interval
tRFC
127.5
–
–
Average periodic refresh (commercial)
tREFI
–
7.8
μs
tREFIIT
–
3.9
μs
Average periodic refresh (industrial)
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
18, 41
41
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
AC Characteristics
-25E
Parameter
Units
Notes
3.9
μs
18, 41
MIN limit = tIS + tCK + tIH; MAX limit = n/a
ns
42
Symbol
Min
Max
Average periodic refresh (automotive)
tREFIAT
–
CKE LOW to CK, CK# uncertainty
tDELAY
Self Refresh
Exit SELF REFRESH to onREAD command
tXSNR
MIN limit = tRFC (MIN) + 10; MAX limit = n/a
ns
Exit SELF REFRESH to READ command
tXSRD
MIN limit = 200; MAX limit = n/a
tCK
18
Exit SELF REFRESH timing reference
tISXR
MIN limit = tIS; MAX limit = n/a
ps
33, 43
Power Down
Exit active power- down to READ command
MR12 = 0
MR12 = 1
Exit precharge power-down and active power-down to any
nonREAD command
CKE MIN HIGH/LOW time
tXARD
2
–
tCK
8 - AL
–
tCK
2
–
tCK
tXP
tCKE
tCK
MIN = 3; MAX = n/a
18
18, 44
ODT
ODT to power- down entry latency
tANPD
3
–
tCK
ODT power-down exit latency
tAXPD
8
–
tCK
ODT turn-on delay
tAOND
2
tCK
ODT turn-off delay
tAOFD
2.5
tCK
18, 45
ps
19, 46
ps
47, 48
ps
49
ODT turn-on
tAON
ODT turn-off
tAOF
ODT turn-on (power-down mode)
tAONPD
ODT turn-off (power-down mode)
tAOFPD
ODT enable from MRS command
tMOD
tAC
MIN =
tAC
MIN =
tAC
(MIN)
tAC
(MIN) + 2000
tAC
(MIN); MAX =
tAC
(MAX) +600
(MAX) + 600
2 × tCK + tAC (MAX) + 1000
(MIN) + 2000; MAX = 2.5 ×
tCK
MIN = 12; MAX = n/a
+
tAC
(MAX) + 1000
18
ps
ns
18, 50
Notes:
1. All voltages are referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/
supply voltage levels, but the related specifications and the operation of the device are warranted for the
full voltage range specified. ODT is disabled for all measurements that are not ODT-specific.
3. Outputs measured with equivalent load.
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environment, and parameter
specifications are guaranteed for the specified AC input levels under normal use conditions. The slew rate
for the input signals used to test the device is 1.0 V/ns for signals in the range between VIL(AC) and VIH(AC).
Slew rates other than 1.0 V/ns may require the timing parameters to be derated as specified.
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
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Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (that is, the receiver will
effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as
the signal does not ring back above [below] the DC input LOW [HIGH] level).
6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).
7. Operating frequency is only allowed to change during self refresh mode, precharge power-down mode,
or system reset condition. SSC allows for small deviations in operating frequency, provided the SSC
guidelines are satisfied.
8. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the
smallest clock rate allowed (except for a deviation due to allowed clock jitter). Input clock jitter is allowed
provided it does not exceed values specified. Also, the jitter must be of a random Gaussian distribution in
nature.
9. Spread spectrum is not included in the jitter specification values. However, the input clock can
accommodate spread spectrum at a sweep rate in the range 8–60 kHz with an additional one percent
tCK (AVG); however, the spread spectrum may not use a clock rate below tCK (AVG) MIN or above tCK
(AVG) MAX.
10. MIN (tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time driven
to the device. The clock’s half period must also be of a Gaussian distribution; tCH (AVG) and tCL (AVG)
must be met with or without clock jitter and with or without duty cycle jitter. tCH (AVG) and tCL (AVG) are
the average of any 200 consecutive CK falling edges. tCH limits may be exceeded if the duty cycle jitter is
small enough that the absolute half period limits (tCH [ABS], tCL [ABS]) are not violated.
11. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK# inputs; thus, tHP (MIN) ≥
the lesser of tCL (ABS) MIN and tCH (ABS) MIN.
12. The period jitter (tJITper) is the maximum deviation in the clock period from the average or nominal clock
allowed in either the positive or negative direction. JEDEC specifies tighter jitter numbers during DLL
locking time. During DLL lock time, the jitter values should be 20 percent less those than noted in the
table (DLL locked).
13. The half-period jitter (tJITdty) applies to either the high pulse of clock or the low pulse of clock; however,
the two cumulatively can not exceed tJITper.
14. The cycle-to-cycle jitter (tJITcc) is the amount the clock period can deviate from one cycle to the next.
JEDEC specifies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter values
should be 20 percent less than those noted in the table (DLL locked).
15. The cumulative jitter error (tERRnper), where n is 2, 3, 4, 5, 6–10, or 11–50 is the amount of clock time
allowed to consecutively accumulate away from the average clock over any number of clock cycles.
16. JEDEC specifies using tERR6–10per when derating clock-related output timing (see notes 19 and 48).
Micron requires less derating by allowing tERR5per to be used.
17. This parameter is not referenced to a specific voltage level but is specified when the device output is no
longer driving (tRPST) or beginning to drive (tRPRE).
18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock that latches it
in. However, the input timing (in ns) references to the tCK (AVG) when determining the required number of
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
43
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
clocks. The following input parameters are determined by taking the specified percentage times the tCK
(AVG) rather than tCK: tIPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.
19. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must
be derated by the actual jitter error when input clock jitter is present; this will result in each parameter
becoming larger. The following parameters are required to be derated by subtracting tERR5per (MAX): tAC
(MIN), tDQSCK (MIN), tLZDQS (MIN), tLZDQ (MIN), tAON (MIN); while the following parameters are required
to be derated by subtracting tERR5per (MIN): tAC (MAX), tDQSCK (MAX), tHZ (MAX), tLZDQS (MAX), tLZDQ
(MAX), tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITper (MAX), while tRPRE
(MAX), is derated by subtracting tJITper (MIN). The parameter tRPST (MIN) is derated by subtracting
tJITdty (MAX), while tRPST (MAX), is derated by subtracting tJITdty (MIN). Output timings that require
tERR
5per derating can be observed to have offsets relative to the clock; however, the total window will not
degrade.
20. When DQS is used single-ended, the minimum limit is reduced by 100ps.
21. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These
parameters are not referenced to a specific voltage level, but specify when the device output is no longer
driving (tHZ) or begins driving (tLZ).
22. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition.
23. This is not a device limit. The device will operate with a negative value, but system performance could be
degraded due to bus turnaround.
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown
(DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If
a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS.
25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-driven signal
should either be HIGH, LOW, or High-Z, and that any signal transition within the input switching region
must follow valid input requirements. That is, if DQS transitions HIGH (above VIH[DC]min), then it must not
transition LOW (below VIH[DC]) prior to tDQSH (MIN).
26. Referenced to each output group: x4 = DQS with DQ[3:0]; x8 = DQS with DQ[7:0]; x16 = LDQS with
DQ[7:0]; and UDQS with DQ[15:8].
27. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH =
tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical
data valid window can be derived.
28. tQH = tHP - tQHS; the worst case tQH would be the lesser of tCL (ABS) MAX or tCH (ABS) MAX times tCK
(ABS) MIN - tQHS. Minimizing the amount of tCH (AVG) offset and value of tJITdty will provide a larger tQH,
which in turn will provide a larger valid data out window.
29. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over tDQSCK (MAX) +
tRPST (MAX) condition.
30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/
ns (1 V/ns for each signal). There are two sets of values listed: tDSa, tDHa and tDSb, tDHb. The tDSa, tDHa
values (for reference only) are equivalent to the baseline values of tDSb, tDHb at VREF when the slew rate is
2 V/ns, differentially. The baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
44
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
tDSb
logic trip points.
is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling signal, while tDHb
is referenced from VIL(DC) for a rising signal and VIH(DC) for a falling signal. If the differential DQS slew rate is
not equal to 2 V/ns, then the baseline values must be derated. If the DQS differential strobe feature is not
enabled, then the DQS strobe is single-ended and the baseline values must be derated. Single-ended
DQS data timing is referenced at DQS crossing VREF.
31. VIL/VIH DDR2 overshoot/undershoot.
32. For each input signal—not the group collectively.
33. There are two sets of values listed for command/address: tISa, tIHa and tISb, tIHb. The tISa, tIHa values
(for reference only) are equivalent to the baseline values of tISb, tIHb at VREF when the slew rate is 1 V/ns.
The baseline values, tISb, tIHb, are the JEDEC-defined values, referenced from the logic trip points. tISb is
referenced from VIH(AC) for a rising signal and VIL(AC) for a falling signal, while tIHb is referenced from VIL(DC)
for a rising signal and VIH(DC) for a falling signal. If the command/address slew rate is not equal to 1 V/ns,
then the baseline values must be derated by adding the values from Setup and Hold Time
Derating Values.
34. This is applicable to READ cycles only. WRITE cycles generally require additional time due to tWR during
auto precharge.
35. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisfied because
tRAS lockout feature is supported in DDR2 SDRAM.
36. When a single-bank PRECHARGE command is issued, tRP timing applies. tRPA timing applies when the
PRECHARGE (ALL) command is issued, regardless of the number of banks open. For 8-bank devices
(≥1Gb), tRPA (MIN) = tRP (MIN) + tCK (AVG) (Table 22 (page 39)) lists tRP [MIN] + tCK [AVG] MIN).
37. This parameter has a two clock minimum requirement at any tCK.
38. The tFAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four bank-ACTIVATE
commands may be issued in a given tFAW (MIN) period. tRRD (MIN) restriction still applies.
39. The minimum internal READ-to-PRECHARGE time. This is the time from which the last 4-bit prefetch
begins to when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command
internally latches the READ so that data will output CL later. This parameter is only applicable when tRTP/
(2 × tCK) > 1, such as frequencies faster than 533 MHz when tRTP = 7.5ns. If tRTP/(2 × tCK) ≤ 1, then
equation AL + BL/2 applies. tRAS (MIN) has to be satisfied as well. The DDR2 SDRAM will automatically
delay the internal PRECHARGE command until tRAS (MIN) has been satisfied.
40. tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be rounded up to the next
integer. tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR9–
MR11. For example, -37E at tCK = 3.75ns with tWR programmed to four clocks would have tDAL = 4 +
(15ns/3.75ns) clocks = 4 + (4) clocks = 8 clocks.
41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This equates to an average
refresh rate of 7.8125μs (commercial) or 3.9607μs (industrial and automotive). To ensure all rows of all
banks are properly refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) or
32ms (industrial and automotive). The JEDEC tRFC MAX of 70,000ns is not required as bursting of AUTO
REFRESH commands is allowed.
42. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK#
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
45
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
being removed in a system RESET condition.
43. tISXR is equal to tIS and is used for CKE setup time during self refresh exit.
44. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock edges.
CKE must remain at the valid input level the entire time it takes to achieve the three clocks of registration.
Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2
× tCK + tIH.
45. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value must be
derated by the amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53,
tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 + 0.03, or 2.53, for tAOF (MAX).
46. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance begins to turn on.
ODT turnon time tAON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND.
47. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF
(MAX) is when the bus is in High-Z. Both are measured from tAOFD.
48. Half-clock output parameters must be derated by the actual tERR5per and tJITdty when input clock jitter
is present; this will result in each parameter becoming larger. The parameter tAOF (MIN) is required to be
derated by subtracting both tERR5per (MAX) and tJITdty (MAX). The parameter tAOF (MAX) is required to
be derated by subtracting both tERR5per (MIN) and tJITdty (MIN).
49. The -187E maximum limit is 2 × tCK + tAC (MAX) + 1000 but it will likely be 3 x tCK + tAC (MAX) + 1000 in
the future.
50. Should use 8 tCK for backward compatibility.
51. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a
particular row address may result in reduction of the product lifetime.
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
46
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
1Gb: MYX4DDR264M16HW*
x4, x8, x16 DDR2 SDRAM
Packaging
*Advanced information. Subject to change without notice.
Packaging
10
Package
Package Dimensions
Figure
17: 84-Ball
FBGA
Package
(8mm x –12.5mm)
x16;:H
"NF" Die Rev :M
Figure 8: 84-Ball
FBGA
Package
(8mm
x 12.5mm)
x16 Die–Rev
0.155
Seating plane
A
1.8 CTR
Nonconductive
overmold
84X Ø0.45
Dimensions apply
to solder balls
post-reflow on
Ø0.35 SMD ball pads.
9 8 7
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
11.2 CTR
0.8 TYP
1.1 ±0.1
0.8 TYP
0.25 MIN
6.4 CTR
Exposed gold plated pad
1.0 MAX X 0.7 nominal.
8 ±0.1
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
Ball A1 ID
Ball A1 ID
12.5 ±0.1
Notes:
0.12 A
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or leaded Eutectic (62% Sn,
36%Pb, 2% Ag).
47
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 005
1Gb: x4, x8, x16 DDR2 SDRAM
Packaging
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
Packaging
Package Dimensions
*Advanced information. Subject to change without notice.
Figure
18: 84-Ball
FBGA
Package
(8mm x –12.5mm)
x16 :H
Die "HR" Rev :H
Figure 8: 84-Ball
FBGA
Package
(8mm
x 12.5mm)
x16 Die–Rev
0.155
Seating plane
A
1.8 CTR
Nonconductive
overmold
84X Ø0.45
Dimensions apply
to solder balls
post-reflow on
Ø0.35 SMD ball pads.
Ball A1 ID
Ball A1 ID
9 8 7
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
12.5 ±0.1
11.2 CTR
0.8 TYP
1.1 ±0.1
0.8 TYP
0.25 MIN
6.4 CTR
Exposed gold plated pad
1.0 MAX X 0.7 nominal.
8 ±0.1
Notes:
0.12 A
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or leaded Eutectic (62% Sn,
36%Pb, 2% Ag).
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
18
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
48
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
11
Ordering Information
Table 23: Ordering Information
Part Number
Data Rate (Mbps)
MYX4DDR264M16HWBG-25EIT
Device Grade
Industrial
800
MYX4DDR264M16HWBG-25EXT
Military
Please contact a Micross sales representative for IBIS or thermal models at [email protected].
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
49
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
Document Title
64M16 DDR2 SDRAM - 84-Ball FBGA Package (8mm x 12.5mm) – x16
Revision History
Revision #
History
Release Date
Status
1.0
Initial Release
November 2014
Preliminary
1.1
Page 37 – Replaced Figure 13: 84-Ball FBGA Package (8mm x 12.5mm) – x16 Die Rev :H
December 2014
Preliminary
1.2
Page 1 – Changed Options: 1.875ns @ CL = 7 (DDR2-1066); Code:-187E to Options: 2.5ns @
CL = 5 (DDR2-800); Code:-25E
February 2, 2015
Preliminary
July 13, 2015
Preliminary
Page 1, Table 1 – Deleted row for -187E; replaced with -25E
Page 32, Table 12 – Deleted column for -187E; replaced with column for -25E
Page 33, Table 13 – Deleted column for -187E; replaced with column for -25E
Page 33, Table 13 – Deleted row for “CL = 7” under AC Characteristics > Parameter > Clock
cycle time
Page 38, Table 14 – Changed Part Number: MYX4DDR264M16HWBG-187EIT; Data Rate: 1066
to Part Number: MYX4DDR264M16HWBG-25EIT; Data Rate: 800
Page 38, Table 14 – Changed Part Number: MYX4DDR264M16HWBG-187E; Data Rate: 1066
to Part Number: MYX4DDR264M16HWBG-25E; Data Rate: 800
1.3
Page 1
• Changed "84-ball FBGA (8mm x 12.5mm) ... HW" to
• "84-ball FBGA (8mm x 12.5mm) Die Rev: H ... HR" under Options.
• Added "84-ball FBGA (8mm x 12.5mm) Die Rev:M ... NF" under Options.
• Removed " Industrial temperature (IT) option" under Features
• Added Military temp. under Options > Operating Temperature
• Added "AEC-Q100 (MIL version)" under Features
• Added "PPAP submission (MIL version)" under Features
• Added "8D response time" under Features
Page 6
• Removed "NF - No function" row from Table 3
Page 7
• Added section 3.2 - Enhanced Temperature
Page 29 - 34
• Added sections for "ODT DC Electrical Characteristics", "Input Electrical Characteristics
and Operating Conditions", "Output Electrical Characteristics and Operating Conditions"
Page 34
• Revised section for "Temperature and Thermal Impedance"
Page 36
• Added "4" in "Notes" column of "Input capacitance" row
• Changed "1, 4" to "1, 5" in "Notes" column of "Input/output capacitance" row
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
50
Form #: CSI-D-685 Document 005
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
1.3 (continued)
• Changed Table 18, Note 4 from "Reduce MAX limit by 0.25pF for speed devices" to
"Reduce MAX limit by 0.25pF for -25, -25E, and -187E speed devices".
• Added Note 5 to Table 18.
July 13, 2015
Preliminary
Page 37
• Added sections for "IDD Specifications and Conditions" and "IDD7 Conditions"
Page 38
• Table 21, Column "-25E", Row "Precharge power-down current": changed "7" to "7 (Rev
H) | 10 (Rev M)"
• Table 21, Column "-25E", Row "Active power-down current": changed "20" to "20 (Rev H)
| 30 (Rev M)" and "10" to "10 (Rev H) | 20 (Rev M)"
• Table 21, Column "-25E", Row "Active standby current": changed "35" to "35 (Rev H) | 38
(Rev M)"
• Table 21, Column "-25E", Row " Burst refresh current": changed "150" to "150 (Rev H) |
160 (Rev M)"
Page 42
• Added notes to Table 22
Page 47
• Added Figure 17: 84-Ball FBGA Package (8mm x 12.5mm) – x16; "NF" Die Rev :M
Page 48
• Added "HR" to title of Figure 18
Page 49
• Added military part number
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Revision 1.4 - 03/29/2016
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Form #: CSI-D-685 Document 005