IDT7130SA/LA IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM Integrated Device Technology, Inc. FEATURES DESCRIPTION • High-speed access —Military: 25/35/55/100ns (max.) —Commercial: 25/35/55/100ns (max.) —Commercial: 20ns 7130 in PLCC and TQFP • Low-power operation —IDT7130/IDT7140SA —Active: 550mW (typ.) —Standby: 5mW (typ.) —IDT7130/IDT7140LA —Active: 550mW (typ.) —Standby: 1mW (typ.) • MASTER IDT7130 easily expands data bus width to 16-or-more-bits using SLAVE IDT7140 • On-chip port arbitration logic (IDT7130 Only) • BUSY output flag on IDT7130; BUSY input on IDT7140 • Interrupt flags for port-to-port communication • Fully asynchronous operation from either port • Battery backup operation–2V data retention (LA only) • TTL-compatible, single 5V ±10% power supply • Military product compliant to MIL-STD-883, Class B • Standard Military Drawing #5962-86875 • Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" DualPort RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-more-bit memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 550mW of power. Low-power (LA) versions offer battery backup data retention capability, with each Dual-Port typically consuming 200µW from a 2V battery. The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC, and 64-pin TQFP and STQFP. Military grade product is manufactured in compliance with the latest revision of MILSTD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM OER OEL CEL R/WL CER R/WR I/O0L- I/O7L I/O Control I/O0R-I/O7R I/O Control (1,2) BUSYR BUSYL A9L A0L Address Decoder MEMORY ARRAY 10 NOTES: 1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω. IDT7140 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270Ω. Address Decoder A9R A0R 10 ARBITRATION and INTERRUPT LOGIC CEL OEL R/WL CER OER R/WR INTL (2) INTR The IDT logo is a registered trademark of Integrated Device Technology, Inc. (2) 2689 drw 01 MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. (1,2) For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. 6.01 OCTOBER 1996 DSC-2689/7 1 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES BUSYR 7 6 INTR A1L OER A2L A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R 5 4 3 2 8 9 INTR N/C WR BUSYR CER R/ VCC CEL WL BUSYL R/ INTL INDEX 52 51 50 49 48 47 1 46 45 OER 44 43 A1R A0R A4L 10 11 A5L A6L 12 13 IDT7130/40 J52-1 42 41 A3R A4R A7L 14 15 52-PIN PLCC TOP VIEW (3) 40 39 A5R 16 17 38 37 A7R 18 19 20 36 35 34 A9R A3L A8L A9L I/O0L I/O1L I/O2L I/O3L A2R A6R A8R N/C I/O7R 21 22 23 24 25 26 27 28 29 30 31 32 33 2689 drw 04 I/O6R A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND WR R/ I/O4R I/O5R OEL CER GND I/O0R I/O1R I/O2R I/O3R INTL VCC N/C BUSYL 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 IDT7130/ 41 9 IDT7140 40 10 P48-1 39 & 11 C48-2 38 12 37 13 DIP 36 TOP 14 VIEW 35 (3) 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 A0L WL I/O4L I/O5L I/O6L I/O7L N/C CEL R/ OEL PIN CONFIGURATIONS (1,2) N/C N/C N/C INTR BUSYR WR CER R/ VCC VCC CE L WL R/ INTL BUSYL N/C N/C N/C A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R 2689 drw 03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IDT7130/40 PP64-1 & PN64-1 64-PIN STQFP 64-PIN TQFP TOP VIEW (3) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 OEL A0R 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 INDEX 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 I/O3L N/C I/O4L I/O5L I/O6L I/O7L N/C GND GND I/O0R I/O1R I/O2R I/O3R N/C I/O4R I/O5R INTR OER WR BUSYR CER R/ VCC R/ CEL WL BUSYL INTL 6 5 4 3 2 48 47 46 45 44 43 1 7 42 8 41 9 40 10 39 IDT7130/40 L48-1 11 38 & 12 37 F48-1 13 36 48-PIN LCC/ FLATPACK 14 35 TOP VIEW (3) 15 34 16 33 17 32 18 31 19 20 21 22 23 24 25 26 27 28 29 30 I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L A0L INDEX OEL 2689 drw 02 OER A0R A1R A2R A3R A4R A5R A6R N/C A7R A8R A9R N/C N/C I/O7R I/O6R 2689 drw 05 NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of the actual part-marking. 6.01 2 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating VTERM(2) Terminal Voltage with Respect to GND Operating TA Temperature Temperature TBIAS Under Bias Storage TSTG Temperature IOUT Commercial Military Unit –0.5 to +7.0 –0.5 to +7.0 V 0 to +70 –55 to +125 °C –55 to +125 –65 to +135 –65 to +150 °C 50 50 mA Symbol VCC GND Parameter Supply Voltage Supply Voltage VIH Input High Voltage VIL °C –55 to +125 DC Output Current RECOMMENDED DC OPERATING CONDITIONS Min. 4.5 0 Typ. 5.0 0 Max. 5.5 0 Unit V V 2.2 — 6.0(2) V — 0.8 V (1) Input Low Voltage –0.5 NOTES: 1. VIL (min.) > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V. 2689 tbl 02 2689 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Military Commercial Ambient Temperature –55°C to +125°C 0°C to +70°C GND 0V 0V VCC 5.0V ± 10% 5.0V ± 10% 2689 tbl 03 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%) 7130SA Symbol Parameter 7130LA 7140SA Min. Max. Test Conditions 7140LA Max. Max. Unit |lLl| Input Leakage Current(1) VCC = 5.5V, VIN = 0V to VCCIN = GND to VCC — 10 — 5 µA |lLO| Output Leakage Current(1) VCC = 5.5V, CE = VIH, VOUT = 0V to VCCC — 10 — 5 µA VOL Output Low Voltage (l/O0-l/O7) lOL = 4mA lOL= 16mA — 0.4 — 0.4 V VOL Open Drain Output Low Voltage (BUSY, INT) lOL = 16mA — 0.5 — 0.5 V VOH Output High Voltage lOH = -4mA 2.4 — 2.4 — V NOTE: 1. At Vcc < 2.0V leakages are undefined. 2689 tbl 04 CAPACITANCE(1) (TA = +25°C, f = 1.0MHz) TQFP ONLY(3) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VIN = 3dV Max. Unit 9 pF 10 pF 2689 tbl 05 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 3. 11pF max. for other packages. 6.01 3 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (VCC = 5.0V ± 10%) Symbol Parameter ICC Dynamic Operating Current (Both Ports Active) CEL and CER = VIL, MIL. SA Outputs open, LA COM'L. SA f = fMAX(4) LA — — 110 280 — — 110 220 110 250 110 220 110 200 110 170 110 230 110 170 110 165 110 120 110 110 110 110 190 140 155 110 110 110 110 110 190 140 155 110 mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and CER = VIH, MIL. SA f = fMAX(4) LA COM'L. SA LA — — 30 30 — — 65 45 30 30 30 30 80 60 65 45 25 25 25 25 80 60 65 45 20 20 20 20 65 45 65 35 20 20 20 20 65 45 55 35 mA ISB2 Standby Current (One Port - TTL Level Inputs) MIL. — — 65 65 — — 165 125 65 65 65 65 160 125 150 115 50 50 50 50 150 115 125 90 40 125 40 90 40 110 40 75 40 40 40 40 125 90 110 75 mA ISB3 Full Standby Current (Both Ports - All CMOS Level Inputs MIL. SA LA COM'L. SA LA — — 1.0 0.2 — — 15 5 1.0 0.2 1.0 0.2 30 10 15 5 1.0 0.2 1.0 0.2 30 10 15 4 1.0 0.2 1.0 0.2 30 10 15 4 1.0 0.2 1.0 0.2 30 10 15 4 mA MIL. — — 60 60 — — 155 115 60 60 60 60 155 115 145 105 45 45 45 45 145 105 110 85 40 110 40 85 40 100 40 70 40 40 40 40 110 80 95 70 mA ISB4 Full Standby Current (One Port - All CMOS Level Inputs) Test Conditions Version 7130X20(2) 7130X25(3) 7130X35 7130X55 7130X100 7140X25(3) 7140X35 7140X55 7140X100 Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit CE"A" = VIL and CE"B" = VIH (7) SA LA Active Port Outputs COM'L. SA LA Open, f = fMAX(4) CEL and CER > VCC -0.2V, VIN > VCC -0.2V or VIN < 0.2V,f = 0(5) CE"A" < 0.2V and CE"B" > VCC -0.2V(7) VIN > VCC -0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX(4) SA LA COM'L. SA LA NOTES: 2689 tbl 06 1. 'X' in part numbers indicates power rating (SA or LA). 2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages. 3. Not available in DIP packages. 4. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels of GND to 3V. 5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 6. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ.) 7. Port "A" may be either left or right port. Port "B" is opposite from port "A". DATA RETENTION CHARACTERISTICS (LA Version Only) Symbol VDR VCC for Data Retention ICCDR Data Retention Current tCDR(3) Chip Deselect to Data Retention Time tR(3) lDT7130LA/IDT7140LA Min. Typ.(1) Max. Test Conditions Parameter VCC = 2.0V, CE > VCC -0.2V VIN > VCC -0.2V or VIN < 0.2V 2.0 — — V Mil. — 100 4000 µA Com’l. — 100 1500 µA 0 — — ns — — ns tRC(2) Operation Recovery Unit Time 2689 tbl 07 NOTES: 1. VCC = 2V, TA = +25°C, and is not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not production tested. 6.01 4 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES DATA RETENTION WAVEFORM DATA RETENTION MODE VCC VDR ≥ 2.0V 4.5V tCDR 4.5V tR VDR CE VIH VIH 2692 drw 06 AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1, 2, and 3 2689 tbl 08 5V 5V 1250Ω 1250Ω DATA OUT DATA OUT 775Ω 30pF* 775Ω 5pF* (*100pF for 55 and 100ns versions) Figure 1. Output Test Load Figure 2. Output Test Load (for tHZ, tLZ, tWZ, and tOW) * including scope and jig 5V 270Ω BUSY or INT 30pF* *100pF for 55 and 100ns versions 2689 drw 07 Figure 3. BUSY and INT AC Output Test Load 6.01 5 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3) Symbol 7130X20(2) 7130X25(5) 7130X35 7130X55 7130X100 7140X25(5) 7140X35 7140X55 7140X100 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Parameter Read Cycle tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold From Address Change Output Low-Z Time(1,4) Output High-Z Time(1,4) Chip Enable to Power Up Time(4) Chip Disable to Power Down Time(4) 20 — — 3 0 — 0 — — 20 20 11 — — 10 — 20 25 — — — 3 0 — 0 — — 25 25 12 — — 10 — 25 35 — — — 3 0 — 0 — — 35 35 20 — — 15 — 35 NOTES: 1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2). 2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP package. 3. “X” in part numbers indicates power rating (SA or LA). 4. This parameter is guaranteed by device characterization, but is not production tested. 5. Not available in DIP packages. 55 — — — 3 5 — 0 — — 55 55 25 — — 25 — 50 100 — — — 10 5 — 0 — — 100 100 40 — — 40 — 50 ns ns ns ns ns ns ns ns ns 2689 tbl 09 TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1) tRC ADDRESS tAA tOH tOH DATAOUT PREVIOUS DATA VALID DATA VALID BUSYOUT tBDD (2,3) 2689 drw 08 NOTES: 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations, BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. 6.01 6 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(3) tACE tAOE tLZ (4) tHZ (1) tHZ (2) VALID DATA DATAOUT tLZ ICC CURRENT ISS (2) (1) tPD tPU (4) 50% 50% 2689 drw 09 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. R/W = VIH and the address is valid prior to or coincidental with CE transition Low. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5) 7130X20(2) 7130X25(6) (6) Symbol Parameter Write Cycle Write Cycle Time(3) tWC tEW Chip Enable to End-of-Write Address Valid to End-of-Write tAW tAS Address Set-up Time Write Pulse Width(4) tWP tWR Write Recovery Time Data Valid to End-of-Write tDW tHZ Output High-Z Time(1) Data Hold Time tDH tWZ Write Enabled to Output in High-Z(1) Output Active From End-of-Write(1) tOW Min. 20 15 15 0 15 0 10 — 0 — 0 Max. — — — — — — — 10 — 10 — 7140X25 Min. Max. 25 20 20 0 15 0 12 — 0 — 0 — — — — — — — 10 — 10 — 7130X35 7130X55 7140X35 7140X55 Min. Max. Min. Max. 35 30 30 0 25 0 15 — 0 — 0 — — — — — — — 15 — 15 — 55 40 40 0 30 0 20 — 0 — 0 — — — — — — — 25 — 25 — 7130X100 7140X100 Min. Max. 100 90 90 0 55 0 40 — 0 — 0 — — — — — — — 40 — 40 — Unit ns ns ns ns ns ns ns ns ns ns ns NOTES: 2689 tbl 10 1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. 0°C to +70°C temperature range only, PLCC and TQFP packages. 3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA. 4. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 5. “X” in part numbers indicates power rating (SA or LA). 6. Not available in DIP packages. 6.01 7 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/W CONTROLLED TIMING)(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE tWP(2) tAS(6) tWR (7) (3) tHZ W R/ tWZ (7) DATA OUT tOW (4) (4) tDW tDH DATA IN 2689 drw 10 TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CE CONTROLLED TIMING)(1,5) tWC ADDRESS tAW CE tAS(6) (3) tEW (2) tWR W R/ tDW tDH DATA IN 2689 drw 11 NOTES: 1. R/W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 6.01 8 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)8M824S258M824S30 Symbol Parameter 7130X20(1) 7130X25(9) Min. Max. 7140X25(9) 7140X35 Min. Max. Min. Max. 7130X35 7130X55 7132158M824S4 7130X100 7140X55 7140X100 Min. Max. Min. Max. Unit Busy Timing (For Master lDT7130 Only) BUSY Access Time from Address tBAA — 20 — 20 — 20 — 30 — 50 ns tBDA tBAC — — 20 20 — — 20 20 — — 20 20 — — 30 30 — — 50 50 ns ns — 20 — 20 — 20 — 30 — 50 ns BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Hold After BUSY(6) tBDC tWH tWDD Write Pulse to Data Delay(2) 12 — — 40 15 — — 50 20 — — 60 20 — — 80 20 — — 120 ns ns tDDD tAPS Write Data Valid to Read Data Delay(2) Arbitration Priority Set-up Time(3) — 5 30 — — 5 35 — — 5 35 — — 5 55 — — 5 100 — ns ns — 5 25 — — 5 35 — — 5 35 — — 5 50 — — 5 65 ns tBDD BUSY Disable to Valid Data(4) Busy Timing (For Slave IDT7140 Only)e Write to BUSY Input(5) 0 — 0 — 0 — 0 — 0 — ns tWH tWDD Write Hold After BUSY(6) Write Pulse to Data Delay(2) 12 — — 40 15 — — 50 20 — — 60 20 — — 80 20 — — 120 ns ns tDDD Write Data Valid to Read Data Delay(2) — 30 — 35 — 35 — 55 — 100 ns tWB NOTES: 2689 tbl 11 1. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages only. 2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY." 3. To ensure that the earlier of the two ports wins. 4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual). 5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'. 6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'. 7. “X” in part numbers indicates power rating (SA or LA). 8. Not available in DIP packages. TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,3,4) tWC ADDR’A’ MATCH tWP W’A’ R/ tDW DATAIN’A’ tDH VALID tAPS (1) ADDR’B’ MATCH tBDD t BDA BUSY’B’ tWDD DATAOUT’B’ VALID tDDD NOTES: 1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". 6.01 2689 drw 12 9 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE WITH BUSY(3) tWP W R/ 'A' tWB BUSY'B' tWH(1) W R/ 'B' (2) 2689 drw 13 NOTES: 1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High. 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (1) ADDR 'A' ADDRESSES MATCH AND 'B' CE'B' tAPS (2) CE'A' tBAC tBDC BUSY'A' 2689 drw 14 TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1) tRC OR tWC ADDR'A' ADDRESSES MATCH ADDRESSES DO NOT MATCH (2) tAPS ADDR'B' tBAA tBDA BUSY'B' 2689 drw 15 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only). 6.01 10 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2) 7130X20(1) Symbol Parameter Interrupt Timing Address Set-up Time tAS tWR Write Recovery Time Interrupt Set Time tINS tINR Interrupt Reset Time Min. Max. 0 0 — — — — 20 20 7130X25(3) 7140X25(3) Min. Max. 0 0 — — 7130X35 7140X35 Min. Max. — — 25 25 0 0 — — — — 25 25 8M824S25 7130X55 7140X55 Min. Max. 0 0 — — — — 45 45 8M824S308M824S35 7130X100 7140X100 Min. Max. Unit 0 0 — — — — 60 60 ns ns ns ns 2689 tbl 12 NOTES: 1. 0°C to +70°C temperature range only, PLCC and TQFP packages. 2. “X” in part numbers indicates power rating (SA or LA). 3. Not available in DIP packages . TIMING WAVEFORM OF INTERRUPT MODE INT SET: tWC ADDR'A' INTERRUPT ADDRESS (2) (4) tAS (3) tWR W'A' R/ tINS (3) INT'B' INT CLEAR: 2689 drw 16 tRC ADDR'B' INTERRUPT CLEAR ADDRESS tAS (3) OE'B' tINR (3) INT'B' 2689 drw 17 NOTES:. 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 6.01 11 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES TRUTH TABLES TABLE I — NON-CONTENTION READ/WRITE CONTROL(4) Left or Right Port(1) CE OE R/ D0–7 X H X Z W X H X Z L H H L L L X L H DATAIN DATAOUT Z Function Port Disabled and in PowerDown Mode, ISB2 or ISB4 CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3 Data on Port Written Into Memory(2) Data in Memory Output on Port(3) High Impedance Outputs NOTES: 2689 tbl 13 1. A0L – A10L ≠ A0R – A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE TABLE II — INTERRUPT FLAG(1,4) R/WL L X X X CEL Left Port OEL L X X L X X X L INTL A9L – A0L 3FF X X 3FE X X L(3) H(2) R/WR X X L X Right Port CER OER X L L X X L X X NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE A9L – A0R X 3FF 3FE X INTR L(2) H(3) X X Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag 2689 tbl 14 TABLE III — ADDRESS BUSY ARBITRATION Inputs CEL CER A0L-A9L A0R-A9R Outputs BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) NOTES: 2689 tbl 15 1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain, not push-pull outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can not be low simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving Low regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving Low regardless of actual logic level on the pin. 6.01 12 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES The IDT7130/IDT7140 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7130/ IDT7140 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. INTERRUPTS If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 3FE (HEX), where a write is defined as the CE = R/W = VIL per the Truth Table. The left port clears the interrupt by access address location 3FE access when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 3FF. The message (8 bits) at 3FE or 3FF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 3FE and 3FF are not used as mail boxes, but as part of the random access memory. Refer to Table II for the interrupt operation. The Busy outputs on the IDT7130 RAM (Master) are open drain type outputs and require open drain resistors to operate. If these RAMs are being expanded in depth, then the Busy indication for the resulting array does not require the use of an external AND gate. WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS When expanding an RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT7130/IDT7140 RAMs the Busy pin is an output if the part is Master (IDT7130), and the Busy pin is an input if the part is a Slave (IDT7140) as shown in Figure 4. 5V 270Ω MASTER Dual Port RAM BUSY (L) BUSYL BUSY LOGIC Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The Busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. In slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins High. If desired, unintended write operations can be prevented to a port by tying the Busy pin for that port Low. 6.01 MASTER Dual Port RAM BUSY (L) CE BUSY (R) CE BUSY (R) SLAVE Dual Port RAM BUSY (L) SLAVE Dual Port RAM BUSY (L) CE BUSY (R) DECODER FUNCTIONAL DESCRIPTION 5V 270Ω CE BUSY (R) BUSYR 2689 drw 18 Figure 4. Busy and chip enable routing for both width and depth expansion with IDT7130 (Master) and IDT7140 (Slave) RAMs. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The Busy arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. 13 IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXX A Device Type Power 999 Speed A Package A Process/ Temperature Range Blank B Commercial (0°C to +70°C) Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B P C J L48 F PF TF 48-pin Plastic DIP (P48-1) 48-pin Sidebraze DIP (C48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) 64-pin TQFP (PN64-1) 64-pin STQFP (PP64-1) 20 25 35 55 100 Commercial PLCC and TQFP Only LCC, PLCC, and TQFP Only LA SA Low Power Standard Power 7130 7140 8K (1K x 8-Bit) MASTER Dual-Port RAM 8K (1K x 8-Bit) SLAVE Dual-Port RAM Speed in nanoseconds 2689 drw 19 6.01 14