AN232
AK5393 to CS5361/81 Conversion
by Kevin L Tretter
1. Introduction
The CS5361 and CS5381 are complete analog-to-digital converters for digital audio systems. They perform sampling, analog-to-digital conversion and anti-alias filtering, generating 24-bit values for both left
and right channels.
The CS5361 and CS5381 offer some unique advantages over the AK5393 including:
-
Over 70% REDUCTION in package size (TSSOP)
-
50% less power consumption
-
192kHz sampling capability
-
Overflow detect
-
Integrated level shifters
-
Over 65% less group delay (48kHz output sample rate)
-
External components consume less board space (See Section 2)
Table 1 shows a comparison of the key specifications of these three devices.
AK5393
Conversion (Bits)
24
Dynamic Range (A-weighted)
dB
117
THD+N
dB
-105
Analog Core Power Supply (VA)
V
+5.0 V
Digital Core Power Supply (VD)
+3.3 V to +5.0 V
Digital Interface Power Supply (VL)
N/A
Maximum Power
mW
680
Maximum Sample Rate
kHz
108
Package
28-pin SOP
CS5361
24
114
-105
+5.0 V
+3.3 V to +5.0 V
+2.5 V to +5.0 V
161
200
24-pin SOIC/TSSOP
CS5381
24
120
-110
+5.0 V
+3.3 V to +5.0 V
+2.5 V to +5.0 V
348
200
24-pin SOIC/TSSOP
Table 1. Comparison of Key Specifications
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
JUL ‘03
AN232REV1
1
AN232
2. Typical Connection Diagrams
+5 V to 3.3 V
+5V
+
1 µF
0.01 µF
0.01 µF
*
+
1 µF
+5V to 2.5V
1 µF
0.01 µF
5.1 Ω
0.01 µF
+
VD
VA
VL
FILT+
+
47 µF
VL
0.01 µF
REFGND
1 µF
+
10 kΩ
0.01 µF
OVFL
RST
I2S/LJ
M/ S
HPF
M0
M1
MDIV
VQ
AINL+
Analog
Input
Buffer
(Section 8)
CS5361
A/D CONVERTER
Power Down
and Mode
Settings
AINLAudio Data
Processor
SDOUT
LRCK
AINR+
Analog
Input
Buffer
(Section 8)
Timing Logic
and Clock
SCLK
MCLK
AINR-
GND
GND
* Resistor may only be
used if VD is derived
from VA. If used, do
not drive any other
logic from VD
Figure 1. CS5361 Typical Connection Diagram
+5 V to 3.3 V
+5V
+
1 µF
0.1 µF
0.1 µF
*
+
1 µF
0.1 µF
VA
200 µF
VD
VL
VL
0.1 µF
10 k
REFGND
+
1 µF
0.1 µF
VQ
Analog
Input
Buffer
(Section 8)
+5V to 2.5V
1 µF
0.1 µF
5.1 Ω
FILT+
+
+
AINL+
CS5381
A/D CONVERTER
OVFL
RST
I2S/LJ
M/S
HPF
M0
M1
MDIV
Power Down
and Mode
Settings
AINLSDOUT
Analog
Input
Buffer
(Section 8)
AINR+
Audio Data
Processor
LRCK
SCLK
MCLK
Timing Logic
and Clock
AINR* Resistor may only
GND
GND
be used if VD is
derived from VA. If
used, do not drive
any other logic
from VD.
Figure 2. CS5381 Typical Connection Diagram
2
AN232
+5V
+
10µF
0.1µF
0.1µF
10 µF
+5V to 3.3V
10µF
VD
VA
VREFL
+
+
0.1 µF
GNDL
0.22 µF
ZCAL
RST
CAL
VCOML
AINL+
Analog
Input
Buffer
(Section 8)
AK5393
A/D CONVERTER
HPFE
SMODE2
SMODE1
DFS
Reset and
Calibration
Control
Mode
Control
AINLSDATA
AINR+
Analog
Input
Buffer
(Section 8)
Audio Data
Processor
LRCK
SCLK
MCLK
Timing Logic
and Clock
FSYNC
AINR-
VREFR
10 µF
+
0.1µF
GNDR
0.22 µF
VCOMR
AGND
BGND
TEST
DGND
Figure 3. AK5393 Typical Connection Diagram
3
AN232
3. Pin Compatibility
Table 2 shows the pins of the AK5393 and the corresponding pins of the CS5361/81. Please note that the
AK5393 has 28 pins, and the CS5361/81 has 24 pins.
AK5393
Pin Number
1, 28
2, 27
3, 26
4
5
6
7
8
9
10
Pin Name
VREFL, VREFR
GNDL, GNDR
VCOML, VCOMR
AINL+
AINLZCAL
VD
DGND
CAL
CS5361/81
Pin Number
24
23
22
16
17
6
7
-
Pin Name
FILT+
REFGND
VQ
AINL+
AINLVD
GND
-
Description
1
RST
11
RST
SMODE2
12
I2S/LJ
12
13
14
15
16
17
18
19
SMODE1
LRCK
SCLK
SDATA
FSYNC
MCLK
DFS
HPFE
2
3
4
9
5
13
11
M/S
LRCK
SCLK
SDOUT
MCLK
M0
20
21
22
23
24
25
TEST
BGND
AGND
VA
AINRAINR+
18
19
20
21
14
8
10
15
HPF
GND
VA
AINRAINR+
M1
VL
MDIV
OVFL
Positive reference voltage
Ground reference
Internal quiescent reference voltage
Differential Left Channel Input
Differential Left Channel Input
Zero Calibration Control
Digital power
Ground reference
Calibration Active Signal
Reset
Serial Audio Interface Format Select
Master/Slave Mode Select
Left right clock
Serial clock
Serial data
Frame Synchronization Signal
Master clock
Mode Selection
High Pass Filter Enable
Test
Substrate Ground
Ground reference
Analog power
Differential Right Channel Input
Differential Right Channel Input
Mode Selection
Logic Power
MCLK divider
Overflow
Table 2. Pin Compatibility Between AK5393 and CS5361/81
4. Offset Calibration
The CS5361, CS5381, and AK5393 all have offset calibration capability. However, the calibration process
varies slightly between the AK5393 and the CS5361/CS5381.
4.1 CS5361 and CS5381
The CS5361 and CS5381 implement a high pass filter that can be controlled via the HPF pin (pin 11). The
high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter.
If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen
and this DC offset will continue to be subtracted from the conversion result.
4
AN232
A system calibration can then be performed by first running the CS5361 or CS5381 with the high pass
filter enabled (HPF = LOW) until the filter settles. At this point, disable the high pass filter (HPF = HI),
thereby freezing the stored DC offset.
4.2 AK5393
The AK5393 will automatically initiate a calibration sequence following a reset. The CAL pin (pin 9) is an
output that indicates when a calibration sequence is in progress. This calibration technique is very similar
to that described above for the CS5361 and CS5381.
The AK5393 also has a ZCAL pin (pin 6) which allows the calibration input to be obtained from either the
analog input pins or the VCOM pins. The high pass filter can be controlled via the HPFE pin (pin 19). In
the AK5393, the high pass filter is either continuously running or completely removed from the signal path.
5. Master/Slave Selection and Digital Interface Format
The CS5361, CS5381, and AK5393 are pin compatible in terms of selecting Master/Slave operation and
digitial interface format. The pins match up as noted in Table 2.
6. Speed Mode Selection
The AK5393 supports two speed modes, “normal” and “double” as determined by the DFS pin (pin 18).
This pin is compatible with the M0 pin (pin 13) of the CS5361 and CS5381, as shown in Table 2. In this
case, the M1 pin (pin 14) of the CS5361 and CS5381 must be tied low.
7. System Clocking
The CS5361 and CS5381 are fully compatible with the clocking requirements of the AK5393. However,
there is a slight difference when operating in Master mode. If DFS = LOW, the AK5393 will generate an
SCLK that is 128×Fs. The CS5361 and CS5381 generate an SCLK that is 64×Fs.
The CS5361 and CS5381 offer an integrated MCLK divider, which can be controlled via the MDIV pin (pin
10). This pin allows multiple external MCLK/LRCK ratios to be supported. In order to maintain complete
compatibility between the AK5393 and the CS5361/CS5381, connect the MDIV pin (pin 10) of the
CS5361/CS5381 to GND.
8. Input Buffer Topology
The analog input buffers shown in Figures 7 and 8 of the AK5393 datasheet (dated April, 2000) will also
work for the CS5361/81. In this case, the “Bias” reference should be sourced from the VQ pin of the
CS5361/81. However, these input buffers require a large input voltage level at the input to the buffer and
attenuate the signal prior to the converter. This much signal swing is not always possible in a real system,
and not necessary to achieve the full performance of the CS5361 and CS5381.
The following sections contain a description of a single-ended to differential input buffer (comparable to
Figure 7 of the AK5393 datasheet) and a fully differential input buffer (comparable to Figure 8 of the
AK5393 datasheet). These two buffer topologies are unity gain, and therefore do not rely on a large input
voltage at the buffer input.
8.1 Single-Ended to Differential Input Buffer
Figure 4 shows a single-ended to differential analog input buffer. This buffer provides the proper biasing,
isolation from the switched capacitor currents, low output impedance, and anti-alias filtering. The second
op-amp stage is set up in an inverting configuration to produce the negative node of the differential input.
In the input buffer shown below, the second stage has unity gain, and the single-ended input level will
effectively be doubled when presented differentially to the converter. For example, a 2.8 Vpp single-ended input will provide a full-scale 5.6 Vpp differential input to the CS5361/CS5381.
5
AN232
634 Ω
470 pF
C0G
CS5361/81
91 Ω
-
1 µF
AIN+
+
634 Ω
634 Ω
100 kΩ
VA
2700 pF
C0G
470 pF
C0G
100 kΩ
3.3 kΩ
91 Ω
-
AIN-
+
3.3 kΩ
0.01 µF
100 µF
1 µF
0.01 µF
VQ
634 Ω
470 pF
C0G
91 Ω
-
1 µF
+
AIN+
634 Ω
634 Ω
100 kΩ
VA
2700 pF
C0G
470 pF
C0G
100 kΩ
3.3 kΩ
91 Ω
-
AIN-
+
0.01 µF
3.3 kΩ
100 µF
Figure 4. Single-Ended to Differential Input Buffer
8.2 Fully Differential Input Buffer
Figure 5 shows a fully differential analog input buffer. This buffer provides the proper biasing, isolation
from the switched capacitor currents, low output impedance, and anti-alias filtering. This input buffer is
unity gain, so a 5.6 Vpp differential input will provide a full-scale 5.6 Vpp differential input into the
CS5361/CS5381.
634 Ω
470 pF
C0G
10 µF
100 kΩ
CS5361/81
91 Ω
634 Ω
10 kΩ
2700 pF
C0G
470 pF
10 kΩ
100 kΩ
AIN+
+
0.01 µF
-
C0G
91 Ω
AIN-
+
10 µF
VQ
1 µF
0.01 µF
634 Ω
470 pF
-
C0G
10 µF
91 Ω
AIN+
+
100 kΩ
634 Ω
10 kΩ
2700 pF
C0G
470 pF
10 kΩ
0.01 µF
-
C0G
91 Ω
+
100 kΩ
10 µF
Figure 5. Fully Differential Input Buffer
6
AIN-
AN232
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com/
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information
is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to
the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation
of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale
of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information,
Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property
rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for
use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such
as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in
this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or
quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material
is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED
OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE
SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND
PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY
CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF
CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS,
THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may
be trademarks or service marks of their respective owners.
7