ADS809 ADS 809 SBAS170C – NOVEMBER 2000 – REVISED JANUARY 2003 12-Bit, 80MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● DYNAMIC RANGE: SNR: 65dB at 10MHz fIN SFDR: 68dB at 10MHz fIN ● PREMIUM TRACK-AND-HOLD: Low Jitter: 0.5ps rms Differential or Single-Ended Inputs Selectable Full-Scale Input Range ● FLEXIBLE CLOCKING: Differential or Single-Ended Accepts Sine or Square Wave Clocking Down to 0.5Vp-p Variable Threshold Level The ADS809 is a high-dynamic range, 12-bit, 80MHz, pipelined Analog-to-Digital Converter (ADC). It includes a high-bandwidth linear track-and-hold that has a low jitter of only 0.5ps rms, leading to excellent Signal-to-Noise Ratio (SNR) performance. The clock input can accept a low-level differential sine wave or square wave signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has flexible threshold levels. The ADS809 has a 2Vp-p differential input range (1Vp-p • 2 inputs) for optimum signal-to-noise ratio. The differential operation gives the lowest even-order harmonic components. A lower input voltage of 1.5Vp-p or 1Vp-p can also be selected using the internal references, further optimizing Spurious-Free Dynamic Range (SFDR). Alternatively, a singleended input range can be used by tying the IN input to the common-mode voltage if desired. APPLICATIONS The ADS809 also provides an over-range flag that indicates when the input signal has exceeded the converter’s full-scale range. This flag can also be used to reduce the gain of the front-end signal conditioning circuitry. It also employs digital error-correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS809 is available in a small TQFP-48 PowerPAD™ thermallyenhanced package. ● BASESTATION WIDEBAND RADIOS: CDMA, GSM, TDMA, 3G, AMPS, and NMT ● TEST INSTRUMENTATION ● CCD IMAGING PowerPAD is a registered trademark of Texas Instruments. +VS DV CLK ADS809 Timing Circuitry CLK 1Vp-p IN 12-Bit Pipelined ADC Core T&H 1Vp-p IN Error Correction Logic 3-State Outputs CM (+2.5V) OVR Reference Ladder and Driver Reference and Mode Select REFT VREF SEL1 SEL2 D0 • • • D11 REFB OE VDRV Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2000-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VS ....................................................................................................... +6V Analog Input .......................................................... (–0.3V) to (+VS + 0.3V) Logic Input ............................................................ (–0.3V) to (+VS + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) ADS809Y TQFP-48 PHP –40°C to +85°C ADS809Y ADS809Y/250 Tape and Reel, 250 " " " " ADS809Y/2K Tape and Reel, 2000 " TRANSPORT MEDIA, QUANTITY NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTRICAL CHARACTERISTICS At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 80MHz, VS = +5V, and internal reference, unless otherwise noted. ADS809Y PARAMETER CONDITIONS MIN RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Standard Differential Input Range Single-Ended Input Voltage Common-Mode Voltage Optional Input Ranges Analog Input Bias Current Track-Mode Input Bandwidth Input Impedance Ambient Air (1Vp-p • 2, +10dBm) 1Vp-p DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz f = 10MHz No Missing Codes Integral Nonlinearity Error, f = 1MHz Spurious-Free Dynamic Range(1) f = 1MHz f = 10MHz f = 31MHz 2-Tone Intermodulation Distortion fIN = 19.4MHz and 20.4MHz (–7dB each tone) Signal-to-Noise Ratio (SNR) f = 1MHz f = 10MHz f = 31MHz Signal-to-(Noise + Distortion) (SINAD) f = 1MHz f = 10MHz f = 31MHz Output Noise Aperture Delay Time Aperture Jitter Over-Voltage Recovery Time Full-Scale Step Acquisition Time MAX Bits °C 2 3 V V V V µA GHz MΩ || pF 80M Samples/s Clk Cyc +1.7/–1.0 LSB LSB ±7.0 LSBs 2.5 1Vp-p or 1.5Vp-p 1 1 1.25 || 9 –3dBFS Static, No Clock 1M 5 ±0.7 ±0.7 Tested ±4.0 65 Input AC-Grounded UNITS –40 to +85 1 2 Selectable CONVERSION CHARACTERISTICS Sample Rate Data Latency TYP 12 Tested 71 68 67 dBFS(2) dBFS dBFS –77 dBFS 65.5 65 63 dBFS dBFS dBFS 64 63 61 0.13 3 0.5 2 5 dBFS dBFS dBFS LSBs rms ns ps rms ns ns NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) A 50kΩ pull-down resistor is inserted internally. (4) Includes internal reference. (5) Excludes internal reference. 2 ADS809 www.ti.com SBAS170C ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 80MHz, VS = +5V, and internal reference, unless otherwise noted. ADS809Y PARAMETER DIGITAL INPUTS Logic Family Convert Command High-Level Input Current (VIN = 5V)(3) Low-Level Input Current (VIN = 0V) High-Level Input Voltage Low-Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA to 1.6mA) High Output Voltage, (IOH = 50µA to 0.5mA) Low Output Voltage, (IOL = 50µA to 1.6mA) High Output Voltage, (IOH = 50µA to 1.6mA) 3-State Enable Time 3-State Disable Time Output Capacitance CONDITIONS MIN MAX UNITS +3V/+5V Compatible CMOS Rising Edge of Convert Clock Start Conversion 100 ±10 +2.0 +1.0 5 µA µA V V pF +3V/+5V Compatible CMOS Straight Offset Binary VDRV = 3V +0.2 +2.5 VDRV = 5V +0.2 +2.5 OE = LOW OE = HIGH 20 2 5 ACCURACY (Internal Reference, = 2V, Unless Otherwise Noted) Zero Error (midscale) at 25°C Zero Error Drift (midscale) Gain Error(4) at 25°C Gain Error Drift(4) Gain Error(5) at 25°C Gain Error Drift(5) Power-Supply Rejection of Gain ∆VS = ±5% Internal REF Tolerance (VREFP – VREFN) Deviation from Ideal Reference Input Resistance POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Output Driver Supply Current (VDRV) Power Dissipation: VDRV = 5V VDRV = 3V VDRV = 5V VDRV = 3V Power Down Thermal Resistance, θJA TQFP-48 TYP Operating Operating Internal Reference Internal Reference External Reference External Reference Operating 0.5 12 ±1.5 38 ±0.75 20 68 ±10 660 +4.75 +5.0 170 12 925 900 905 880 20 28.8 40 10 ±40 +5.25 945 V V V V ns ns pF %FS ppm/°C %FS ppm/°C %FS ppm/°C dB mV Ω V mA mA mW mW mW mW mW °C/W NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) A 50kΩ pull-down resistor is inserted internally. (4) Includes internal reference. (5) Excludes internal reference. ADS809 SBAS170C www.ti.com 3 PIN DIAGRAM +VS IN GND IN GND GND REFT CM REFB GND GND TQFP +VS Top View 48 47 46 45 44 43 42 41 40 39 38 37 BYP 1 36 GND +VS 2 35 GND +VS 3 34 VREF +VS 4 33 SEL1 GND 5 32 SEL2 CLK 6 CLK 7 30 BTC GND 8 29 PD GND 9 28 OE 31 GND ADS809Y OVR 10 27 GND 21 22 23 24 D1 20 D2 19 D3 18 D4 17 D5 16 D6 15 D7 14 D8 13 D9 25 D0 (LSB) D10 NC 12 D11 (MSB) 26 VDRV NC DV 11 NC = No Connection PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 4 I/O I I O O O O O O O O O O O O O O DESIGNATOR BYP +VS +VS +VS GND CLK CLK GND GND OVR DV NC NC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION Bypass Point Supply Voltage Supply Voltage Supply Voltage Ground Clock Input Complementary Clock Input Ground Ground Over-Range Indicator Data Valid Pulse: HI = Data Valid No Connection No Connection Data Bit 11, (MSB) Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0, (LSB) PIN I/O DESIGNATOR 26 27 28 I VDRV GND OE 29 30 I I PD BTC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I I GND SEL2 SEL1 VREF GND GND GND GND REFB CM REFT GND GND IN GND IN +VS +VS DESCRIPTION Output Bit Driver Voltage Supply Ground Output Enable: HI = High Impedance; LO or Floating: Normal Operation Power Down: HI = Power Down; LO = Normal HI = Binary Two’s Complement; LO = Straight Binary Ground Reference Select 2: See Table on Page 5 Reference Select 1: See Table on Page 5 Internal Reference Voltage Ground Ground Ground Ground Bottom Reference Voltage Bypass Common-Mode Voltage (midscale) Top Reference Voltage Bypass Ground Ground Complementary Analog Input Ground Analog Input Supply Voltage Supply Voltage ADS809 www.ti.com SBAS170C TIMING DIAGRAM N+6 Analog In N N+4 N+3 N+7 N+5 N+1 N+2 tA tH tCONV tL Clock t1 5 Clock Cycles Data Bits Out N–5 N–4 N–3 N–2 N–1 N N+1 t2 tDV Data Valid Pulse SYMBOL t CONV tH tL tA tDV t1 t2 DESCRIPTION MIN(1) Convert Clock Period Clock Pulse HIGH Clock Pulse LOW Aperture Delay Data Valid Pulse Delay(2) Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 12.5 6.2 6.2 4 TYP t CONV /2 t CONV /2 4.6 10 5.8 9 MAX(1) UNITS 1µs ns ns ns ns ns ns ns 6.1 12 11 NOTES: (1) Timing values based on simulation at room temperature. Min/Max values provided for design estimation only. (2) Measured from the 50% point of the clock to the time when signals are within valid logic levels. REFERENCE AND FULL-SCALE RANGE SELECT DESIRED FULL-SCALE RANGE SEL1 SEL2 INTERNAL VREF 1Vp-p 1.5Vp-p 2Vp-p VREF GND GND GND +VS GND 0.5V 0.75V 1.0V NOTE: For external reference operation, tie VREF to +VS and apply REFT and REFB externally. Internal voltage buffer of CM is powered up. The full-scale input range is equal to 2x the reference value (REFT – REFB). ADS809 SBAS170C www.ti.com 5 TYPICAL CHARACTERISTICS At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 80MHz, and internal reference, unless otherwise noted. SPECTRAL PERFORMANCE (Differential, 2Vp-p) SPECTRAL PERFORMANCE (Differential, 2Vp-p) 0 0 fIN = 1MHz (–1.0dBFS) SFDR = 70.1dBFS SNR = 65.4dBFS SINAD = 63.8dBFS –40 –60 –80 –100 5 10 15 20 25 30 35 –80 40 0 5 10 15 20 25 30 Frequency (MHz) Frequency (MHz) SPECTRAL PERFORMANCE (Differential, 1.5Vp-p) SPECTRAL PERFORMANCE (Differential, 1Vp-p) 0 35 40 0 fIN = 10MHz (–1.0dBFS) SFDR = 68.9dBFS SNR = 63.2dBFS fIN = 10MHz (–1.0dBFS) SFDR = 69.6dBFS SNR = 60.7dBFS –20 Amplitude (dBFS) –20 Amplitude (dBFS) –60 –120 0 –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 Frequency (MHz) Frequency (MHz) 2-TONE INTERMODULATION DISTORTION DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY (2Vp-p, Differential) 0 35 40 80 SFDR, SNR, and SINAD (dBFS) f1 = 19.4MHZ f2 = 20.4MHZ IMD(3) = 77.2dBFS –20 Amplitude (dBFS) –40 –100 –120 –40 –60 –80 –100 –120 fIN = 10MHz 75 SFDR 70 SNR 65 60 SINAD 55 50 0 5 10 15 20 25 30 35 40 30 Frequency (MHz) 6 fIN = 10MHz (–1.0dBFS) SFDR = 68.3dBFS SNR = 65.1dBFS SINAD = 63.0dBFS –20 Amplitude (dBFS) Amplitude (dBFS) –20 40 50 60 70 80 90 Sampling Frequency (MHz) ADS809 www.ti.com SBAS170C TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 80MHz, and internal reference, unless otherwise noted. DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY (2Vp-p, Differential) SUPPLY CURRENTS vs SAMPLING FREQUENCY 180 80 SFDR, SNR, and SINAD (dBFS) fIN = 20MHz 160 75 Supply Currents (mA) SFDR 70 SNR 65 60 SINAD VS 140 120 100 80 60 40 VDRV 55 20 0 50 30 40 50 60 70 80 20 90 30 40 60 70 80 90 Sampling Frequency (MHz) Sampling Frequency (MHz) DYNAMIC PERFORMANCE vs INPUT FREQUENCY DYNAMIC PERFORMANCE vs INPUT FREQUENCY 80 75 (–1.0dBFS) 70 SFDR, SNR, and SINAD (dBFS) SFDR, SNR, and SINAD (dBFS) 50 SFDR 65 SNR 60 SINAD 55 50 (–6.0dBFS) 75 SFDR 70 SNR 65 60 SINAD 55 50 0 5 10 15 20 25 30 35 40 0 45 5 10 15 20 25 30 35 40 45 Input Frequency (MHz) Input Frequency (MHz) INTEGRAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR 3 1 0.8 2 0.6 1 ILE (LSB) DLE (LSB) 0.4 0.3 0 –0.2 0 –1 –0.4 –0.6 –2 –0.8 –3 –1 0 1024 2048 3072 0 4096 ADS809 SBAS170C 1024 2048 3072 4096 Code Code www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 80MHz, and internal reference, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE DYNAMIC PERFORMANCE vs TEMPERATURE 180 fIN = 10MHz (–1.0dBFS) SFDR 160 70 Supply Current (mA) SFDR, SNR, and SINAD (dBFS) 75 SNR 65 60 SINAD VS 140 120 100 80 60 40 55 VDRV 20 0 50 –60 –40 –20 0 20 40 60 80 –60 100 –40 –20 0 20 40 60 80 Temperature (°C) Temperature (°C) OUTPUT NOISE HISTOGRAM (2Vp-p, Grounded Input) SWEPT POWER—SFDR 250k 100 90 200k dBFS 80 SFDR (dBc, dBFS) Counts 100 150k 100k 50k 70 60 50 dBc 40 30 20 10 0 0 N–2 N–1 N N+1 N+2 –80 –70 Code –60 –50 –40 –30 –20 –10 0 Analog Input Level (dBFS) SWEPT POWER—SNR 80 dBFS 70 SNR (dBc, dBFS) 60 50 40 dBc 30 20 10 0 –10 –20 –80 –70 –60 –50 –40 –30 –20 –10 0 Analog Input Level (dBFS) 8 ADS809 www.ti.com SBAS170C APPLICATION INFORMATION THEORY OF OPERATION The ADS809 is a high-speed, high performance, CMOS ADC built with a fully differential, 9-stage pipeline architecture. Each stage contains a low-resolution quantizer and digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The conversion process is initiated by a rising edge of the external convert clock. Once the signal is captured by the input trackand-hold amplifier, the bits are sequentially encoded starting with the Most Significant Bit (MSB). This process results in a data latency of five clock cycles, after which the output data is available as a 12-bit parallel word either coded in a straight binary or binary two’s complement format. The analog input of the ADS809 consists of a differential track-and-hold circuit, as shown in Figure 1. The differential topology produces a high level of AC-performance at high sampling rates. It also results in a very high usable input bandwidth that is especially important for IF, or undersampling applications. Both inputs (IN, IN) require external biasing up to a common-mode voltage that is typically at the mid-supply level (+VS/2). This is because the on-resistance of the CMOS switches is lowest at this voltage, minimizing the effects of the signal dependent nonlinearity of RON. The track-and-hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. For ease of use, the ADS809 incorporates a selectable voltage reference, a versatile clock input, and a logic output driver designed to interface to 3V or 5V logic. S5 ADS809 S3 S1 CIN S2 CIN IN T&H IN S4 S6 Tracking Phase: S1, S2, S3, S4 Closed; S5, S6 Open Hold Phase: S1, S2, S3, S4 Open; S5, S6 Closed FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier. DRIVING THE ANALOG INPUTS Types of Applications The analog input of the ADS809 can be configured in various ways and driven with different circuits, depending on the application and the desired level of performance. Offering a high dynamic range at high input frequencies, the ADS809 is particularly suited for communication systems that digitize wideband signals. Features on the ADS809, like the input range selector or the option of an external reference, provide the needed flexibility to accommodate a wide range of applications. In any case, the analog interface/driver requirements should be carefully examined before selecting the appropriate circuit configuration. The circuit definition should include considerations on the input frequency spectrum and amplitude, single-ended versus differential driver configuration, as well as the available power supplies. Differential versus Single-Ended The ADS809 input structure allows it to be driven either single-ended or differentially. Differential operation of the ADS809 requires an input signal that consists of an in-phase and a 180° out-of-phase component simultaneously applied to the inputs (IN, IN). Differential signals offer a number of advantages that, in many applications, will be instrumental in achieving the best harmonic performance of the ADS809: • The signal amplitude is half of that required for the singleended operation, and is therefore less demanding to achieve while maintaining good linearity performance from the signal source. • The reduced signal swing allows for more headroom of the interface circuitry, and therefore a wider selection of the best suitable driver amplifier. • Even-order harmonics are minimized. • Improves the noise immunity based on the converter’s common-mode input rejection. For the single-ended mode, the signal is applied to one of the inputs while the other input is biased with a DC voltage to the required common-mode level. Both inputs are identical in terms of their impedance and performance except that applying the signal to the complementary input (IN) instead of the IN-input will invert the orientation of the input signal relative to the output code. For example, if the input driver operates in inverting mode, using IN as the signal input, it will restore the phase of the signal to its original orientation. Timedomain applications may benefit from a single-ended interface configuration and a reduced circuit complexity. Driving the ADS809 with a single-ended signal will result in a tradeoff of the excellent distortion performance, while maintaining a good SNR. The trade-off of the differential input configuration over the single-ended is its increase in circuit complexity. In either case, the selection of the driver amplifier should be such that the amplifier’s performance will not degrade the ADC’s performance. Input Full-Scale Range versus Performance Employing dual-supply amplifiers and AC-coupling will usually yield the best results. DC-coupling and/or single-supply amplifiers impose additional design constrains due to their headroom requirements, especially when selecting the 2Vp-p input range. The full-scale input range of the ADS809 is defined either by the settings of the reference select pins (SEL1, SEL2) or by an external reference voltage (see Table I). ADS809 SBAS170C www.ti.com 9 By choosing between the three different signal input ranges, tradeoffs can be made between noise and distortion performance. For maximizing the SNR, which is important for timedomain applications, the 2Vp-p range may be selected. This range may also be used with low-level (–6dBFS to –40dBFS) to high-frequency inputs (multi-tone). The 1.5Vp-p range may be considered for achieving a combination of both low noise and distortion performance. Here, the SNR number is typically 3dB down compared to the 2Vp-p range, while an improvement in the distortion performance of the driver amplifier may be realized due to the reduced output power level required. The third option, 1Vp-p FSR, may be considered mainly for applications requiring DC-coupling and/or single-supply operation of the driver and the converter. Input Biasing (VCM) The ADS809 operates from a single +5V supply, and requires each of the analog inputs to be externally biased to a commonmode voltage of typically +2.5V. This allows a symmetrical signal swing while maintaining sufficient headroom to either supply rail. Communication systems are usually AC-coupled in-between signal processing stages, making it convenient to set individual common-mode voltages and allow optimizing the DC operating point for each stage. Other applications (e.g., imaging) process only unipolar or DC-restored signals. In this case, the common-mode voltage may be shifted such that the full-input range of the converter is utilized. It should be noted that the CM pin is internally buffered. However, it is recommended to keep the loading of this pin to a minimum to avoid an increase in the converter’s nonlinearity. Also, the DC voltage at the CM pin is not exactly +2.5V, but is subject to the tolerance of the top and bottom references as well as the resistor ladder. Input Impedance The input of the ADS809 is of a capacitive nature and the driving source needs to provide the slew current to charge or discharge the input sampling capacitor while the track-andhold amplifier is in track mode, see Figure 1. This effectively results in a dynamic input impedance that is a function of the sampling frequency. Figure 2 depicts the differential input impedance of the ADS809 as a function of the input frequency. For applications that use op amps to drive the ADC, it is recommended to add a series resistor between the amplifier output and the converter inputs. This will isolate the converter’s capacitive input from the driving source and avoid gain peaking, or instability. Furthermore, it will create a 1st-order, low-pass filter in conjunction with the specified input capacitance of the ADS809. Its cutoff frequency can be adjusted even further by adding an external shunt capacitor from each signal input to ground. However, the optimum values of this RC network depend on a variety of factors, including the ADS809’s sampling rate, the selected op amp, the interface configuration, and the particular application (time domain versus frequency domain). Generally, increasing the size of the series resistor and/or capacitor will improve the signal-tonoise ratio, however, depending on the signal source, large resistor values may reduce the harmonic distortion performance. In any case, the use of the RC network is optional but optimizing the values to adapt to the specific application is encouraged. INPUT DRIVER CONFIGURATIONS The following section provides some principal circuit suggestions on how to interface the analog input signal to the ADS809. A first example of a typical analog interface circuit is shown in Figure 3. Here, it is assumed that the input signal is already available in differential form, e.g.: coming from a preceding mixer stage. The differential driver performs an impedance transformation as well as amplifying the signal to match the selected full-scale input range of the ADS809 (for example, 2Vp-p). The common-mode voltage (VCM) for the converter input is established by connecting the inputs to the midpoints of the resistor divider. The input signal is ACcoupled through capacitors CIN to the inputs of the converter that are set to a VCM of approximately +2.5VDC. 1kΩ 1kΩ CIN 0.1µF IN Differential Driver ADS809 INPUT IMPEDANCE vs INPUT FREQUENCY REFT VIN CIN 0.1µF VCM = +2.5V ADS809 VIN 1000 IN REFB 1kΩ 100 ZIN (kΩ) NOTE: Reference bypassing omitted for clarity. 10 FIGURE 3. AC Coupling Allows for Easy DC Biasing of the ADS809 Inputs While the Input Signal is Applied by the Differential Input Driver. 1 0.1 0.01 0.1 1 10 100 1000 fIN (MHz) FIGURE 2. Differential Input Impedance versus Input Frequency. 10 1kΩ Some differential driver circuits may allow setting an appropriate common-mode voltage directly at the driver input. This will simplify the interface to the ADS809 and eliminate the external biasing resistors and the coupling capacitors. Texas Instruments offers a line of fully differential highspeed amplifiers. The THS4150, for example, may be used ADS809 www.ti.com SBAS170C Furthermore, the appropriate model must support the targeted distortion level and should not exhibit any core saturation at full-scale voltage levels. Since the transformer does not appreciably load the ladder, its center tap can be directly tied to the CM pin of the converter, as shown in Figure 4. The value of termination resistor (RT) should be chosen to satisfy the termination requirements of the source impedance (RS). It can be calculated using the equation RT = n2 • RS to ensure proper impedance matching. for input frequencies from DC to approximately 10MHz, for which the part maintains good distortion performance providing a 2Vp-p (max) output swing on ±5V supplies. Combining a differential driver circuit with a step-up transformer can lead to significant improvement of the distortion performance (see Figure 6). Transformer Coupled Interface Circuits If the application allows for AC-coupling, but requires a signal conversion from a single-ended source to drive the ADS809 differentially, using a transformer offers a number of advantages. As a passive component, it does not add to the total noise, plus using a step-up transformer, further signal amplification can be realized. As a result, the signal swing out of the amplifier driving the transformer can be reduced, leading to more headroom for the amplifier and improved distortion performance. Transformer-Coupled, Single-Ended to Differential Configuration For applications in which the input frequency is limited to about 40MHz (i.e.: baseband), the wideband, current-feedback, operational amplifier OPA685 may be used. As shown in Figure 5, the OPA685 configured for the noninverting mode amplifies the single-ended input signal, and drives the primary of an RF transformer. To maintain the very low-distortion performance of the OPA685, it may be advantageous to reduce the fullscale input range (FSR) of the ADS809 from 2Vp-p to 1.5Vpp or 1Vp-p (refer to the paragraph “Reference” for details on selecting the converter’s full-scale range). One possible interface solution that uses a transformer is given in Figure 4. The input signal is assumed to be an Intermediate Frequency (IF) and bandpass filtered prior to the IF amplifier. Dedicated IF amplifiers, for example the RF2312 or MAR-6, are fixed-gain broadband amplifiers and feature a very high bandwidth, a low-noise figure, and a high intercept point at the expense of high quiescent currents of 50-120mA. The IF amplifier may be AC-coupled or directly connected to the primary side of the transformer. The circuit also shows the use of an additional RC low-pass filter placed in series with each converter input. This optional filter can be used to set a defined corner frequency and attenuate some of the wideband noise. The actual component values would need to be tuned for the individual application requirements. As a guideline, resistor values are typically in the range of 10Ω to 100Ω, capacitors in the range of 10pF to 200pF. In any case, the RIN and CIN values should have a low tolerance. This will ensure that the ADS809 sees closely matched source impedances. A variety of miniature RF transformers are readily available from different manufacturers, i.e.: Mini-Circuits, Coilcraft, or Trak. For the selection, it is important to carefully examine the application requirements and determine the correct model, the desired impedance ratio, and frequency characteristics. +5V +VS Optional Bandpass Filter VIN (IF) RS IF Amp 0.1µF 1:n XFMR RIN IN RT CIN RIN ADS809 IN CIN –VS CM VCM +2.5V + 0.1µF 4.7µF FIGURE 4. Driving the ADS809 with a Low-Distortion RF Amplifier and a Transformer Suited for IF Sampling Applications. +V –V +5V RG RS VIN OPA685 0.1µF 1:n XFMR RIN IN RT R1 RIN CIN ADS809 IN CIN R2 CM VCM +2.5V + 2.2µF 0.1µF FIGURE 5. Converting a Single-Ended Input Signal into a Differential Signal Using an RF Transformer. ADS809 SBAS170C www.ti.com 11 AC-Coupled, Differential Interface with Gain The interface circuit example presented in Figure 6 employs two OPA685s, (current-feedback op amps), optimized for gains of 8V/V or higher. The input transformer (T1) converts the single-ended input signal to a differential signal required at the amplifier’s inverting inputs, that are tuned to provide a 50Ω impedance match to an assumed 50Ω source. To achieve the 50Ω input match at the primary of the 1:2 transformer, the secondary input must see a 200Ω load impedance. Both amplifiers are configured for the inverting mode resulting in close gain and phase matching of the differential signal. This technique, along with a highly symmetrical layout, is instrumental in achieving a substantial reduction of the 2nd-harmonic, while retaining excellent 3rdorder performance. A common-mode voltage (VCM) is ap- plied to the noninverting inputs of the OPA685. Additional series of 43.2Ω resistors isolate the output of the op amps from the capacitive load presented by the 22pF capacitors and the input capacitance of the ADS809. This 43.2Ω/22pF combination sets a pole at approximately 167MHz and rolls off some of the wideband noise. REFERENCE REFERENCE OPERATION Integrated into the ADS809 is a bandgap reference circuit including some logic that provides a +0.5V, +0.75V, or +1V reference output by selecting the corresponding pin-strap configuration. Table I gives a complete overview of the possible reference options and pin configurations. +5V Power-supply decoupling not shown. DIS VCM OPA685 50Ω Source VI T1 1:2 100Ω –5V 600Ω 43.2Ω 22pF VO Noise Figure 11.8dB 100Ω 600Ω ADC Input 43.2Ω +5V 22pF DIS OPA685 VCM VO = 12V/V (21.6dB) VI –5V FIGURE 6. Wideband Differential ADC Driver. DESIRED FULL-SCALE RANGE, FSR (Differential) CONNECT SEL1 (Pin 33) CONNECT SEL2 (Pin 32) VOLTAGE AT VREF (Pin 34) VOLTAGE AT REFT (Pin 41) VOLTAGE AT REFB (Pin 39) 2Vp-p (+10dBm) GND GND +1.0V +3V +2V 1.5Vp-p (+7.5dBm) GND +VS +0.75V +2.875V +2.125V 1Vp-p VREF GND +0.5V +2.75V +2.25V External Reference — — > +3.5V +2.75V to +4.5V +0.5V to +2.25V TABLE I. Reference Pin Configurations and Corresponding Voltage on the Reference Pins. 12 ADS809 www.ti.com SBAS170C Using External References Figure 7 shows the basic model of the internal reference circuit. The functional blocks are a 1V bandgap voltage reference, a selectable gain amplifier, the drivers for the top and bottom reference (REFT, REFB), and the resistive reference ladder. The ladder resistance measures approximately 660Ω between the REFT and REFB pin. The ladder is split into two equal segments, establishing a common-mode voltage at the ladder midpoint, labeled “CM.” The ADS809 requires solid bypassing for all reference pins to keep the effect of clock feedthrough to a minimum and to achieve the specified level of performance. Figure 7 also demonstrates the recommended decoupling scheme. All 0.1µF capacitors should be located as close to the pins as possible. For even more design flexibility, the ADS809 can be operated with an external reference. The utilization of an external reference voltage may be considered for applications requiring higher accuracy, improved temperature stability, or a continuous adjustment of the converter’s full-scale range. Especially in multichannel applications, the use of a common external reference offers the benefit of improving the gain matching between converters. Selection between internal or external reference operation is controlled through the VREF pin. The internal reference will become disabled if the voltage applied to the VREF pin exceeds +3.5VDC. Once selected, the ADS809 requires two reference voltages—a top-reference voltage applied to the REFT pin and a bottom-reference voltage applied to the REFB pin (see Table I). As illustrated in Figure 8, a micropower reference (REF1004) and a dual, single-supply amplifier may be used to generate a precision external reference. Note that the function of the range select pins, SEL1 and SEL2, are disabled while the converter is in external mode. When operating the ADS809 from the internal reference, the effective full-scale input span for each of the inputs, IN and IN, is determined by the voltages at REFT and REFB pins, given as: Input Span (differential) = 2x (REFT – REFB), in Vp-p = 2 • VREF The top and bottom reference outputs may be used to provide up to 1mA (sink or source) of current to external circuits. Degradation of the differential linearity (DNL) and, consequently, of the dynamic performance of the ADS809 may occur if this limit is exceeded. SEL1 SEL2 PD Range Select and Gain Amplifier ByP 0.1µF Top Reference Driver REFT 0.1µF 330Ω +1VDC Bandgap Reference 1 CM 0.1µF 0.1µF 1µF 330Ω Bottom Reference Driver REFB 0.1µF ADS809 0.1µF VREF FIGURE 7. Internal Reference Circuit of the ADS809 and Recommended Bypass Scheme. +5V –5V 1/2 OPA2234 4.7kΩ REFT + R3 + 0.1µF ADS809 R4 R1 REF1004 +2.5V 2.2µF 10µF 1/2 OPA2234 R2 REFB + 0.1µF 2.2µF 0.1µF FIGURE 8. Example for an External Reference Circuit Using a Dual, Single-Supply Op Amp. ADS809 SBAS170C www.ti.com 13 DIGITAL INPUTS AND OUTPUTS CLOCK INPUT Unlike most ADCs, the ADS809 contains an internal clock conditioning circuitry. This enables the converter to adapt to a variety of application requirements and different clock sources. Some interface examples are given in the following section. With no input signal connected to either clock pin, the threshold level is set to about +1.6V by the on-chip resistive voltage divider, as shown in Figure 9. The parallel combination of R1 || R2 and R3 || R4 sets the input impedance of the clock inputs (CLK, CLK) to approximately 2.7kΩ single-ended or 5.4kΩ differentially. The associated ground-referenced input capacitance is approximately 5pF for each input. If a logic voltage other than the nominal +1.6V is desired, the clock inputs can be externally driven to establish an alternate threshold voltage. +5V ADS809 R1 8.5kΩ Applying a single-ended clock signal will provide satisfactory results in many applications. However, unbalanced highspeed logic signals often introduce a high amount of disturbances, such as ringing or ground bouncing. Also, a high amplitude may cause the clock signal to have unsymmetrical rise and fall times, potentially effecting the converter distortion performance. Proper termination practice and a clean PCB layout will help to keep those effects to a minimum. To take full advantage of the excellent distortion performance of the ADS809, it is recommended to drive the clock inputs differentially. A low-level, differential clock improves the digital feedthrough immunity and minimizes the effect of modulation between the signal and the clock. Figure 11 illustrates a simple method of converting a square wave clock from single-ended to differential using a RF transformer. Small surface-mount transformers are readily available from several manufacturers (e.g.: model ADT1-1 by Mini-Circuits). A capacitor in series with the primary side may be inserted to block any DC voltage present in the signal. Since the clock inputs are self-biased, the secondary side connects directly to the two clock inputs of the converter. R3 8.5kΩ 0.1µF CLK CLK Square Wave Clock Source R2 4kΩ 1:1 CLK R4 4kΩ ADS809 CLK FIGURE 9. The Differential Clock Inputs are Internally Biased. The ADS809 can be interfaced to standard TTL or CMOS logic and accepts 3V or 5V compliant logic levels. In this case, the clock signal should be applied to the CLK-input, while the complementary clock input (CLK) should be bypassed to ground by a low-inductance ceramic chip capacitor, as shown in Figure 10. Depending on the quality of the signal, inserting a series, damping resistor may be beneficial to reduce ringing. When digitizing at high sampling rates (fS > 50MHz), the clock should have a 50% duty cycle (tH = tL) to maintain a good distortion performance. CLK TTL/CMOS Clock Source (3V/5V) ADS809 CLK 47nF FIGURE 10. Single-Ended TTL/CMOS Clock Source. FIGURE 11. Connecting a Ground Referenced Square Wave Clock Source to the ADS809 Using a RF Transformer. The clock inputs of the ADS809 can be connected in a number of ways. However, the best performance is obtained when the clock input pins are driven differentially. When operating in this mode, the clock inputs accommodate signal swings ranging from 2.5Vp-p down to 0.5Vp-p, differentially. This allows direct interfacing of clock sources, such as voltage-controlled crystal oscillators (VCXO) to the ADS809. The advantage here is the elimination of external logic usually necessary to convert the clock signal into a suitable logic (TTL or CMOS) signal, that otherwise would create an additional source of jitter. In any case, a very low-jitter clock is fundamental to preserving the excellent AC performance of the ADS809. The converter itself is specified for a very low 0.25ps (rms) jitter, characterizing the outstanding capability of the internal clock and track-and-hold circuitry. Generally, as the input frequency increases, the clock jitter becomes more dominant in maintaining a good SNR. This is particularly critical in IF sampling applications where the sampling frequency is lower than the input frequency (or undersampling). The following equation can be used to calculate the achievable SNR for a given input frequency and clock jitter (tJA in ps rms): SNR = 20 log10 14 1 π f 2 ( INt JA ) ADS809 www.ti.com SBAS170C Depending on the nature of the clock source’s output impedance, an impedance matching might become necessary. For this, a termination resistor (RT) may be installed, as shown in Figure 12. To calculate the correct value for this resistor, consider the impedance ratio of the selected transformer and the differential clock input impedance of the ADS809, which is approximately 5.4kΩ. It is not recommended to employ any type of differential TTL logic that suffers from mismatch in delay time and slew-rate leading to performance degradation. Alternatively, a low jitter ECL or PECL clock may be AC-coupled directly to the clock inputs using small (0.1µF) capacitors. STRAIGHT OFFSET BINARY (SOB) BINARY TWO’S COMPLEMENT (BTC) +FS – 1LSB (IN = +3V, IN = +2V) 1111 1111 1111 0111 1111 1111 +1/2 FS 1100 0000 0000 0100 0000 0000 Bipolar Zero (IN = IN = CMV) 1000 0000 0000 0000 0000 0000 –1/2 FS 0100 0000 0000 1100 0000 0000 –FS (IN = +2V, IN = +3V) 0000 0000 0000 1000 0000 0000 DIFFERENTIAL INPUT TABLE III. Coding Table for Differential Input Configuration and 2Vp-p Full-Scale Input Range. Output Enable (OE ) 1:1 RF Sine Source CLK ADS809 RT CLK FIGURE 12. Applying a Sinusoidal Clock to the ADS809. MINIMUM SAMPLING RATE The pipeline architecture of the ADS809 uses the switched capacitor technique in its internal track-and-hold stages. With each clock cycles charges representing the captured signal level are moved within the ADC pipeline core. The high sampling speed necessitates the use of very small capacitor values. In order to hold the droop errors LOW, the capacitors require a minimum “refresh rate.” Therefore, the sampling clock on the ADS809 should not drop below the specified minimum of 1MHz. Power Down (PD) A power-down of the ADS809 is initiated by taking the PD pin HIGH. This shuts down portions within the converter and reduces the power dissipation to about 20mW. The remaining active blocks include the internal reference, ensuring a fast reactivation time. During power-down, data in the converter pipeline will be lost and new valid data will be subject to the specified pipeline delay. In case the PD pin is not used, it should be tied to ground or a logic LOW level. Over-Range Indicator (OVR) DATA OUTPUT FORMAT (BTC) The ADS809 makes two data output formats available, either the “Straight Offset Binary” code (SOB) or the “Binary Two’s Complement” code (BTC). The selection of the output coding is controlled through the BTC pin. Applying a logic HIGH will enable the BTC coding, while a logic LOW will enable the SOB code. The BTC output format is widely used to interface to microprocessors and such. The two code structures are identical with the exception that the MSB is inverted for the BTC format, as shown in Tables II and III. STRAIGHT OFFSET BINARY (SOB) BINARY TWO’S COMPLEMENT (BTC) +FS – 1LSB (IN = CMV + FSR/2) 1111 1111 1111 0111 1111 1111 +1/2 FS 1100 0000 0000 0100 0000 0000 Bipolar Zero (IN = CMV) 1000 0000 0000 0000 0000 0000 –1/2 FS 0100 0000 0000 1100 0000 0000 –FS (IN = CMV – FSR/2) 0000 0000 0000 1000 0000 0000 DIFFERENTIAL INPUT The digital outputs of the ADS809 can be set to high impedance (tri-state), exercising the output enable pin (OE). For normal operation, this pin must be at a logic LOW potential while a logic HIGH voltage disables the outputs. Even though this function effects the output driver stage, the threshold voltages for the OE pin do not depend on the output driver supply (VDRV), but are fixed (see “Specifications, Digital Inputs”). Operating the OE function dynamically (i.e., high-speed multiplexing, should be avoided, as it will corrupt the conversion process. TABLE II. Coding Table for Singles-Ended Input Configuration with IN Tied to the Common-Mode Voltage (CMV). If the analog input voltage exceeds the full-scale range set by the reference voltages, an over-range condition exists. The ADS809 incorporates a function that monitors the input voltage and detects any such out-of-range condition. The current state can be read at the over-range indicator pin (OVR). This output is LOW when the input voltage is within the defined input range. It will change to HIGH if the applied signal exceeds the full-scale range. It should be noted that the OVR output is updated along with the data output, corresponding to the particular sampled analog input voltage. Therefore, the OVR data is subject to the same pipeline delay as the digital data (5 clock cycles). Output Loading It is recommended to keep the capacitive loading on the data output lines as low as possible, preferably below 15pF. Higher capacitive loading will cause larger dynamic currents to flow as the digital outputs are changing. For example, with a typical output slew-rate of 0.8V/ns and a total capacitive loading of 10pF (including 4pF output capacitance, 5pF input capacitance of external logic buffer, and 1pF pc-board parasitics), a bit transition can cause a dynamic current of (10pF • 0.8V/1ns = 8mA). Those high current surges can ADS809 SBAS170C www.ti.com 15 feed back to the analog portion of the ADS809 and adversely affect the performance. External buffers, or latches, close to the converter’s output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS809 from any digital activities on the bus from coupling back high-frequency noise. POWER SUPPLIES When defining the power supplies for the ADS809, is it highly recommended to consider linear supplies instead of switching types. Even with good filtering, switching supplies may radiate noise that could interfere with any high-frequency input signal and cause unwanted modulation products. At its full conversion rate of 80MHz, the ADS809 requires typically 170mA of supply current on the +5V supply (+VS). Note that this supply voltage should stay within a 5% tolerance. The ADS809 does not require separate analog and digital supplies, but only one single +5V supply to be connected to all its +VS pins. This is with the exception of the output driver supply pin, denoted VDRV (see the following section). Digital Output Driver Supply (VDRV) A dedicated supply pin, denoted VDRV, provides power to the logic output drivers of the ADS809, and may be operated with a supply voltage in the range of +3.0V to +5.0V. This can simplify interfacing to various logic families, in particular lowvoltage CMOS. It is recommended to operate the ADS809 with a +3.0V supply voltage on VDRV. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line that may affect the AC performance of the converter. The analog supply (+VS) and driver supply (VDRV) may be tied together, with a ferrite bead or inductor between the supply pins. Each of the these supply pins must be bypassed separately with at least one 0.1µF ceramic chip capacitor, forming a pi-filter. The recommended operation for the ADS809 is +5V for the +VS pins and +3.0V on the output driver pin (VDRV). be connected to a low-noise supply. Supplies of adjacent digital circuits may carry substantial current transients. The supply voltage must be thoroughly filtered before connecting to the VDRV supply of the converter. All ground connections on the ADS809 are internally bonded to the metal flag (bottom of package) that forms a large ground plane. All ground pins should directly connect to an analog ground plane that covers the pc-board area under the converter. Because of its high sampling frequency, the ADS809 generates high-frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. If not sufficiently bypassed, this will add noise to the conversion process. Figure 13 shows the recommended supply decoupling scheme for the ADS809. All +VS pins may be connected together and bypassed with a combination of 10nF to 0.1µF ceramic chip capacitors (0805, low ESR) and a 10µF tantalum tank capacitor. A similar approach may be used on the driver supply pins, VDRV. In order to minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible. Where double-sided component mounting is allowed, they are best placed directly under the package. In addition, larger bipolar decoupling capacitors (2.2µF to 10µF), effective at lower frequencies, should also be used on the main supply pins. They can be placed on the pc-board in proximity (< 0.5") of the ADC. ADS809 GND +VS 35, 36, 37, 38 42, 43, 45 2, 47, 48 GND 5, 8, 31 +VS 3, 4 GND 9, 27 VDRV 26 0.01µF 0.01µF 0.01µF 0.1µF 0.1µF 0.1µF LAYOUT AND DECOUPLING CONSIDERATIONS Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for highfrequency designs. Achieving optimum performance with a fast sampling converter, like the ADS809, requires careful attention to the pc-board layout to minimize the effect of board parasitics and optimize component placement. A multilayer board usually ensures best results and allows convenient component placement. The ADS809 should be treated as an analog component with the +VS pins connected to clean analog supplies. This will ensure the most consistent results, since digital supplies often carry a high level of switching noise that could couple into the converter and degrade the performance. As mentioned previously, the driver supply pins (VDRV) should also 16 +5V +3V, +5V FIGURE 13. Recommended Supply Decoupling Scheme. If the analog inputs to the ADS809 are driven differentially, it is especially important to optimize towards a highly symmetrical layout. Small trace length differences may create phase shifts compromising a good distortion performance. For this reason, the use of two single op amps (rather than one dual amplifier) enables a more symmetrical layout and a better match of parasitic capacitances. The pin orientation of the ADS809 package follows a “flow-through” design with the analog inputs located on one side of the package while the digital outputs are located on the opposite side of the quadflat package. This provides a good physical isolation be- ADS809 www.ti.com SBAS170C tween the analog and digital connections. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog portion. Also, try to match trace length for the differential clock signal (if used) to avoid mismatches in propagation delays. Singleended clock lines must be short and should not cross any other signal traces. Short-circuit traces on the digital outputs will minimize capacitive loading. Trace length should be kept short to the receiving gate (< 2") with only one CMOS gate connected to one digital output. If possible, the digital data outputs should be buffered (with a 74LCX571, for example). Dynamic performance may also be improved with the insertion of series resistors at each data output line. This sets a defined time constant and reduces the slew rate that would otherwise flow, due to the fast edge rate. The resistor value may be chosen to result in a time constant of 15% to 25% of the used data rate. LAYOUT OF PCB WITH PowerPAD THERMALLY ENHANCED PACKAGES The ADS809 is housed in a 48-lead PowerPAD thermally enhanced package. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this technology in mind. Please refer to SLMA004 PowerPAD brief “PowerPAD Made Easy” (refer to our web site at www.ti.com), which addresses the specific considerations required when integrating a PowerPAD package into the PCB design. For more detailed information, including thermal modeling and repair procedures, please see SLMA002 technical brief “PowerPAD Thermally Enhanced Package” (www.ti.com). ADS809 SBAS170C www.ti.com 17 PACKAGE DRAWING PHP (S-PQFP-G48) PowerPAD PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 Thermal Pad (see Note D) 48 13 0,13 NOM 1 12 5,50 TYP Gage Plane 7,20 SQ 6,80 9,20 SQ 8,80 0,25 0,15 0,05 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 1,20 MAX 0,08 4146927/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026 18 ADS809 www.ti.com SBAS170C PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS809Y/250 ACTIVE TQFP PFB 48 250 None CU NIPDAU Level-3-220C-168 HR ADS809Y/2K ACTIVE TQFP PFB 48 2000 None Call TI Level-3-220C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. 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