FAIDM Series FAST / TTL Buffered 5-Tap Delay Modules Electrical Specifications at 25OC Low Profile 14-Pin Package Two Surface Mount Versions FAST 5 Tap 14-Pin DIP P/N FAST/TTL Logic Buffered FAIDM-7 FAIDM-9 FAIDM-11 FAIDM-13 FAIDM-15 FAIDM-20 FAIDM-25 FAIDM-30 FAIDM-35 FAIDM-40 FAIDM-50 FAIDM-60 FAIDM-75 FAIDM-100 FAIDM-125 FAIDM-150 FAIDM-200 FAIDM-250 FAIDM-350 FAIDM-500 5 Equal Delay Taps Operating Temperature Range 0OC to +70OC 8-Pin Versions: FAMDM Series SIP Versions: FSIDM Series Low Voltage CMOS Versions refer to LVMDM / LVIDM Series FAIDM 14-Pin Schematic Vcc Tap1 Tap3 Tap5 14 12 10 8 1 4 6 7 IN Tap2 Tap4 GND Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns) Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 3.0 3.0 3.0 3.0 3.0 4.0 5.0 6.0 7.0 8.0 10.0 12.0 15.0 20.0 25.0 30.0 40.0 50.0 70.0 100.0 4.0 4.5 5.0 5.5 6.0 8.0 10.0 12.0 14.0 16.0 20.0 24.0 30.0 40.0 50.0 60.0 80.0 100.0 140.0 200.0 5.0 6.0 7.0 8.0 9.0 12.0 15.0 18.0 21.0 24.0 30.0 36.0 45.0 60.0 75.0 90.0 120.0 150.0 210.0 300.0 6.0 7.5 9.0 10.5 12.0 16.0 20.0 24.0 28.0 32.0 40.0 48.0 60.0 80.0 100.0 120.0 160.0 200.0 280.0 400.0 7 ± 1.0 9 ± 1.0 11 ± 1.0 13 ± 1.5 15 ± 1.5 20 ± 2.0 25 ± 2.0 30 ± 2.0 35 ± 2.0 40 ± 2.0 50 ± 2.5 60 ± 3.0 75 ± 3.75 100 ± 5.0 125 ± 6.25 150 ± 7.5 200 ± 10.0 250 ± 12.5 350 ± 17.5 500 ± 25.0 Tap-to-Tap (ns) ∗∗ 1 ± 0.5 ∗∗ 1.5 ± 0.5 ∗∗ 2 ± 0.7 ∗∗ 2.5 ± 1.0 3 ± 1.0 4 ± 1.5 5 ± 2.0 6 ± 2.0 7 ± 2.0 8 ± 2.0 10 ± 2.0 12 ± 2.0 15 ± 2.5 20 ± 3.0 25 ± 3.0 30 ± 3.0 40 ± 4.0 50 ± 5.0 70 ± 7.0 100 ± 10.0 ** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1. TEST CONDITIONS -- FAST / TTL VCC Supply Voltage ................................................ 5.00VDC Input Pulse Voltage ................................................... 3.20V Input Pulse Rise Time ....................................... 3.0 ns max. Input Pulse Width / Period ........................... 1000 / 2000 ns 1. Measurements made at 25OC 2. Delay Times measured at 1.50V level of leading edge. 3. Rise Times measured from 0.75V to 2.40V. 4. 10pf probe and fixture load on output under test. Dimensions in Inches (mm) .285 (7.24) MAX. .785 (19.94) MAX. .250 .020 (6.35) (0.51) MAX. DIP .120 (3.05) MIN. OPERATING SPECIFICATIONS VCC Supply Voltage ................................... 5.00 ± 0.25 VDC ICC Supply Current .................................... 48 mA Maximum Logic “1” Input: VIH ....................... 2.00 V min., 5.50 V max. IIH .............................. 20 µA max. @ 2.70V Logic “0” Input: VIL .......................................... 0.80 V max. IIL ............................................ -0.6 mA mA VOH Logic “1” Voltage Out .................................. 2.40 V min. VOL Logic “0” Voltage Out ............................... 0.50 V max. PWI Input Pulse Width ............................. 40% of Delay min. Operating Temperature Range ............................ 0O to 70OC Storage Temperature Range ...................... -65O to +150OC P/N Description FAIDM - XXX X .020 (0.51) TYP. MAX. .250 (6.35) MAX. .100 (2.54) TYP. .015 (0.38) TYP. .030 (0.76) TYP. .265 (6.73) MAX. J-SMD .020 (0.51) TYP. .050 (1.27) TYP. For other values & Custom Designs, contact factory. G-SMD .008 R (0.20) .010 (0.25) TYP. .430 (10.92) .400 (10.16) .285 (7.24) MAX. .785 (19.94) MAX. Examples: FAIDM-25G = 25ns (5ns per tap) 74F, 14-Pin G-SMD FAIDM-100 = 100ns (20ns per tap) 74F, 14-Pin DIP Rhombus Industries Inc. .050 (1.27) TYP. .010 (0.25) TYP. .285 (7.24) G-SMD .020 (0.51) TYP. .300 (7.62) .008 R (0.20) .365 (9.27) MAX. .100 (2.54) TYP. .785 (19.94) MAX. Buffered 5 Tap Delay Molded Package Series: 14-pin DIP: FAIDM Total Delay in nanoseconds (ns) Lead Style: Blank = Thru-hole G = “Gull Wing” SMD J = “J” Bend SMD Specifications subject to change without notice. .050 (1.27) TYP. DIP .100 (2.54) TYP. .030 (0.76) TYP. J-SMD .285 (7.24) .260 (6.60) .020 R (0.51) .330 (8.38) MAX. FAIDM 9901 15801 Chemical Lane, Huntington Beach, CA 92649-1595 Phone: (714) 898-0960 • FAX: (714) 896-0971 www.rhombus-ind.com • email: [email protected]