EPSON Timing Solution for ALTERA FPGA (PCI Express Gen1,2)

EPSON
E
N timing
g soluttion for Altera
a® FPG
GA
Stratix® V
V, Arria
a® V, Cy
yclone® V Tran
nsceive
er PCI E
Express
s® Gen
n1, 2
PCI
P
Expresss® (PCIe®) is a high-s
speed seriall transmission widely adopted in PC, serve
er, FA equip
pment’s,
me
easurement equipment’ss, broadcast products e
etc. FPGAs provide
p
PCIe
e® transceivvers for these applications.
Epson
E
oscilla
ators have been confirm
med as refere
ence clock functionality by actual evvaluations.
<M
Method of refference clocck availabilitty confirm >
1. Connecct Epson osccillator to Alttera Arria® V PCIe® board as reference clock.
2.
2 Measurre PCIe® TX
X output with
h oscilloscop
pe.
3.
3 Calcula
ate BER with
h oscilloscop
pe’s Eye Dia
agram and RMS
R
data.
<B
Basic PCIe T
Transceiver diagram>
d
PCIe Devic
ce
(Parallel
TX
Æ serial)
s
PCIe
e Device
RX
CDR
(Serial Æ parallel)
100MHz Oscillator
O
<B
Basic Measu
urement sche
ematic>
®
®
Altera Arrria V Board
PC
CIe hard IP
TX
Softw
ware CDR
PCIe buss connector
Digitaal Oscilloscope Keysight DSAX
X91604A
External OSC
L 100MHz
LV-PECL
<M
Measuremen
nt scene>
Digital
Pow
ower Supply
Oscilloscope
External OSC
O
LV-PECL 10
00MHz
CBB2
FPGA
A Board
PC
CIe® TX o
oscillato
or measu
urement rresult, PCIe® Transmissio
on performance
Evaluation
E
re
esult of 3 osccillators (XG
G-2102CA, S
SG7050EBN
N, Other). XG
G-2102CA hhas the best performancce.
Oscillator (100MH
Hz Referencee Clock)
BER ((bit error rate
e)
Other oscilllator
XG-2
2102CA
SG7050EBN
S
N
Calculate
ed by RMS jitter
1.2 x 10 -20
1.3 x 10 -27
PCIe Ge
en.1 (2.5 Gb
bps)
7.5
5 x 10 -31 (Best)
7.9 x 10 -08
4.5 x 10 -08
PCIe Ge
en.2 (5 Gb
bps)
2.6
6 x 10 -08 (Best)
1
EPSON
E
N timing
g soluttion for Altera
a® FPG
GA
Stratix® V
V, Arria
a® V, Cy
yclone® V Tran
nsceive
er PCI E
Express
s® Gen
n1, 2
<P
PCIe® Ge
en.1
Da
ata speed
d 2.5 Gbp
ps>
RMS and Eyye Pattern
Eye D
Diagram Jitte
er
RM
MS (Unit : ps))
(2nnd PLL CDR)
XG-2102C
CA
5.56
Oscillator (100MH
Hz referencee Clock)
SG70
050EBN
4.92
4
Other
O
oscillato
or
6.11
Oscillator (100MH
Hz referencee Clock)
SG70
050EBN
7.5 x 10 -31
Other
O
oscillato
or
1.2 x 10 -20
BER (bit error rate) calculated witth RMS.
BER (bit error rate)
Capitula
ated by RMS jitter
(2nnd PLL CDR)
XG-2102C
CA
1.3 x 10 -27
The
T timing period to th
he first errorr occasion.
PCIe® Ge
en.2
<P
(Unit: sec
c).
Da
ata speed
d 5 Gbps
s>
RMS
R
and Eyye Pattern
Eye D
Diagram Jitte
er
RM
MS (Unit : ps))
(2nnd PLL CDR)
XG-2102C
CA
5.29
Oscillator (100MH
Hz referencee Clock)
SG70
050EBN
5.19
5
Other
O
oscillato
or
5.39
Oscillator (100MH
Hz referencee Clock)
SG70
050EBN
2.6 x 10 -08
Other
O
oscillato
or
-08
7.9 x 10
BER (bit error rate) calculated witth RMS.
BER (bit error rate)
Capitula
ated by RMS jitter
(2nnd PLL CDR)
XG-2102C
CA
4.5 x 10 -08
The
T timing period to th
he first errorr occasion.
(Unit: sec
c).
PCI Express, a
and PCIe are th
he registered tra
ademarks of PC
CI-SIG.
Altera, Stratix,, Arria, and Cyclone are the reg
gistered tradema
arks of Altera Corporation.
C
2