ADVANCED MICRO DEVICES
AMD Opteron™ A1100 Series Processor
ACPI Porting Guide
Version 1.00
1/20/2015
Version 1.00 – Jan 20, 2015
Page | 2
AMD Opteron™ 1100 Series Processor
ACPI Porting Guide
Document History
Date
Version
Jan 20, 2015
1.00
Change
Initial release for Seattle RevA0
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
Page | 3
Contents
Contents ........................................................................................................................................................ 3
Introduction .................................................................................................................................................. 4
References .................................................................................................................................................... 6
TO-DO: What’s next in this document? ........................................................................................................ 6
Required ACPI Tables .................................................................................................................................... 7
Appendix A – Sample Description Tables...................................................................................................... 8
Root System Description Pointer Structure (RSD PTR) ............................................................................. 8
Extended System Description Table (XSDT) .............................................................................................. 8
Fixed ACPI Description Table (FADT) ........................................................................................................ 9
Firmware ACPI Control Structure (FACS) ................................................................................................ 11
Multiple APIC Description Table (MADT) ................................................................................................ 12
Generic Timer Description Table (GTDT) ................................................................................................ 17
Debug Port Table 2 (DBG2) ..................................................................................................................... 18
Serial Port Console Redirection Table (SPCR) ......................................................................................... 20
Memory-mapped Configuration-space Table (MCFG)............................................................................ 21
Differentiated System Description Table (DSDT) .................................................................................... 22
Appendix B - Sample DSDT (CPU Cores) ..................................................................................................... 23
Sample DSDT (AHCI and Ethernet).......................................................................................................... 24
Sample DSDT (UART, and SPI) ................................................................................................................. 25
Sample DSDT (GPIO, I2C and CCP) .......................................................................................................... 26
Sample DSDT (PCIe Root bus) ................................................................................................................. 27
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
Page | 4
Introduction
The ACPI (Advanced Configuration and Power Interface) Specification defines a common set of firmware
interfaces between the OS and the hardware platform that enables configuration and power
management of the computer system and its devices. ACPI was co-developed by Hewlett-Packard, Intel,
Microsoft, Phoenix, and Toshiba with the initial specification published in 1996. Since October 2013, the
UEFI Forum has taken the responsibility of developing and maintaining ACPI.
ACPI is a prevalent abstraction method used today for PC, Workstation, and Server platforms. Hardware
manufacturers have products and processes built around ACPI descriptions and are requesting the same
technology between x86 and ARM product offerings.
The intent of this document is to provide guidance on the ACPI interfaces required to support compliant
operating systems running on a platform using an AMD Opteron™ A1100 Series Processor. It represents
definitions AMD has developed based on published specifications and documents (see References
section) in collaboration with firmware and operating systems partners.
Platform firmware must comply with the following requirements:
UEFI must support the EFI_ACPI_20_TABLE_GUID (or later) configuration table.
The pointer to the RSDP is passed via UEFI to the OSPM as described in UEFI 2.4 or later
specification.
The structure of all tables is consistent with the ACPI 5.1 specification.
Use the 64-bit address option for address fields in ACPI tables.
Implement the ACPI Hardware-reduced model.
Support GPIO-signaled events for runtime notifications to the OSPM.
The Operating System directed Power Management (OSPM) on the platform receives a pointer to the
Root System Description Pointer (RSDP) from the boot loader. OSPM then uses the information in the
RSDP to determine the addresses of all other ACPI tables.
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
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Figure 1 – ACPI Description Tables
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
References
[1] Advanced Configuration and Power Interface Specification, Revision 5.1 (ACPI 5.1 Spec)
http://www.uefi.org/ACPIv5.1
[2] ARM Server Base System Architecture (SBSA)
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029/index.html
[3] ARM Server Base Boot Requirements (SBBR)
http://infocenter.arm.com/help/topic/com.arm.doc.den00044a/index.html
[4] Processor Programming Reference (PPR) for AMD Family 20h (PID# 53790)
Access to this document currently requires and NDA with AMD
[5] GIC-400 Generic Interrupt Controller Technical Reference Manual (GIC-400 TRM)
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0471b/index.html
[6] Multi-processor Startup for ARM Platforms
https://acpica.org/sites/acpica/files/MP%20Startup%20for%20ARM%20platforms.doc
[7] Windows ACPI Design Guide for SoC Platforms - Dev Center
http://msdn.microsoft.com/en-us/library/windows/hardware/dn495676(v=vs.85).aspx
TO-DO: What’s next in this document?
APEI Tables: Pending definition of RAS support in Seattle
I/O Remapping Table: Pending definition of spec for SMMU (IORT) table
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
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Required ACPI Tables
The following tables comprise the minimal set required for compliant systems.
1. RSDP - Root System Description Pointer
The RsdtAddress field must be zero, and the XsdtAddress field must be a non-zero 64-bit value.
2. XSDT - Extended System Description Table
Must contain an array of 64-bit addresses that point to all other description tables.
3. FADT - Fixed ACPI Description Table
For legacy reasons the signature field is “FACP”, and does not match the table’s name.
The DSDT field must be zero, and the X_ DSDT field must be a non-zero 64-bit value.
If an FACS table is provided, the FIRMWARE_CTRL field must be zero, and the
X_FIRMWARE_CTRL field must be a non-zero 64-bit value.
The Preferred_PM_Profile field should be set to a server profile (see section 5.2.9.1, ACPI 5.1
Spec [1]).
All SMI and SCI related fields must be set to zero.
All legacy Hardware Register Block fields must be set to zero.
The Flags field must indicate support for HW_REDUCED_ACPI and
LOW_POWER_S0_IDLE_CAPABLE (Seattle does not support S3/S4 states).
4. DSDT - Differentiated System Description Table
This table provides definition blocks (AML code) for devices and system resources.
5. MADT - Multiple APIC Description Table
This table describes the ARM Generic Interrupt Controller (GIC).
6. GTDT - Generic Timer Description Table
This table describes the ARM Generic Timer in the Cortex-A57 cores.
7. DBG2 - Microsoft Debug Port Table 2
http://msdn.microsoft.com/en-us/library/windows/hardware/dn639132(v=vs.85).aspx
8. SPCR - Serial Port Console Redirection Table
http://msdn.microsoft.com/en-us/library/windows/hardware/dn639132(v=vs.85).aspx
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
Page | 8
Appendix A – Sample Description Tables
Root System Description Pointer Structure (RSD PTR)
RSD PTR Structure (36 bytes):
<<RSD PTR >>
Field
Byte
Length
Byte
Offset
Value
Signature
Checksum
OEMID
Revision
RsdtAddress
Length
XsdtAddress
Extended Checksum
Reserved
8
1
6
1
4
4
8
1
3
0
8
9
15
16
20
24
32
33
'RSD PTR '
<checksum>
'AMDINC'
2
0
36
<XSDT Address>
<ext checksum>
0
Extended System Description Table (XSDT)
XSDT Table Format
<<XSDT>>
Field
Byte
Length
Byte
Offset
Value
Signature
Length
Revision
Checksum
OEMID
OEM Table ID
OEM Revision
Creator ID
Creator Revision
Description Header[0]
Description Header[1]
Description Header[2]
Description Header[3]
Description Header[4]
Description Header[5]
4
4
1
1
6
8
4
4
4
8
8
8
8
8
8
0
4
8
9
10
16
24
28
32
36
44
52
60
68
76
'XSDT'
<36+8*n descriptors>
1
<checksum>
'AMDINC'
'SEATTLE '
0
<'AMD '>
< 0 >
<FADT
<MADT
<GTDT
<DBG2
<SPCR
<MCFG
Address>
Address>
Address>
Address>
Address>
Address>
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
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Page | 9
Fixed ACPI Description Table (FADT)
FADT Table Format
<<FACP>>
Field
Byte
Length
Byte
Offset
Value
Signature
Length
Revision (Major Version)
Checksum
OEMID
OEM Table ID
OEM Revision
Creator ID
Creator Revision
FIRMWARE_CTRL
DSDT
Reserved
Preferred_PM_Profile
SCI_INT
SCI_CMD
ACPI_ENABLE
ACPI_DISABLE
S4BIOS_REQ
PSTATE_CNT
PM1a_EVT_BLK
PM1b_EVT_BLK
PM1a_CNT_BLK
PM1b_CNT_BLK
PM2_CNT_BLK
PM_TMR_BLK
GPE0_BLK
GPE1_BLK
PM1_EVT_LEN
PM1_CNT_LEN
PM2_CNT_LEN
PM_TMR_LEN
GPE0_BLK_LEN
GPE1_BLK_LEN
GPE1_BASE
CST_CNT
P_LVL2_LAT
4
4
1
1
6
8
4
4
4
4
4
1
1
2
4
1
1
1
1
4
4
4
4
4
4
4
4
1
1
1
1
1
1
1
1
2
0
4
8
9
10
16
24
28
32
36
40
44
45
46
48
52
53
54
55
56
60
64
68
72
76
80
84
88
89
90
91
92
93
94
95
96
'FACP'
268
5
<checksum>
'AMDINC'
'SEATTLE '
0
<'AMD '>
< 0 >
0
0
0
4 <Enterprise Server>
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
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Page | 10
Field
Byte
Length
Byte
Offset
Value
P_LVL3_LAT
FLUSH_SIZE
FLUSH_STRIDE
DUTY_OFFSET
DUTY_WIDTH
DUTY_ALRM
MON_ALRM
CENTURY
IAPC_BOOT_ARCH
Reserved
FADT Flags
RESET_REG
RESET_VALUE
ARM_BOOT_ARCH
FADT Minor Version
X_FIRMWARE_CTRL
X_DSDT
X_PM1a_EVT_BLK
X_PM1b_EVT_BLK
X_PM1a_CNT_BLK
X_PM1b_CNT_BLK
X_PM2_CNT_BLK
X_PM_TMR_BLK
X_GPE0_BLK
X_GPE1_BLK
SLEEP_CONTROL_REG
SLEEP_STATUS_REG
2
2
2
1
1
1
1
1
2
1
4
12
1
2
1
8
8
12
12
12
12
12
12
12
12
12
12
98
100
102
104
105
106
107
108
109
111
112
116
128
129
131
132
140
148
160
172
184
196
208
220
232
244
256
0
0
0
0
0
0
0
0
0
0
<<FADT Flags>>
<<NULL GAS>>
0
<<ARM_Arch Flags>>
1
<FACS Address>
<DSDT Address>
<<NULL GAS>>
<<NULL GAS>>
<<NULL GAS>>
<<NULL GAS>>
<<NULL GAS>>
<<NULL GAS>>
<<NULL GAS>>
<<NULL GAS>>
<<NULL GAS>>
<<NULL GAS>>
FADT Flags (4 bytes):
<<FADT Flags>>
Field
Bit
Length
Bit
Offset
Value
Various Flags
HEADLESS
Various Flags
HW_REDUCED_ACPI
LOW_POWER_S0_IDLE_CAPABLE
Reserved
12
1
7
1
1
10
0
12
13
20
21
22
0
1
0
1
1
0
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
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ARM_Arch Flags (2 bytes):
<<ARM_Arch Flags>>
Field
Bit
Length
Bit
Offset
Value
PSCI_COMPLIANT
PSCI_USE_HVC
1
1
0
1
Reserved
14
2
1 if PSCI is implemented, else 0
1 if HVC should be preferred to SMC
as the PSCI conduit, else 0
0
NULL Generic Address Structure (12 bytes):
<<NULL GAS>>
Field
Byte
Length
Byte
Offset
Address Space ID
Register Bit Width
Register Bit Offset
Access Size
Address
1
1
1
1
8
0
1
2
3
4
Value
0
0
0
0
0
Firmware ACPI Control Structure (FACS)
FACS Structure Format
<<FACS>>
Field
Byte
Length
Byte
Offset
Value
Signature
Length
Hardware Signature
Firmware Waking Vector
Global Lock
Flags
X_Firmware Waking Vector
Version
Reserved
OSPM Flags
Reserved
4
4
4
4
4
4
8
1
3
4
24
0
4
8
12
16
20
24
32
33
36
40
'FACS'
64
0
0
0
0
0
2
0
0
0
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Page | 12
Multiple APIC Description Table (MADT)
MADT Table Format
<<APIC>>
Field
Byte
Length
Byte
Offset
Value
Signature
Length
Revision
Checksum
OEMID
OEM Table ID
OEM Revision
Creator ID
Creator Revision
Controller Address
APIC Flags
Local GIC[0]
Local GIC[1]
Local GIC[2]
Local GIC[3]
Local GIC[4]
Local GIC[5]
GIC Distributor
GIC MSI Frame
4
4
1
1
6
8
4
4
4
4
4
76
76
76
76
76
76
24
24
0
4
8
9
10
16
24
28
32
36
40
44
120
196
272
348
424
500
524
'APIC'
548
3
<checksum>
'AMDINC'
'SEATTLE '
0
Comments
<'AMD '>
< 0 >
0xE112_F000
0
<<GICC Structure[0]>>
<<GICC Structure[1]>>
<<GICC Structure[2]>>
<<GICC Structure[3]>>
<<GICC Structure[4]>>
<<GICC Structure[5]>>
<<GICD Structure>>
<<GIC MSI Frame>>
PPR [4]
Non PC-AT-compatible
GIC Distributor (GICD) Structure (24 bytes):
<<GICD Structure>>
Field
Byte
Length
Byte
Offset
Value
Comments
Type
Length
Reserved
GICD ID
Physical Base Address
System Vector Base
GIC Version
Reserved
1
1
2
4
8
4
1
3
0
1
2
4
8
16
20
21
0xC
24
0
0
0xE111_0000
0
0x2
0
0xC=GICD (Distributor)
PPR [4]
0x2=GIC2vm
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
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GIC CPU Interface (GICC) Structure[0]:
<<GICC Structure[0]>>
Field
Byte
Offset
0
1
2
4
Value
Comments
Type
Length
Reserved
CPU Interface Number
Byte
Length
1
1
2
4
0xB
76
0
0
0xB=GICC (CPU Interface)
ACPI Processor UID
GICC Flags
Parking Protocol Version
4
4
4
8
12
16
0x0
<<GICC Flags>>
1
Performance Interrupt GSIV
Parked Address
Physical Base Address
GICV Base Address
GICH Base Address
VGIC Maintenance Interrupt
GICVR Base Address
MPIDR
4
8
8
8
8
4
8
8
20
24
32
40
48
56
60
68
39
<set by UEFI>
0xE112_F000
0xE116_F000
0xE114_0000
25
0
0x0
Bit index in distributor’s
GICD_ITARGETSR register
Same as MPIDR value
1=Enabled
Set to 1 for valid Parked
Address
ID39, PPR [4]
SBBR [3]
PPR [4]
PPR [4]
PPR [4]
ID25, GIC-400 TRM [5]
Not used in GICv2m
(ClusterId << 8) + CoreId;
ClusterId=0..3, CoreId=0..1
GIC CPU Interface (GICC) Structure[1]
<<GICC Structure[1]>>
Field
Byte
Offset
0
1
2
4
Value
Comments
Type
Length
Reserved
CPU Interface Number
Byte
Length
1
1
2
4
0xB
76
0
1
0xB=GICC (CPU Interface)
ACPI Processor UID
GICC Flags
Parking Protocol Version
4
4
4
8
12
16
0x1
<<GICC Flags>>
1
Performance Interrupt GSIV
Parked Address
Physical Base Address
GICV Base Address
GICH Base Address
VGIC Maintenance Interrupt
GICVR Base Address
MPIDR
4
8
8
8
8
4
8
8
20
24
32
40
48
56
60
68
40
<set by UEFI>
0xE112_F000
0xE116_F000
0xE114_0000
25
0
0x1
Bit index in distributor’s
GICD_ITARGETSR register
Same as MPIDR value
1=Enabled
Set to 1 for valid Parked
Address
ID40, PPR [4]
SBBR [3]
PPR [4]
PPR [4]
PPR [4]
ID25, GIC-400 TRM [5]
Not used in GICv2m
(ClusterId << 8) + CoreId;
ClusterId=0..3, CoreId=0..1
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Page | 14
GIC CPU Interface (GICC) Structure[2]:
<<GICC Structure[2]>>
Field
Byte
Offset
0
1
2
4
Value
Comments
Type
Length
Reserved
CPU Interface Number
Byte
Length
1
1
2
4
0xB
76
0
2
0xB=GICC (CPU Interface)
ACPI Processor UID
GICC Flags
Parking Protocol Version
4
4
4
8
12
16
0x100
<<GICC Flags>>
1
Performance Interrupt GSIV
Parked Address
Physical Base Address
GICV Base Address
GICH Base Address
VGIC Maintenance Interrupt
GICVR Base Address
MPIDR
4
8
8
8
8
4
8
8
20
24
32
40
48
56
60
68
41
<set by UEFI>
0xE112_F000
0xE116_F000
0xE114_0000
25
0
0x100
Bit index in distributor’s
GICD_ITARGETSR register
Same as MPIDR value
1=Enabled
Set to 1 for valid Parked
Address
ID41, PPR [4]
SBBR [3]
PPR [4]
PPR [4]
PPR [4]
ID25, GIC-400 TRM [5]
Not used in GICv2m
(ClusterId << 8) + CoreId;
ClusterId=0..3, CoreId=0..1
GIC CPU Interface (GICC) Structure[3]
<<GICC Structure[3]>>
Field
Byte
Offset
0
1
2
4
Value
Comments
Type
Length
Reserved
CPU Interface Number
Byte
Length
1
1
2
4
0xB
76
0
3
0xB=GICC (CPU Interface)
ACPI Processor UID
GICC Flags
Parking Protocol Version
4
4
4
8
12
16
0x101
<<GICC Flags>>
1
Performance Interrupt GSIV
Parked Address
Physical Base Address
GICV Base Address
GICH Base Address
VGIC Maintenance Interrupt
GICVR Base Address
MPIDR
4
8
8
8
8
4
8
8
20
24
32
40
48
56
60
68
42
<set by UEFI>
0xE112_F000
0xE116_F000
0xE114_0000
25
0
0x101
Bit index in distributor’s
GICD_ITARGETSR register
Same as MPIDR value
1=Enabled
Set to 1 for valid Parked
Address
ID42, PPR [4]
SBBR [3]
PPR [4]
PPR [4]
PPR [4]
ID25, GIC-400 TRM [5]
Not used in GICv2m
(ClusterId << 8) + CoreId;
ClusterId=0..3, CoreId=0..1
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Page | 15
GIC CPU Interface (GICC) Structure[4]:
<<GICC Structure[4]>>
Field
Byte
Offset
0
1
2
4
Value
Comments
Type
Length
Reserved
CPU Interface Number
Byte
Length
1
1
2
4
0xB
76
0
4
0xB=GICC (CPU Interface)
ACPI Processor UID
GICC Flags
Parking Protocol Version
4
4
4
8
12
16
0x200
<<GICC Flags>>
1
Performance Interrupt GSIV
Parked Address
Physical Base Address
GICV Base Address
GICH Base Address
VGIC Maintenance Interrupt
GICVR Base Address
MPIDR
4
8
8
8
8
4
8
8
20
24
32
40
48
56
60
68
43
<set by UEFI>
0xE112_F000
0xE116_F000
0xE114_0000
25
0
0x200
Bit index in distributor’s
GICD_ITARGETSR register
Same as MPIDR value
1=Enabled
Set to 1 for valid Parked
Address
ID43, PPR [4]
SBBR [3]
PPR [4]
PPR [4]
PPR [4]
ID25, GIC-400 TRM [5]
Not used in GICv2m
(ClusterId << 8) + CoreId;
ClusterId=0..3, CoreId=0..1
GIC CPU Interface (GICC) Structure[5]
<<GICC Structure[5]>>
Field
Byte
Offset
0
1
2
4
Value
Comments
Type
Length
Reserved
CPU Interface Number
Byte
Length
1
1
2
4
0xB
76
0
5
0xB=GICC (CPU Interface)
ACPI Processor UID
GICC Flags
Parking Protocol Version
4
4
4
8
12
16
0x201
<<GICC Flags>>
1
Performance Interrupt GSIV
Parked Address
Physical Base Address
GICV Base Address
GICH Base Address
VGIC Maintenance Interrupt
GICVR Base Address
MPIDR
4
8
8
8
8
4
8
8
20
24
32
40
48
56
60
68
44
<set by UEFI>
0xE112_F000
0xE116_F000
0xE114_0000
25
0
0x201
Bit index in distributor’s
GICD_ITARGETSR register
Same as MPIDR value
1=Enabled
Set to 1 for valid Parked
Address
ID44, PPR [4]
SBBR [3]
PPR [4]
PPR [4]
PPR [4]
ID25, GIC-400 TRM [5]
Not used in GICv2m
(ClusterId << 8) + CoreId;
ClusterId=0..3, CoreId=0..1
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Version 1.00 – Jan 20, 2015
Page | 16
GICC Flags (4 bytes):
<<GICC Flags>>
Field
Bit
Length
Bit
Offset
Value
Comments
Processor Enabled
Performance Interrupt Mode
VGIC Maintenance Interrupt Mode
Reserved
1
1
1
29
0
1
2
3
1
0
0
0
0=Level-Trigger, 1=Edge-Trigger
0=Level-Trigger, 1=Edge-Trigger
GIC MSI Frame Structure (24 bytes):
<<GIC MSI Frame>>
Field
Byte
Length
Byte
Offset
Value
Comments
Type
Length
Reserved
GIC MSI Frame ID
Physical Base Address
Flags
SPI Count
SPI Base
1
1
2
4
8
4
2
2
0
1
2
4
8
16
20
22
0xD
24
0
0
0xE118_0000
<<MSI Frame Flags>>
256
64
0xD (MSI Frame)
PPR [4]
1=Use SPI Count/Base fields
MSI Frame Flags (4 bytes):
<<MSI Frame Flags>>
Field
Bit
Length
Bit
Offset
Value
Comments
SPI Count/Base Select
1
0
1
0=Ignore SPI Count/Base fields,
and use MSI_TYPER register.
1=Ignore MSI_TYPER register, and
use SPI Count/Base fields.
Reserved
31
1
0
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
Page | 17
Generic Timer Description Table (GTDT)
GTDT Table Format:
<<GTDT>>
Field
Byte
Length
Byte
Offset
Value
Comments
Signature
Length
Revision
Checksum
OEMID
OEM Table ID
OEM Revision
Creator ID
Creator Revision
CntControlBase Address
Reserved
Secure EL1 Timer GSIV
Secure EL1 Timer Flags
Non-Secure EL1 Timer GSIV
Non-Secure EL1 Timer Flags
Virtual Timer GSIV
Virtual Timer Flags
Non-Secure EL2 Timer GSIV
Non-Secure EL2 Timer Flags
CntReadBase Address
Platform Timer Count
Platform Timer Offset
4
4
1
1
6
8
4
4
4
8
4
4
4
4
4
4
4
4
4
8
4
4
0
4
8
9
10
16
24
28
32
36
44
48
52
56
60
64
68
72
76
80
88
92
'GTDT'
96
2
<checksum>
'AMDINC'
'SEATTLE '
0
<'AMD '>
< 0 >
0xFFFF_FFFF_FFFF_FFFF
0
29
<<Timer Flags>>
30
<<Timer Flags>>
27
<<Timer Flags>>
26
<<Timer Flags>>
0
0
0
All 0xF’s (Optional)
ID29, GIC-400 TRM
<Timer Flags>
ID30, GIC-400 TRM
<Timer Flags>
ID27, GIC-400 TRM
<Timer Flags>
ID26, GIC-400 TRM
<Timer Flags>
No CntReadBase
No SBSA Timers
Table offset
Timer Flags: Secure & Non-Secure EL1, Virtual & Non-Secure EL2 (4 bytes):
<<Timer Flags>>
Field
Bit
Length
Bit
Offset
Value
Comments
Timer Interrupt Mode
Timer Interrupt Polarity
Always-On Capability
Reserved
1
1
1
29
0
1
2
3
0
0
0
0
0=Level-Trigger, 1=Edge-Trigger
0=Active-High, 1=Active-Low
0=May lose context, 1=Context saved
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
[5]
[5]
[5]
[5]
Version 1.00 – Jan 20, 2015
Page | 18
Debug Port Table 2 (DBG2)
DBG2 Table Format
<<DBG2>>
Field
Byte
Length
Byte
Offset
Value
Signature
Length
Revision
Checksum
OEMID
OEM Table ID
OEM Revision
Creator ID
Creator Revision
OffsetDbgDeviceInfo
NumberDbgDeviceInfo
DbgDeviceInfo
4
4
1
1
6
8
4
4
4
4
4
46
0
4
8
9
10
16
24
28
32
36
40
44
'DBG2'
90
0
<checksum>
'AMDINC'
'SEATTLE '
0
<'AMD '>
< 0 >
44
1
<<DbgDeviceInfo>>
DBG Device Information Structure (46 bytes):
<<DbgDeviceInfo>>
Field
Byte
Length
Byte
Offset
Value
Revision
Length
NumberofGenericAddressRegisters
NameSpaceStringLength
NameSpaceStringOffset
OemDataLength
OemDataOffset
Port Type
Port Subtype
1
2
1
2
2
2
2
2
2
0
1
3
4
6
8
10
12
14
0
46
1
8
38
0
0
0x8000
0x0003
Reserved
BaseAddressRegisterOffset
AddressSizeOffset
BaseAddressRegister[0]
AddressSize[]
NamespaceString[]
2
2
2
12
4
8
16
18
20
22
34
38
0
22
34
<<DBG GAS>>
4096
“COM1”
Comments
DBG2 Spec: Serial
DBG2 Spec: ARM
PL011 UART
ASCIIZ String
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Version 1.00 – Jan 20, 2015
Page | 19
DBG Generic Address Structure (12 bytes):
<<DBG GAS>>
Field
Byte
Length
Byte
Offset
Address Space ID
Register Bit Width
Register Bit Offset
Access Size
Address
1
1
1
1
8
0
1
2
3
4
Value
0
32
0
3
0xE101_0000
Comments
System Memory
32-bit
Dword (32-bit)
PPR [4]
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Page | 20
Serial Port Console Redirection Table (SPCR)
SPCR Table Format
<<SPCR>>
Field
Byte
Offset
0
4
8
9
10
16
24
28
32
36
37
40
52
53
54
Value
Signature
Length
Revision
Checksum
OEMID
OEM Table ID
OEM Revision
Creator ID
Creator Revision
Interface Type
Reserved
Base Address
Interrupt Type
IRQ
Global System Interrupt
Byte
Length
4
4
1
1
6
8
4
4
4
1
3
12
1
1
4
Baud Rate
Parity
Stop Bits
Flow Control
Terminal Type
Reserved
PCI Device ID
PCI Vendor ID
PCI Bus Number
PCI Device Number
PCI Function Number
PCI Flags
PCI Segment
Reserved
1
1
1
1
1
1
2
2
1
1
1
4
1
4
58
59
60
61
62
63
64
66
68
69
70
71
75
76
7
0
1
0
3
0
0xFFFF
0xFFFF
0
0
0
0
0
0
'SPCR'
80
2
<checksum>
'AMDINC'
'SEATTLE '
0
<'AMD '>
< 0 >
0x03
0
<<GAS>>
0x08
0
360
Comments
DBG2 Spec: ARM PL011 UART
Must be 0
PPR [4]
Bit[3] ARMH GIC (GSIV)
(328 + 32)
PPR [4] (IRQS_328)
SPCR Spec: 7 = 115200
SPCR Spec: 0 = No Parity
SPCR Spec: 1 = 1 Stop-bit
SPCR Spec: 0 = None
SPCR Spec: 3 = ANSI
Must be 0
Not a PCI device
Not a PCI device
Not a PCI device
Not a PCI device
Not a PCI device
Must be 0
Generic Address Structure (12 bytes):
<<GAS>>
Field
Address Space ID
Register Bit Width
Register Bit Offset
Access Size
Address
Byte
Length
1
1
1
1
8
Byte
Offset
0
1
2
3
4
Value
0
32
0
3
0xE101_0000
Comments
System Memory
32-bit
Dword (32-bit)
PPR [4]
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
Page | 21
Memory-mapped Configuration-space Table (MCFG)
MCFG Table Format
<<MCFG>>
Field
Byte
Length
Byte
Offset
Value
Signature
Length
Revision
Checksum
OEMID
OEM Table ID
OEM Revision
Creator ID
Creator Revision
Reserved
ConfigSpace Structure[]
4
4
1
1
6
8
4
4
4
8
24
0
4
8
9
10
16
24
28
32
36
44
'MCFG'
60
1
<checksum>
'AMDINC'
'SEATTLE '
0
<'AMD '>
< 0 >
0
<<CfgSpace>>
Configuration-space Structure Format
<<CfgSpace>>
Field
Byte
Length
Byte
Offset
Value
Comments
Base Address
PCI Segment Group Number
Start Bus Number
Start End Number
Reserved
8
2
1
1
4
0
8
10
11
12
0xF000_0000
0
0
15
0
PPR [4]
PPR [4]
PPR [4]
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Page | 22
Differentiated System Description Table (DSDT)
DSDT Table Format
<<DSDT>>
Field
Byte
Length
Byte
Offset
Value
Signature
Length
Revision
Checksum
OEMID
OEM Table ID
OEM Revision
Creator ID
Creator Revision
Definition Block[0]
4
4
1
1
6
8
4
4
4
n
0
4
8
9
10
16
24
28
32
36
'DSDT'
<36 + n bytes of AML code>
1
<checksum>
'AMDINC'
'SEATTLE '
0
<ASL Compiler ID>
<ASL Compiler Revision>
<n bytes of AML Code>
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
Page | 23
Appendix B - Sample DSDT (CPU Cores)
DefinitionBlock ("dsdt.aml", "DSDT", 1, "AMDINC", "SEATTLE ", 3)
{
Scope (_SB)
{
Device (CPU0)
{
Name (_HID, "ACPI0007")
// Hardware ID
Name (_UID, 0x000)
// Unique ID
}
Device (CPU1)
{
Name (_HID, "ACPI0007")
Name (_UID, 0x001)
}
Device (CPU2)
{
Name (_HID, "ACPI0007")
Name (_UID, 0x100)
}
Device (CPU3)
{
Name (_HID, "ACPI0007")
Name (_UID, 0x101)
}
Device (CPU4)
{
Name (_HID, "ACPI0007")
Name (_UID, 0x200)
}
Device (CPU5)
{
Name (_HID, "ACPI0007")
Name (_UID, 0x201)
}
// Hardware ID
// Unique ID
// Hardware ID
// Unique ID
// Hardware ID
// Unique ID
// Hardware ID
// Unique ID
// Hardware ID
// Unique ID
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
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Sample DSDT (AHCI and Ethernet)
Device (AHC0) // AHCI Controller
{
Name(_HID, "AMDI0600")
// Seattle AHCI/SATA
Name (_CCA, 1)
// Cache-coherent controller
Name (_CLS, Package (3)
{
0x01,
// Base Class: Mass Storage
0x06,
// Sub-Class: Serial ATA
0x01,
// Interface: AHCI
})
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xE0300000, 0x00010000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 387 } // GSIV
}) // ResourceTemplate()
} // Device()
Device (ETH0) // Ethernet
{
Name(_HID, "AMDI8000")
// Seattle XGMAC
Name(_UID, 0)
Name (_CCA, 1)
// Cache-coherent controller
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xE0700000, 0x00010000) // XGMAC
Memory32Fixed (ReadWrite, 0xE0780000, 0x00080000) // XPCS
Memory32Fixed (ReadWrite, 0xE1240800, 0x00000400) // SERDES_RxTx
Memory32Fixed (ReadWrite, 0xE1240000, 0x00000800) // SERDES_CMU
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 357 } //XGMAC
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 355 } // XPCS
}) // ResourceTemplate()
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) {"mac-address", Package (6) { 0, 0, 0, 0, 0, 0 }},
Package (2) {"phy-mode", "xgmii"},
Package (2) {"amd,serdes-channel", 0},
Package (2) {"amd,speed-set", 0},
Package (2) {"amd,dma-freq", 250000000},
Package (2) {"amd,ptp-freq", 250000000}
}
}) // _DSD()
} // Device()
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
Page | 25
Sample DSDT (UART, and SPI)
Device(COM1)
// Generic UART
{
Name(_HID, "AMDI0511”)
Name(_CID, "ARMH0011")
Name (_ADR, 0xE1010000)
Name(_CRS, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xE1010000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 360 } // GSIV
})
}
Device (SPI0) // SPI controller
{
Name(_HID, "AMDI0500")
Name(_UID, 0)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xE1020000, 0x1000) // GPIO Base Address
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 362 } //GSIV
})
} // Device()
Device (SPI1) // SPI controller
{
Name(_HID, "AMDI0500")
Name(_UID, 1)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xE1030000, 0x1000) // GPIO Base Address
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 361 } //GSIV
})
Device(SDC0)
{
Name(_HID, "AMDI0501") // SD Card/MMC slot
Name(_CRS, ResourceTemplate() {
SPISerialBus(1,
// DeviceSelection
PolarityLow,
// DeviceSelectionPolarity
FourWireMode,
// WireMode
8,
// DataBitLength
ControllerInitiated,
// SlaveMode
20000000,
// ConnectionSpeed
ClockPolarityLow,
// ClockPolarity
ClockPhaseFirst,
// ClockPhase
“\\SB.SPI1”,
// ResourceSource
0,
// ResourceSourceIndex
ResourceConsumer,
// ResourceUsage
) // SPISerialBus()
// SD Card “Presence” signal
GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullDown, , "\\_SB.GIO0") {7}
}) // ResourceTemplate()
} // Device()
} // Device()
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Page | 26
Sample DSDT (GPIO, I2C and CCP)
Device (GIO0)
// GPIO controller
{
Name(_HID, "AMDI0400")
Name(_UID, 0)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xE1040000, 0x1000) // GPIO Base Address
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 391 } //GSIV
})
} // Device()
Device (GIO1) // GPIO controller
{
Name(_HID, "AMDI0400")
Name(_UID, 1)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xE1050000, 0x1000) // GPIO Base Address
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 390 } //GSIV
})
} // Device()
Device(I2C0)
// I2C controller
{
Name(_HID, "AMDI0510")
Name(_CRS, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xE1000000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 389 } // GSIV
})
}
Device (CCP0) // Crypto Co-Processor
{
Name(_HID, "AMDI0C00")
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xE0100000, 0x10000) // GPIO Base Address
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 35 } //GSIV
})
} // Device()
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Sample DSDT (PCIe Root bus)
//
// PCIe Root bus
//
Device (PCI0)
{
Name (_HID, "PNP0A08")
Name (_CID, "PNP0A03")
Name(_SEG, 0)
Name(_BBN, 0)
Name (_CCA, 1)
//
//
//
//
//
PCI Express Root Bridge
Compatible PCI Root Bridge
Segment of this Root complex
Base Bus Number
Cache-coherent bus
Name(_PRT, Package(4) {
// PCI
Package(4) {0x000000FFFF, 0, 0,
Package(4) {0x000000FFFF, 1, 0,
Package(4) {0x000000FFFF, 2, 0,
Package(4) {0x000000FFFF, 3, 0,
})
Routing Table
320}, // A
321}, // B
322}, // C
323} // D
Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0,
// AddressGranularity
0,
// AddressMinimum - Minimum Bus Number
15,
// AddressMaximum - Maximum Bus Number
0,
// AddressTranslation - Set to 0
16
// RangeLength - Number of Busses
)
DWordMemory ( // 32-bit BAR Windows (1-1.5G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
0x40000000, // Min Base Address
0x5FFFFFFF, // Max Base Address
0x00000000, // Translate
0x20000000 // Length
)
DWordMemory ( // 32-bit BAR Windows (1.5-2G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
0x60000000, // Min Base Address
0x7FFFFFFF, // Max Base Address
0x00000000, // Translate
0x20000000 // Length
)
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
DWordMemory ( // 32-bit BAR Windows (2-2.5G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
0x80000000, // Min Base Address
0x9FFFFFFF, // Max Base Address
0x00000000, // Translate
0x20000000 // Length
)
DWordMemory ( // 32-bit BAR Windows (2.5G-3G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
0xA0000000, // Min Base Address
0xBFFFFFFF, // Max Base Address
0x00000000, // Translate
0x20000000 // Length
)
QWordMemory ( // 64-bit BAR Windows (4-8G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000100000000, // Min Base Address
0x00000001FFFFFFFF, // Max Base Address
0x0000000000000000, // Translate
0x0000000100000000 // Length
)
QWordMemory ( // 64-bit BAR Windows (8-16G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000200000000, // Min Base Address
0x00000003FFFFFFFF, // Max Base Address
0x0000000000000000, // Translate
0x0000000200000000 // Length
)
QWordMemory ( // 64-bit BAR Windows (16-32G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000400000000, // Min Base Address
0x00000007FFFFFFFF, // Max Base Address
0x0000000000000000, // Translate
0x0000000400000000 // Length
)
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Version 1.00 – Jan 20, 2015
QWordMemory ( // 64-bit BAR Windows (32-64G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000800000000, // Min Base Address
0x0000000FFFFFFFFF, // Max Base Address
0x0000000000000000, // Translate
0x0000000800000000 // Length
)
QWordMemory ( // 64-bit BAR Windows (64-128G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000001000000000, // Min Base Address
0x0000001FFFFFFFFF, // Max Base Address
0x0000000000000000, // Translate
0x0000001000000000 // Length
)
QWordMemory ( // 64-bit BAR Windows (128-256G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000002000000000, // Min Base Address
0x0000003FFFFFFFFF, // Max Base Address
0x0000000000000000, // Translate
0x0000002000000000 // Length
)
QWordMemory ( // 64-bit BAR Windows (256-512G)
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000004000000000, // Min Base Address
0x0000007FFFFFFFFF, // Max Base Address
0x0000000000000000, // Translate
0x0000004000000000 // Length
)
}) // Name(RBUF)
Return (RBUF)
} // Method(_CRS)
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Version 1.00 – Jan 20, 2015
//
// OS Control Handoff
//
Name(SUPP,0) // PCI _OSC Support Field value
Name(CTRL,0) // PCI _OSC Control Field value
Method(_OSC, 4) {
CreateDWordField(Arg3, 0, CDW1)
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
CreateDWordField(Arg3,4,CDW2)
CreateDWordField(Arg3,8,CDW3)
Store(CDW2,SUPP)
Store(CDW3,CTRL)
If (LNotEqual(And(SUPP, 0x16), 0x16)) {
And(CTRL,0x1E,CTRL)
}
And(CTRL,0x1D,CTRL)
If (LNotEqual(Arg1,One)) {
Or(CDW1,0x08,CDW1)
}
If (LNotEqual(CDW3,CTRL)) {
Or(CDW1,0x10,CDW1)
}
Store(CTRL,CDW3)
Return (Arg3)
} Else {
Or(CDW1,4,CDW1)
Return (Arg3)
}
} // Method(_OSC)
//
// Device-Specific Methods
//
Method(_DSM, 0x4, NotSerialized) {
If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
switch (ToInteger(Arg2)) {
//
// Function 0: Return supported functions
case(0) {
Return (Buffer() {0xFF})
}
//
// Function 1: Return PCIe Slot Information
//
case(1) {
Return (Package(2) {
One, // Success
Package(3) {
0x1, // x1 PCIe link
0x1, // PCI express card slot
0x1
// WAKE# signal supported
}
})
}
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Page | 30
Version 1.00 – Jan 20, 2015
//
// Function 2: Return PCIe Slot Number.
//
case(2) {
Return (Package(1) {
Package(4) {
2, // Source ID
4, // Token ID: ID refers to a slot
0, // Start bit of the field to use.
7
// End bit of the field to use.
}
})
}
//
// Function 3: Return Vendor-specific Token ID Strings.
//
case(3) {
Return (Package(0) {}) // TO-DO: Fill this in
}
//
// Function 4: Return PCI Bus Capabilities
//
case(4) {
Return (Package(2) {
One, // Success
Buffer() {
1,0,
// Version
0,0,
// Status, 0:Success
24,0,0,0,
// Length
1,0,
// PCI
16,0,
// Length
0,
// Attributes
0x0D,
// Current Speed/Mode
0x3F,0,
// Supported Speeds/Modes
0,
// Voltage
0,0,0,0,0,0,0
// Reserved
}
})
}
//
// Function 5: Return Ignore PCI Boot Configuration
//
case(5) {
Return (Package(1) {1})
}
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Page | 32
//
// Function 6: Return LTR Maximum Latency
//
case(6) {
Return (Package(4) {
// TO-DO: Fill these in
Package(1){0}, // Maximum Snoop Latency Scale
Package(1){0}, // Maximum Snoop Latency Value
Package(1){0}, // Maximum No-Snoop Latency Scale
Package(1){0}
// Maximum No-Snoop Latency Value
})
}
//
// Function 7: Return PCI Express Naming
//
case(7) {
Return (Package(2) {
Package(1) {0},
Package(1) {Unicode("PCI0")}
})
}
//
// Not supported
//
default {
}
}
}
Return (Buffer(){0})
} // Method(_DSM)
//
// Root Complex 0
//
Device (RP0) {
Name(_ADR, 0xF0000000)
}
} // Device(PCI0)
// Dev 0, Func 0
} // Scope()
} // DefinitionBlock()
AMD Opteron™ A1100 Series Processor ACPI Porting Guide
Version 1.00 – Jan 20, 2015
Page | 33
© 2014 Advanced Micro Devices, Inc. All rights reserved.
DISCLAIMER
The information contained herein is for informational purposes only, and is subject to change without
notice. While every precaution has been taken in the preparation of this document, it may contain
technical inaccuracies, omissions and typographical errors, and AMD is under no obligation to update or
otherwise correct this information. Advanced Micro Devices, Inc. makes no representations or warranties
with respect to the accuracy or completeness of the contents of this document, and assumes no liability
of any kind, including the implied warranties of non-infringement, merchantability or fitness for particular
purposes, with respect to the operation or use of AMD hardware, software or other products described
herein. No license, including implied or arising by estoppel, to any intellectual property rights is granted
by this document. Terms and limitations applicable to the purchase or use of AMD’s products are as set
forth in a signed agreement between the parties or in AMD's Standard Terms and Conditions of Sale.
Trademarks
AMD, the AMD Arrow logo, AMD Catalyst, AMD Opteron and combinations thereof are trademarks of
Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes
only and may be trademarks of their respective owners.
ARM is a registered trademark of ARM Limited.
PCIe is a registered trademark of PCI-SIG Corporation.
AMD Opteron™ A1100 Series Processor ACPI Porting Guide