AS8E128K32

EEPROM
AS8E128K32
128K x 32 EEPROM
PIN ASSIGNMENT
EEPROM Memory Array
(Top View)
66 Lead PGA
AVAILABLE AS MILITARY
SPECIFICATIONS
•
•
(Pins 8, 21, 28, 39 are no connects on the PN package)
SMD 5962-94585
MIL-STD-883
FEATURES
OPTIONS
•
•
66 Lead PGA
(Pins 8, 21, 28, 39 are grounds on the P package)
MARKINGS
Timing
120 ns
140 ns
150 ns
200 ns
250 ns
300 ns
Package
Ceramic Quad Flat Pack
Ceramic Quad Flat Pack
Pin Grid Array- 8 Series
Pin Grid Array- 8 Series
-120
-140
-150
-200
-250
-300
68 Lead CQFP
Q
Q3
P
PN
4
•
•
•
•
Access times of 120, 140, 150, 200, 250, and 300 ns
Built in decoupling caps for low noise operation
Organized as 128K x32; User configurable
as 256K x16 or 512K x8
Operation with single 5 volt supply
Low power CMOS
TTL Compatible Inputs and Outputs
Operating Temperature Ranges:
Military: -55oC to +125oC
Industrial: -40oC to +85oC
3
•
•
•
GENERAL DESCRIPTION
The AS8E128K32 is a 4 Megabit EEPROM Module organized
as 128K x 32 bit. User configurable to 256K x16 or 512Kx 8. The
module achieves high speed access, low power consumption and high
reliability by employing advanced CMOS memory technology.
The military grade product is manufactured in compliance to the
SMD and MIL-STD 883, making the AS8E128K32 ideally suited for
military or space applications.
The module is offered in a 1.075 inch square ceramic pin grid
array substrate. This package design provides the optimum space
saving solution for boards that accept through hole packaging.
The module is also offered as a 68 lead 0.990 inch square ceramic
quad flat pack. It has a max. height of 0.200 inch. This package design is targeted for those applications which require low profile SMT
Packaging.
For more products and information
please visit our web site at
www.micross.com
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
1
EEPROM
AS8E128K32
of the last byte written will result in the complement of the written data
to be presented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle may begin.
DATA Polling may begin at anytime during the write cycle.
DEVICE IDENTIFICATION
An extra 128 bytes of EEPROM memory is available on each
die for user identification. By raising A9 to 12V + 0.5V and using
address locations 1FF80H to 1FFFFH the bytes may be written to
or read from in the same manner as the regular memory array.
TOGGLE BIT
In addition to DATA Polling the module provides another method
for determining the end of a write cycle. During the write operation,
successive attempts to read data from the device will result in I/O6
of the accessed die toggling between one and zero. Once the write
has completed, I/O6 will stop toggling and valid data will be read.
Reading the toggle bit may begin at any time during the write cycle.
DEVICE OPERATION
The 128K x 32 EEPROM memory solution is an electrically
erasable and programmable memory module that is accessed like a
Static RAM for the read or write cycle without the need for external
components. The device contains a 128-byte-page register to allow
writing of up to 128 bytes of data simultaneously. During a write cycle,
the address and 1 to 128 bytes of data are internally latched, freeing
the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched
data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.
DATA PROTECTION
If precautions are not taken, inadvertent writes may occur during
transitions of the host power supply. The E2 module has incorporated
both hardware and software features that will protect the memory
against inadvertent writes.
READ
HARDWARE PROTECTION
The memory module is accessed like a Static RAM. When CE\
and OE\ are low and WE\ is High, the data stored at the memory location determined by the address pins is asserted on the outputs. The
module can be read as a 32 bit, 16 bit or 8 bit device. The outputs are
put in the high impedance state when either CE\ or OE\ is high. This
dual-line control gives designers flexibility in preventing bus contention in their system.
Hardware features protect against inadvertent writes to the module
in the following ways: (a) Vcc sense - if Vcc is below 3.8 V (typical)
the write function is inhibited; (b) Vcc power-on delay - once Vcc has
reached 3.8 V the device will automatically time out 5 ms (typical)
before allowing a write; (c) write inhibit - holding any one of OE\ low,
CE\ high or WE\ high inhibits write cycles; (d) noise filter - pulses of
less than 15 ns (typical) on the WE\ or CE\ inputs will not initiate a
write cycle.
BYTE WRITE
A low pulse on the WE\ or CE\ input with CE\ or WE\ low (respectively) and OE\ high initiates a write cycle. The address is latched
on the falling edge of CE\ or WE\, whichever occurs last. The data is
latched by the first rising edge of CE\ or WE\. Once a BWDW (byte,
word or double word) write has been started it will automatically time
itself to completion.
SOFTWARE DATA PROTECTION
A software controlled data protection feature has been implemented on the memory module. When enabled, the software data
protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user and is shipped with SDP disabled, SDP is enabled by the host system issuing a series of three write
commands; three specific bytes of data are written to three specific
addresses (refer to Software Data Protection Algorithm). After writing
the three byte command sequence and after tWC the entire module will
be protected from inadvertent write operations. It should be noted,
that once protected the host may still perform a byte of page write to
the module. This is done by preceding the data to be written by the
same three byte command sequence used to enable SDP. Once set,
SDP will remain active unless the disable command sequence is issued.
Power transitions do not disable SDP and SDP will protect the 128K x
32 EEPROM during power-up and Power-down conditions. All command sequences must conform to the page write timing specifications.
The data in the enable and disable command sequences is not written
to the device and the memory addresses used in the sequence may be
written with data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the
three byte command sequence will start the internal write timers. No
data will be written to the device; however, for the duration of tWC,
read operations will effectively be polling operations.
PAGE WRITE
The page write operation of the 128K x 32 EEPROM allows 1
to 128 BWDWs of data to be written into the device during a single
internal programming period. Each new BWDW must be written
within 150-μ sec (tBLC) of the previous BWDW. If the tBLC limit is
exceeded the memory module will cease accepting data and commence
the internal programming operation. For each WE high to low transition during the page write operation, A7-A16 must be the same.
The A0-A6 inputs are used to specify which bytes within the page
are to be written. The bytes may be loaded in any order and may be
altered within the same load period. Only bytes which are specified
for writing will be written; unnecessary cycling of other bytes within
the page does not occur.
DATA POLLING
This memory module features DATA Polling to indicate the end
of a write cycle. During a byte or page write cycle an attempted read
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
2
EEPROM
AS8E128K32
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
Vcc .......................................................................-.5V to +7.0V
Storage Temperature ....................... ....................-65°C to +150°C
Voltage on any Pin Relative to Vss.....................-.5V to Vcc+1 V
Max Junction Temperature**............................................+150°C
Thermal Resistance junction to case (θJC):
Package Type Q...............................................11.3° C/W
Package Type P & PN.......................................2.8° C/W
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
**Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow, and humidity (plastics).
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V + 10%)
μΑ
μΑ
PARAMETER
Power Supply Current:
Operating
Power Supply Current:
Standby
AS8E128K32
Rev. 8.2 07/10
CONDITIONS
CE\<VIL; VCC=MAX,
SYM
MAX
For All Speed Options UNITS
Icc
250
mA
CE\>VIH; All Other Inputs
<VIL or >VIH; VCC=MAX,
f =0 Hz
ISBT1
15
mA
CE\>VCC-0.2V; VCC=MAX,
VIL<VSS +0.2V or
VIH>VCC -0.2V; f = 0 Hz
ISBT2
1
mA
CE\=VCC, OE\=VIH;
I/O 0 through 31 = open;
Input=VCC=5.5Vdc.;
A0 through A16 change at 5 MHz;
CMOS levels
ISBT3
5
mA
f = MAX = 1/tRC (MIN)
Outputs Open
Micross Components reserves the right to change products or specifications without notice.
3
EEPROM
AS8E128K32
CAPACITANCE TABLE1 (VIN = 0V, f = 1 MHz, TA = 25oC)
SYMBOL
CADD
PARAMETER
A0 - A16 Capacitance
MAX
40
UNITS
pF
COE
OE\ Capacitance
40
pF
CWE, CCE
WE\ and CE\ Capacitance
10
pF
CIO
I/O 0- I/O 31 Capacitance
12
pF
NOTE: 1. This parameter is guaranteed but not tested.
TRUTH TABLE
MODE
Read
CE
VIL
OE
VIL
WE
VIH
I/O
DOUT
Write (2)
VIL
VIH
VIL
DIN
Standby/Write
X
VIH
High Z
VIH
X (1)
Write Inhibit
X
Write Inhibit
X
X
VIL
Output Disable
X
VIH
X
X
High Z
NOTES: 1. X can be VIL or VIH
2. Refer to AC Programming Waveforms
AC TEST CONDITIONS
TEST SPECIFICATIONS
Input pulse levels...........................................VSS to 3V
Input rise and fall times...........................................5ns
Input timing reference levels.................................1.5V
Output reference levels.........................................1.5V
Output load................................................See Figure 1
Figure 1
NOTES:
Vz is programmable from -2V to + 7V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load
circuit.
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
4
EEPROM
AS8E128K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 5V +10%)
DESCRIPTION
SYMBOL MIN
CE\ to Output Delay
tACC
tCE
OE\ to Output Delay
tOE
CE\ or OE\ to Output Float
tDF
Output Hold from OE\, CE\ or Address,
whichever comes first
tOH
Address to Output Delay
120
MAX
0
140
MIN MAX
MIN
150
MAX
MIN
200
MAX
MIN
250
MAX
MIN
300
MAX UNITS
120
140
150
200
250
300
ns
120
140
150
200
250
300
ns
55
ns
55
ns
50
0
55
0
55
0
55
55
0
55
0
0
55
0
55
0
55
0
55
0
0
ns
AC READ WAVEFORMS(1,2,3)
tRC
ADDRESS
ADDRESS VALID
tCE
tCE
tDF
tDF
CE/
tOE
tOE
tOH
tOH
OE\
ttACC
ACC
DQ
OUTPUT VALID
NOTES:
1. CE\ may be delayed to tACC-tCE after the address transition without impact on tACC.
2. OE\ may be delayed to tCE-tOE after the falling edge of CE\ without impact on tCE or by tACC-tOE after an address change
without inpact on tACC.
3. tDF is specified from OE\ or CE\ whichever occurs first (CL = 5pF).
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
5
EEPROM
AS8E128K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE CHARACTERISTICS
(-55oC < TA < +125oC; Vcc = 5V +10%)
Symbol
Parameter
Min
tWC
Write Cyce Time
tAS
Address Set-up Time
tAH
tDS
Max
Units
10
ms
4
ns
Address Hold Time
50
ns
Data Set-up Time
50
ns
tDH
Data Hold Time
10
ns
tWP
Write Pulse Width
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
tOES
tOES
100
ns
150
50
μs
ns
WRITE CYCLE NO 1.
(Chip Enable Controlled)
t
OEH
tOEH
OE\
t
WC
tWC
t
ttAS
AS
ADDRESS
AH
tAH
ADDRESS VALID
tCH
tCH
tCS
tCS
WE\
t
t
WP
tWP
WPH
tWPH
CE\
t
DS
tDS
t
DH
tDH
DQ
DATA VALID
tOES
tOES
WRITE CYCLE NO 2.
(Write Enable Controlled)
tOEH
tOEH
OE\
ttAS
AS
ttAH
AH
ADDRESS
ttCS
CS
tCH
tCH
CE\
tWPH
tWPH
ttWP
WP
WE\
tDS
tDS
DQ
AS8E128K32
Rev. 8.2 07/10
tDH
tDH
DATA VALID
Micross Components reserves the right to change products or specifications without notice.
6
EEPROM
AS8E128K32
PAGE MODE CHARACTERISTICS
Symbol
Parameter
tAS, tOES
Min
Max
Unit
Address, OE\ Set-Up time
4
ns
tAH
Address, Hold time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE\ or CE\)
100
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE\ Hold Time
10
ns
PAGE MODE WRITE WAVEFORMS(1,2)
OE
CE\
tWP
tWP
ttWPH
WPH
tBLC
tBLC
WE\
ttAS
AS
A0 - A16
tAH
tAH
VA
VA
VA
NOTES: 1.
2.
3.
4.
VA
VA
VA
tDH
tDH
ttDS
DS
DATA
VA
ttWC
WC
VD
VD
VD
VD
BYTE 0
BYTE 1
BYTE 2
BYTE 3
VD
VD
BYTE 126
VD
VD
BYTE127
A7 through A16 must specify the page address during each high to low transition of WE\ (or CE\).
OE\ must be high only when WE\ and CE\ are both low.
VD - Valid Data
VA - Valid Address
CHIP ERASE WAVEFORMS
VIH
CE\
VIL
VH
OE\
VIH
VIH
t = 5 msec (min.)
S
t
W
= tH = 10 msec (min.)
VH = 12.0V + 0.5V
AS8E128K32
Rev. 8.2 07/10
t
t
H
S
WE\
VIL
t
W
Micross Components reserves the right to change products or specifications without notice.
7
EEPROM
AS8E128K32
Software Data Protection Disable
Algorithm(1)
Software Data Protection Enable
Algorithm(1)
Load Data >AA
Address >5555
Load Data AA
to
Address 5555
Load Data >55
Address >2AAA
Load Data 55
to
Address 2AAA
Load Data A0
to
Address 5555
Load Data >80
Address >5555
Writes Enabled(2)
Load Data >AA
Address >5555
Load Data XX
to
Any Address(4)
Load Last Byte
to
Last Address
Load Data >55
Address >2AAA
Load Data >20
Address >5555
Enter Data
Protect State
Load Data XX
NOTES:
1. Byte Data Format: I/O7 - I/O0, I/
Address Format: A14 - A0 (Hex)
2. Write Protect state will be active at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of period even if no
other data is loaded.
4. 1 to 128 bytes of data are loaded.
;Exit Data Protect State(3)
Any Address (4)
Load
LoadLast
LastByte(s)
Byte(s)
Last Address
SOFTWARE PROTECTED PROGRAM CYCLE WAVEFORM(1)(2)(3)
OE\
CE\
t WPH
t WP
WE\
tAS
tAH
A0-A6
BYTE ADDRESS
5555
2AAA
5555
PAGE ADDRESS
A7-A16
tDS
DATA
tBLC
AA
tDH
55
A0
BYTE 0
BYTE 126
BYTE 127
tWC
1. A0-A14 of the selected I/O bytes must conform to the addressing sequence for the first three bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7-A16) of the selected I/O bytes must be the same for each high to low transition
of WE\ (or CE\).
3. OE Must be high only when WE\ and CE\ are both low.
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
8
EEPROM
AS8E128K32
DATA POLLING CHARACTERISTICS(1)
Symbol
Parameter
Min
Max
Units
tDH
Data Hold Time
10
ns
tOEH
OE\ Hold Time
10
ns
(2)
tOE
OE\ to Output Delay
tWR
Write Recovery Time
100
ns
0
ns
NOTES: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
DATA POLLING WAVEFORMS
WE\
CE\
tOEH
OE\
tWR
tDH
tOE
I/O7
High-Z
An
A0 - A16
An
An
An
An
TOGGLE BIT CHARACTERISTICS(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE\ Hold Time
tOE
t
tOEPH
OEHP
ItCC
WR
OE\ to Output Delay
Min
Max
10
ns
10
(2)
ns
100
OE\ High Pulse
Write Recovery Time
Units
ns
150
ns
0
ns
NOTES: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
TOGGLE BIT WAVEFORMS(1,2,3)
WE\
CE\
ttOEH
OEH
tOEHP
OE\
tDH
tDH
ttOE
OE
HIGH Z
ttWR
WR
I/O 6
NOTES:
1. Toggling either OE or CE or Both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
9
EEPROM
AS8E128K32
MECHANICAL DEFINITIONS*
Micross Case #703 (Package Designator Q)
SMD 5962-94585, Case Outline M
4 x D2
DETAIL A
4 x D1
4xD
R
Pin 1
A
A2
b
A3
L1
e
B
SEE DETAIL A
A1
A
D3
SYMBOL
A
A1
A2
b
B
D
D1
D2
D3
e
R
L1
MICROSS PACKAGE SPECIFICATIONS
MIN
MAX
0.123
0.200
0.118
0.186
0.005
0.020
0.013
0.017
0.010 REF
0.800 BSC
0.870
0.890
0.980
1.000
0.936
0.956
0.050 BSC
0.005
--0.035
0.045
*All measurements are in inches.
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
10
EEPROM
AS8E128K32
MECHANICAL DEFINITIONS*
Micross Package Designator Q3
D2
D1
D
0.015
b
D3
e
PACKAGESPECIFICATION
Symbol
Min
Max
A
.200
A2
.010
.025
A3
.070
.080
b
.013
.017
.010REF
B
D
.800BSC
D1
.870
.890
D2
.980
1.00
e
.050BSC
R
.010TYP
L1
.035
.045
Dimensionsareininches.
R
A2
A
A3
L1
B
*All measurements are in inches.
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
11
EEPROM
AS8E128K32
MECHANICAL DEFINITIONS*
Micross Case #904 (Package Designator P & PN)
SMD 5962-94585, Case Outline 4 and 5
4xD
D1
A
D2
Pin 56
A1
Pin 1
φb1
(identified by
0.060 square pad)
E1
e
φb
Pin 66
e
66 x φb2
Pin 11
L
SMD SPECIFICATIONS
SYMBOL
A
A1
φb
φb1
φb2
D
D1/E1
D2
e
L
MIN
0.135
0.025
0.016
0.045
0.065
1.065
MAX
0.181
0.035
0.020
0.055
0.075
1.085
1.000 BSC
0.600 BSC
0.100 BSC
0.132
0.155
*All measurements are in inches.
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
12
EEPROM
AS8E128K32
ORDERING INFORMATION
EXAMPLE: AS8E128K32Q-250/XT
Device Number
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
Package
Type
Q
Q3
Q
Q3
Q
Q3
Q
Q3
Q
Q3
Q
Q3
Speed
ns
-120
-120
-140
-140
-150
-150
-200
-200
-250
-250
-300
-300
Process
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
EXAMPLE: AS8E128K32P-200/883C
Device Number
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
Package
Type
P
PN
P
PN
P
PN
P
PN
P
PN
P
PN
Speed
ns
-120
-120
-140
-140
-150
-150
-200
-200
-250
-250
-300
-300
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
Process
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PACKAGE NOTES
P = Pins 8, 21, 28, and 39 are grounds.
PN = Pins 8, 21, 28, and 39 are no connects.
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
13
EEPROM
AS8E128K32
MICROSS TO DSCC PART NUMBER
CROSS REFERENCE*
Micross Package Designator Q
Micross Part #
SMD Part #
AS8E128K32Q-120/883C
AS8E128K32Q-120/883C
AS8E128K32Q-140/883C
AS8E128K32Q-140/883C
AS8E128K32Q-150/883C
AS8E128K32Q-150/883C
AS8E128K32Q-200/883C
AS8E128K32Q-200/883C
AS8E128K32Q-250/883C
AS8E128K32Q-250/883C
AS8E128K32Q-300/883C
AS8E128K32Q-300/883C
5962-9458506HMA
5962-9458506HMC
5962-9458505HMA
5962-9458505HMC
5962-9458504HMA
5962-9458504HMC
5962-9458503HMA
5962-9458503HMC
5962-9458502HMA
5962-9458502HMC
5962-9458501HMA
5962-9458501HMC
ASI Package Designator P & PN
Micross Part #
SMD Part #
AS8E128K32P-120/883C
AS8E128K32P-120/883C
AS8E128K32P-140/883C
AS8E128K32P-140/883C
AS8E128K32P-150/883C
AS8E128K32P-150/883C
AS8E128K32P-200/883C
AS8E128K32P-200/883C
AS8E128K32P-250/883C
AS8E128K32P-250/883C
AS8E128K32P-300/883C
AS8E128K32P-300/883C
5962-9458506H5A
5962-9458506H5C
5962-9458505H5A
5962-9458505H5C
5962-9458504H5A
5962-9458504H5C
5962-9458503H5A
5962-9458503H5C
5962-9458502H5A
5962-9458502H5C
5962-9458501H5A
5962-9458501H5C
AS8E128K32PN-120/883C
AS8E128K32PN-120/883C
AS8E128K32PN-140/883C
AS8E128K32PN-140/883C
AS8E128K32PN-150/883C
AS8E128K32PN-150/883C
AS8E128K32PN-200/883C
AS8E128K32PN-200/883C
AS8E128K32PN-250/883C
AS8E128K32PN-250/883C
AS8E128K32PN-300/883C
AS8E128K32PN-300/883C
5962-9458506H4A
5962-9458506H4C
5962-9458505H4A
5962-9458505H4C
5962-9458504H4A
5962-9458504H4C
5962-9458503H4A
5962-9458503H4C
5962-9458502H4A
5962-9458502H4C
5962-9458501H4A
5962-9458501H4C
*Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
AS8E128K32
Rev. 8.2 07/10
Micross Components reserves the right to change products or specifications without notice.
14
EEPROM
AS8E128K32
DOCUMENT TITLE
128K x 32 EEPROM EEPROM Memory Array
Rev #
8.2
AS8E128K32
Rev. 8.2 07/10
History
Updated Q3 Package, pg 11
Release Date
July 2010
Status
Release
Micross Components reserves the right to change products or specifications without notice.
15