ROHM BM5446EFV_10

Middle Power Class-D Speaker Amplifiers
Class-D Speaker Amplifier
for Digital Input with Built-in DSP
BM5446EFV
No.10075EBT13
●Description
BM5446EFV is a Class D Speaker Amplifier with built-in DSP (Digital Sound Processor) designed for Flat-panel TVs in
particular for space-saving and low-power consumption, delivers an output power of 20W+20W. This IC employs
state-of-the-art Bipolar, CMOS, and DMOS (BCD) process technology that eliminates turn-on resistance in the output power
stage and internal loss due to line resistances up to an ultimate level. With this technology, the IC can achieve high
efficiency of 86% (10W+10W output with 8Ω load). In addition, the IC is packaged in a compact reverse heat radiation type
power package to achieve low power consumption and low heat generation and eliminates necessity of external heat-sink
up to a total output power of 40W. This product satisfies both needs for drastic downsizing, low-profile structures and many
function, high quality playback of sound system.
●Features
1) This IC includes the DSP (digital sound processor) for Audio signal processing for Flat TVs.
2) This IC has two input systems of digital audio interface.
2
(I S/LJ/RJ format, LRCLK: 32 kHz/ 44.1kHz / 48kHz, SYS_CLK: 256fs / 512fs,
BCLK: 48fs / 64fs, SDATA: 16 / 20 / 24bit)
3) With wide range of power supply voltage, it is possible to operate with single power supply. (Vcc = 10~26V)
4) With high efficiency and low heat dissipation contributing to miniaturization, slim design, and also power saving of the
system.
5) S/N of the system can be optimized by adjusting the gain selection in 16 steps. (20~35dB,1dB/step)
6) With built-in feedback circuitry at the output, prevents the decrease in sound quality due to change in power supply
voltage. In addition, low noise and low distortion are achieved.
7) With a built-in DAC provides best stereo-output for headphone function. As a result, the selection of output of the
digital input in two systems is possible.
8) It has additional S/PDIF output for the LINE output usage.
9) Eliminates pop-noise generated during the power supply on/off. High quality muting performance is realized by using
the soft-muting technology.
10) This IC is built-in with various protection functions for highly reliability design.
(High temperature protection, Under voltage protection, Output short protection, Output DC-Voltage protection and
Clock stop protection).
●Applications
Flat Panel TVs (LCD, Plasma), Home Audio, Desktop PC, Amusement equipments, Electronic Music equipments, etc.
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© 2010 ROHM Co., Ltd. All rights reserved.
1/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
Ratings
Unit
Supply voltage
VCC
30
V
Pin 27, 30, 31, 51, 52
2.0
W
*3
Power dissipation
Pd
4.5
W
*4
6.2
W
*5
VIN
-0.3 ~ 4.5
V
Pin 5 ~ 14, 22
*1
Open-drain terminal voltage
VERR
-0.3 ~ 30
V
Pin 26
*1
Operating temperature range
Topr
-25 ~ +85
℃
Storage temperature range
Tstg
-55 ~ +150
℃
Tjmax
+150
℃
Input voltage
Maximum junction temperature
Conditions
*1*2
*1 The voltage that can be applied reference to GND (Pin 4, 36, 37, 45, 46) and VSS (Pin 15, 20).
*2 Do not, however exceed Pd and Tjmax=150℃.
*3 70mm×70mm×1.6mm, FR4, 1-layer glass epoxy board (Copper on bottom layer 0%)
Derating in done at 16mW/℃ for operating above Ta=25℃.
*4 70mm×70mm×1.6mm, FR4, 2-layer glass epoxy board (Copper on bottom layer 100%)
Derating in done at 36mW/℃ for operating above Ta=25℃. There are thermal via on the board.
*5 70mm×70mm×1.6mm, FR4, 4-layer glass epoxy board (Copper on bottom layer 100%)
Derating in done at 49.6mW/℃ for operating above Ta=25℃. There are thermal via on the board.
●Operating conditions (Ta=25℃)
Parameter
Symbol
Ratings
Unit
VCC
10 ~ 26
V
Pin 27, 30, 31, 51, 52
RL_SP
5.4
Ω
*6
RL_DA
20
kΩ
Pin 24, 25
Supply voltage
Minimum load impedance
(Speaker Output)
Minimum load impedance
(DAC Output)
Conditions
*1 *2
*6 Do not, however exceed Pd.
* No radiation-proof design.
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2/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Electrical characteristics
(Unless otherwise specified Ta=25℃,Vcc=13V,f=1kHz,RL_SP=8Ω,RL_DA=20kΩ,RESETX=3.3V,MUTEX=3.3V,PDX=3.3V,
Gain=20dB, DSP: Through, fs =48kHz)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
Total circuit
Circuit current
ICC1
-
60
120
mA
Pin 27, 30, 31, 51, 52,No load
ICC2
-
2.5
5
mA
Pin 27, 30, 31, 51, 52,No load
RESETX=0V, MUTEX=0V,PDX=0V
VERR
-
-
0.8
V
Pin 26,IO=0.5mA
Regulator output voltage 1
VREG_G
5.0
5.5
6.0
V
Pin 28, 54
Regulator output voltage 2
VREG_3
3.0
3.3
3.6
V
Pin 3
Regulator output voltage 3
VREG_15
1.3
1.5
1.7
V
Pin 16
High level input voltage
VIH
2.5
-
3.3
V
Pin 5 ~ 14, 22
Low level input voltage
VIL
0
-
0.8
V
Pin 5 ~ 14, 22
IIL
50
100
150
µA
Pin 5 ~ 9,VIN = 0V
IIH
30
70
105
µA
Pin 10 ~ 12, 22,VIN = 3.3V
II
-
0
1
µA
Pin 13, 14,VIN = 3.3V
IO
-1
0
-
µA
Pin 13, 14,VIN = 0V
VOH
2.75
3.3
-
V
Pin 23,IO=-0.6mA
VOL
-
0
0.55
V
Pin 23,IO= 0.6mA
PO1
-
10
-
W
THD+n=10%,Gain=26dB
*7
PO2
-
20
-
W
Vcc=18V,THD+n=10%,Gain=26d
B
*7
THDSP
-
0.07
-
%
PO=1W,BW=20～20kHz
*7
CTSP
65
80
-
dB
PO=1W,BW=IHF-A
*7
VNO_SP
-
140
280
µVrms
-∞dBFS,BW=IHF-A
*7
VNOR_SP
-
5
10
µVrms
MUTEX=0V,-∞dBFS,BW=IHF-A
*7
fPWM1
-
512
-
kHz
fs=32kHz
*7
fPWM2
-
705.6
-
kHz
fs=44.1kHz
*7
fPWM3
-
768
-
kHz
fs=48kHz
*7
VOMAX
0.85
1.0
-
Vrms
0dBFS,THD+n=1%
CB
-1
0
1
dB
0dBFS
THDDA
-
0.05
0.5
%
-20dBFS,BW=20～20kHz
CTDA
65
80
-
dB
0dBFS,BW=IHF-A
Output noise voltage
VNO_DA
-
10
20
µVrms
-∞dBFS,BW=IHF-A
Residual noise voltage
VNOR_DA
-
3
10
µVrms
MUTEX=0V,PDX=0V,
-∞dBFS,BW=IHF-A
Circuit current
(Power down mode)
Open-drain terminal
Low level voltage
Input current
(Input pull-up terminal)
Input current
(Input pull-down terminal)
Input current
(SCL, SDA terminal)
Output current
(SCL, SDA terminal)
High level output voltage
(S/PDIF output terminal)
Low level output voltage
(S/PDIF output terminal)
Speaker Output
Maximum momentary
output power 1
Maximum momentary
output power 2
Total harmonic distortion
Crosstalk
Output noise voltage
(Sampling mode)
Residual noise voltage
(Mute mode)
PWM sampling frequency
DAC Output
Maximum output voltage
Channel Balance
Total harmonic distortion
Crosstalk
*7 These items show the typical performance of device and depend on board layout, parts, and power supply.
The standard value is in mounting device and parts on surface of ROHM’s board directly.
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3/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●DSP Block Functional Overview
1) Main Signal line function
No.
Function
Specification
1
Pre-scalar
･Lch / Rch synchronous control
･+24 ~ -103dB (0.5dB step),-∞dB
2
DC cut HPF
･FC : 1Hz
3
Channel Mixer
4
P2Volume
(Perfect Pure Volume)
･Mixing of the sound of the left and right channel of the input digital signal to DSP is
set up.
･There are some scenes when sound becomes large suddenly, like the
explosion-scene
in TV commercial or in an action movie. The “P2Volume” function controls volume
automatically and adjusts the output level.
･It makes easy to hear small whisper voice, and is adjusted.
･Attack time : 1ms ~ 40ms (8steps)
･Recovery time : 0.25s ~ 10s (16 steps)
BASS
･Peaking filter is used.
･Lch / Rch Concurrent control
･Soft transition function
･Fc Select : Same as 7 Band Parametric
Equalizer
･Gain Select : ±18dB (0.5dB step)
･Q (Quality Factor) : Same as 7 Band
Parametric Equalizer
MIDDLE
･Peaking filter is used.
･Lch / Rch Concurrent control
･Soft transition function
･Fc Select : Same as 7 Band Parametric Equalizer
･Gain Select : ±18dB (0.5dB step)
･Q (Quality Factor) : Same as 7 Band Parametric Equalizer
7
TREBLE
･Peaking filter is used.
･Lch / Rch Concurrent control
･Soft transition function
･Fc Select : Same as 7 Band Parametric
Equalizer
･Gain Select : ±18dB (0.5dB step)
･Q (Quality Factor) : Same as 7 Band
Parametric Equalizer
8
Scalar 1
9
Pseudo Stereo
10
Matrix Surround 3D
11
P Bass
(Perfect Pure Bass)
12
P Treble
(Perfect Pure Treble)
･Real, pure and crystal clear sound.
･Lch / Rch Concurrent control
･Soft transition function
･Gain select : 0 ~ 15dB (1dB step)
13
Scalar 2
･Lch / Rch Concurrent control
･+24 ~ -103dB (0.5dB step), - ∞dB
5
6
2
2
･Low shelf filter is used.
･Lch / Rch Concurrent control
･Soft transition function
･Fc Select : Same as 7 Band Parametric
Equalizer
･Gain Select : ±18dB (0.5dB step)
･Q (Quality Factor) : Same as 7 Band
Parametric Equalizer
･High shelf filter is used.
･Lch / Rch Concurrent control
･Soft transition function
･Fc Select : Same as 7 Band Parametric
Equalizer
･Gain Select : ±18dB (0.5dB step)
･Q (Quality Factor) : Same as 7 Band
Parametric Equalizer
･Lch / Rch Concurrent control
･ +24 ~ -103dB (0.5dB step), -∞dB
･A stereo-feel sound is reproduced for a monophonic sound by signal processing.
･3 steps : Pseudo Stereo OFF / Pseudo Stereo ON (Weak) / Pseudo Stereo ON
(Strong)
･Matrix Surround 3D of a wider sweet spot, and it also with little prolonged viewing
and listening with a feeling of fatigue.
･The acoustic field which does not spoil a vocal feeling of the normal position is played
back.
･Surround : ON / OFF function
･Loop
: ON / OFF function
･Surround gain select : 16 steps
･Clear deep Bass with low distortion.
･Lch / Rch Concurrent control
･Soft transition function
･Frequency select : 4 steps
･Gain select : 0 ~ 15dB (1dB step)
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4/32
2010.05 - Rev.B
Technical Note
BM5446EFV
No.
Function
14
7-Band
Parametric Equalizer
･Peaking filter is used. (Possible to set the 5 coefficients directly for b0,b1,b2,a1,a2)
･Lch / Rch Concurrent control
･Fc select : Setup of 61 divisions (20Hz ~ 20kHz) is possible.
･Gain select : ±18dB ( 0.5dB step )
･Q(Quality Factor) : 0.33, 0.43, 0.56, 0.75, 1.0, 1.2, 1.5, 1.8, 2.2, 2.7, 3.3, 3.9, 4.7,
5.6, 6.8, 8.2
15
Volume
･+24 ~ -103dB ( 0.5dB step ), -∞dB
･Soft transition and soft mute function
･Lch / Rch Concurrent control, Sub-Woofer ch Independent control
16
Balance
･It decreases by 1dB step from a volume setting value.
( Lch/Rch : 0dB/-∞dB, 0dB/-126dB, 0dB/-125dB, ･････, 0dB/0dB, ･････,
-125dB/0dB, -126dB/0dB, -∞dB/0dB )
17
Post-scaler
･Lch / Rch Concurrent control, Sub-Woofer ch Independent control
･+24 ~ -103dB (0.5dB step), -∞dB
18
Output Clipper
･A clip with an arbitrary output amplitude is possible.
･Lch / Rch Concurrent control, Sub-Woofer ch Independent control
2) Sub Signal line function
No.
Function
Specification
･Mixing of the sound of the left and right channel of the input digital signal to DSP is
set up.
･Lch (Lch is input, (Lch+Rch)/2 is input, Rch is input), Rch (Rch is input, (Lch+Rch)/2
is input, Lch is input)
･LPF for Sub-Woofer
･Fc= 60Hz, 80Hz, 100Hz, 120Hz, 160Hz, 200Hz, 240Hz, 280Hz
19
Channel Mixer
20
LPF
21
3-Band
Parametric Equalizer
･Peaking or low shelf or high shelf filter is used.
･Lch / Rch Concurrent control
22
Volume
･+24 ~ -103dB ( 0.5dB step ), -∞dB
･Soft transition and soft mute function
･ Lch / Rch Concurrent control, Sub-Woofer ch Independent control
23
Balance
･It decreases by 1dB step from a volume setting value.
( Lch/Rch : 0dB/-∞dB, 0dB/-126dB, 0dB/-125dB, ･････, 0dB/0dB, ･････,
-125dB/0dB, -126dB/0dB, -∞dB/0dB )
24
Post-scaler
･Lch / Rch Concurrent control, Sub-Woofer ch Independent control.
･+24 ~ -103dB (0.5dB step), -∞dB
25
Output Clipper
･A clip with an arbitrary output amplitude is possible.
･Lch / Rch Concurrent control, Sub-Woofer ch Independent control.
SEL1
SDATA1
Specification
Pre
Scalar
DC Cut
HPF
Channel
Mixer
BASS
MIDDLE
TREBLE
Scalar
1
Scalar
2
Surround
Channel
Mixer
SDATA2
LPF
7 Band
Parametric
Equalizer
EVR
＆
Balance
Post
Scalar
&
Clipper
3 Band
Parametric
Equalizer
EVR
＆
Balance
Post
Scalar
&
Clipper
SEL2
SDATAO1
SPEAKER
OUTPUT
SDATAO2
SEL3
Digital Audio Processing Signal Flow
DAC
DSP Block diagram
S/PDIF
OUTPUT
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5/32
ANALOG
OUTPUT
2010.05 - Rev.B
Technical Note
BM5446EFV
●Electrical characteristic curves(VCC=13V,RL_SP=8Ω,RL_DA=20kΩ,Gain=20dB,fin=1kHz,fs=48kHz,by passing DSP)
Measured by ROHM designed 4 layer board.
80
70
60
50
40
30
20
Mute
10
0
3
44
40
36
32
28
24
20
16
12
8
4
0
THD=10%
0
8 10 12 14 16 18 20 22 24 26 28
8 10 12 14 16 18 20 22 24 26 28
VCC(V)
VCC(V)
26
24
22
50
40
30
20
10
0
6
8
10
12
-140
100
1k
10
100k
0.1
1
1
0.1
100Hz
10
0.01
100
10
100
1k
10k
100k
FREQUENCY(Hz)
OUTPUT POWER(W)
Fig.7
Fig.8
THD+N - Output power
THD+N - Frequency
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
fin=300Hz
Po=3.3W
Po=1W
BW=20～20KHz
10k
100k
FFT of Output noise voltage
CROSSTALK(dB)
1KHz
1k
Fig.6
Po=1W
BW=20～20KHz
10
0.001 0.01
100
FREQUENCY(Hz)
Voltage gain - Frequency
THD+N(%)
THD+N(%)
10k
100
0.01
-80
-100
-120
BW=20～20KHz
6KHz
40
-60
Fig.5
10
35
-40
FREQUENCY(Hz)
100
30
Without Signal
BW=20～20KHz
-20
20
18
16
14
12
10
10
Efficiency - Output power
20 25
0
Fig.4
0.1
15
Fig.3
Po=1W
L=22µH
C=0.47µF
Cg=0.068µF
OUTPUT POWER(W/ch)
1
10
Current consumption
- Output power
NOISE FFT(dBV)
80
70
60
VOLTAGE GAIN(dB)
EFFICIENCY(%)
30
28
4
5
TOTAL OUTPUT POWER(W)
Output power
- Power supply voltage
100
90
2
0
Fig.2
Fig.1
0
VCC=18V
1
THD=1%
Current consumption
- Power supply voltage
CROSSTALK(dB)
VCC=13V
2
ICC(A)
Sampling
OUTPUT POWER(W/ch)
ICC(mA)
100
90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
BW=20～20KHz
0.001
0.01
0.1
1
10
OUTPUT POWER(W)
Fig.9
Speaker output
Crosstalk - Output power
Speaker output
fin=300Hz
Po=3.3W
5V/div
5V/div
MUTEX
2V/div
MUTEX
2V/div
10ms/div
10ms/div
10
100
1k
10k
100k
FREQUENCY(Hz)
Fig.10
Crosstalk - Frequency
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© 2010 ROHM Co., Ltd. All rights reserved.
Fig.11
Wave form when
Releasing Soft-start
6/32
Fig.12
Wave form when
Activating Soft-mute
2010.05 - Rev.B
Technical Note
BM5446EFV
●Electrical characteristic curves(VCC=18V,RL_SP=8Ω,RL_DA=20kΩ,Gain=20dB,fin=1kHz,fs=48kHz,by passing DSP)
Measured by ROHM designed 4 layer board.
50
40
30
20
10
0
0
2
4
6
8
10
12
14
0
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
Po=1W
L=22µH
C=0.47µF
Cg=0.068µF
100
-80
-100
-120
1k
10k
10
100k
Fig.14
Efficiency – Output power
Voltage gain - Frequency
1KHz
0.1
CROSSTALK(dB)
THD+N(%)
6KHz
1
0.1
100Hz
0.01
0.01
0.001 0.01
0.1
1
10
100
100
1k
100k
10k
100k
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
BW=20～20KHz
0.001 0.01
0.1
1
10
100
OUTPUT POWER(W)
FREQUENCY(Hz)
Fig.16
Fig.17
Fig.18
THD+N - Frequency
Crosstalk – Output power
THD+N - Output power
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
10
10k
FFT of output noise voltage
Po=1W
BW=20～20KHz
10
1k
Fig.15
100
10
100
FREQUENCY(Hz)
Fig.13
BW=20～20KHz
THD+N(%)
-60
FREQUENCY(Hz)
100
CROSSTALK(dB)
-40
-140
10
OUTPUT POWER(W/ch)
1
Without Signal
BW=20～20KHz
-20
NOISE FFT(dBV)
80
70
60
VOLTAGE GAIN(dB)
EFFICIENCY(%)
100
90
OUTPUT POWER(W)
Po=1W
BW=20～20KHz
10
100
1k
10k
100k
FREQUENCY(Hz)
Fig.19
Crosstalk - Frequency
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7/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Pin configuration and Block diagram
1
FILP
2
FILA
3
REG_3
4
GNDA
REG_G1
54
NC 53
VCCP1
52
51
NC 50
5
6
49
Driver
1P
I2S/LJ/
7
RJ
Interface
48
REG_G1
47
8
9
46
Driver
1N
10
45
GNDP1
11
Control
Interface
44
12
43
REG_G1
13
14
15
I2C
Interface
DSP
42
PWM
Modulator
NC 41
40
VSS1
REG_G2
16
39
REG_15
17
TEST1
18
VDD
19
PLL
20
VSS2
38
37
Driver
2N
36
GNDP2
35
REG_G2
21
TEST2
34
Driver
2P
22
33
23
NC 32
31
24
DAC
25
26
High Temperature Protection
Under Voltage Protection
Clock Stop Protection
30
VCCP2
NC 29
Output Short Protection
Output DC Voltage Protection
REG_G2
27
28
VCCA
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8/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Pin function explanation (Provided pin voltages are typ. Values)
Pin No. Pin name
Pin voltage
Pin explanation
Internal equivalence circuit
52,51
30,31
54
28
REG_G1
REG_G2
5.5V
Internal power supply pin for ch1 Gate driver
Internal power supply pin for ch2 Gate driver
54
28
Please connect the capacitor.
550K
45,46
36,37
27
Bias pin for PWM signal
1
FILP
1.75～2.55V
1
Please connect the capacitor.
4
27
50K
Bias pin for Analog signal
2
FILA
2.5V
2
Please connect the capacitor.
50K
4
27
Internal power supply pin for Digital circuit
3
REG3
3.3V
3
Please connect the capacitor.
500K
4
4
GNDA
0V
－
GND pin for Analog signal
18
5
SYS_CLK
3.3V
System-Clock input pin
5
15,20
18
6
7
8
9
BCLK
LRCLK
SDATA1
SDATA2
3.3V
Digital audio signal input pin
6,7
8,9
15,20
10
RESETX
11
MUTEX
12
PDX
0V
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Reset pin for Digital circuit
H: Reset OFF
L: Reset ON
Speaker output mute control pin
H: Mute OFF
L: Mute ON
Power down control pin
H: Power down OFF
L: Power down ON
9/32
18
10,11,12
15,20
2010.05 - Rev.B
Technical Note
BM5446EFV
Pin
No.
Pin name
Pin voltage
Pin explanation
Internal equivalence circuit
13
13
SCL
－
I2C transmit clock input pin
15,20
14
14
SDA
－
I2C data input/output pin
15,20
15
20
VSS1
VSS2
0V
GND pin for Digital I/O
－
18
16
REG_15
1.5V
Internal power supply pin for Digital circuit
16
15,20
18
Test pin
17
TEST1
－
17
Please connect to VSS.
15,20
18
VDD
3.3V
Power supply pin for Digital I/O
－
18
19
PLL
1V
PLL’s filter pin
19
15,20
18
Test pin
21
TEST2
0V
21
Please connect to VSS.
15,20
18
22
ADDR
0V
I2C Slave address select pin
22
15,20
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10/32
2010.05 - Rev.B
Technical Note
BM5446EFV
Pin
No.
Pin name
Pin voltage
Pin explanation
Internal equivalence circuit
18
23
OUT_SPDIF
－
S/PDIF output pin
23
15,20
27
OUT_DAC2
OUT_DAC1
2.5V
24,25
Please connect it with the latter part circuit
through the capacitor.
50K
24
25
ch2 DAC output pin
ch1 DAC output pin
4
Error flag pin
26
ERROR
3.3V
27
Please connect pull-up resistor.
H: While Normal
L: While Error
500
26
4
27
VCCA
Vcc
Power supply pin for Analog signal
30
31
VCCP2
Vcc
Power supply pin for ch2 PWM signal
Vcc～0V
Output pin of ch2 positive PWM signal
Please connect to Output LPF.
33
34
35
－
30,31
OUT2P
BSP2P
－
36
37
GNDP2
0V
38
39
OUT2N
Vcc～0V
40
BSP2N
42
BSP1N
－
－
Boot-strap pin of ch2 positive
Please connect the capacitor.
GND pin for ch2 PWM signal
Boot-strap pin of ch2 negative
Please connect the capacitor.
Boot-strap pin of ch1 negative
Please connect the capacitor.
OUT1N
Vcc～0V
45
46
GNDP1
0V
GND pin for ch1 PWM signal
Boot-strap pin of ch1 positive
Please connect the capacitor.
Output pin of ch1 negative PWM signal
Please connect to Output LPF.
47
BSP1P
－
48
49
OUT1P
Vcc～0V
Output pin of ch1 positive PWM signal
Please connect to Output LPF.
51
52
VCCP1
－
Power supply pin for ch1 PWM signal
29
32
41
50
53
N.C.
－
Non connection pin
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33,34
38,39
Output pin of ch2 negative PWM signal
Please connect to Output LPF.
43
44
© 2010 ROHM Co., Ltd. All rights reserved.
35
40
11/32
36,37
51,52
42
47
43,44
48,49
45,46
－
2010.05 - Rev.B
Technical Note
BM5446EFV
●RESETX pin function
RESETX
State of Digital block
(10pin)
L
Reset ON
H
Reset OFF
●PDX pin,MUTEX pin function
PDX
MUTEX
(12pin)
(11pin)
L
L or H
H
L
H
H
Power Down
DAC output
(24,25pin)
ON
HiZ_Low
OFF
Normal operation
PWM output
(33,34,38,39,43,44,48pin)
HiZ_Low
Normal operation
●Input digital audio sampling frequency (fs) explanation
PWM sampling frequency, Soft-start, Soft-mute time, and the detection time of the DC voltage protection in the speaker
depends on sampling frequency (fs) of the digital audio input.
Sampling frequency of the
Digital audio input
(fs)
PWM sampling frequency
(fpwm)
Soft-start / Soft-mute time
DC voltage protection in
the speaker detection time
32kHz
512kHz
64msec.
64msec.
44.1kHz
705.6kHz
46msec.
46msec.
48kHz
768kHz
43msec.
43msec.
●For voltage gain (Gain setting)
BM5446EFV prescribe voltage gain at speaker output (BTL output) under the definition 0dBV (1Vrms) as full scale input of
the digital audio input signal. For example, digital audio input signal = Full scale input, Gain setting = 20dB, Load resistance
2
RL_SP= 8Ω will give speaker output (BTL output) amplitude as 10Vrms. (Output power Po = Vo /RL_SP=12.5W )
●Speaker output
DSP output signal SDATAO1 will be output to the speaker. (SDATAO2 will not be output to the speaker. DAC output can be
selected either from DSP output signal SDATAO1 or SDATAO2.)
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12/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●I2C Bus control signal specification
1) Electrical characteristics and Timing of Bus line and I/O stage
SDA
tBUF
tF
tHD;STA
tR
tLOW
SCL
tHD;STA
P
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
S
Sr
P
SDA and SCL bus line characteristics(Unless otherwise specified Ta=25℃, VCC=13V)
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
High speed mode
Min.
Max.
0
400
1.3
-
Symbol
SCL clock frequency
Bus free time between ”Stop” condition and ”Start” condition
Hold-time of (sending again)”Start” condition. After this period
the first clock pulse is generated.
SCL clock’s LOW state Hold-time
SCL clock’s HIGH state Hold-time
Set-up time of sending again ”Start” condition
Data hold time
Data set-up time *2
Rise-time of SDA and SCL signal
Fall-time of SDA and SCL signal
Set-up time of ”Stop” condition
Capacitive load of each bus line
fSCL
tBUF
Unit
kHz
µs
tHD;STA
0.6
-
µs
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
Cb
1.3
0.6
0.6
0 *1
500/250/150
20+Cb
20+Cb
0.6
-
300
300
400
µs
µs
µs
µs
ns
ns
ns
µs
pF
The above-mentioned numerical values are all the values corresponding to VIH min and the VIL max level.
*1 To exceed an undefined area on the fall-edge of SCL (VIH min of the SCL signal), the transmitting set should internally
offer the holding time of 300ns or more for the SDA signal.
*2 The data set-up time is different according to the setting of SYS_CLK.
When SYS_CLK=128fs it is 500ns, for SYS_CLK=256fs it is 250ns, for SYS_CLK=512fs it will be 150ns.
*3 SCL and SDA pin is not corresponding to threshold tolerance of 5V.
Please use it within 4.5V of the absolute maximum rating.
2) Command interface
I2C Bus control is used for command interface between host CPU. It not only writes but also it is possible to read it
excluding a part of register. In addition to “Slave Address “ , set and write 1 byte of “Select Address “ to read out the
2
data. I C bus Slave mode format is illustrated below.
MSB
LSB
MSB
LSB
MSB
S
Slave Address
A
Select Address
A
LSB
Data
A
P
S : Start Condition
Slave Address : The data of eight bits in total is sent putting up bit of Read mode (H) or Write mode (L) after slave
address (7bit) set with the terminal ADDR. (MSB first)
A : The acknowledge bit adds to data that the acknowledge is sent and received in each byte.
When data is correctly sent and received,“L”is sent and received.
There was no acknowledgement for “H”.
Select Address : The select address in one byte is used.(MSB first)
Data : Data byte is sent and received data(MSB first)
P : Stop Condition
SDA
MSB
6
5
LSB
SCL
Start Condition
SDA↓ SCL=”H”
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© 2010 ROHM Co., Ltd. All rights reserved.
Stop condition
SDA↑ SCL=”H”
13/32
2010.05 - Rev.B
Technical Note
BM5446EFV
3) Slave Address
・While ADDR pin (22pin) is“L”
MSB
A6
A5
A4
1
0
0
A3
0
A2
0
A1
0
A0
0
LSB
R/W
1/0
・While ADDR pin (22pin) is“H”
MSB
A6
A5
A4
1
0
0
A3
0
A2
0
A1
0
A0
1
LSB
R/W
1/0
4) Writing of data
・Basic format
S
Slave Address
A
Select Address
A
:
Data
A
P
Master to Slave,
:
Slave to Master
・Auto-increment format
S
Slave Address
A
Select Address
A
:
Data 1
A
Data 2
Master to Slave,
:
A
Data 3…N
A
P
Slave to Master
5)Reading of data
First of all, the address ( 20h in the example) for reading is written in the register of the D0h address at the time of
reading. In the following stream, data is read after the slave address. Please do not return the acknowledge when you
end the reception.
S
Slave Address
(ex.) 80h
A
Req_Addr
D0h
S
Slave Address
(ex.) 81h
A
**h
:
Master to Slave，
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© 2010 ROHM Co., Ltd. All rights reserved.
Data 1
**h
:
A
A
Select Address
20h
Data 2
A
A
P
A
**h
Data N
Ā
P
Slave to Master，A : With Acknowledge，Ā : Without Acknowledge
14/32
2010.05 - Rev.B
Technical Note
BM5446EFV
6) Instruction Code Chart (Select Address)
LSB
MSB
0
1
2
3
4
5
6
7
8
0
I/O Setting
CLK Setting
SPDIF
MUTE
Setting
DSP
PRE Scaler
Volume
Setting
Sub Clipper Sub Clipper
2
P Volume
ON/OFF
DSP
BASS
TONE
Control
DSP
7Band1
7BandP-EQ Control
DSP
7Band5
7BandP-EQ Control
DSP
Surround
Sound Effect Setting
DSP
3Band1
3BandP-EQ Control
1
RAM
Clear
SPDIF OUT
Setting1
DC Cut
HPF
Sub Clipper
Setting1
BASS
Frequency
7Band1
Frequency
7Band5
Frequency
Pseudo
Stereo
3Band1
Frequency
2
3
Input SEL
S-P2,S-P1
SPDIF OUT
Setting2
CH Mixer1
DSP
Sub Clipper
Setting2
BASS
Quality factor
7Band1
Quality factor
7Band5
Quality factor
2
P Bass
Setting1
3Band1
Quality factor
4
5
Output SEL
P-S2,P-S1
SPDIFO
Output SEL
Scaler1
Setting
Scaler2
Setting
6
7
SPDIF OUT
CH Mixer2
DF2, DF1
2
2
2
Main Volume
Setting
2
Main Balance
Setting
2
P V Setting1
P V_MIN
P V_MAX
P V_K
P V_OFS
BASS
Gain
7Band1
Gain
7Band5
Gain
2
P Bass
Setting2
3Band1
Gain
MIDDLE
Control
7Band2
Control
7Band6
Control
2
P Bass
Setting3
3Band2
Control
MIDDLE
Frequency
7Band2
Frequency
7Band6
Frequency
2
P Treble
Setting1
3Band2
Frequency
MIDDLE
Quality factor
7Band2
Quality factor
7Band6
Quality factor
2
P Treble
Setting2
3Band2
Quality factor
MIDDLE
Gain
7Band2
Gain
7Band6
Gain
2
P Bass
Soft_T Start
3Band2
Gain
Power Stage
Test4
Power Stage
Test5
Sync
Detect1
Power Stage
Test6
Sync
Detect2
Power Stage
Test7
PLLA Initial
Setting1
PLLA Initial
Setting2
PLLA Initial
Setting3
PLLA Initial
Setting4
9
PLLA
Setting1
Power Stage
Gain
A PLLA
Power
B Stage
Power Stage
Test1
Power Stage
Test2
Power Stage
Test3
C
Read Base
D Address
Read Base
Address
E
TEST
F Mode
PU
Setting
LSB
MSB
8
0
I/O Setting SYSCLK SEL1
CLK Setting DSP
1
SPDIF
2
DSP
Volume
3
P Volume
4
5
6
7
8
2
DSP
TONE
DSP
7Band P-EQ
DSP
7Band P-EQ
DSP
Sound Effect
DSP
3BandP-EQ
Initial Setting
MCLK DIV
TEST Mode2
TEST Mode1
Setting
9
A
B
2
Main Post
Scalar Setting
A_RATE
R_RATE
TREBLE
Control
7Band3
Control
7Band7
Control
2
P Treble
Soft_T Start
3Band3
Control
Main Clipper
ON/OFF
A_TIME
R_TIME
TREBLE
Frequency
7Band3
Frequency
7Band7
Frequency
Sync
Detect3
Sync
Detect4
3Band3
Frequency
Main Clipper
Setting1
A_RATE_Low
R_RATE_Low
TREBLE
Quality factor
7Band3
Quality factor
7Band7
Quality factor
Sub Woofer
LPF Setting
3Band3
Quality factor
C
2
D
2
E
F
2
I S Format1
S-P1
I S Format2
S-P2
I S Format3
P-S1
I S Format4
P-S2
Main Clipper
Setting2
AR_TIME_
Low
TREBLE
Gain
7Band3
Gain
7Band7
Gain
Sub Volume
Setting
Pulse Sound
Setting1
TONE Control
Soft_T Start
7Band4
Control
Sub Balance
Setting
Sub Post
Sub Input
Scalar Setting Selector
7Band4
Frequency
CRAM Auto
Over Write
7Band4
Quality factor
CRAM Auto
Setting1
7Band4
Gain
CRAM Auto
Setting2
3Band3
Gain
P-EQ
Setting1
P-EQ
Setting2
P-EQ
Setting3
P-EQ
Setting4
RAM Test
Setting4
RAM Test
Setting5
DSP Mute
Set
9
A PLLA
B Power Stage C2D speed
Refresh
Test8
RAM Test
Setting2
RAM Test
Setting3
C
D
Read Base
Address
E
F
TEST
Mode
RAM Test
Setting1
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15/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Format of digital audio input
・SYS_CLK: It is System Clock input signal.
It will input LRCLK, BCLK, SDATA1 (SDATA2) that synchronizes with this clock that are 128 times of sampling frequency
(128fs), 256 times of sampling frequency (256fs), or 512 times frequency (512fs) of sampling frequency (fs).
・LRCLK: It is L/R clock input signal.
It corresponds to 32kHz/44.1kHz/48kHz with those clock (fs) that are same to the sampling frequency (fs) .
The audio data of a left channel and a right channel for one sample is input to this section.
・BCLK:
It is Bit Clock input signal.
It is used for the latch of data in every one bit by sampling frequency’s 48 times frequency (48fs) or 64 times sampling
frequency (64fs). However if the 48fs being selected, the input will be Right-justified data format and held static.
・SDATA1 & SDATA2: It is Data input signal.
It is amplitude data. The data length is different according to the resolution of the input digital data.
It corresponds to 16/ 20/ 24 bit.
The digital input has I2S, Left-justified and Right-justified formats.
The figure below shows the timing chart of each transmission mode.
I2S data format
LRCLK
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
LSB
S
SDATA
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Left-justified data format
LRCLK
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB
SDATA S
15
16
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Right-justified data format
LRCLK
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MSB
SDATA
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LSB
MSB
S
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Right-justified data format (48fs)
LRCLK
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MSB
SDATA
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
LSB
9
10
11
12
13
14
15
16
17
MSB
S
18
19
20
21
22
23
24
LSB
S
16bit
16bit
20bit
20bit
24bit
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© 2010 ROHM Co., Ltd. All rights reserved.
24bit
16/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Power supply start-up sequence
VCCA (27pin)
VCCP1 (51, 52pin)
VCCP2 (30, 31pin)
① Power up VCCA, VCCP1, VCCP2 simultaneously.
VCCA, VCCP1,VCCP2
REG_3 (3pin)
VDD (18pin)
REG_3, VDD
t
SYS_CLK (5pin)
② Start sending SYS_CLK
after REG_3 is stabilized.
Send SYS_CLK before setting
RESETX to High.
t
10 cycle 10 cycle
or more or more
BCLK
LRCLK
SDATA1
SDATA2
(6pin)
(7pin)
(8pin)
(9pin)
③ Send digital input signal
before RESETX release.
t
RESETX (10pin)
④ Send SYS_CLK 10 cycle or more
before setting RESETX to High.
t
SCL
SDA
(13pin)
(14pin)
⑤ Release RESETX then send 10 cycle or
more SYS_CLK before starting I2C BUS
data communication.
t
⇒ Start data transmission
PDX (12pin)
⑥ Set PDX to High after initial setting by I2C BUS.
t
OUT_DAC1 (25pin)
OUT_DAC2 (24pin)
2.5V(BIAS)
t
MUTEX (11pin)
⑦ Change MUTEX to High after FILA terminal stabilized.
FILA terminal changes from 0V → 2.5V by setting PDX=High.
t
Soft-start
43msec(fs=48kHz.)
Speaker output
t
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17/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Power supply shut-down sequence
VCCA (27pin)
VCCP1 (51, 52pin)
VCCP2 (30, 31pin)
⑥Power down VCCA, VCCP1, VCCP2
simultaneously.
VCCA,VCCP1,VCCP2
REG_3 (3pin)
VDD
(18pin)
REG_3, VDD
t
SYS_CLK (5pin)
⑤ Set RESETX to Low then input
SYS_CLK for 10 cycle or more. And then
stop SYS_CLK signal.
t
10 cycle
or more
BCLK
LRCLK
SDATA1
SDATA2
(6pin)
(7pin)
(8pin)
(9pin)
④ Stop digital input signal.
t
RESETX (10pin)
③ Set RESETX to Low.
t
SCL
SDA
(13pin)
(14pin)
t
PDX (12pin)
② Set PDX to Low.
t
OUT_DAC1 (25pin)
OUT_DAC2 (24pin)
2.5V(BIAS)
t
MUTEX (11pin)
① Change MUTEX to Low.
t
Speaker output
Soft-mute
43msec(fs=48kHz)
t
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18/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●About the protection function
Protection function
Detecting & Releasing condition
Output short protection
Detecting
condition
Detecting current = 10A (TYP.)
DC voltage protection
in the speaker
Detecting
condition
PWM output Duty=0% or 100%
43msec(fs=48kHz) above fixed
Detecting
condition
Chip temperature to be above 150℃ (TYP.)
High temperature
protection
Under voltage
protection
Clock stop protection
DAC
Output
PWM
Output
HiZ_Low
L
(Latch) (Latch)
Normal
operation HiZ_Low
L
(Latch) (Latch)
Normal
operation
HiZ_Low
Releasing
condition
Chip temperature to be below 120℃ (TYP.)
Detecting
condition
Power supply voltage to be below 8V (TYP.)
Releasing
condition
Power supply voltage to be above 9V (TYP.)
Detecting
condition
No change to SYS_CLK more than 1usec (TYP.)
Irregular
output
Input to SYS_CLK
Normal
Normal
operation operation
Releasing
condition
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19/32
ERROR
Output
Normal
operation
Normal
operation
H
HiZ_Low
Normal
operation
H
HiZ_Low
H
2010.05 - Rev.B
Technical Note
BM5446EFV
1) Output short protection(Short to the power supply)
This IC has the output short protection circuit that stops the PWM output when the PWM output is short-circuited to the
power supply due to abnormality.
Detecting condition - It will detect when MUTE pin is set High and the current that flows in the PWM output pin
becomes 10A(TYP.) or more. The PWM output instantaneously enters the state of HiZ-Low if
detected, and IC does the latch.
Releasing method - ①After the MUTEX pin is set Low once, the MUTEX pin is set High again.
②Turning on the power supply again.
Short to VCC
Release from short to VCC
OUT1P (48, 49pin)
OUT1N (43, 44pin)
OUT2P (33, 34pin)
OUT2N (38, 39pin)
t
PWM out：　IC latches with HiZ-Low.
Normal operation after released
from Latch state.
Over current
10A(TYP.)
t
ERROR (26pin)
t
１μsec(TYP.)
MUTEX（11pin）
Latch release
t
2) Output short protection(Short to GND)
BM5446EFV has the output short protection circuit that stops the PWM output when the PWM output is short-circuited to
GND due to abnormality.
Detecting condition - It will detect when MUTE pin is set High and the current that flows in the PWM output terminal
becomes 10A(TYP.) or more. The PWM output instantaneously enters the state of HiZ-Low if
detected, and IC does the latch.
Releasing method – ①After the MUTEX pin is set Low once, the MUTEX pin is set High again.
②Turning on the power supply again.
Short to GND
Release from short to GND
OUT1P (48, 49pin)
OUT1N (43, 44pin)
OUT2P (33, 34pin)
OUT2N (38, 39pin)
t
PWM out ： IC latches with HiZ-Low state.
Normal operation after released
from latch state.
Ovre current
10A(TYP.)
t
ERROR (26pin)
t
１μsec(TYP.)
MUTEX(11pin)
Latch release
t
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20/32
2010.05 - Rev.B
Technical Note
BM5446EFV
3) DC voltage protection in the speaker
When the DC voltage in the speaker is impressed due to abnormality, this IC has the protection circuit where the speaker
is defended from destruction.
Detecting condition - It will detect when MUTE pin is set High and PWM output Duty=0% or 100% , 43msec(fs=48kHz)
or above. Once detected, The PWM output instantaneously enters the state of HiZ-Low, and IC
does the latch.
Releasing method – ①After the MUTEX pin is set Low once, the MUTEX pin is set High again.
②Turning on the power supply again
PWM out locked duty=100% abnormal state.
Abnormal state release
OUT1P (48, 49pin)
OUT1N (43, 44pin)
OUT2P (33, 34pin)
OUT2N (38, 39pin)
t
PWM out ： IC latches with HiZ-Low state.
Latch release state.
Speaker out
t
Soft-start
ERROR (26pin)
43msec(fs=48kHz)
Protection start surge current
into speaker output for 43
msec and over.
t
MUTEX(11pin)
Latch release
t
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© 2010 ROHM Co., Ltd. All rights reserved.
21/32
2010.05 - Rev.B
Technical Note
BM5446EFV
4) High temperature protection
BM5446EFV has the high temperature protection circuit that prevents thermal reckless driving under an abnormal state
for the temperature of the chip to exceed Tjmax=150℃.
Detecting condition - It will detect when MUTE pin is set High and the temperature of the chip becomes 150℃(TYP.) or
more. The speaker output is muted through a soft-mute when detected.
Releasing condition - It will release when MUTE pin is set High and the temperature of the chip becomes 120℃(TYP.)
or less. The speaker output is outputted through a soft-start when released.
Temparature of
IC chip junction(℃)
150℃
120℃
t
OUT1P (48, 49pin)
OUT1N (43, 44pin)
OUT2P (33, 34pin)
OUT2N (38, 39pin)
HiZ-Low
t
Soft-mute
43msec(fs=48kHz)
Soft-start
43msec(fs=48kHz)
Speaker output
t
ERROR (26pin)
3.3V
t
OUT_DAC1 (25pin)
OUT_DAC2 (24pin)
t
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© 2010 ROHM Co., Ltd. All rights reserved.
22/32
2010.05 - Rev.B
Technical Note
BM5446EFV
5) Under voltage protection
BM5446EFV has the under voltage protection circuit that make speaker output mute once detecting extreme drop of the
power supply voltage.
Detecting condition – It will detect when MUTE pin is set High and the power supply voltage becomes lower than 8V.
The speaker output is muted through a soft-mute when detected.
Releasing condition – It will release when MUTE pin is set High and the power supply voltage becomes more than 9V.
The speaker output is outputted through a soft-start when released.
VCCA (27pin)
VCCP1 (51, 52pin)
VCCP2 (30, 31pin)
9V
8V
t
OUT1P (48, 49pin)
OUT1N (43, 44pin)
OUT2P (33, 34pin)
OUT2N (38, 39pin)
HiZ-Low
t
Soft-mute
43msec(fs=48kHz)
Soft-start
43msec(fs=48kHz)
Speaker output
t
ERROR (26pin)
3.3V
t
OUT_DAC1 (25pin)
OUT_DAC2 (24pin)
t
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© 2010 ROHM Co., Ltd. All rights reserved.
23/32
2010.05 - Rev.B
Technical Note
BM5446EFV
6) Clock stop protection
BM5446EFV has the clock stop protection circuit that make the speaker output mute when the SYS_CLK signal of the
digital audio input stops.
Detecting condition - It will detect when MUTE pin is set High and the SYS_CLK signal doesn't change for about 1usec
or more. The speaker output is muted through a soft-mute when detected.
Releasing condition - It will release when MUTE pin is set High and the SYS_CLK signal returns to the normal clock
operation. The speaker output is outputted through a soft-start when released.
Clock stop
Clock recover
SYS_CLK (5pin)
t
Protection start with
about 1μsec clock stop.
BCLK (6pin)
t
OUT1P (48, 49pin)
OUT1N (43, 44pin)
OUT2P (33, 34pin)
OUT2N (38, 39pin)
HiZ-Low State.
t
Soft-start (Auto recovery)
43msec(fs=48kHz)
Speaker output
t
ERROR (26pin)
3.3V
t
OUT_DAC1 (25pin)
OUT_DAC2 (24pin)
Unstable
t
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© 2010 ROHM Co., Ltd. All rights reserved.
24/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Application Circuit Example (RL_SP=8Ω)
C1 1μF
C2 1μF
C3 1μF
GNDA
1
FILP
2
FILA
3
REG_3
4
GNDA
REG_G1
54
C54
3.3μF
NC 53
VCCP1
VCCP1
52
51
+
SYS_CLK
BCLK
Digital Audio
Source
NC 50
5
6
LRCLK
7
SDATA1
8
SDATA2
9
RESETＸ
C45
0.1μF
L48
22μH
49
Driver
1P
I2S/LJ/
RJ
Interface
48
REG_G1
470pF
C48B C48A
0.068μF
R48B
5.6Ω
C47
1μF
47
0.33μF
C43C
46
Driver
1N
10
45
GNDP1
MUTEＸ
μ-con
11
PDX
GNDP1
Control
Interface
44
12
3.3V
10kΩ
SCL
3.3V
10kΩ
SDA
VSS
14
15
C16
1μF
I2 C
Interface
DSP
C18
1μF
C19
0.027μF R19
1.5kΩ
C20 2700pF
NC 41
40
VSS1
17
TEST1
38
18
VDD
37
19
PLL
20
VSS2
Driver
2N
21
1μF
C25
22
33
23
NC 32
VCCA
DAC
25
26
High Temperature Protection
Under Voltage Protection
Clock Stop Protection
+
SP 2ch
(8Ω)
L33
22μH
C30
0.1μF
C30D
220μF
30
VCCP2
VCCP2
NC 29
Output Short Protection
Output DC Voltage Protection
REG_G2
27
C27D
GNDA
C31C
0.33μF
31
24
3.3V
100kΩ
C38A
0.068μF
GNDP2
5.6Ω
0.068μF
C33B
C33A
470pF
C33
1μF
+
ERROR
1μF
C24
R38B
5.6Ω
34
Driver
2P
VSS
OUT_SPDIF
C38B 470pF
GNDP2
R33B
35
TEST2
22μH
L38
36
GNDP2
3.3V
I2C BUS
Address Select
OUT_DAC1
(1ch)
C38
1μF
39
REG_15
REG_G2
OUT_DAC2
(2ch)
22μH
L43
42
PWM
Modulator
SP 1ch
(8Ω)
C42
1μF
REG_G2
16
R43BGNDP1
5.6Ω
0.068μF
C43B C43A
470pF
43
REG_G1
13
220μF
C45D
C28
3.3μF
28
VCCA
10μF
C27
0.1μF
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© 2010 ROHM Co., Ltd. All rights reserved.
25/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●BOM list(RL_SP =8Ω)
Parts
Parts No.
Value
Company
Product No.
Rated
Voltage
Tolerance
Size
IC
U1
-
ROHM
BM5446EFV
-
-
18.5mm×9.5mm
TOKO
1168ER-0001
-
(±20%)
10.3mm×7.6mm
Inductor
L33, L38, L43, L48
22µH
SAGAMI
DBE7210H-220M
-
(±20%)
10.5mm×6.4mm
MCR18PZHZFL5R60
1/4W
F(±1%)
3.2mm×1.6mm
Resistor
Capacitor
R33B, R38B
R43B, R48B
5.6Ω
R19
1.5kΩ
MCR01MZPF1501
-
-
1.0mm×0.5mm
C33, C38, C42, C47
1µF
GRM185B31C105KE43
16V
B(±10%）
1.6mm×0.8mm
C27, C30, C45
0.1µF
GRM188B31H104KA92
50V
B(±10%）
1.6mm×0.8mm
C33A, C38A
C43A, C48A
0.068µF
GRM21BB11H683KA01
50V
B(±10%）
2.0mm×1.25mm
C31C, C43C
0.33µF
GRM219B31H334KA87
50V
B(±10%）
2.0mm×1.25mm
C28, C54
3.3µF
GRM188B31A335KE15
10V
B(±10%）
1.6mm×0.8mm
1µF
GRM185B30J105KE25
6.3V
B(±10%）
1.6mm×0.8mm
470pF
GRM188B11H471KA
50V
B(±10%）
2.0mm×1.2mm
C19
0.027µF
GRM188B11C273KA01
16V
B(±10%）
1.6mm×0.8mm
C20
2700pF
GRM188B11E272KA01
25V
B(±10%）
1.6mm×0.8mm
C30D, C45D
220µF
ECA1VMH221
35V
±20%
φ8mm×11.5mm
EEUFC1H100L
50V
±20%
φ5mm×11mm
C1, C2, C3
C16, C18, C25, C24
C33B, C38B
C43B, C48B
Electrolytic
Capacitor
ROHM
MURATA
Panasonic
C27D
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© 2010 ROHM Co., Ltd. All rights reserved.
10µF
26/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Application Circuit Example(RL_SP =6Ω)
C1 1μF
C2 1μF
C3 1μF
GNDA
1
FILP
2
FILA
3
REG_3
4
GNDA
REG_G1
54
C54
3.3μF
NC 53
VCCP1
VCCP1
52
51
+
SYS_CLK
BCLK
Digital Audio
Source
NC 50
5
6
LRCLK
7
SDATA1
8
SDATA2
9
RESETＸ
C45
0.1μF
L48
15μH
49
Driver
1P
I2S/LJ/
RJ
Interface
48
REG_G1
C47
1μF
470pF
C48B C48A
0.1μF
5.6Ω
47
0.47μF
C43C
46
Driver
1N
10
45
GNDP1
MUTEＸ
μ-con
11
PDX
GNDP1
Control
Interface
44
12
3.3V
10kΩ
SCL
3.3V
10kΩ
SDA
14
VSS
15
C16
1μF
I2 C
Interface
DSP
C18
1μF
C19
0.027μF R19
1.5kΩ
C20 2700pF
NC 41
40
VSS1
17
TEST1
38
18
VDD
37
19
PLL
20
VSS2
Driver
2N
21
35
TEST2
1μF
C25
22
33
23
NC 32
VCCA
DAC
25
26
High Temperature Protection
Under Voltage Protection
Clock Stop Protection
+
SP 2ch
(6Ω)
L33
15μH
C30
0.1μF
C30D
220μF
30
VCCP2
VCCP2
NC 29
Output Short Protection
Output DC Voltage Protection
REG_G2
27
C27D
GNDA
R33BGNDP2
5.6Ω
C33B 0.1μF
C33A
470pF
C33
1μF
C31C
0.47μF
31
24
3.3V
100kΩ
R38B
5.6Ω
+
ERROR
1μF
C24
C38B 470pF
C38A
0.1μF
GNDP2
34
Driver
2P
VSS
OUT_SPDIF
15μH
L38
36
GNDP2
3.3V
I2C BUS
Address Select
OUT_DAC1
(1ch)
C38
1μF
39
REG_15
REG_G2
OUT_DAC2
(2ch)
15μH
L43
42
PWM
Modulator
SP 1ch
(6Ω)
C42
1μF
REG_G2
16
GNDP1
5.6Ω
C43B C43A
470pF 0.1μF
43
REG_G1
13
220μF
C45D
C28
3.3μF
28
VCCA
10μF
C27
0.1μF
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© 2010 ROHM Co., Ltd. All rights reserved.
27/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●BOM list(RL_SP =6Ω)
Parts
Parts No.
Value
Company
Product No.
Rated
Voltage
Tolerance
Size
IC
U1
－
ROHM
BM5446EFV
－
－
18.5mm×9.5mm
Inductor
L33, L38, L43, L48
15µH
SAGAMI
DBE7210H-150M
－
(±20%)
10.5mm×6.4mm
R33B, R38B
R43B, R48B
5.6Ω
MCR18PZHZFL5R60
1/4W
F(±1%)
3.2mm×1.6mm
R19
1.5kΩ
MCR01MZPF1501
C33, C38, C42, C47
1µF
GRM185B31C105KE43
16V
B(±10%）
1.6mm×0.8mm
C27, C30, C45, C33A,
C38A, C43A, C48A
0.1µF
GRM188B31H104KA92
50V
B(±10%）
1.6mm×0.8mm
C31C, C43C
0.47µF
GRM21BB31H474KA87
50V
B(±10%）
2.0mm×1.2mm
C28, C54
3.3µF
GRM188B31A335KE15
10V
B(±10%）
1.6mm×0.8mm
1µF
GRM185B30J105KE25
6.3V
B(±10%）
1.6mm×0.8mm
470pF
GRM188B11H471KA
50V
B(±10%）
2.0mm×1.2mm
C19
0.027µF
GRM188B11C273KA01
16V
B(±10%）
1.6mm×0.8mm
C20
2700pF
GRM188B11E272KA01
25V
B(±10%）
1.6mm×0.8mm
C30D, C45D
220µF
ECA1VMH221
35V
±20%
φ8mm×11.5mm
EEUFC1H100L
50V
±20%
φ5mm×11mm
Resistor
Capacitor
Electrolytic
Capacitor
ROHM
1.0mm×0.5mm
MURATA
C1, C2, C3
C16, C18, C25, C24
C33B, C38B
C43B, C48B
Panasonic
C27D
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© 2010 ROHM Co., Ltd. All rights reserved.
10µF
28/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Output LC Filter Circuit
An output filter is required to eliminate radio-frequency components exceeding the audio-frequency region supplied to a
load (speaker). Because this IC uses sampling clock frequencies from 200kHz to 400kHz in the output PWM signals, the
high-frequency components must be appropriately removed.
This section takes an example of an LC type LPF shown in Fig.12, in which coil L and capacitor C compose a differential
filter with an attenuation property of -12dB/oct. A large part of switching currents flow to capacitor C, and only a small part
of the currents flow to speaker RL. This filter reduces unwanted emission this way. In addition, coil L and capacitor Cg
compose a filter against in-phase components, reducing unwanted emission further.
Filter constants depend on load impedances. The following are formulas to calculate values of L, C, and Cg when Q=0.707
is specified.
48, 49
or
38, 39
L =
L
Cg
C
45, 46
or
33, 34
L
RL
2
1
C =
RL
H
4π f C
F
2 π f C RL
Cg
Cg =
0 .2 C
2
F
Fig. 12
RL : Load impedance (Ω)
fC : LPF cut off frequency (Hz)
Following presents output LC filter constants with typical load impedances.
RL
6Ω
8Ω
L
22µH
33µH
fC = 30kHz
C
0.68µF
0.47µF
Cg
0.15µF
0.1µF
RL
6Ω
8Ω
fC = 40kHz
L
C
15µH
0.47µF
22µH
0.33µF
Cg
0.1µF
0.068µF
16Ω
68µH
0.22µF
0.047µF
16Ω
47µH
0.033µF
0.15µF
Use coils with a low direct-current resistance and with a sufficient margin of allowable currents. A high direct-current
resistance causes power losses. In addition, select a closed magnetic circuit type product in normal cases to prevent
unwanted emission.
Use capacitors with a low equivalent series resistance, and good impedance characteristics at high frequency ranges
(100kHz or higher). Also, select an item with sufficient withstand voltage because flowing massive amount of
high-frequency currents is expected.
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© 2010 ROHM Co., Ltd. All rights reserved.
29/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Notes for use
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may
result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when
such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a
special mode where the absolute maximum ratings may be exceeded is anticipated.
2) Power supply lines
As return of current regenerated by back EMF of output coil happens, take steps such as putting capacitor between
power supply and GND as a electric pathway for the regenerated current. Be sure that there is no problem with each
property such as emptied capacity at lower temperature regarding electrolytic capacitor to decide capacity value. If the
connected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage
on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute
maximum ratings. It is recommended to implement a physical safety measure such as the insertion of a voltage clamp
diode between the power supply and GND pins.
3) GND potential (Pin 4, 36, 37, 45, 46), VSS potential (Pin 15, 20)
Any state must become the lowest voltage about GND terminal and VSS terminal.
4) Input terminal
The parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating causes the
wrong operation and destruction. Therefore, please be careful so as not to operate the parasitic elements by impressing
to input terminals lower voltage than GND and VSS. Please do not apply the voltage to the input terminal when the
power-supply voltage is not impressed.
5) Setting of heat
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
This IC exposes its frame of the backside of package. Note that this part is assumed to use after providing heat
dissipation treatment to improve heat dissipation efficiency. Try to occupy as wide as possible with heat dissipation
pattern not only on the board surface but also the backside.
Class D speaker amplifier is high efficiency and low heat generation by comparison with conventional Analog power
amplifier. However, In case it is operated continuously by maximum output power, Power dissipation (Pdiss) may exceed
package dissipation. Please consider about heat design that Power dissipation (Pdiss) does not exceed Package
dissipation (Pd) in average power (Poav). (Tjmax : Maximum junction temperature=150 ℃ , Ta : Peripheral
temperature[℃], θja : Thermal resistance of package[℃/W], Poav : Average power[W], η : Efficiency)
Package dissipation : Pd(W)=(Tjmax - Ta) / θja
Power dissipation : Pdiss(W)= Poav ×(1 / η- 1)
6) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.
7) Thermal shutdown circuit
This product is provided with a built-in thermal shutdown circuit. When the thermal shutdown circuit operates, the output
transistors are placed under open status. The thermal shutdown circuit is primarily intended to shut down the IC avoiding
thermal runaway under abnormal conditions with a chip temperature exceeding Tjmax = 150℃.
8) Shorts between pins and misinstallation
When mounting the IC on a board, pay adequate attention to orientation and placement discrepancies of the IC. If it is
misinstalled and the power is turned on, the IC may be damaged. It also may be damaged if it is shorted by a foreign
substance coming between pins of the IC or between a pin and a power supply or a pin and a GND.
9) Power supply on/off (Pin 27, 30, 31, 51, 52)
In case power supply is started up, RESETX(Pin 10), MUTEX(Pin 11) and PDX (Pin 12) always should be set Low. And in
case power supply is shut down, it should be set Low likewise. Then it is possible to eliminate pop noise when power
supply is turned on/off. And also, all power supply terminals should start up and shut down together.
10) ERROR terminal(Pin 26)
A error flag is outputted when Output short protection and DC voltage protection in the speaker are operated. These flags
are the function which the condition of this product is shown in.
11) N.C. terminal (Pin 29, 32, 41, 50, 53)
N.C. terminal (Non Connection Pin) does not connect to the inside circuit. Therefore, possible to use open.
12) TEST terminal (Pin 17, 21)
TEST terminal connects with ground to prevent the malfunction by external noise.
13) Precautions for Spealer-setting
If the impedance characteristics of the speakers at high-frequency range while increase rapidly, the IC might not have
stable-operation in the resonance frequency range of the LC-filter. Therefore, consider adding damping-circuit, etc.,
depending on the impedance of the speaker.
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© 2010 ROHM Co., Ltd. All rights reserved.
30/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Allowable Power Dissipation
7
PCB③ 6.2W
Power Dissipation Pd （W)
6
5
PCB② 4.5W
4
3
PCB① 2.0W
2
1
0
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140 150
Ambient Temperature:Ta( ℃)
Measuring instrument: TH-156(Shibukawa Kuwano Electrical Instruments Co., Ltd.)
Measuring conditions: Installation on ROHM’s board
Board size: 70mm×70mm×1.6mm(with thermal via on board)
Material: FR4
・The board on exposed heat sink on the back of package are connected by soldering.
PCB① : 1-layer board(back copper foil size: 0mm×0mm)， θja=62.5℃/W
PCB② : 2-layer board(back copper foil size: 70mm×70mm)，θja=27.8℃/W
PCB③ : 4-layer board(back copper foil size: 70mm×70mm)，θja=20.2℃/W
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
31/32
2010.05 - Rev.B
Technical Note
BM5446EFV
●Ordering part number
B
M
5
Part No.
4
4
6
E
Part No.
F
V
Package
EFV : HTSSOP-B54
-
E
2
Packaging and forming specification
E2: Embossed tape and reel
HTSSOP-B54
<Tape and Reel information>
18.5±0.1
(MAX 18.85 include BURR)
+6°
4° −4°
(6.0)
1PIN MARK
1.0±0.2
0.5±0.15
(5.0)
1
Embossed carrier tape (with dry pack)
Quantity
1500pcs
28
7.5±0.1
9.5±0.2
54
Tape
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
27
+0.05
0.17 -0.03
0.8
0.08±0.05
1.0MAX
0.85±0.05
S
0.08 S
0.65
+0.05
0.22 -0.04
0.08
1pin
M
Reel
(Unit : mm)
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
32/32
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.05 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
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More detail product informations and catalogs are available, please contact us.
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