BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 2.5Gbps Tx Burst Mode Laser Transceiver For FTTX Applications The BL1908 is a highly integrated, programmable burst mode laser driver and limiting amplifier intended for ONU/ONT applications up to 2.5 Gbps. Using LVDS/PECL/CML differential burst and data inputs. The BL1908 laser driver has burst enable/disable times of less than 3.3 ns and will automatically maintain the desired extinction ratio. The laser bias and modulation currents can independently be controlled in one of 3 ways - (1) dual closed loop control where the monitor photodiode dynamic response is held to target values, (2) single closed loop control where the average monitor photodiode output is held to a target value or (3) open loop control where the bias and/or modulation current are controlled by a temperature based look-up table. In the closed loop cases, the bias and modulation current value for the first burst may also use the internal temperature sensor and external look-up table. The BL1908 limiting amplifier inputs have a selectable bandwidth and selectable output swing. The input sensitivity is better than 4mV at 1.25Gbps and 5mV at 2.5Gbps.The limiting amplifier features a programmable signal level detector with a typical 2dB of optical hysteresis and an internally programmed JAM function which can be used to squelch chatter on the outputs when no signal is present. If the limiting amplifier is not needed, it may be powered down. Application Fields - APON, BPON, EPON, WDM PON, GPON and GEPON FTTX ONU/ONT modules - SFF/SFP modules Features - Laser driver modulation current up to 100 mA. Bias current up to 80 mA. Typical rise/fall times < 60 ps. Burst on/off < 3.3 ns - DDMI Compatible - Auxiliary 9-bit DAC, 12-bit A/D - Limiting Amplifier 5mV input sensitivity at 2.5 Gbps, selectable gain and bandwidth, signal detect and Jam functions - Programmable SPI or 2-wire interface from external EEPROM or optional microcontroller. (Separate slave and master interfaces.) - Supports IEC-60825 eye safety, including programmable bias and modulation current limits - Tx system current reduced during Burst-off - Operating temperature -40°C to +85°C, 5x5 QFN package 1 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 Block Diagram RxOUTP RxOUTN RxINP limiting amplifier output buffer RxINN JAM bias Offset cancel IREF VDDR VDDR RSSI comparator LOS level detect los threshold GNDR JAM SCL_M /SDO SDA_M /CS SCL_S/ SCLK SDA_S/ SDI control register LA and LDD master I2C slave I2C STSET temp sensor 12bits ADC Inputs select 12bits ADC 9bits DAC DAC_OUT ADC_IN(i) AUX_D A/JAM/ AUX_A D(I) vdd monitor POR VDDT RSSI SPI RSSI/ AUX_A D(V) I2C/ SPI laser driver (data drive) DINP input buffer laser predriver OUTP OUTN TX power monitor (IPIN current) DINN over current alarm VDDT low speed 1010 patern gen BENP internal osc automatic and open loop power control input buffer BENN TX DIS DIS safety logic & fault detection GNDT0 laser bias IBIAS OUT VDDTA IPIN GNDT FAIL Ordering Information Part number Package BL1908 QFN32 Operating temperature Revision History Revision Level Date A Preliminary December 2013 Description Belling Internal Release 2 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 TABLE OF CONTENTS BL1908 1 APPLICATION FIELDS 1 FEATURES 1 BLOCK DIAGRAM 2 ORDERING INFORMATION 2 1.0 PRODUCT SPECIFICATION 4 1.1 A BSOLUTE M AXIMUM R ATINGS 4 1.2 R ECOMMENDED OPERATING C ONDITIONS 6 1.3 DC C HARACTERISTICS 6 1.4 AC C HARACTERISTICS 9 1.5 S AFETY L OGIC T IMING 10 1.6 INPUT /OUTPUT S PECIFICATIONS 10 1.6.1 Internally Generated Slow 1-0 Pattern 10 1.6.2 Two-wire I/O Specifications (Standard or Fast Mode Two-wire Serial) 11 1.6.3 Two-wire Timing Specifications (Standard Mode or Fast Mode Two-wire Serial) 1.7 SPI S PECIFICATIONS 12 1.8 A UXILIARY ADC S PECIFICATIONS 13 1.8.1 General Purpose 9-bit DAC Specification 14 1.9 BL1908 P ACKAGING S PECIFICATIONS 15 1.10 P IN D EFINITIONS 17 2.0 FUNCTIONAL DESCRIPTION 11 24 2.1 BL1908 L ASER D RIVER OVERVIEW 24 2.2 BL1908 L ASER D RIVER D ESCRIPTION 24 2.2.1 Bias and Modulation Current Control 25 2.2.2 Modulator Output 28 2.2.3 Data Inputs 29 2.2.4 Burst Enable Inputs 29 2.2.5 IPIN Input 29 2.3 BL1908 L IMITING A MPLIFIER OVERVIEW 30 2.3.1 Receive Inputs 31 2.3.2 DC Offset Compensation 31 2.3.3 CML Outputs 31 2.3.4 Loss of Signal (LOS) or Signal Detect 31 2.3.5 JAM Function 32 2.3.6 Peak-to-Peak Received Signal Strength Indicator (RSSIpp) 32 2.4 BL1908 S ERIAL C OMMUNICATIONS OVERVIEW 34 2.5 BL1908 L ASER E YE SAFETY 34 2.6 S AFETY CIRCUITRY 34 2.7 R OGUE ONU 34 3.0 APPLICATIONS 35 3.1 A PPLICATIONS INFORMATION 35 3.1.1 BL1908 Laser Driver Applications 35 3.2 C ONNECTING A L ASER TO THE BL1908 35 3.2.1 Serial Interface Functional Description 36 3.3 BL1908 L IMITING A MPLIFIER A PPLICATIONS INFORMATION 3.3.1 Reference Current Generation 41 3.3.2 Input AC-Coupling Capacitor Choosing 42 3.3.3 Rate Selection 42 3.3.4 Setting the Signal Detect Level 42 3.3.5 CMLP and CMLN Termination 43 3.3.6 JAM Function 43 3.4 M ONITORING THE T X AND R X C HANNELS WITH THE BL1908 4.0 REGISTERS 41 43 44 3 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 1. Product Specification 1.1 Absolute Maximum Ratings These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged. Reliable operation at these extremes for any length of time is not implied. NOTE: The package bottom must be adequately grounded to ensure correct thermal and electrical performance, and it is recommended that vias are inserted through to a lower ground plane. Table 1-1. Absolute Maximum Ratings Symbol Parameter Rating Units VCC3R Power supply voltage (VCC-GND) -0.5 to +4V V VCC3T Power supply voltage (VCC-GND) -0.5 to +4V V TJctn Junction temperature -40 to +1251, °C TSTG Storage temperature -65 to +150 °C RXOUTN,RXOUTP CML Output pins voltage VCC - 0.4 to VCC + 0.4 V |RXINP - RXINN| Absolute difference of voltage at data input pins 0.80 V RXINP, RXINN Data input pins voltage meeting |RXINP - RXINN| requirement - 0.4 to VCC + 0.4 V RSSIP-P/AUX A/D(V) RSSI output or voltage A/D input - 0.4 to VCC + 0.4 V AUX DAC/JAM/AUX A/D(I) DAC output, JAM output or A/D input - 0.4 to VCC + 0.4 LOS Loss of Signal status output pin voltage - 0.4 to VCC + 0.4 V 4 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 IA/D(I) Current input A/D(I) TBD IREF Current into Reference input +120 to -120 μA I(LOS) Current into Loss of Signal pin -100 to+1500 μA IBOUT + IMOD Sum of IBIAS and OUTP current 1202 mA DINP/N Data inputs -0.4 to VCC + 0.4 V BENP/N Burst Enable inputs -0.4 to VCC + 0.4 V VIPIN Photodiode anode voltage -0.4 to VCC + 0.4 V DIS Disable input -0.4 to VCC + 0.4 V IPIN Maximum sink current 4 mA FAIL Status flag -0.4 to VCC + 0.4 V OUTP, OUTN Output -0.4 to VCC + 0.4 V 5 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 1. QFN package: Air Velocity θJA 0 m/s 41.7 ºC/W 1 m/s 36.5 ºC/W 2.5 m/s 32.7 ºC/W The above thermal resistance is based on a four layer JEDEC standard board (76.2 x 114.3 mm) with four vias under the center pad. More vias will improve thermal performance. The internal temperature sensor should not be used to verify compliance with the absolute maximum junction temperature above 100 ºC. 2. Higher currents are allowable, but operating temperature must be de-rated. 1.2 Recommended Operating Conditions Table 1-2. Recommended Operating Conditions Parameter Rating Units Power supply: (VCC-GND) +3.3V ± 7.5% V Operating ambient -40 to +85 °C 1.3 DC Characteristics VCC = +3.3V ± 7.5%, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted. Table 1-3. Symbol General DC Characteristics Parameter Conditions Min Typ Max 85 1,2,3 125 55 80 35 50 Units 0x16h[1:0] = 00b, 0x00h[3] = 0b Due closed loop ICC Single Closed Loop Setting register 0x06[4] = 1b will reduce current by ~20 mA during burst-off. 0x16h[1:0] = 01b or 10b 0x00h[3] = 0b setting 0x04[1]=1b Dual Open Loop mA 0x16h[1:0] = 11b, 0x04h[1:0] = 11b 0x00h[3] = 0b 6 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 VIH Input high voltage. DIS, JAM, SCL_S, SDA_S, SCLK, SDI and Burst Enable single-ended input logic high voltage 2 – VCC V VIL Input low voltage. DIS, JAM, SCL_S, SDA_S, SCLK, SDI and Burst Enable single-ended input logic high voltage 0 – 0.8 V VOH Output high voltage FAIL, LOS, SDO 2.6 – VCC V 0 – 0.4 V Output Low voltage VOL FAIL, LOS, SDO,SCL_M, SDA_M POR Power-On SET/RESET Sinking 2 mA or less 2.7 Set (for positive going supply voltage) Reset (for negative going supply voltage) V 2.6 Notes: 1. Excludes laser bias and modulation current. 2. Disabling the DAC will reduce the current by 270 μA + DAC programmed source current. 3. Disabling the limiting amplifier reduces the current consumption by TBD. Table 1-4. Symbol IMODOUT PWR_SAVE IBIASOUT Laser Driver DC Characteristics Parameter Conditions Modulation Current Range Min. Typ. Max. Units - 0 to 100 -- mA Reduction in Bias Current register 0x015h[0]=1b and bias current above 30mA During Burst Off1 Bias Current Range 60 % – 0 to 80 -- mA – – 15 Ohm IBIASOUT resistance to VCC1 BEN = LOW, 40 mA bias current, register 0x15h[0]=0b Bias current DAC resolution and accuracy 12 bit resolution, V(IBIASOUT) > 0.85V measured at IBIASOUT =24mA 16.58 19.5 22.43 uA/ count Modulation current DAC resolution and accuracy 12 bit resolution, V(OUTP) >1.1V, IMODOUT=50 mA 2 20.74 24.4 28.06 uA/ count Monitor photodiode average current adjustment range Single Closed loop bias current control – 0 to 2000 – uA PAVE_TARGET Monitor photodiode DAC resolution 8 bit resolution 18h[3]=0b 18h[3]=1b, 0x08h[0]=0b - 8.33 2.08 - uA/ count IMD_Threshold Monitor photodiode threshold current adjustment range. (P0 current amplitude) Dual Closed loop bias current control – 0 to 1000 – uA RBOFF IMD_AVE 7 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 8 bit resolution 18h[3]=0b 18h[3]=1b, 0x08h[0]=0b - 4.169 1.042 - uA/ count Monitor photodiode peak Dual Closed loop modulation current current adjustment range control 0 0 to 3000 – uA Monitor photodiode DAC resolution 3000uA range 300uA range - 12.5 3.125 - P0TARGET Monitor photodiode DAC IMD_PEAK P1TARGET 8 bit resolution 18h[3]=0b 18h[3]=1b, 0x08h[0]=0b Maximum monitor photodiode capacitance for APC loop stability for dual loop mode. Includes all associated parasitic capacitances. Voltage at IPIN. This will be the monitor photodiode anode voltage CPD_MAX VIPIN For dual closed loop bias and modulation current control. uA/ count 15 pF For closed loop average bias or average modulation current control. 56(3) Average IPIN current < 2000 uA 1 V Differential input impedance Data inputs (and Burst Enable inputs when set to differential mode) -- 100 – Ohm Common-mode input compliance voltage Data inputs (and Burst Enable inputs when set to differential mode) 1.15 – VCC-0.2 V VIN(DIFF) Differential input voltage = 2 x (DINPHIGH - DINPLOW) and 2 x (BENPHIGH - BENPLOW) when Burst Enable Inputs set to differential mode 200 – 1600 mVpp Rogue ONU Detect Laser Forward Voltage necessary to assert FAIL during Burst OFF VCC-700 mV RIN_DIFF VINCM VFAULTL Lower voltage threshold for fault inputs IBIASOUT, FAIL asserts if any of these signals fall below this value. OUTP, IPIN 400 mV VFAULTH Upper voltage threshold for fault input IPIN 2100 mV FAIL asserts if any of these signals rise above this value. Notes: 1. Use power saver mode to insure laser is off during burst off at high temperatures and bias currents. 2. OUTP and OUTN will operate at voltages as low as 0.7V, however, open loop look-up table operation will be less accurate. 3. Up to 50pF of capacitance is allowed if isolated from IPIN by 100~200 ohms or equivalent inductance. Table 1-5. Symbol Limiting Amplifier DC Characteristics Parameter Conditions Min Typ Max Units VOUTL300 CML Output Low Voltage (RxOUTP, RxOUTN) 300mV swing Single ended; 50 Ohm load to VCC, 20 mvp-p input 0x00h[3]=0b - VCC-0.34 - V VOUTH300 CML Output High Voltage (RXOUTP, RXOUTN) 300mV swing Single ended; 50 Ohm load to VCC, 20 mvp-p input 0x00h[3]=0b - VCC0.002 VCC V VOUT300 IVOUTL300 - VOUTH300I Output swing of CML outputs Single ended; 50 Ohm load to VCC on RxOUTP and RxOUTN 0x00h[3]=0b 270 340 VOUTL500 CML Output Low Voltage (RxOUTP, RxOUTN) 500mV swing Single ended; 50 Ohm load to VCC, 20mvp-p input, -40°C to 100°C, 0x00h[3]=1b - VCC-0.6 mV - V 8 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 VOUTH500 CML Output High Voltage (RXOUTP, RXOUTN) 500mV swing Single ended; 50 Ohm load to VCC, 20mvp-p input, -40°C to 100°C 0x00h[3]=1b VOUT500 IVOUTL500 - VOUTH500I Output swing of CML outputs Single ended; 50 Ohm load to VCC on RxOUTP and RxOUTN 0x00h[3]=1b VCC-0.01 395 VRSSI_p-p Peak to Peak RSSI of RxIN RINDIFF Differential Input Resistance V 590 40 Measured between RXINP and RXINN 785 mV 300 mV – 120 1.4 AC Characteristics VCC = +3.3V ± 7.5%, TA = -40°C to +85°C, input bit rate = 2.67 Gbps high rate mode (register RATESEL = 1b(1)), 50mA modulation current unless otherwise noted. Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted. Table 1-6. Laser Driver AC Characteristics Symbol Parameter tr Modulation output rise time tf Modulation output fall time DJ Deterministic jitter Conditions 20% to 80% into 20 Ohm. For Imod = 50mA. Measured using 11110000 pattern at 2.67 Gbps Min. Typ. – 60 ps – 60 ps Measured with 50 mA of modulation current into a 21 Ohm load, 215 - 1 Max. Units. 35 pspp 5.2 ns 4.8 ns PRBS at 2.67 Gbps (includes DCD) IBIAS_ON 50% BEN to 90% IBIAS BEN low -> high, LVDS differential input (measured electrically) Configured for operation at less than 100 °C Register 0x15h[0]=0b Propagation turn-on delay between BEN and IBIAS. Configured for operation up to 100 degrees C and bias currents greater than DAC code 110000000000 (~30mA) Register 0x15h[0]=1b IBIAS_OFF Propagation turn-off delay between BEN and IBIAS. 50% BEN to 90% IBIAS BEN low -> high, LVDS differential input (measured electrically) Configured for operation at less than 100 °C Register 0x15h[0]=0b Configured for operation up to 100 degrees C and bias currents greater than DAC code 110000000000 (~30mA) Register 0x15h[0]=1b Table 1-7. Symbol VIN(MIN) Limiting Amplifier AC Characteristics Parameter Differential Input Sensitivity Conditions Laser Driver operating in burst mode or CW at Gbps, 20 mA modulation and 0 mA bias 1.25 Gbps, BER < 10-12, (RATESEL = 0b) 2.5Gbps, BER < 10-12, (RATESEL = 1b) VIN(MAX) Input Overload BER < 10-12, differential input 2.5 Gbps BER < 10-12, single-ended input, 2.5 Gbps Min Typ Max Units – – 3 4.5 6 8 1200 – – mV 600 – – mV mV 9 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 vn RMS Input Referred Noise RATESEL = 1b – 280 – uVRMS VLOS Loss of Signal Programmable Differential inputs Assert Range 10 – 50 mV HYS Signal Detect Hysteresis Electrical; across LOS programmable range 2 3.5 5.5 dB Differential input signal range 4 – 100 mV Small-Signal –3dB Low Frequency Cutoff Excluding AC coupling capacitors – 4 – kHz DJ Deterministic Jitter (includes DCD) PRBS 2^15-1 pattern at 2.67 Gbps, 10 mVPP input. High Rate mode (register 0x00h[5]=1b), Laser Driver active. – 25 48 ps RJ Random Jitter 10 mVPP input at 2.5Gbps. High Rate mode (register 0x00h[5]=1b), Laser Driver active. – 4.7 – psRMS Receive Data Output Rise and Fall Times 20% to 80%; outputs terminated into 50 Ohm; 0 mVPP input. Measured using 11110000 pattern at 2.67 Gbps High Rate mode (register 0x00h[5]=1b), Low Rate mode (register 0x00h[5]=0b), – – 80 110 255 RSSIPK-PK Peak-to-peak received signal strength indicator range BWLF tr / tf ps TLOS_ON Time from LOS state until LOS output is asserted LOS assert time after 1 VPP input signal is turned off; signal detect level set to 10 mV 2.3 – 80 μs TLOS_OFF Time from non-LOS state until LOS is deasserted LOS deassert time after input crosses signal detect level; signal detect set to 10 mV with applied input signal of 20 mVPP 2.3 – 80 μs Notes: 1. Scales proportionally with the datarate. Value given for Gbps. 1.5 Safety Logic Timing (VCC = 3.3V +/-7.5%, TA =-40 °C to +85 °C, unless otherwise noted). Typical values are at VCC = 3.3 V, IBIASOUT = 20 mA, IMOD = 50 mA, TA = 25 °C, unless otherwise noted. Table 1-8. Symbol Safety Logic Timing Parameter t_off DIS assert time t_init Time to initialize part after power-up Conditions Rising edge of DIS pin to falling edge of IBIAS current and OUTP current below 10% of nominal Includes reading 48 bytes from EEPROM, (48 X 8) X 2 X ( 3.75 us) Min Typ 2.9 Max Units 0.1 μs ms 1.6 Input/Output Specifications 1.6.1 Internally Generated Slow 1-0 Pattern Symbol Parameter Slow 1-0 pattern at OUTP and OUTN Conditions Outputs 0x0Ch[0]=1b 10 MHz (+/-30%)1 1-0 pattern Notes: 1. Guaranteed by design and characterization. 10 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 1.6.2 Two-wire I/O Specifications (Standard or Fast Mode Two-wire Serial) Table 1-9. Symbol 2-Wire Serial Interface CMOS I/O Electrical Specifications (1, 2) Parameter Conditions Min Typ Max Units fixed address 9Ch for writing 9Dh for reading Slave Address, pins 4 and 5 VOL Output logic low voltage IOL = 2 mA 0 – 0.4 V IIH Input current (logic high) No RPULL-UP present -10 – 10 μA IIL Input current (logic low) No RPULL-UP present -10 – 10 μA CI Capacitance of SDA and SCL pins – – 10 pF Notes: 1. Guaranteed by design and characterization. 2. Specified at recommended operating conditions 1.6.3 Two-wire Timing Specifications (Standard Mode or Fast Mode Two-wire Serial) Table 1-10. Master and Slave 2-Wire Timing Specifications (pins 4 and 5) (1, 2,3) (see Figure 1-1) Parameter Symbol Conditions fSCL_MASTER Clock Frequency, SCL Min Typ Max Units – – 400 kHz tLOW Clock Pulse Width Low 1.3 – – μs tHIGH Clock Pulse Width High 1.0 – – μs tAA Clock Low to Data Out Valid 0.05 – 0.9 μs tBUF Time the bus must be free before a new transmission can start 1.3 – – μs tHDSTA Start Hold Time 0.6 – – μs tSUSTA Start Set-up Time 0.6 – – μs tHDDAT Data In Hold Time 0 – – ns tSUDAT Data In Set-up Time 100 – – ns – 250 – kOhm Stop Set-up Time 0.6 – – μs Data Out Hold Time 50 – – ns RPULL-UP tSUSTO tDH Outputs (SDA_M, SCL_M, SDA_S and SCL_S) internal pull-up resistor value (4) Notes: 1. Guaranteed by design and characterization. 2. Specified at recommended operating conditions 3. The master two wire bus is designed to be compatible with the ATMEL AT24C0X or equivalent. It does not necessarily comply with any other 2-wire standard. 4. 4.7 kOhm should be added externally (typical). Figure 1-1. Host and EEPROM Controller Timing Diagram 11 BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 1.7 SPI Specifications Figure 1-2. SPI Sequential WRITE Figure 1-3. SPI Random WRITE Figure 1-4. SPI Sequential READ 12 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 Figure 1-5. SPI Random READ Table 1-11. SPI Timing Specification Symbol Parameter Notes Min Typ Max Units Tds Data set-up time 8 ns Tdh Data hold time 8 ns Tcs Enable xCS set-up time 8 ns Tch xCS hold time 8 ns Tfreq SPI clock frequency 1, 2 SCLK pulse width Trdd Read data output delay following rising edge of SCLK 1 25 MHz 45 55 % 3 12 ns 1. Maximum 25 MHz SCLK for write and 25 MHz for read. 2. To WRITE BL1908 registers with the SPI interface at a clock rate of less than 20 MHz requires that the register be written twice. 1.8 Auxiliary ADC Specifications Table 1-12. A/D Electrical Specifications (12-bit) Range Input Accuracy Type Notes Minimum Maximum Average IPIN Current 0 Units 1400 uA 400 nA 3.55 V Minimum Maximum Units -3 +3 dB 1, 2 -4 +4 % 1, 6 Tx Power Monitor LSB (12 bit) Power Supply (Internal) Voltage 2.7 13 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 Monitor LSB (12 bit) Internal Temperature Monitor (Internal) Temperature -40 +120 °C 0.231 °C/count 4 100 mV 0 2125 mV 519 uV 0 1470 uA 0 375 uA -5 +5 % 1, 7 1 2 kHz – – – – – – – -1 -3 +1 +4 LSB LSB 6 LSB (10-bit) RSSI pk-pk Voltage AUX A/D (V) 1 mV LSB (12 bit) Current AUX A/D (I) Update Rate Linearity: DNL INL All ADCs -3 +3 °C 1, 3, 8 -5 +5 % 1, 4, 5 7 Notes: 1. Single Point module calibration required for valid units and offset correction. 0 μA is ~ 100 counts. 2. Code FFFh means 1500 uA. However, the result is only valid in the range specified. 3. ADC output will be offset binary. Code 000h means the lowest temperature the ADC can measure, while FFFh means the highest temperature the ADC can measure. 4. Input impedance of ADC is larger than 100 kOhm. 5. Code 000h means 0 V, code FFFh means 3 V. However, the result is only valid in the range specified. 6. Measured at 3.05V, 3.3V and 3.55V. 7. 0x17h[3:2]=00b. 8. 0x00h[2]=1b (limiting amplifier powered down), 0x03h[7]=1b (laser driver output disabled), 0x04h=DBh (IPIN circuitry powered down), 0x16h=03h (Dual Open Loop mode), 0x19h=6Fh (Temperature Sensor Slope)" 1.8.1 General Purpose 9-bit DAC Specification Table 1-13. General Purpose 9 bit DAC Parameter Resolution Minimum Typical Maximum Units – 9 – bits - mA Current Mode Operation Input format Full scale output current (current sourcing) (current sinking) Offset binary: 000h = 0 mA 1FFh = full scale 1 0.2 LSB Step Size (current sourcing) (current sinking) Linearity: DNL(current sourcing) DNL (current sinking) INL (current sourcing) INL (current sinking) 2.08 0.41 -1 -1 A -0.3 0.3 0.45 0.45 0.25 0.7 LSB Offset -1 – 1 uA Settling time – 10 – us VCC-2 0 – Compliance (voltage for sourcing current) (voltage for sinking) 1 V 14 BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 1.9 BL1908 Packaging Specifications Figure 1-6. QFN32 Package Information 15 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 32 RxOUTN RxINP RxINN GND RSSIP-P or AUX A/D(I) AUX DAC or JAM or AUX A/D(I) LOS IREF Pin Assignments for BL1908 Device STSET Figure 1-7. 25 24 1 VCC3R RxOUTP /I2C/SPI VCC3R VCC3T 5mm x 5mm SCL_S or SCLK OUTN SDA_S or SDI OUTP GND, connect to PCB ground with an array of > 9 vias. SCL_M or SDO GND0 IBIASOUT SDA_M or /CS 8 17 GND IPIN FAIL DIS DINN DINP BENN 16 BENP 9 VCC3TA VCC3T 16 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 1.10 Pin Definitions Table 1-14. BL1908 Pin Definitions (1 of 7) Pin Number Pin Name 1 RxOUTN 2 RxOUTP 3 VCC3R SCL_S Pin Equivalent Load Function Inverting CML data output. To reverse the positions of RxOUTN and RxOUTP set 0x01h[5] = 1b. see RxOUTN drawing Non-inverting CML data output. 3.3V supply for Limiting Amplifier circuitry A decoupling capacitor should be added at this pin on the same side of the PCB as the BL1908 2 wire interface serial clock input. This function is selected when pin 23 is low. Attach to external microcontroller if used. A 4.7 kOhm to 10 kOhm external pull-up resistor to VCC may be needed. 4 SCLK SDA_S SPI serial interface clock input. This function is selected when pin 23 is high. Attach to external microcontroller if used. 2 wire interface serial data input/output. This function is selected when pin 23 is low. Attach to external microcontroller if used. A 4.7 kOhm to 10 kOhm external pull-up resistor to VCC may be needed. 5 SPI serial interface data input. This function is selected when pin 23 is high. Attach to external microcontroller if used. SDI The SPI interface is as expected for clock rates of 20 MHz or higher. Clock rates of less than 20 MHz require that the register be written twice. 17 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 2 wire interface serial clock output. Attach to external EEPROM if used. SCL_M A 4.7 kOhm to 10 kOhm external pull-up resistor to VCC should be used if an EEPROM is present. 6 SPI serial interface data output. This function is selected when pin 23 is high. Attach to external microcontroller if used. SDO 2 wire interface serial data input/output. Attach to external EEPROM if used. SDA_M 7 8 same as pin SDA_S A 4.7 kOhm to 10 kOhm external pull-up resistor to VCC should be used if an EEPROM is present. CS_bar SPI serial interface chip select. This function is selected when pin 23 is high. Active low. VCC3T 3.3V supply for Laser Driver and I/O circuitry. A decoupling capacitor should be added at this pin on the same side of the PCB as the BL1908. 3.3V supply for IPIN circuitry. 9 VCC3TA A decoupling capacitor should be added at this pin on the same side of the PCB as the BL1908. Do not use the same decoupling capacitor as is used for pin 8. The decoupling capacitors for pins 8 and 9 should have independent ground vias. 18 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 Non-inverting LVDS/PECL burst enable input. Optical output enabled when BENP - BENN = high. To reverse the positions of BENP and BENN set [glob_ctrl1:polflip_ldd_ben] = 1b. To set BENP to single-ended operation set [glob_ctrl1:set_ben_cmos] = 1b. 10 BENP In single-ended operation the BENP threshold is approximately VCC/2. Register glob_ctrl1(0x01h) on page 36 of the data sheet. Bit 3 squelches (forces) the BEN internally regardless of the status of the pins. Bit 6 specifies the polarity (H or L) 11 BENN 12 DINP 13 DINN see pin BENP Inverting LVDS/PECL burst enable input. Optical output enabled when BENP - BENN = high. Leave open when BENP is programmed for single- ended operation. Non-inverting LVDS/PECL data input. OUTP will sink current when DINP - DINN = high. To reverse the positions of DINP and DINN set [glob_ctrl1:polflip_ldd_din] = 1b. See pin DINP Inverting LVDS/PECL data input. OUTN will sink current when DINP - DINN = low. Bias and modulation output disable (TTL/CMOS). 14 DIS When high the bias and modulation outputs are disabled. Set low for normal operation. 19 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 15 FAIL Safety circuit fault output (CMOS). Goes high when a safety logic fault is detected. This output will also be high when DIS is high. This output may be used to drive the gate of a FET sourcing the laser current. 16 IPIN Current input from monitor photodiode anode. 17 GND Connect to circuit board ground. Laser bias current output. Connect directly to laser cathode or at higher bit rates through a ferrite or a small resistor to isolate the capacitance of this pin from the modulation driver, (~1 pF). 18 IBIASOUT Maintain a voltage at least 0.85V above GND at this pin. When BEN is low, a 15Ohm internal resistor to VCC3T is enabled which shunts the bias current away from the laser. Set register 0x015h[0] = 1b to reduce the bias current during ―burstoff‖ to 1/3 of the ―burst-on‖ current (bias current will only be reduced when it is greater than 30 mA). 19 GNDO Ground for output stage. May be connected directly to circuit board ground. Grounding 1 mm to 2 mm away from the BL1908 may result in improved eye quality. 20 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 Positive modulation current output (DC coupled to cathode of laser). Sinks current when DINP is HIGH. 20 OUTP Transient response will degrade if voltage at this pin goes below < 0.7V. The transient response of this output is optimized for a 25 Ohm load. Negative modulation current output. Sinks current when DINN is HIGH. 21 OUTN similar to pin OUTP Maintain a voltage > 1.1V at this pin. The transient response of this output is optimized for a 25 Ohm load. 3.3V supply for Laser Driver and I/O circuitry. 22 A decoupling capacitor should be added at this pin on the same side of the PCB as the BL1908. VCC3T Do not use the same decoupling capacitor as is used for pin 24. The decoupling capacitors for pins 22 and 24 should have independent ground vias. 23 Select I2C or SPI serial protocol for pins 4,5,6 and 7. This pin must be fixed at VCC or ground before VCC reaches the power-on-reset voltage. This pin should not change state after power-on. I2C_bar/SPI similar to pin DIS 3.3V supply for limiting Amplifier circuitry. 24 VCC3R A decoupling capacitor should be added at this pin on the same side of the PCB as the BL1908. VCC3R 1.2K RxINP 25 60 RxINP RxINN 60 Non-inverting data input. Internally terminated with 60 Ohm. 18K 26 RxINN 27 GND see pin RxINP Inverting data input. Internally terminated with 60 Ohm. Connect to circuit board ground. 21 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 Receiver peak-to-peak input voltage monitor. Provides a DC voltage (ground referenced) proportional to the peak-to-peak input voltage swing. RSSIPk-Pk 28 AUX_AD(V) (if selected) AUX_DAC (if selected) AUX_A/D(I) (if selected) Output disable input. When high, data outputs are disabled (with non-inverting output held high and inverting output held low). 29 JAM Same as pin DIS (if selected) Connect to LOS output to disable outputs with loss of signal. Outputs are enabled when JAM is low or floating. Internal 150 kOhm resistor to ground. If not used, connect to ground. 30 LOS Same as pin FAIL Loss of signal output. Goes high when input signal falls below threshold set by STSET. CMOS output. Internal reference current. Must be connected to ground through a 12.5 kOhm 1% resistor. 31 IREF 32 STSET The accuracy of this resistor will affect the accuracy of limiting amplifier thresholds and laser driver output currents. Loss of signal threshold setting input. Connect a 1% resistor between this pin and VCC to set the loss of signal threshold. 22 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 CENTER PAD GND Ground. Must be connected to ground through an array of vias for proper thermal and electrical operation. 23 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 2. Functional Description 2.1 BL1908 Laser Driver Overview The BL1908 contains a highly integrated burst mode laser driver intended for applications to 2.5 Gbps. It is designed to meet the burst mode requirements of all PON applications and it supports fast and accurate turn- on and turn-off of the laser bias and modulation currents. There is 0ns effective initialization time of the bias and modulation current following the power-up sequence because the initial currents can be set by a temperature based look-up table. The configuration and control of the laser driver is accomplished by downloading register settings from an external EEPROM or microcontroller. Safety circuitry is included to signal fault conditions and support eye safety requirements. Internal register settings may be read by an external microcontroller via a 2-wire interface or 3-wire SPI interface to read digitized values of temperature, supply voltage, bias current, modulation current, transmit power and received power for DDMI applications. ―Rogue ONU detection‖ is provided by monitoring the forward voltage of the laser during the burst-off state. Figure 2-1. BL1908 Laser Driver Block Diagram SCL_M /SDO SDA_M /CS SCL_S/ SCLK SDA_S/ SDI master I2C slave I2C control register LA and LDD temp sensor 12bits ADC 12bits ADC Inputs select DAC_OUT 9bits DAC ADC_IN(i) AUX_D A/JAM/ AUX_A D(I) vdd monitor POR VDDT RSSI SPI RSSI/ AUX_A D(V) I2C/ SPI laser driver (data drive) DINP input buffer laser predriver OUTN TX power monitor (IPIN current) DINN GNDT0 over current alarm VDDT BENP OUTP low speed 1010 patern gen internal osc input buffer BENN TX DIS DIS safety logic & fault detection laser bias automatic and open loop power control IBIAS OUT VDDTA IPIN GNDT FAIL 2.2 BL1908 Laser Driver Description Table 2-1. APC Control modes Configuration Dual Closed Loop, with instant start-up Bias Current Control Modulation Current Control Benefits • First burst instant start-up. • Optimum extinction ratio performance over temperature. Dynamic Monitor Dynamic Monitor • Automatic compensation for laser aging of threshold photodiode controlphotodiode control, current (bias current), slope efficiency (modulation look-up table at start- look-up table at startcurrent) and temperature. up up • Does not require a 50% Mark/Space duty factor to maintain accurate bias and modulation current amplitudes. 24 BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 Dual Closed Loop, continuous Dynamic Monitor photodiode control Dynamic Monitor photodiode control • Optimum extinction ratio performance over temperature. • Laser temperature characterization not necessary. • Automatic compensation for laser aging of threshold current (bias current), slope efficiency (modulation current) and temperature. • Does not require a 50% Mark/Space duty factor to maintain accurate bias and modulation current amplitudes. • Low power operation. Single Closed Loop, Bias Current Control Average Monitor Open Loop, Photodiode current Temperature based control, look-up table look-up table at start-up • First burst instant start-up. • Automatic compensation of bias current over temperature and aging. • Look-up table temperature compensation for modulation current. Single Closed Loop, Modulation Current Control Open Loop, Temperature based look-up table • First burst instant start-up. Average Monitor • Automatic compensation of modulation current over Photodiode Current, temperature and aging. look-up table at start• Look-up table temperature compensation for bias up current. Dual Open Loop Open Loop, Temperature based look-up table Open Loop, Temperature based look-up table • First burst instant start-up. • Look-up table temperature compensation for both bias and modulation current. • No Monitor Photodiode needed. 2.2.1 Bias and Modulation Current Control The bias and modulation currents may each be controlled in one of 3 configurations: dual closed loop, single closed loop or dual open loop. The modulation and bias current are controlled by 12 bit DACs. In both the closed loop and open loop configurations, the bias and modulation currents can instantly be brought to the correct amplitude at the beginning of the first burst after power-up with the use of a temperature based look-up table. When Burst Enable is low, the values in the modulation and bias current DACs are frozen. When Burst Enable goes high the bias and modulation currents return to their value at the end of the previous burst. In both the open loop and closed loop configurations, the burst enable and burst disable time of the bias and modulation current is less than 3.3 ns. When burst enable is low, the modulation current is switched to the OUTN output and the bias current is switched through an internal FET to VCC. The impedance of the internal FET is less than 15 Ohm. At high temperatures the laser bias current may be large and the voltage drop across the 15 Ohm may be unacceptable. By setting 0x15h[0] = 1b, the bias current will be reduced during the burst off state to 1/3 of its value during the burst on state when the bias current is 30 mA or greater. When the bias current is less than 30 mA the bias current will not be reduced during the burst off state. 2.2.1.1 Dual Closed Loop with Instant Start-up Dual Closed Loop allows an optical system to maintain its output power and extinction ratio even if the laser performance degrades unpredictably over time. Unlike traditional optical closed loop systems, the Belling’s dual closed loop system uses the monitor photodiode to control both the bias and modulation current. This results in a stable P1 (optical high level) and a stable P0 (optical low level). The minimum value of the monitor photodiode current is used to control the bias current (P0 level) and the maximum value of the monitor photodiode current is used to control the modulation current (P1 level). With the dual closed loop system, extinction ratio and optical power are held constant under all operating conditions. It is not necessary to characterize the temperature characteristics of the laser because the laser bias and modulation current will automatically adjust to hold the monitor photodiode P1 and P0 amplitudes, regardless of temperature or aging. 25 BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 In systems using the average level, the Mark/Space (Data 1/Data 0) duty factor must be 50%. The BL1908 does not require a 50% Mark/Space duty factor when operating in dual closed loop as the dual loop is data duty cycle insensitive. To hold the P1 and P0 monitor photodiode currents constant, the BL1908 determines when the monitor photodiode current is settled at its high or low level. Then the BL1908 compares the monitor photodiode current with target values. Using information from this comparison, internal DACs controlling the bias and modulation current are adjusted to make the monitor photodiode current match the target amplitudes. In many laser packages the laser anode and monitor photodiode cathode share a pin. The monitor photodiode signal can be corrupted by electrical signals coupled from the laser anode. This results in a false reading of the minimum and maximum monitor photodiode current values by the dual closed loop controller. IPIN Masking (or Glitch Mask) will allow the Dual Closed Loop Controller to ignore the monitor photodiode current during these periods when the signal is corrupted. The high and low target amplitudes are stored in registers p1_target (0x09h) and p0_target (0x0Ah). The BL1908 determines when the monitor photodiode current is settled according to values loaded into registers apc_ctrl0 (0x05h[7:2]), apc_ctrl1 (0x06h[3:0]), apc_ctrl2 (0x07h[7:0]) and apc_tia (0x08h[0]). These registers control internal clocks, digital filter settling times and internal TIA gain and bandwidth. The monitor photodiode capacitance is the dominant factor in the settling time. For stability reasons, a maximum of 15 pF of capacitance is allowed on the IPIN node (includes monitor photodiode capacitance plus any parasites, higher capacitances may be used if isolated by a series resistor). The photodiode settling time will need to be programmed according to the monitor photodiode characteristics and the data pattern and bit rate. It is possible to program the BL1908 to recognize the settling time at larger numbers of Marks or Spaces. However, the loop will take longer to close in this case because this data pattern will occur less frequently. The frequency of occurrence in the data pattern decreases by 50% for each Mark or Space added to the length of the settling time. For instant start-up at power-up, the BL1908 will measure the temperature and digitize it with an internal A/D convertor. Using this temperature measurement, a corresponding bias and modulation current amplitude is automatically loaded into registers i0_msb (0x0Dh), ib0_lsb (0x0Eh) and im0_lsb (0x0Fh) from an external EEPROM or these values should be loaded from an external microcontroller if no EEPROM is used. During operation, the BL1908 will automatically adjust the bias and modulation current amplitude for variation in temperature and aging of the laser. When the high or low monitor photodiode current changes, the BL1908 will adjust the modulation or bias current amplitude in registers i_msb (0x59h), im_lsb (0x5Bh) and ib_lsb (0x5Ah) until the monitor photodiode currents again match p1_target (0x09h) and p0_target (0x0Ah). I2.2.1.2 Continuous Mode - Dual Closed Loop Continuous mode Dual Closed Loop allows multi-rate operation over temperature with a single point calibration at room temperature. For continuous mode operation, the burst enable input should be fixed in the enable state. This can be done either in hardware by setting the BEN inputs to single-ended (0x01h[0]=1b) and connecting BENP (pin 10) to VCC. Alternatively, it may be done in the register settings by setting bits 0x01h[3]=1b and 0x01h[6]=1b (BENP may be connected to VCC, ground or left open in this case). In all cases BENN (pin 11) should be left open. All of the DDMI monitoring functions will operate normally in continuous mode. If the BL1908 registers are loaded from EEPROM, the instant start-up look-up table may be used in continuous mode if it is desired that the bias and modulation current start at a value close to the optimum value. If the BL1908 registers are loaded from an external microcontroller, the initial bias and modulation currents can be set in registers 0x0Dh, 0x0Eh and 0x0Fh. 2.2.1.3 Single Closed Loop - Bias Current Control In this mode of operation, the bias current is adjusted to maintain a constant average laser monitor photodiode current. The modulation current is controlled by a temperature based look-up table. This mode of operation is selected by writing register 0x16h[1:0]=10b (selects the operating mode) and 0x16h[3]=1b. (enables averaging). In burst mode applications, the monitor photodiode current will not instantly return to its average value when BEN is enabled. As a result WAIT states should be enabled in the BL1908 when using single closed loop control. Use of WAIT states is described in section IPIN INPUT (Section 2.2.5). To allow the first burst after power-up to instantly come to the correct amplitude, the initial bias and modulation current amplitudes can be selected from a temperature based look-up table, but over time the bias current is adjusted 26 BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 to make the digitized average photodiode current match a target value. The target average monitor photodiode value is located in register p0_target (0x0Ah, 8.33 uA/cnt monitor photodiode current resolution or 2.083 uA/cnt monitor photodiode current resolution if 0x18h[3]=1b). After the BL1908 configuration registers are loaded, the BL1908 will measure the temperature and digitize it with an internal A/D convertor. Using this temperature measurement a corresponding bias current amplitude and modulation current amplitude will be automatically loaded into registers i0_msb (0x0Dh), ib0_lsb (0x0Eh) and im0_lsb (0x0Fh) from an external EEPROM or these registers should be loaded by an external microcontroller at the same time the other configuration registers are loaded. 12 bit DACs in the BL1908 will convert the values in register i0_msb (0x0Dh), ib0_lsb (0x0Eh) and im0_lsb (0x0Fh) into analog currents which will be sunk at the IBIAS and OUTP outputs when the BL1908 DIS pin is low and BEN pin is high. Then the bias control loop will take over and refine the bias output to more closely match p0_target (0x0Ah). During operation, the BL1908 will automatically adjust the bias current amplitude for variation in temperature and aging of the laser. When the average monitor photodiode current changes, the BL1908 will adjust the bias current amplitude in registers i_msb (0x59h) and ib_lsb (0x5Ah) until the average monitor photodiode current again matches the target average monitor photodiode current value. The BL1908 temperature sensor will automatically measure the temperature and update the modulation current from EEPROM when the temperature changes. If no EEPROM is used, an external microcontroller should periodically read the temperature at register temp (0x58h [7:0] +0x57h[7:4]) and update the bias current amplitudes at registers i0_msb (0x0Dh [3:0]) and ib0_lsb (0x0Eh). 2.2.1.4 Single Closed Loop Modulation Current Control In this mode of operation, the modulation current is adjusted to maintain a constant average laser monitor photodiode current. The bias current is controlled by a temperature based look-up table. Both the bias and modulation current amplitude are digitized and when the burst is enabled following a burst off period they return to the last digitized amplitude in 3.3 ns. This mode of operation is not commonly used, but it is useful in very high extinction ratio applications where the bias current is below the laser threshold current. The P1 level and the average power level will be controlled by the monitor photodiode and will be very accurate. In burst mode applications the monitor photodiode current will not instantly return to its average value when BEN is enabled. As a result WAIT states should be enabled in the BL1908 when using single closed loop control. Use of WAIT states is described in section IPIN INPUT (Section 2.2.5). To allow the first burst after power-up to instantly come to the correct amplitude, the initial bias and modulation current amplitudes are selected from a temperature based look-up table, but over time the modulation current is adjusted to make the digitized average photodiode current match a target value. At power-up a configuration register setting of value avg = 1b and lk_up = 01b is loaded automatically by EEPROM into register opmode_ctrl (0x16h[3], 0x16h[1:0]). This instructs the BL1908 that single closed loop modulation current control is to be used. The BL1908 will then download the target average monitor photodiode value into register p0_target (0x0Ah) if an external EEPROM is used. The resolution of the setting is 8.33 uA/cnt or 2.083 uA/cnt if 0x18h[3]=1b. If an external microprocessor is used, the above registers should be loaded at power-up. Following the loading of the configuration registers, the BL1908 will measure the temperature and digitize it with an internal A/D convertor. Using this temperature measurement a corresponding bias current amplitude and modulation current amplitude will be automatically loaded into registers i0_msb (0x0Dh), ib0_lsb (0x0Eh) and im0_lsb (0x0Fh) from an external EEPROM or these registers should be loaded by an external microcontroller. 12 bit DACs in the BL1908 will convert the values in register i0_msb (0x0Dh), ib0_lsb (0x0Eh) and im0_lsb (0x0Fh) into analog currents which will be sunk at the IBIAS and OUTP outputs when the BL1908 DIS pin is low and BEN pin is high. Then the modulation control loop will take over and refine the modulation output to more closely match the target monitor photodiode level. During operation, the BL1908 will automatically adjust the modulation current amplitude for variation in temperature and aging of the laser. When the average monitor photodiode current changes, the BL1908 will adjust the modulation current amplitude in registers i_msb (0x59h) and im_lsb (0x5Bh) until the digitized average monitor photodiode current again matches the target average monitor photodiode current value. The BL1908 temperature sensor will automatically measure the temperature and update the bias current from 27 BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 EEPROM when the temperature changes. If no EEPROM is used, an external microcontroller should periodically read the temperature at register temp (0x0Bh[5:0]) or an external temperature sensor and update the modulation current amplitudes at registers i0_msb (0x0Dh[7:4]) and im0_lsb (0x0Fh). 2.2.1.5 Dual Open Loop Control If Dual Open Loop Control is selected, the bias and modulation current amplitudes are controlled by the internal BL1908 temperature sensor or an external microcontroller. In this configuration the signal from the monitor photodiode in the laser package is not used and the monitor photodiode is not needed. At power-up a configuration register setting of value lk_up = 11b is loaded automatically by EEPROM into register opmode_ctrl (0x16h[3], [1:0]). This instructs the BL1908 that Dual Open Loop control is to be used. If an external microprocessor is used, the above register should be loaded at power-up to select Dual Open Loop control. Following the loading of the control registers, the BL1908 will measure the temperature and digitize it with an internal A/D convertor. Using this temperature measurement corresponding bias and modulation current amplitudes (12 bits) will be automatically loaded into registers i0_msb (0x0Dh), ib0_lsb (0x0Eh) and im0_lsb (0x0Fh) from an external EEPROM or the current amplitudes can be loaded into this register by an external microcontroller. 12 bit DACs in the BL1908 will convert the values in registers i0_msb (0x0Dh), ib0_lsb (0x0Eh) and im0_lsb (0x0Fh) into analog currents which will be sunk at the IBIAS and OUTP outputs when the BL1908 DIS pin is low and BEN pin is high. During operation, the BL1908 will automatically adjust the bias and modulation current amplitudes for variation in temperature if an external EEPROM is used. When the temperature changes, the BL1908 temperature sensor will recognize the change and select the new corresponding bias and modulation current amplitudes from the external EEPROM and load it into registers i0_msb (0x0Dh), ib0_lsb (0x0Eh) and im0_lsb (0x0Fh). If an external microcontroller is used, the microcontroller will need to periodically read the temperature at BL1908 register temp (0x0Bh [5:0]) or any other external temperature sensor and adjust the bias and modulation current amplitudes in registers i0_msb (0x0Dh), ib0_lsb (0x0Eh) and im0_lsb (0x0Fh) as necessary. 2.2.2 Modulator Output The output stages OUTP and OUTN are designed to drive 0 Ohm to 50 Ohm or higher output loads over a wide range of currents and circuit architectures. Nominally the output is critically damped for a 25 Ohm load, highly underdamped for a 0 Ohm load and highly overdamped for a 50 Ohm load. The output should be DC coupled in burst mode applications. In burst mode applications, the OUTP and OUTN outputs are not interchangeable since the modulation current will be switched to the OUTN output when BEN is low. In continuous mode applications the OUTP and OUTN outputs may be switched when the data input polarity is reversed at register 0x01h[7]. In a typical application OUTP will be connected directly to the laser cathode through a series resistor. The series combination of the laser and resistor is typically 10 Ohm to 30 Ohm. The choice of series resistance depends on the minimum VCC and maximum modulation current and laser forward voltage. In general, choose the largest series resistor which does not violate the minimum allowable voltage at OUTP. To maintain accuracy when a look-up table is used, OUTP should stay above 1.1V (Dual Open Loop and Single Closed Loop (Bias). In closed loop applications lookup table accuracy is not important and the series resistor should be chosen to keep OUTP above 0.8V. A higher value series resistance will minimize overshoot and make it easier to achieve high extinction ratios with low jitter. A corresponding 10 Ohm to 30 Ohm pull-up resistor to VCC is typically on the OUTN output. The laser driver output stage is separately grounded from the rest of the circuitry (through GND0). At high data rates (2.5 Gbps) GND0 may be connected to ground through a maximum of 15 nH of inductance to improve the transient response. (In general, the inductor is not needed and eye quality is optimal with this pin connected directly to ground). Care should be taken to insure that the modulation outputs are not driven below 0.7V or the eye margin of the optical waveform will degrade. An RC snubbing network from OUTP to laser anode will probably be needed to compensate for the parasitic inductance of the laser package. 28 BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 2.2.3 Data Inputs In burst mode applications data inputs DINP and DINN are usually DC coupled at their inputs. The BL1908 will automatically compensate for LVDS, PECL or CML input levels. The pin location of the DIN inputs may be reversed in register polflip_ldd_din (0x01h[7] = 1) but the laser cathode should always be connected to pin OUTP in burst mode applications since the modulation current will be shunted to the OUTN output during ‖burst off‖ regardless of the polarity configuration of the data inputs. When the data inputs are AC coupled, the internal self biasing will need to be enabled. This is done by setting ac_coupl_ldd = 1 (0x01h[1] = 1). There is an internal 100 Ohm termination resistor between DINP and DINN. The BL1908 data inputs do not match the SFP MSA requirement of 500 mV to 2400 mV. However, the BL1908 inputs are much more sensitive than the requirement so it is easy to attenuate the signal with series resistors at the data inputs to exceed the requirement. The BL1908 sensitivity at the data inputs is specified for operation from 200 mV to 1600 mV. By adding 50 Ohm in series at pins DINP and DINN the acceptable input range is translated to 400 mV to 3200 mV which exceeds the SFP MSA. 2.2.4 Burst Enable Inputs Burst enable inputs BENP and BENN should be DC coupled at their inputs. The BL1908 will automatically compensate for LVDS, PECL, CML differential input levels (0x01h[0]=0b) and CMOS single-ended input levels (0x01h[0]=1b). The pin location of the BEN inputs may be reversed by bit polflip_ldd_ben = 1 in register glob_ctrl1 (0x01h[6] = 1). Set sel_ben_cmos = 1 in register glob_ctrl1 (0x01h[0] = 1) to make pin BENP a single-ended input (leave pin BENN open in this case). The threshold level for BENP in single-ended operation is approximately VCC/2. In continuous mode applications, pin BENP should be connected to VCC and Set sel_ben_cmos = 1 in register glob_ctrl1 (0x01h[0] = 1) to make pin BENP a single-ended input (leave pin BENN open). For calibration purposes it is sometimes useful to force burst enable to the enable or disable state and ignore the state of the Burst Enable pins. To force Burst Enable to the disable state (―squelch‖ burst enable) write registers 0x01h[3]=1b and 0x01[6]=0b. To force Burst Enable to the enable state) write registers 0x01h[3]=1b and 0x01[6]=1b. Squelching burst enable is an alternative way to disable the laser output while keeping the system current constant (the bias and modulation current are shunted away from the laser but remain at the operating level). 2.2.5 IPIN Input Pin IPIN is the input to a high speed trans-impedance amplifier (TIA). If too much capacitance is connected to this pin, this amplifier may become unstable. Up to 15 pF total capacitance (including the monitor photodiode and PCB capacitance) may be connected directly to IPIN. If there is 100 Ohm between the capacitance and pin IPIN, up to 50 pF of capacitance may be attached. If both the modulation and bias currents are operating in open loop mode, pin IPIN should be left open. Care should be taken to avoid current spikes into IPIN which will overdrive the TIA and corrupt the operation of the control loops for the bias and modulation current. External filtering may be required depending on the output characteristics of the laser monitor photodiode. In Dual Closed Loop mode the settling time of the external filtering and monitor PD should be less than the settling time programmed into the BL1908 at apc_ctrl2 (0x07h [7:4]). In Single Closed Loop mode the internal filters (register 0x08h[5:2]) are adequate and no filtering is required between the monitor photodiode and the IPIN input. If spikes are present on the monitor photodiode signal in Dual Closed Loop mode, then it may be possible to mask 29 BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 them using the IPIN glitch mask. By default, the IPIN glitch mask is enabled. The IPIN glitch mask can be disabled by setting registers 0x0Bh[1]=1b and 0x0Ch[1]=1b. The width of the IPIN glitch mask must be set to a value less than the programmed settling time. The IPIN TIA operating parameters will need to be programmed according to the monitor photodiode characteristics and the data pattern, bit rate, and operating mode. In both Dual and Single Closed Loop modes the TIA gain will need to be set at apc_tia (0x08h[0]) and ipin_midrange (0x03h[1]). If the peak to peak monitor photodiode current is expected to range between 5 uA and 300 uA set 0x08h[0]=0b and 0x03h[1]=0b. If the peak to peak monitor photodiode current is expected to range between 8.2 uA and 620 uA set this bit to 0x08h[0]=0b and 0x03h[1]=1b. If the peak to peak monitor photodiode current is expected to range between 30 uA and 3000 uA set this bit to 0x08h[0]=1b and 0x03h[1]=0b. The P1 and P0 settling times (p1_settling at 0x07h[3:0] and p0_settling at 0x07h[7:4]) and decimation factors (deci_p1 at 0x05h[7:5] and deci_p0 at 0x05h[4:2]) must be set in Dual Closed Loop mode. The P1 settling times should be chosen to be less than the bit duration multiplied by the maximum number of consecutive logic 1 states. For example, GePON has a bit duration of 800 ps and is 8b10b encoded so not more than 5 consecutive 1’s or 0’s are present in the data stream. As a result the P1 and P0 settling times should be set to 5 x 800ps = 4ns or less. The decimation factor acts as a low pass filter on the loop that corrects the P1 and P0 optical levels. If the P1 decimation factor is set to 2, then the P1 level will not be adjusted until the loop control logic sees 2 consecutive P1 errors of the same polarity. If the P1 decimation factor is set to 64, then the P1 level will not be adjusted until the logic sees 64 occurrences of P1 errors of the same polarity. Similarly with the P0 decimation factor. When operating in Single Closed Loop mode, the PAVE decimation factors are set in apc_ctrl0 (0x05h [4:2]). The PAVE settling times are set in apc_ctrl2 (0x05h [7:4]). The low pass filter bandwidth of the TIA is set at apc_tia (0x08h[5:2]). In continuous mode operation the filter bandwidth of the TIA can be set to a very low frequency. In burst mode applications it may be necessary to choose a higher frequency filter or a large number of WAIT states will be required to insure that IPIN signal has settled before the single closed loop corrects the operating point. The decimation factor in Single Closed Loop mode operates in the fashion as the decimation factor in Dual Closed Loop mode. It is necessary to set the WAIT states in Single Closed Loop mode. In burst mode applications the IPIN signal bandwidth is low and the signal will not reach it settled level for several nanoseconds following a burst enable. The WAIT state counts have a duration of 25 ns. The WAIT states should be set to a number of counts large enough to allow the external and internal filters on IPIN to settle. The duration of the WAIT state must also be less than the Burst Enable duration or no correction will be made to the bias current amplitude. For example, if the internal filter is set to 17 MHz and there is no external filter then an appropriate WAIT state setting may be 16 (06h[5:2] = 110b) which is a WAIT period of 400 ns. WAIT states should be set to 0 for continuous operation (BENP always high) and greater than zero for burst mode operation. 2.3 BL1908 Limiting Amplifier Overview The BL1908 contains an integrated high-gain limiting amplifier. This limiting amplifier has selectable CML output levels and is intended for use in applications to 2.5 Gbps. Full output swing is achieved even at minimum input sensitivity. If the limiting amplifier function is not needed, it can be powered down by setting register 0x00h[1]=1b. The CML output swing of 300mV can be increased to 500mV by setting register 0x00h[3]=1b. When the CML output swing is increased, the current consumption of the BL1908 is increased by ~10mA When rate select bit la_ratesel[5] = 0b in register glob_ctrl0 (0x00h[5] =0), the limiting amplifier is optimized for downstream data rates ≤ 1.25 Gbps and the sensitivity is improved. The BL1908 also includes a analog RSSI output proportional to the peak to peak input signal and a programmable signal-level detector allows the user to set thresholds at which the logic outputs are enabled. The pin location of the RxOUT outputs may be reversed by bit polflip_la = 1 in register glob_ctrl1 (0x01h[5] =1). Figure 2-2. BL1908 Limiting Amplifier Block Diagram 30 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 RxOUTP RxOUTN RxINP limiting amplifier output buffer RxINN JAM bias Offset cancel IREF VDDR VDDR RSSI comparator LOS level detect los threshold JAM STSET GNDR 2.3.1 Receive Inputs The data inputs RxINP and RxINN are internally connected to an internal reference voltage VTT via 60 Ohm resistors, and generally need to be AC coupled to the TIA outputs. Referring to Figure 2-3, the nominal VTT bias voltage is Vcc - 0.5V. See the applications information section for further details on choosing the AC-coupling capacitor. If the user want to use DC couple, Please set 0x00h[2]=1, The internal bias reference is disenabled. Figure 2-3. Receive Data Inputs VCC3R 1.2K RxINP 60 RxINN 60 18K 2.3.2 DC Offset Compensation For video and OLT applications it is sometimes useful to get the low frequency cut-off as close as possible to 0 Hz. The BL1908 low frequency cut-off is set by an internal DC auto-zero circuit that can remove the effect of DC offsets without using external components. This circuit is configured such that the feedback is effective only at frequencies well below the lowest frequency of interest in typical communications applications. The low frequency cut off is typically 4 kHz. The DC offset compensation can be disabled by setting register 0x02h[0]=1b. The low frequency cut off will then be determined by the external coupling capacitors. However, this will degrade the input sensitivity of the limiting amplifier. 2.3.3 CML Outputs The BL1908 features CML outputs. The outputs may be terminated using any standard AC or DC-coupling CML termination technique. AC-coupling may be used in applications where the average DC content of the data is zero e.g. GPON and GePON. The advantage of this approach is no susceptibility to DC offsets in supply voltages and compatibility with non-CML interfaces such as PECL or LVDS. 2.3.4 Loss of Signal (LOS) or Signal Detect The polarity of the LOS pin can be configured as either a loss of signal output (los_pol = 0) or signal detect output (los_pol = 1) in register (0x02h[1]). Signal detect is simply an inverted LOS signal. 31 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 The BL1908 features input signal level detection over an extended range. Using an external resistor, RST, between pin STSET and VCC the user can program the input signal threshold. The signal detect status is indicated on the LOS output pin. The LOS signal is active when the signal is below the threshold value. The signal detection circuitry has the equivalent of 3.5 dB (typical) electrical hysteresis. RST establishes a threshold voltage at the STSET pin as shown in Figure 2-5. Internally, the input signal level is monitored by the Level Detector which is the RSSIPP voltage. As described in the RSSIPP section, this voltage is proportional to the input signal peak to peak value. The voltage at STSET is internally compared to the signal level from the Level Detector. When the Level Detect voltage is less than V(STSET), LOS is asserted and will stay asserted until the input signal level increases by a predefined amount of hysteresis. When the input level increases by more than this hysteresis above V(STSET), LOS is deasserted. See the applications information section for the selection of RST. Note that STSET can be left open if the loss of signal detector function is not required. In this case LOS would be low. Figure 2-4. STset Input VCC VCC Rst STset Vstset 2.3.5 JAM Function The Jam function is available either at pin 29 when register 0x013[7] = 1b or as a register setting when 0x02h[2] = 1b. When asserted, the JAM pin forces the limiting amplifier outputs to a logic ―one‖ state (RxOUTP high and RxOUTN low). This ensures that no data is propagated through the system. The JAM function is normally used to allow data to propagate only when the signal is above the user's bit-error-rate requirement. It therefore inhibits the data outputs toggling due to noise when there is no signal present (this function is sometimes referred to as ―squelch‖). The loss of signal detection circuit can be used to automatically force the data outputs to a high state when the input signal falls below the threshold. The connection between LOS and JAM may be made externally between the LOS pin and the JAM pin. In this case the LOS pin must be defined as loss of signal (los_pol = 0b, register 0x02h[1]). Jam can also be controlled by LOS without connecting the LOS pin to the JAM input. If register jam_los = 1b (register 0x02h[2]) then the JAM function will be controlled by the internal state of the LOS function regardless of whether the LOS pin is programmed to be the LOS or SD output. 2.3.6 Peak-to-Peak Received Signal Strength Indicator (RSSIpp) The RSSIpp output voltage is logarithmically proportional to the peak-to-peak level of the input signal as shown in the figures below. Figure 2-5. Typical RSSIpp Transfer Function (1.25G PRBS) 32 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 rssi 350 300 RSSI(mv) 250 200 150 100 50 0 0 Figure 2-6. 50 100 150 input(mV) 200 250 300 Typical RSSIpp Transfer Function (2.5G PRBS) rssi 350 300 rssi(mv) 250 200 150 100 50 0 0 50 100 150 input(mV) 200 250 300 33 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 2.4 BL1908 Serial Communications Overview The BL1908 has two 2-wire interfaces and a 3-wire SPI interface. The two 2-wire interfaces are active if pin 23 is low. The 3-wire interface is active if pin 23 is high. Once the BL1908 has been powered, the state of pin 23 should not be changed (it is not allowed to change from 2-wire communications to 3-wire communications after the chip has been powered). Pin 23 Status Active Serial Interface Low I2C slave - Pins 4 and 5, I2C master – Pins 6 and 7 High SPI – Pins 4, 5, 6 and 7 The primary interface (SCL_M and SDA_M, pins 6 and 7) connects the BL1908 to an AT24C08 EEPROM (if it is present). In this case the BL1908 is the master and EEPROM is the slave. A second 2-wire interface (SCL_S and SDA_S, pins 4 and 5) connect the BL1908 to an external microcontroller. In this case the microcontroller is the host and the BL1908 is the slave. At power-up, control registers 0x00h through 0x02Fh in the BL1908 need to be loaded using one of these 2-wire interfaces or using the 3-wire interface. It is not necessary to use both an EEPROM and microcontroller, either is sufficient. If the bias and modulation current are being controlled in a dual closed loop configuration, no further interaction is required between the BL1908 and the EEPROM or external microcontroller after loading the registers at power-up. If the bias or modulation current are being controlled in an open loop configuration, the temperature sensor internal to the BL1908 will update the bias and modulation control registers from EEPROM whenever the temperature changes. If a microcontroller is used, the microcontroller will need to poll the BL1908 temperature sensor register (or an external temperature sensor) and update the bias and modulation control registers when necessary. Register information is also available to an external microcontroller after power-up via the second 2-wire bus. This information includes digitized DDMI values. 2.5 BL1908 Laser Eye Safety Using this laser driver in the manner described herein does not ensure that the resulting laser transmitter complies with established standards such as IEC 825. Users must take the necessary precautions to ensure that eye safety and other applicable standards are met. Note that determining and implementing the level of fault tolerance required by the applications that this part is going into is the responsibility of the transmitter designer and manufacturer since the application of this device cannot be controlled by Belling. 2.6 Safety Circuitry Safety Circuitry in the BL1908 will assert the FAIL output immediately upon detecting a fault condition. In addition, if the an external PFET controlled by FAIL is used to source the laser modulation and bias current the laser current will immediately go open circuit and prevent any current from passing through the laser. Fault detection circuit will monitor the voltage of IPIN, OUTP, OUTN, and monitor the bias and modulation current of laser diode to guarantee the laser diode work properly in all conditions. For an initialization or power-up sequence to be successful, all the fault detection monitors must signal that the chip is ―healthy‖. When DIS goes low, pins are checked for shorts to ground or VCC and a FAIL condition is signalled if there is a fault. The source of the fault can be determined by reading the status register at address 0x3Ch. 2.7 Rogue ONU In addition to the conditions above, a ―rogue ONU‖ condition can also cause FAIL to assert if 0x018h[4]=0b 34 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 (rogue_dis). In PON applications a laser that continues to emit light when it should be off will disrupt communications with all ONUs connected to the same OLT. Rogue ONU will assert the FAIL pin when 0x018h[4]=0b, Burst Enable is low and OUTP is higher in voltage than VCC-0.6V. To determine whether Rogue ONU has caused FAIL to assert, toggle 0x18h[4] and see if the state of FAIL changes. 3. Applications 3.1 Applications Information 3.1.1 BL1908 Laser Driver Applications Figure 3-1. BL1908 Application Schematic C3 C1 ROP RON JAM C4 External MCU R5 RSSI Comp LOS TIA RINN Bias Offset cancel LIMITING AMPLIFIER VCC RINP Limiting Amplifier Output Buffer level detect IREF LOS Threshold TOSA JAM SDA_M /CSB SCL_S/ SCLK SDA_S/ SDI R7 ROSA R6 SCL_M /SDO External EEPROM C2 ST_SET R8 VCC DAC_OUT Aux DAC Master I2C Control Register Slave I2C Aux ADC ADC_IN(i) VCCT R3 C6 Laser POR SPI AUX_DAC/ JAM/ AUX_AD_I VDDT R1 Temp Sensor I2CB/ SPI RSSI R9 RSSI/ AUX_AD_V R2 TINP TINN Input Buffer Laser Pre_driver internal osc BENP BENN Input Buffer APC and Mode Control Fault detection DIS TOP Laser Diode Driver TON Laser Bias L1 IBIAS R4 IPIN FAULT R3 C5 LASER DRIVER 3.2 Connecting a Laser to the BL1908 The BL1908 is designed to operate with a minimal amount of external circuitry. Connecting a laser to the BL1908 is best accomplished by using as few external resistors and capacitors as possible. Ferrites or inductors may be used to improve the optical eye by isolating the BIASout pin and VCC. However, use of ferrites and inductors will slow the burst-on of the laser so the lowest possible inductance value should be used in ONT applications or the inductors should be shunted with low value resistors. Differential currents are used at the output of the BL1908 laser driver, so decoupling capacitors near the laser are usually not necessary and may degrade the optical eye. The printed circuit board traces from OUTP and OUTN to the laser should ideally be 25 Ohm or lower impedance transmission lines. This is often impractical, so the traces should be short and OUTP and OUTN should be sourced from a common VCC point. Excess coupling capacitance between OUTN and OUTP should be avoided. A PFET controlled by the FAIL output may be used to source VCC to the laser for eye safety compliance. Following is a brief description of how to select each of the components shown in Figure 3-2. 35 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 Figure 3-2. Connecting a Laser to the BL1908 VCC 0 Ohm to open 10Ω 10uF 120n OUTN 27Ω BL1908 200Ω BOSA 2.2pF OUTP 300Ω 5.6Ω IBIASOUT 220nH 0~150Ω IPIN 0~56pF The resistor from OUTN to VCC should be as large a value as possible while guaranteeing that OUTN does not go below 0.7V at all operating voltages and temperatures. By making OUTN large, less power is dissipated in the BL1908. The resistor from OUTP to the laser cathode should also be as large as possible while guaranteeing that OUTP does not go below 0.7V. If this resistor is too small, the laser transient waveform is more likely to overshoot in both the positive and negative direction which will make it difficult to achieve high extinction ratios. The series resistor and capacitor from OUTP to the laser anode may be necessary to compensate for the parasitic inductance of the laser package. The resistor should be as large as possible, but small enough to minimize the amplitude of the turn-on spike at the laser cathode. The capacitor should be as small as possible, but large enough that the RC time constant of the 2 components is similar to the LR time constant of the laser parasitic inductance and the series resistance. The resistor between IBIASout and the laser cathode should be at least 10 Ohm and eye quality is better if this resistor is 50 Ohm or greater. It should be as large a value as possible, but small enough that the burst-on time is acceptable. A ferrite or inductor is usually added in parallel with this resistor to make the DC impedance <10 Ohm. IPIN may be left open if both the modulation and bias currents are operating in open loop modes. In dual closed loop modes, care should be taken to avoid large positive or negative going spikes. The spikes may be absorbed by optional RC filtering as shown in the figure. No more than 15 pF should be directly connected to pin IPIN (including monitor photodiode capacitance and parasitic circuit board capacitance). Up to 50 pF of capacitance may be connected to IPIN if it is isolated by at least 100 Ohm. In single closed loop modes the internal filtering is adequate and a small series resistor of 50 Ohm is adequate. 3.2.1 Serial Interface Functional Description 3.2.1.1 BL1908 Chip Register Load from External Micro Controller Without EEPROM For microcontroller use, follow these steps: Without EEPROM 1. Write 06h to Host addr 4Bh (to terminate EEC). 2. Write 02h to Host addr 4Bh (to enable EEC). 3. Write to all necessary set-up registers different from the default values. 36 BL1908 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 4. Write ―0‖ to bit 0 of address 27h to signaling to Analog circuit that all set-up registers are loaded. 5. Polling bit 1 of address 49h (active high) to see if 8 bits temperature is ready for reading. 6. Read the 8 MSB bits of the 10 bit temperature sensor at address 58h. 7. Write 3 bytes data for Ibias/Imod to address 0Dh, 0Eh and 0Fh 8. Write ―1‖ to bit 0 of address 4Eh to update 3-bytes of Ibia/Imod to digital filter generate dat_update pulse. 9. Write ―1‖ to bit 0 of address 4Dh to send the initial ―OK‖ signal to Analog circuit. For all other modes but the dual closed loop, continue the software routine from #6 and #7, #8 for every determined period; for example at every 0.3ms interval. 3.2.1.2 Reading from EEPROM at Power-up The BL1908 is designed and tested to be compatible with the Atmel 24C08A EEPROM. Other EEPROMs may be compatible. If an external EEPROM is present at pins SDA_M and SCL_M, a download from EEPROM to the BL1908 will automatically be initiated. 4.7 kΩ pull-up resistors should be attached at SDA_M, SCL_M, SDA_S and SCL_S if these pins are used. 37 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 Figure 3-3. External EEPROM Memory Map NOTE: See Section 3.2.1.3, ―Writing to EEPROM‖ for different EEPROM programming techniques. Table 3-1. EEPROM Address for Temperature Based Bias and Modulation Current Lookup Temperature Modulation Current MSB Bias Current MSB Bias Current LSB Modulation Current LSB 174 °C 3E0h[7:4] 3E0h[3:0] 3E1h[7:0] 3E2h[7:0] 173.1 °C 2FCh[7:4] 2FCh[3:0] 2FDh[7:0] 2FEh[7:0] 172.1 °C 2F9h[7:4] 2F9h[3:0] 2FAh[7:0] 2FBh[7:0] Data not shown between 172.1 °C and 91.0 °C 91.0 °C 203h[7:4] 203h[3:0] 204h[7:0] 205h[7:0] 90.1 °C 200h[7:4] 200h[3:0] 201h[7:0] 202h[7:0] 38 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 89.1 °C 1FCh[7:4] 1FCh[3:0] 1FDh[7:0] 1FEh[7:0] 88.1 °C 1F9h[7:4] 1F9h[3:0] 1FAh[7:0] 1FBh[7:0] Data not shown between 7.1 °C and 88.1 °C 7.1 °C 103h[7:4] 103h[3:0] 104h[7:0] 105h[7:0] 6.1 °C 100h[7:4] 100h[3:0] 101h[7:0] 102h[7:0] 5.1 °C 0FCh[7:4] 0FCh[3:0] 0FDh[7:0] 0FEh[7:0] 4.1 °C 0F9h[7:4] 0F9h[3:0] 0FAh[7:0] 0FBh[7:0] Data not shown between -76.9 °C and 4.1 °C -76.9 °C 003h[7:4] 003h[3:0] 004h[7:0] 005h[7:0] -77.9 °C 000h[7:4] 000h[3:0] 001h[7:0] 002h[7:0] 3.2.1.3 Writing to EEPROM EEPROM used is 4 table select 2 byte addressing. When an external EEPROM is used, it may uploaded through the BL1908. The data is sourced to the BL1908 through the slave port (SDA_S and SCL_S) which then transfers the data to the EEPROM through the master port (SDA_M and SCL_M). The 2-wire slave address of the BL1908 is fixed as 9Ch. 3.2.1.3.1 Writing Chip Registers and Look-up Table to EEPROM Using an External Controller A new EEPROM comes preloaded with all registers set to FFh. It is recommended to use the ―Initialize Blank EEPROM‖ as soon as the device connects to the microcontroller. This will load the EEPROM with the device chip register defaults for you. Uploading chip registers and the look-up table through the BL1908 can be slow. In production it may be preferable to use an alternate upload method. This process will allow for uploading data into the EEPROM by passing the BL1908 altogether. • Disable master I2C port control from BL1908 EVM. • Connect the external I2C control to the EEPROM at EEPROM pins SDA and SCL. • Upload data to EEPROM from the external controller then disconnect. • Cycle the power and the BL1908 should automatically upload the new chip register values saved in the EEPROM. Following is an example of a program that uses the BL1908 to initialize a blank EEPROM with the default chip values. It is not necessary to initialize the EEPROM values if an external controller directly programs the EEPROM. 1. Write 01h to register 0x4Fh. 2. Write 06h to register 0x4Bh. 3. Write 02h to register 0x4Bh. 4. Write desired values to registers 0x00h through 0x1Bh. 5. Calculate checksum and write the seed value to register 0x1Ch. 6. Write 0x03h to register 0x60h to select page 3 of EEPROM. 7. Write 0x01h to register 0x27h. 39 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 8. Write beginning memory byte address to register 0x48h. 9. Write desired chip register values at register locations 0x40h – 47h (8 bytes at a time). 10. Write 00h to register 0x4Bh. 11. Write 0x03h to register 0x4Ah. 12. Repeat steps 8 through 11 until all chip registers are programmed. 13. Write 0x00h to register 0x4Bh. 14. Perform soft reset or cycle power. 3.2.1.3.2 Writing the BL1908 Register Settings to EEPROM To save BL1908 chip register settings to EEPROM, the BL1908 register settings (00h through 2Fh) are first written to the corresponding location in the BL1908, then they are backed up to an external EEPROM simply by writing to EEC_ctrl (4Ah[2:0] = 010b). An internal state machine in the BL1908 will then initiate and control the writing of the chip register settings in the EEPROM. The Checksum seed will need to be calculated and stored in register 0x1Ch. If the seed is correct 98h will be the value in register 0x5Eh following EEPROM download. Checksum Calculation Routine: Seed = 9 8h checksum = 0 regSum = 0 For i = 0 to 27 // add up the registers. regSum = regSum + readReg(i) Next i // AND regSum with FFh to keep the value one byte in size. regSum = regSum AND FFh If regSum <= Seed Then // if regSum = 64h then checksum would be 98h - 64h = 34h checksum = Seed - regSum Else // Seed + 2's complement of regSum, so if regSum = E8h (2s complement = 18h) // then the new checksum would be 98h + 18h = B0h. checksum = Seed + Not(regSum) + 1 End if // Write checksum to register 1Ch. write(reg1Ch, checksum) The Look-up Table spreadsheet will make this calculation for you. 3.2.1.3.3 Writing the Bias and Modulation Current Temperature-Based Look-up Tables to EEPROM The EEPROM page select is determined by the value written to 0x60h[1:0]. See Chapter 4.0, ―Registers‖. It is recommended that the EEPROM is written to directly from an external programming fixture as described in Section 3.2.1.3.1. The BL1908 writes the modulation and bias current look-up table to the EEPROM in blocks of 8 bytes. The 8 bytes of data are first written to BL1908 registers lkup0_dat, lkup1_dat, ...lkup7_dat, (addresses 0x40h through 0x47h). The EEPROM target address of lkup0_dat is written to lkup_addr (0x48h). The transfer from the BL1908 to the EEPROM will occur after selecting write back look-up data in EEC_ctrl (4Ah[2:0] = 011b). The BL1908 will then automatically write lkup0_dat to the location in lkup_addr and it will write lkup1_dat through lkup7_dat to addresses in the EEPROM 1 to 7 counts above the address in lkup_addr. 40 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 The look-up table values for bias and modulation current at a specific temperature occupy 3 bytes. The first byte contains the 4 most significant bits of the bias and modulation current, the next byte contains the 8 least significant bits of the bias current, the final byte contains the 8 least significant bits of the modulation current. EEPROM addresses (see Figure 3-3 for addresses) hold the bias and modulation current look-up tables using a Microcontroller to load the BL1908 registers. If a microcontroller is available to load the BL1908 registers, an external EEPROM is not needed. When the BL1908 power-on reset sequence is complete, the BL1908 will attempt to download register data from an external EEPROM for 6 ms even if one is not present. An external microcontroller can abort the BL1908 download process from EEPROM by writing 1Ch to register 0x4Bh (disable checksum, disable LUT read, terminate EEPROM download). The order of operation required by the BL1908 of the microcontroller is: 1. Disable EEPROM reading by writing 1Ch to register 0x4Bh. 2. Write 08h to register 0x4Bh. 3. Write the desired values to all chip registers from 0x00h through 0x1Bh. (it is not necessary to write registers with value 00h). If an instant start-up value other than 0 mA is to be used for the bias and modulation current, they should be written to i0_msb at 0Dh, ib0_lsb at 0Eh and im0_lsb at 0Fh. 4. Signal that download is complete so the chip can begin normal operation by writing dcomplete = 0b at 27h[0]. 5. Write ucontrol = 1b at 0x2Fh[0] (a 1b at this location signifies microcontroller control of the registers, 0b signifies EEPROM control of the registers). In Single Closed Loop and Dual Open Loop modes perform the above 5 steps, then continue to loop through steps 6 through 11. 6. Poll the temp_ready bit of Dig_status until it equals 1b, (49h[1]). 7. Write 00h to register 0x4Bh. 8. Read the 10-bit temperature sensor value at 0x58h[7:0] and 0x57h[1:0]. 9. Write the start-up bias current amplitude and modulation current amplitude into registers i0_msb (0Dh), ib0_lsb (0Eh) and im0_lsb (0Fh). 10. Strobe the BL1908 to load the bias and modulation current values at 4Eh[0]. 11. Signal that the data received by the BL1908 is OK by writing a 1 at 4Dh[0]. 3.3 BL1908 Limiting Amplifier Applications Information 3.3.1 Reference Current Generation The BL1908 contains an accurate on-chip bias circuit that requires an external 11.6 kΩ 1% resistor, RREF, from pin IREF to ground to set the LOS threshold voltage at STSET precisely and to set other precision internal references. Figure 3-4. Reference Current Generation 41 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 VCC Vref Iref Rref=10.5K 3.3.2 Input AC-Coupling Capacitor Choosing When AC-coupling the input the coupling capacitor should be of sufficient value to pass the lowest frequencies of interest, bearing in mind the number of consecutive identical bits, and the input resistance of the part. A good rule of thumb is to chose a coupling capacitor that has a cut-off frequency less than 1/(10, 000) of the input data rate. For example, for 2.5 Gbps data, the coupling capacitor should be chosen as: f CUTOFF ≤ (2.5 x 109 / 10 x 103) = 250 x 103 The -3 dB cutoff frequency of the low pass filter at the 50 Ohm input is found as: f3dB = 1/ (2 * pi * 50 Ohm * CAC) so solving for C where f3dB = fCUTOFF CAC = 1/ (2 * pi * 50 Ohm * fCUTOFF) EQ.1 and in this case the minimum capacitor is 12 nF. 3.3.3 Rate Selection When the la_rate_sel is high (0x00h[1]=1b), the BL1908 bandwidth is set to its maximum which allows the BL1908 to operate at data rates up to 2.5 Gbps. When operating at data rates ≤ 1.25 Gbps, then la_rate_sel should be low (0x00h[1]=0b). This enables low-rate mode which reduces the bandwidth (and thus the noise level) of the limiting amplifier. 3.3.4 Setting the Signal Detect Level Table 3-3, show the value for RST is chosen to set the LOS threshold at the desired value(1.25G). Table 3-3. Suggested RST Values RST_set (KΩ) Assert level (mV) Deassert level (mV) 6.18 2.94 4.66 42 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 6.02 6.58 11.35 5.88 9.9 13.35 5.6 19.45 27.2 5.44 30.4 37 5.28 38.6 45.4 5.1 49.8 59.2 3.3.5 CMLP and CMLN Termination The outputs of the BL1908 are CML compatible and any standard AC or DC-coupling termination technique can be used. In both cases the transmission line should either be terminated the appropriate resistor (typically 100 Ohms differentially or 50 ohms single-ended). If using transmission lines other than 50 Ohm, the shunt terminating resistance ZT should equal twice the impedance of the transmission line (ZO). AC-coupling is used in applications where the average DC content of the data is zero. The advantage of this approach is no susceptibility to DC drift and compatibility with non-CML interfaces and CML interfaces using different voltage supplies. DC coupling has the advantage of lower component count (2 less capacitors). DC coupling is preferable in video applications or if JAM is used. In these cases the outputs may be fixed in a near DC state. 3.3.6 JAM Function LOS (loss of signal) can be internally connected to JAM regardless of whether pin 30 is assigned to be LOS or Signal Detect. This is done by setting the jam_los bit high (0x02h[2] = 1b). The same thing can be done external to the BL1908 by connecting the LOS output pin to the Jam input pin if pin 29 is assigned to be JAM (0x13h[7]=1b). When LOS is connected to Jam (internally or externally) and LOS asserts, the Jam function sets the data outputs to a fixed ―one‖ state (CMLP is held high and CMLN is held low). This is normally used to allow data to propagate only when the signal is above the users' bit error rate (BER) requirement. It prevents the outputs from toggling due to noise when no signal is present. From the LOS assert and deassert figures above (Figure 3-5 through Figure 3-7), when an input signal is below the LOS assert threshold, LOS asserts (LOS high) causing Jam to assert. When Jam asserts, the data outputs of the BL1908 are disabled. If the input signal reaches or exceeds the LOS deassert threshold, LOS deasserts (LOS low) causing Jam to deassert, and hence enables the data outputs. 3.4 Monitoring the Tx and Rx Channels with the BL1908 The BL1908 can digitize all the parameters needed for DDMI (Digital Diagnostics Monitoring Interface) compliance. The BL1908 has an internal 12-bit A/D with six multiplexed inputs. All six channels are refreshed at a rate of 1kHz of greater. The refreshing of the A/D can be verified by using the ―conversion complete‖ bit at 0x5Ch[0]. If a 1b is written to this bit, it will clear itself to value 0b when the next A/D conversion is complete. The A/D convertor results can be read at any time from registers below. Table 3-4. Parameters Monitored by the BL1908 Parameter Pin (or internal) Range LSB Register Supply Voltage internal 2.8V to 3.6V 0x52h[7:0] + 0x51h[3:0] Temperature internal -40C to +125C 0x58h[7:0] + 0x57h[1:0] Transmitted Power internal Receive Power (data)1 Pin 29 0x56h[7:0] + 0x57h[7:4] 0x11h[0]=0b 0x53h[7:0] + 0x54h[7:4] 43 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 0x11h[0]=1b Receive Power (video)1 Pin 28 0x50h[7:0] + 0x51h[7:4] Receive Power (data, non-linear peak-to-peak) internal 0x55h[7:0] + 0x54h[3:0] Modulation Current internal 0x59h[7:4] + 0x5Bh[7:0] Bias Current internal 0x59h[3:0] + 0x5Ah[7:0] 1. Pins 28 and 29 are general purpose A/D inputs that can be assigned to monitor any parameter. Before pins 28 and 29 can be used as A/D convertors, they must be assigned this function. To assign pin 28 as a voltage input A/D convertor input set 0x18h[6]=0b. To assign pin 29 as a current input A/D convertor input set 0x18h[5]=0b and 0x13h[7]=0b. The accuracy of the A/D convertors degrades with load capacitance. To compensate the A/D clock can be slowed at register 0x17h[3:2]. In Dual Open Loop mode, transmit power monitoring will only be active if the part is initialized in Single Closed Loop mode at power up. To make transmit power monitoring active in Dual Open Loop mode, register 0x16h[1:0] must be set to 01b or 10b and register 0x04[0]=0b prior to writing download complete (0x27h[0]=0b). After writing 0x27h[0]=0b, the part may be changed to Dual Open Loop mode by writing0x16h[1:0]=11b, but 0x04h[0] must remain set to 0b for transmit power monitoring. 4. Registers Caution: Writing to reserved bits may result in unpredictable behavior at the BL1908 outputs. This can also occur when reserved bits are written from a blank EEPROM. If an external EEPROM is to be programmed through the BL1908 registers 0x40h - 0x048h then first use an initialization program to pre-program EEPROMs with the default values before loading desired register values. Limiting Amplifier Control (glob_ctrl0: Address 0x00h) Bits Type Default Lab el 7:6 00 RSVD Reserved 5 R/W 0 la_ratesel Description 0: 1.25Gbs and below data rate. 1: 2.5Gbs data rate. Reserved 0: RxOUT CML 300mV swing 1: RxOUT CML 500mV swing 4 - 0 RSVD 3 R/W 0 cml_hi 2 R/W 0 dc_couple_la 0：ac couple 1: dc couplel 1 R/W 0 la_powerdown 0: limiting amplifier - operational 1: limiting amplifier - powered down This bit should be set during initial loading of registers. may not be powered up after the initial loading. 0 - 0 RSVD The limiting amplifier Reserved Data and BEN Input Configuration (glob_ctrl1: Address 0x01h) Bits Type Default Label 7 R/W 0 polflip_ldd_din 6 R/W 0 polflip_ldd_ben 5 R/W 0 polflip_la Description Laser Driver Data input polarity flip. 0: normal polarity 1: reversed polarity Laser Driver BEN polarity flip. 0: normal polarity 1: reversed polarity Limiting Amplifier polarity flip. 0: normal polarity 1: reversed polarity 44 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 4 R/W 0 squelch_ldd_din 3 R/W 0 squelch_ldd_ben 2 R/W 0 RSVD 1 R/W 0 ac_coupl_ldd 0 R/W 0 ben_cmos 0: normal operation, modulation outputs controlled by data inputs 1: data inputs ignored. OUTN modulation output active if 0x01h[7]=0b. OUTP modulation output active if 0x01h[7]=1b. 0: normal operation, burst enable state controlled by burst enable inputs 1: burst enable inputs ignored. Burst off state at modulation and bias outputs if 0x01h[6]=0b. Burst on state if 0x01h[6]=1b. Reserved Laser Driver Data input AC coupling, set to 1 for self biasing of data inputs. 0: DC coupled 1: AC coupled 0: BEN differential mode 1: BEN single-ended CMOS/LVTTL LOS, JAM and DC Restore (la_ctrl0: Address 0x02h) Bits Type Default Label 733 23 ----- 1 R/W 0 — R/W 0 0 0 0 00 0 0 0 Description RSVD Reserved jam_los 0: No squelch of limiting amplifier or it is controlled by pin 29 if 0x13h[7]=1b. 1: Limiting Amplifier squelch controlled by internal LOS state. 0: LOS pin is LOS (loss of signal). 1: LOS pin is SD (signal detect). 0: Normal operation. 1: Limiting Amplifier DC Restore disabled, sensitivity reduced. los_pol la_dc_restore IPIN Control (la_ctrl1: Address 0x03h) Bits Type Default Label Descriptio n 7 R/W 0 soft_dis Disable laser outputs. 0: laser may be enabled 1: laser disabled 6:4 - 000 RSVD Reserved 3 R/W 0 RSVD Reserved 2 -- 0 RSVD Reserved 1 R/W 0 ipin_midrange 0 R/W 0 RSVD 0: No effect on IPIN gain. 1: IPIN range of 8.2uA to 620uA when register 0x08h[0]=1. Reserved Open Loop Current Reduction (pd_ldd_ctrl: Address 0x04h) Bits Type Default Label Description 7:3 2 -R/W 00000 0 RSVD pd_ad 1 R/W 0 RSVD Reserved Power down A/D convertor. 0: A/D operational 1: A/D powered down (not recommended) Reserved 0 R/W 0 RSVD Reserved Closed Loop Decimation Factor (apc_ctrl0: Address 0x05h) Bits Type Default Label 7:5 R/W 000 deci_p1[2:0] 4:2 R/W 000 deci_p0[2:0] 1:0 -- 00 RSVD Description Select decimation factor for p1 loop. 000: 1 001: 2 010: 4 011: 8 100: 16 101: 32 110: 64 Select decimation factor for p0 loop. 000: 1 001: 2 010: 4 011: 8 100: 16 101: 32 110: 64 Reserved Closed Loop WAIT States (apc_ctrl1: Address 0x06h) Bits 7:5 Type R/W Default 000 Label wait_state[2:0] Description Select WAIT states in single closed loop mode. Set to 0 in continuous mode applications. 000: 0 001: 2 010: 4 011: 8 100: 16 101: 32 110: 64 111: 64 45 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 4 3:0 R/W 0 RSVD Reserved -- 0000 RSVD Reserved MonitorPhotodiode Setting Time (apc_ctrl2: Address 0x07h) Bits Type Default Label Description 7:4 R/W 0000 p0_settling[3:0] Programs settling time of PD from data falling edge. 1111: 25.6ns 1110: 19.2ns 1101: 16ns 1011: 9.6ns 1010: 8ns 1001: 6.4ns 0111: 4ns 0110: N/A 0101: 3.2ns 0011: 2.4ns 0010: 2ns 0001: 1.6ns 3:0 R/W 0000 p1_settling[3:0] Programs settling time of PD from data rising edge. 1111: 25.6 ns 1110: 19.2 ns 1101: 16 ns 1011: 9.6 ns 1010: 8 ns 1001: 6.4 ns 0111: 4 ns 0110: N/A 0101: 3.2 ns 0011: 2.4 ns 0010: 2 ns 0001: 1.6 ns 1100: 12.8ns 1000: 4.8ns 0100: 2.8ns 0000: N/A 1100: 12.8 ns 1000: 4.8 ns 0100: 2.8 n 0000: N/A Single Closed Loop Filter, IPIN Mid-range (apc_tia: Address 0x08h) Bits Type 7:6 -- 5:2 R/W Default 00 0000 RSVD La be l lpfave[3:0] Description Reserved Select low pass filter for single closed loop operation If lk_up[1:0]=10/01, lpfave_sw[5]=1 Lpfave[3:0] lpfave_sw[4:0] 1010 17MHz 1_1111 1001 8.5MHz 0_1111 1000 4.25MHz 0_0111 0111 2.125MHz 0_0011 0110 1.0625MHz 0_0001 0000 LPF off 0_0000 If lk_up[1:0]=11/00, lpfave_sw[5]=0 lpfave_sw[4:0]=5’b0_0000 1 -- 0 RSVD 0 R/W 0 tia_gain Reserved Select TIA gain. Also see register 0x03h[1] for mid-range gain. 0:IPIN [5 μA:300 μA] 1:IPIN [30 μA:3 mA] IPIN P1 Target (p1_target: Address 0x09h) Bits Type Default Label 7:0 R/W 00000000 p1_t[7:0] Description Sets P1 target in 12.5 μA steps/count in Dual Closed Loop. 00000000: 0 μA 00000001: 12.5 μA … 11111111: 3.1875 mA note: If 0x18h[3]=1b, then the P1 target step size is 3.125μA/count. IPIN P0 Target (p0_target: Address 0x0Ah) Bits Type Default Label 7:0 R/W 00000000 p0_t[7:0] Description Sets P0 target in 4.165 μA steps/count in Dual Closed Loop or Pavg target in 8.33 μA steps/count in Single Closed Loop mode. 00000000: 0/0 μA 00000001: 4.165/8.33 μA … 11111111: 1.062/2.124 mA note: If 0x18h[3]=1b, then the P0 target step size is 1.041μA/count and the SCL Pave target step size is 2.083μA/count. P1 Glitch Mask and DCL Power Saving for CW Operation (p1_glitch: Address 0x0Bh) Bits Type Default Label Description 7 R/W 0 RSVD Reserved 6 -- 0 RSVD Reserved p1mask[3:0] P1 Mask width, , if p1m_dis=1, p1mask=0000 1111: 6.0 ns 1110: 5.6 ns 1101: 5.2 ns 1011: 4.4 ns 1010: 4.0 ns 1001: 3.6 ns 0111: 2.8 ns 0110: 2.4ns 0101: 2.0 ns 0011: 1.2 ns 0010: 0.8 ns 0001: 0.4 ns 5:2 R/W 0000 1100: 4.8 ns 1000: 3.2 ns 0100: 1.6 ns 0000: 0 ns 46 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 1 R/W 0 p1m_dis 0: P1 glitch mask enabled 1: P1 glitch mask disabled 0 R/W 0 RSVD Reserved P0 Glitch Mask, 1010 Pattern Generator, FAIL control (p0_glitch: Address 0x0Ch) Bits Type Default Label Description 7 6 — -- 0 fail_dis 0: FAIL and DIS are independent 1: FAIL low if DIS is high 0 RSVD Reserved 5:2 R/W 0000 p0mask[3:0] 1 R/W 0 p0m_dis 0 R/W 0 p1010 P0 Mask width, （if p0m_dis=1, p0mask=0000） 1111: 6.0 ns 1110: 5.6 ns 1101: 5.2 ns 1011: 4.4 ns 1010: 4.0 ns 1001: 3.6 ns 0111: 2.8 ns 0110: 2.4ns 0101: 2.0 ns 0011: 1.2 ns 0010: 0.8 ns 0001: 0.4 ns 0: P0 glitch mask enabled 1: P0 glitch mask disabled 1100: 4.8 ns 1000: 3.2 ns 0100: 1.6 ns 0000: 0 ns 0: normal operation, outputs controlled by data inputs 1: data inputs ignored, 20 MHz internal clock output at OUTP and OUTN for dual closed loop calibration of P1 and P0 targets. Initial Bias and Modulation Current MSB (i0_msb: Address 0x0Dh) Bits Type Default Label Description 7:4 R/W 0000 im0[11:8] Initial modulation current MSB. 3:0 R/W 0000 ib0[11:8] Initial bias current MSB. Initial Bias Current LSB (ib0_lsb: Address 0x0Eh) Bits Type Default Label 7:0 R/W 00000000 ib0[7:0] Description Initial bias current LSB. Initial Modulation Current LSB (im0_msb: Address 0x0Fh) Bits Type Default 7:0 R/W 00000000 Label im0[7:0] Description Initial modulation current LSB. DAC MSB (DAC_msb: Address 0x10h) Bits Type Default Label 7:0 R/W 00000000 dac[8:1] Description 8 most significant bits of 9 bit Auxiliary DAC, DAC and A/D Control (ddmi_ctrl1: Address 0x11h) Bits Type Default Label Description 7 R/W 0 dac[0] Auxiliary DAC lsb, see 0x10h for MSBs 6 R/W 0 dac_pwr 5 R/W 1 dac_pol 4 -- 0 RSVD 0: Auxiliary 1: Auxiliary 0: Auxiliary 1: Auxiliary Reserved 3 R/W 1 vsense_pwr 2 -- 1 Temp_ad 1 R/W 1 rxp_pwr 0 R/W 0 rxp_x4 DAC enabled DAC powered down DAC sinks current DAC sources current 1: VCC sense A/D enabled 0: VCC sense A/D powered down 1: Temperature sensor A/D enabled 0: Temperature sensor A/D powered down 1: Pin 29 A/D enabled 0: Pin 29 A/D powered down 0: Pin 29 A/D normal gain and range 1: Pin 29 A/D x4 gain and 1/4 range DDMI A/D Control 2 (ddmi_ctrl2: Address 0x12h) Bits 7 Type -- Default 0 Label RSVD Description Reserved 47 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 6 R/W 1 rssi_ad 1: RSSI A/D channel enabled 0: RSSI A/D channel powered down 5 -- 0 RSVD Reserved 4 R/W 1 pin28_ad 1: Pin 28 A/D channel enabled 0: Pin 28 A/D channel powered down 3 -- 0 RSVD Reserved 2 R/W 0 RSVD Reserved 1 -- 0 RSVD Reserved 0 R/W 1 txp_ad 1: TxP A/D channel enabled 0: TxP A/D channel powered down JAM PIN and PD current (jam: Address 0x13h) Bits Type Default Label Description 7 R/W 0 6:3 R/W 0000 RSVD 2 R/W 0 RSVD 1: Assign JAM function to Pin 29 0: Pin 29 is assigned to Aux DAC or Aux A/D(I). Reserved Reserved 1 R/W 0 RSVD Reserved 0 R/W 0 pd_current 0: normal operation 1: Photodiode current mirror disabled for TxP jam_pin Disable IPIN Laser FAIL Detector (safety_logic: Address 0x14h) Bits Type Default Label 7:4 3 2:0 -R/W -- 0000 0 000 Description RSVD Reserved ipinfail_dis 0: normal operation (IPIN must be between [0.4V;1.8V] for FAIL = L). 1: IPIN can be tied to VCC or VEE without triggering FAIL (open loop operation). Reserved RSVD Bias Current Power (bias_ctrl: Address 0x15h) Bits Type 7:3 -- 4 3:1 0 R/W -R/W Default 0000 0 00 0 Label Description RSVD Reserved dcd_correction 0: DCD correction disabled. Use this setting when 0x03[3]=1b 1: DCD correction enabled. Use this setting when 0x03[3]=0b Reserved RSVD bias_ctrl 1: Recommended operation: Bias current shunted away from laser and reduced by 2/3 during burst-off when Ibias > 30 mA. 0: Bias current shunted away from laser but not reduced during burst off. Select Laser Driver Operating Mode (opmode_ctrl: Address 0x16h) Bits Type Default Label 7:4 -- 0000 Reserved 0 avg 1: Single closed loop mode. 0x16h[1:0] = 01b or 10b. 0: Dual open loop or dual closed loop mode. 0x16h[1:0] = 00b or 11b. Reserved 3 R/W 2 R/W 0 RSVD 1:0 R/W 00 lk_up[1:0] Modes of operation: 00b: Dual closed loop: bias and modulation controlled by P0 and P1 monitor photodiode levels. 01b: Single closed loop (modulation control) bias current look-up table, modulation current controlled by average monitor photodiode current. 10b: Single closed loop (bias control) modulation current look-up table, bias current controlled by average monitor photodiode current. 11b: Dual open loop: bias and modulation current look-up table. A/D Clock (A/D Clock Rate: Address 0x17h) Bits Type Default Label 7:4 -- Description RSVD 0000 RSVD Description Reserved 48 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 3:2 R/W 11 ad_clk[1:0] A/D Clock rate for all monitoring functions and external A/D inputs. Clock rate can be reduced for improved accuracy. Clock rate should be reduced for capacitive loads >10 pF at A/D inputs at pins 28 or 29. 11 - 312 kHz 10 - 156 kHz 01 - 78 kHz 00 - 39 kHz 1:0 -- 00 RSVD Reserved Rogue ONU, Pin 28/29 Def, MPD target Curr. Resol, Burst-off power down (rogue: Addr.0x18h) Bits Type Default Label Description 7 -- 0 RSVD Reserved 6 R/W 0 pin28_def 5 R/W 0 pin29_def 0b: 1b: 0b: 1b: 4 R/W 0 rogue_dis 3 R/W 0 ptar_div4 2 R/W 0 boff_pd 1:0 -- 00 RSVD Assign AUX A/D(V) to pin 28, results in 0x50h and 0x51h Assign analog RSSIPP output to pin 28. Assign AUX A/D(I) to pin 29, results in 0x53h and 0x54h Assign AUX DAC to pin 29, source value in 0x10h and 0x11h 0x13h[7]=1b will override this setting and assign pin 29 to JAM 0b: FAIL will assert if rogue ONU detected. 1b: FAIL will not assert if rogue ONU detected 0b: P1, P0 and Pave target scaling normal 1b: P1, P0 and Pave target scaling divided by 4 0b: recommended operation 1b: power down laser driver closed loop control during burst off (50 mA). modulation and bias current amplitude may be inaccurate for bursts less than 500 ns in length. Reserved Temp Sensor (RSVD: Address 0x19h) Bits Type Default 7:0 R/W 00111111 Label temp_slope Description Temperature slop default is 3FH Bias Current Limit (bias_lim: Address 0x1Ah) Bits Type Default Label 7:0 R/W 11111111 Description These 8 bits are compared to the 8 MSBs of the bias current output (0x59h and 0x5Ah). When these values are exceeded, FAIL will assert. bias_lim Modulation Current Limit (mod_lim: Address 0x1Bh) Bits 7:0 Type R/W Default 11111111 Label Description These 8 bits are compared to the 8 MSBs of the modulation current output (0x59h and 0x5Bh). When these values are exceeded, FAIL will assert. mod_lim Checksum (checksum: Address 0x1Ch) Bits Type Default Label 7:0 R/W 00000000 Description The sum of register values in 0x00h through 0x1Bh plus the value in this register should be 98h. The correct value must be loaded into this register before writing to EEPROM (0x4Ah[2:0]=010b). When the correct value is in this register, 0x5Eh=98h. Checksum Register Loading Complete (dcomplete: Address 0x27h) Bits Type Default 7:1 -- 0000000 0 R/W 1 Label Description RSVD Reserved dcomplete 0b: Register Download Complete. (registers 0x00h through 0x27h) 1b: Register Download not Complete. Temp Offset ( Address 0x29h) Bits Type Default 7:0 R/W 00000000 Label temp_offset Description Temperature offset register use to compensate the junction temperature and offset of temperature sensor 49 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 EEPROM or MCU control (ucontrol: Address 0x2Fh) Bits Type Default 7:1 -- 0000000 0 R/W 1 Label Description RSVD Reserved ucontrol 0b: EEPROM control 1b: Microcontroller control. Chip Registers Bits Type 7:4 -- 3:0 R/W Default 0000 0000 Label Description RSVD Reserved div_sel I2C clock divider register. FAIL Flags (status: Address 0x3Ch) Bits Type 7:6 -- Default 00 Label Description RSVD Reserved 5 R 0 fail_mod Mod current digital code overflow. 4 R 0 fail_bias Bias current digital code overflow. 3 R 0 fail_ibiasout IBIASOUT pin is below 400 mV. 2 R 0 fail_iout OUT+ pin is below 400 mV. 1 R 0 fail_ipin IPIN voltage is not between 400 mV and 1.8V. 0 R 0 fail Fail pin status. Write EEPROM Look-up Table Byte 0-7 (Address 0x40h--0x47h) Bits Type Default Label Description 7:0 R/W 00000000 lkup0_dat 1st byte of look-up table data to be transferred to EEPROM. 7:0 R/W 00000000 lkup1_dat 2nd byte of look-up table data to be transferred to EEPROM. 7:0 R/W 00000000 lkup2_dat 3rd byte of look-up table data to be transferred to EEPROM. 7:0 R/W 00000000 lkup3_dat 4th byte of look-up table data to be transferred to EEPROM. 7:0 R/W 00000000 lkup4_dat 5th byte of look-up table data to be transferred to EEPROM. 7:0 R/W 00000000 lkup5_dat 6th byte of look-up table data to be transferred to EEPROM. 7:0 R/W 00000000 lkup6_dat 7th byte of look-up table data to be transferred to EEPROM. 7:0 R/W 00000000 lkup7_dat 8th byte of look-up table data to be transferred to EEPROM. Address of Look-up Table Byte 0 (lkup_addr Address 0x48h) Bits Type Default 7:0 R/W 00000000 Label lkup_addr Description Target EEPROM address for lkup0_dat. This address should be divisible by 8. Temperature Sensor and EEPROM Status (Dig_status Address 0x49h) Bits Type Default Label Description 7:2 -- 000000 RSVD Reserved 1 R 0 temp_ready 1: Temperature sensor output ready for reading. 0: Not ready. 0 R 0 RSVD Reserved EEPROM Read/Write (EEC_ctrl Address 0x4Ah) Bits Type Default Label 7:3 -- 00000 RSVD Description Reserved 50 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 2:0 R/W (selfclr) 000 eec_ctrl[2:0] 000: Idle. 001: Read temperature dependent current data to register 0x0D, 0x0E, 0x0F from EEPROM. 010: Write BL1908 registers 0x00-0x2F to EEPROM. 011: Write 8 byte block of look-up data to EEPROM. 100: Read BL1908 register 0x00-0x2F from EEPROM. EEPROM Download Disable (I2C_ctrl: Address 0x4Bh) Bits Type Default Label 7:5 -- 000 RSVD Reserved 1: Disable checksum calculation following download from EEPROM 0: Normal EEPROM READ operation with checksum. 1: Disable reading of external look-up table. 0: Normal operation. 1: Terminate download from EEPROM. 0: Download from EEPROM active. Reserved 4 R/W 0 dis_chksm 3 R/W 0 dis_norm_read 2 R/W 0 term_eeprom 1:0 -- 00 RSVD DAC Status (Data_OK: Address 0x4Dh) Bits Type Default Label 7:1 0 -R/W Description Description 0000000 RSVD Reserved 0 RSVD Reserved WRITE Initial Bias and Modulation Current into DACs (Strobe: Address 0x4Eh) Bits Type Default Label Description 7:2 -- 000000 RSVD Reserved 1 R/W (self-clr) 0 auxdac_strobe Load AUX DACs. 0 R/W (self-clr) 0 strobe Load bias and modulation current to output DACs. RESET (Soft_RESET: Address 0x4Fh) Bits Type Default Label 7:1 0 -R/W (self-clr) READ STATUS Bits Type 0000000 0 Default RSVD Reserved soft_reset RESET Label R Bits Type 7:4 R 0000 adv_lsb<3:0> Pin 28 A/D(V). 4 LSBs. 3:0 R 0000 ads_lsb<3:0> Digitized supply voltage. 4 LSBs. Bits Type 7:0 R Bits Type 7:0 R Bits Type 7:4 R 3:0 R Type 7:0 R Default Default 00000000 Default 00000000 Default adv_msb<11:4> (Address 0x50h) 7:0 Bits 00000000 Description Label Label ads_msb<11:4> Label adi_msb<11:4> Label Pin 28 A/D(V). 8 MSBs. (Address 0x51h) (Address 0x52h) Digitized supply voltage. 8 MSBs. (Address 0x53h) Pin 29 A/D(I). 8 MSBs. (Address 0x54h) 0000 adi_lsb<3:0> Pin 29 A/D(I). 4 LSBs. 0000 adr_lsb<3:0> Digitized internal RSSIpp voltage. 4 LSBs. Default 00000000 Label adr_msb<11:4> (Address 0x55h) Digitized internal RSSIpp voltage. 8 MSBs. 51 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 Bits Type 7:0 R Bits Type 7:4 R 1:0 R Bits Type 7:0 R Bits Type 7:4 R 3:0 R Bits Type 7:0 R Bits Type 7:0 R Default 00000000 Default 0000 00 Default 00000000 Default Label (Address 0x56h) txp_msb<11:4> Digitized transmit power, 8 MSBs. Label (Address 0x57h) txp_lsb<3:0> Digitized transmit power. 4 LSBs. temp_lsb<1:0> Digitized internal temperature.. Label (Address 0x58h) temp_msb<9:2> Digitized internal temperature sensor. 8 MSBs. Label (Address 0x59h) 0000 Im_msb[11:8] Current modulation current MSB. 0000 ib_msb[11:8] Current bias current MSB. Default 00000000 Default 00000000 Label (Address 0x5Ah) ib_lsb[7:0] Current bias current LSB. Label (Address 0x5Bh) lm_lsb[7:0] Current modulation current LSB. A/D Conversion Done (conv_done: Address 0x5Ch) Bits Type Default Label 7:1 -- 0000000 RSVD Reserved 0 R/W self clr 0 RSVD Reserved Description Read Current Limit and Checksum Status (ilim_stat: Address 0x5Dh) Bits Type Default 7:2 -- 000000 Label Description RSVD Reserved 1b: Either the modulation current limit or the bias current limit has been exceeded 0b: Neither the modulation current limit nor the bias current limit has been exceeded 1 R 0 i_limit_fail 0 R 0 checksum_fail 1b: Checksum failed during EEPROM download 0b: Normal operation. Read Checksum (checksum: Address 0x5Eh) Bits Type Default Label 7:0 R 00000000 checksum[7:0] Description The sum of register bits in 0x00h through 0x1Bh plus the value in register 0x1Ch. If the seed value in 0x1Ch is correct, this register will have value 98h. (If not, correct value in 0x1Ch). Select EEPROM page, Freeze DDMI data (eeprom_page: Address 0x60h) Bits Type 7:3 -- Default 00000 Label Description RSVD Reserved 1b: Freeze A/D data in 0x50h through 0x58h 0b: 0x50h through 0x58h update at 1kHz Select EEPROM page 00b: page 0 01b: page 1 10b: page 2 11b: page 3 2 R/W 0 freeze_ddmi 1:0 R/W 00 eeprom_page Temp_cal ( Address 0x61h) Bits Type Default 7 R/W 1 6:0 R/W 0101100 Label Description temp_en enable signal of temperature sensor High active RSVD Reserved 52 Shanghai Belling Corp., Ltd 810Yishan Rd., Shanghai, China. zip: 200233 Tel: 86-021-24261000 Fax: 86-021-64854424 BL1908 APC clock control( Address 0x65h) Bits Type Default Label 7 R/W 0 6:5 R/W 00 4:3 R/W 00 3:2 R/W 00 0 R/W 0 Description Select APC clock source system clk or slicer clock. 0: Use slicer clock recovery from data input of LDD; 1: Use internal system clock to saving power due_loop_clk_sel due loop mode clk div selection for p1 for slicer clk. 00: No divide; 01: Divide by 2; 01: Divide by 2; 10: Divide by 4; 11: Divide by 8 p1_clk_div[1:0] due loop mode clk div selection for p0 for slicer clk. 00: No divide; 01: Divide by 2; 01: Divide by 2; 10: Divide by 4; 11: Divide by 8 p0_clk_div[1:0] Average mode[single loop] clk div selection. 00: No divide; 01: Divide by 2; 01: Divide by 2; 10: Divide by 4; 11: Divide by 8 avg_clk_div[1:0] RSVD reserved 53