TECHNICAL NOTE Video/Audio Interfaces for TV and DVD Recorders PAL Video I/O Interface BH7624KS2 ٨Description 2 BH7624KS2 is a PAL video signal input switch for DVD-Recorder applications. It supports I C-BUS, 75ȍ driver, PAL control functions with fast blinking, I/O BUS port, and the control for BD3825FS audio signal system switch. A built-in scart terminal is incorporated. ٨Features 1) Vcc 5V Single 2) I2C-BUS control (Input switch to high impedance at power-off) 3) BD3825FS control function built-in 4) Built-in three parallel bus control terminal 5) Standby mode 6) CVBS/Y 5 inputs, 5 Bottom Clamp circuits, with Mute function 1 output 0/2dB AMP + Buffer 2 outputs 6/8dB AMP + 75ȍ driver 1 output 0/6dB AMP + Buffer (for VPS, PDC) 7) Chroma 2 inputs, 2 BIAS circuits, with Mute function 2 outputs 6/8dB AMP + 75ȍ driver control 3 outputs Buffer + 8 order LPF (Record) 8) Each SW independent actuation and all the SW simultaneous actuation are possible for the mute circuit, 9) Playback order LPF 6 circuits built-in 10) Record 8 order LPF 3 circuits built-in 11) Fast blanking circuit built-in 12) Function SW Input, 2 circuit built-in 13) Crosstalk -60dB Typ. 14) DG/DP 0.5%/0.5deg Typ. ٨Applications DVD-Recorder, STB, etc. ٨Absolute maximum ratings (Ta=25°C) Parameter Symbol Power supply voltage V Power dissipation Pd Operating temperature range Topr Storage temperature range Tstg *1 Reduced by 13 mW/qC over 25qC. Limits 7.0 1300 *1 -25 㨪 +65 -55 㨪 +125 Unit V mW °C! °C! ٨Operating range (Ta=25°C) Parameter Supply voltage Symbol Limits Unit Vcc1, Vcc2, VDD 4.75 㨪 5.25 V Ver.B Oct.2005 ٨Electrical characteristics (Unless otherwise specified, Vcc1, Vcc2, VDD=5V, Ta=25°C) Item Symbol MIN. Limit TYP. MAX. Unit Conditions Load 75ȍ Resistor 㧨Whole㧪 VCC Circuit current ICC 85 130 175 mA VDD Circuit current IDD 4.6 7.2 9.8 mA VCC Circuit current at standby ICCST 10 15 20 mA VDD Circuit current at standby IDDST 3.5 5.5 7.5 mA GVPS0 -0.7 -0.2 0.3 dB Vin=1Vpp , f=100kHz GVPS6 5.7 6.2 6.7 dB Vin=1Vpp , f=100kHz GAD0 -0.8 -0.3 0.2 dB Vin=1Vpp , f=100kHz GAD2 1.4 1.9 2.4 dB Vin=800mVpp , f=100kHz GL1AUX6 5.5 6.0 6.5 dB Vin=1Vpp , f=100kHz GL1AUX8 7.7 8.2 8.7 dB Vin=800mVpp , f=100kHz GAUX6-1 5.7 6.2 6.7 dB Vin=450mVpp , f=100kHz GAUX6-2 5.5 6.0 6.5 dB Vin=450mVpp , f=100kHz GAUX8 7.7 8.2 8.7 dB Vin=360mVpp , f=100kHz GL16-1 5.5 6.0 6.5 dB Vin=450mVpp , f=100kHz GL18-1 7.7 8.2 8.7 dB Vin=360mVpp , f=100kHz GL16-2 5.5 6.0 6.5 dB Vin=450mVpp , f=100kHz GL18-2 7.7 8.2 8.7 dB Vin=360mVpp , f=100kHz GL16-3 5.7 6.2 6.7 dB Vin=700mV , f=100kHz GRGB0-1 -0.6 -0.1 0.4 dB Vin=560mV , f=100kHz GRGB0-2 -0.8 -0.3 0.2 dB Vin=560mV , f=100kHz ǍG -0.5 0.0 0.5 dB Vin=1.0Vpp,f=100kHz VAD0 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz VAD2 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz VCV-L6 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz VCV-L8 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz VCV-A6 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz CVBS/Y OUT to AUX Maximum output level 8dB VCV-A8 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz C OUT to AUX Maximum output level 6dB VC-A6 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz C OUT to AUX Maximum output level 8dB VC-A8 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz Load 75ȍ Resistor 㧨SW part㧪 L1,AUX CVBS/Y ψ For VPS,PDC 0dB Voltage gain L1,AUX CVBS/Y ψ For VPS,PDC 6dB Voltage gain ENC CVBS,ENC Y ψ to INPUT AD 0dB Voltage gain ENC CVBS,ENC Y ψ to INPUT AD 2dB Voltage gain ENC CVBS,ENC Y ψ to L1&AUX 6dB Voltage gain ENC CVBS,ENC Y ψ to L1&AUX 8dB Voltage gain L1 C ψto AUX 6dB Voltage gain ENC C ψto AUX 6dB Voltage gain ENC C ψto AUX 8dB Voltage gain ENC C ψto L1 6dB Voltage gain ENC C ψto L1 8dB Voltage gain ENC R,G,B ψto L1 6dB Voltage gain ENC R,G,B ψto L1 8dB Voltage gain AUX R,G,B ψto L1 Voltage gain AUX R,G,B ψto R,G,B Voltage gain (LPF OFF) AUX R,G,B ψto R,G,B Voltage gain (LPF ON) Difference voltage gain Between the channel CVBS/Y OUT to INPUT AD Maximum output level 0dB CVBS/Y OUT to INPUT AD Maximum output level 2dB CVBS/Y OUT to L1 Maximum output level 6dB CVBS/Y OUT to L1 Maximum output level 8dB CVBS/Y OUT to AUX Maximum output level 6dB 2/16 Item Limit Unit Conditions 㧙 Vp-p Vin: THD=1.0% f=100kHz 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz VG-L8 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz VB-L6 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz VB-L8 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz R Maximum output level VR 2.8 3.2 㧙 Vp-p Vin: THD=1.0% f=100kHz G Maximum output level VG 2.8 3.2 㧙 V Vin: THD=1.0% f=100kHz B Maximum output level VB 2.8 3.2 㧙 V Vin: THD=1.0% f=100kHz VVPS0 2.8 3.2 㧙 V Vin: THD=1.0% f=100kHz VVPS6 2.8 3.2 㧙 V Vin: THD=1.0% f=100kHz FAD0 -1.0 0 1.0 dB Vin=1Vpp , f=100k/7MHz FAD2 -1.0 0 1.0 dB Vin=800mVpp , f=100k/7MHz FCV-L6 -1.0 0 1.0 dB Vin=1Vpp , f=100k/7MHz FCV-L8 -1.0 0 1.0 dB Vin=800mVpp , f=100k/7MHz FCV-AU6 -1.0 0 1.0 dB Vin=1Vpp , f=100k/7MHz FCV-AU8 -1.0 0 1.0 dB Vin=800mVpp , f=100k/7MHz FC-A6 -1.0 0 1.0 dB Vin=450mVpp , f=100k/7MHz FC-A8 -1.0 0 1.0 dB Vin=360mVpp , f=100k/7MHz FRC-L6 -1.0 0 1.0 dB Vin=700mVpp , f=100k/7MHz FRC-L8 -1.0 0 1.0 dB Vin=560mVpp , f=100k/7MHz FG-L6 -1.0 0 1.0 dB Vin=700mVpp , f=100k/7MHz FG-L8 -1.0 0 1.0 dB Vin=560mVpp , f=100k/7MHz FB-L6 -1.0 0 1.0 dB Vin=700mVpp , f=100k/7MHz FB-L8 -1.0 0 1.0 dB Vin=560mVpp , f=100k/7MHz R Frequency characteristic FR -1.0 0 1.0 dB Vin=700mVpp , f=100k/7MHz G Frequency characteristic FG -1.0 0 1.0 dB Vin=700mVpp , f=100k/7MHz B Frequency characteristic FB -1.0 0 1.0 dB Vin=700mVpp , f=100k/7MHz FCV-LPF1 -1.5 -0.5 0.5 dB Vin=1.0Vpp , f=100k/6.75MHz FCV-LPF2 㧙 -38 -27 dB Vin=1.0Vpp , f=100kHz/27MHz FCR-LPF1 -1.5 -0.5 0.5 dB Vin=1.0Vpp , f=100k/6.75MHz FCR-LPF2 㧙 -38 -27 dB Vin=1.0Vpp , f=100kHz/27MHz R/C OUT to L1 Maximum output level R/C OUT to L1 Maximum output level G OUT to L1 Maximum output level G OUT to L1 Maximum output level B OUT to L1 Maximum output level B OUT to L1 Maximum output level Symbol 6dB 8dB 6dB 8dB 6dB 8dB For VPS, PDC Maximum output level 0dB For VPS, PDC Maximum output level 6dB CVBS/Y OUT to INPUT AD Frequency characteristic 0dB CVBS/Y OUT to INPUT AD Frequency characteristic 2dB CVBS/Y OUT to L1 Frequency characteristic 6dB CVBS/Y OUT to L1 Frequency characteristic 8dB CVBS/Y OUT to AUX Frequency characteristic 6dB CVBS/Y OUT to AUX Frequency characteristic 8dB C OUT to AUX Frequency characteristic 6dB C OUT to AUX Frequency characteristic 8dB R/C OUT to L1 Frequency characteristic 6dB R/C OUT to L1 Frequency characteristic 8dB G OUT to L1 Frequency characteristic 6dB G OUT to L1 Frequency characteristic 8dB B OUT to L1 Frequency characteristic 6dB B OUT to L1 Frequency characteristic 8dB CVBS/Y OUT LPF ON Frequency characteristic CVBS/Y OUT LPF ON Frequency characteristic C-R/C-G-B OUT LPF ON Frequency characteristic C-R/C-G-B OUT LPF ON Frequency characteristic 1 2 1 2 MIN. TYP. MAX. VRC-L6 2.8 3.2 VRC-L8 2.8 VG-L6 3/16 Item Symbol Limit Unit Conditions MIN. TYP. MAX. FRGB1 -3 0 1 dB FRGB2 㧙 -15 -1.5 dB MAD 㧙 -60 -55 dB Vin=1.0Vpp , f=4.43MHz ML1 㧙 -60 -55 dB Vin=1.0Vpp , f=4.43MHz MAUX 㧙 -60 -55 dB Vin=1.0Vpp , f=4.43MHz MC 㧙 -60 -55 dB Vin=1.0Vpp , f=4.43MHz MRC 㧙 -60 -55 dB Vin=1.0Vpp , f=4.43MHz MG 㧙 -60 -55 dB Vin=1.0Vpp , f=4.43MHz MB 㧙 -60 -55 dB Vin=1.0Vpp , f=4.43MHz SW1 Switch crosstalk CSW1 㧙 -60 -55 dB SW2 Switch crosstalk CSW2 㧙 -60 -55 dB SW3 Switch crosstalk CSW3 㧙 -60 -55 dB SW4 Switch crosstalk CSW4 㧙 -60 -55 dB SW5 Switch crosstalk CSW5 㧙 -60 -55 dB SW7 Switch crosstalk CSW7 㧙 -60 -55 dB SW8 Switch crosstalk CSW8 㧙 -60 -55 dB SW10 Switch crosstalk CSW10 㧙 -60 -55 dB CCVBS 㧙 -60 -55 dB CCR/CGB 㧙 -60 -55 dB CRGB 㧙 -60 -55 dB BIAS input impedance RBIAS 14 20 26 kȍ BIAS input impedance AUX R/C terminal RRC 100 150 200 kȍ VFB 0.4 0.7 0.9 V L1 FB OUT Output voltage H VFB-HI 3.6 4 4.4 V RL=150ȍ L1 FB OUT Output voltage L VFB-L0 0 㧙 0.7 V RL=150ȍ FSW Output voltage H VFSW-HI VCC -0.5 VCC -0.1 VCC V No load FSW Output voltage L VFSW-LOW 0 㧙 0.7 V No load Input voltage H VADR-HI 2.0 㧙 VCC V Input voltage L VADR-LOW 0 㧙 1.0 V RADR 65 100 135 kȍ R-G-B LPF ON Frequency characteristic 1 R-G-B LPF ON Frequency characteristic 2 CVBS/Y OUT to INPUT AD MUTE attenuation CVBS/Y OUT to L1 MUTE attenuation CVBS/Y OUT to AUX MUTE attenuation C OUT to AUX MUTE attenuation R/C OUT to L1 MUTE attenuation G OUT to L1 MUTE attenuation B OUT to L1 MUTE attenuation CVBS/Y OUT Between the channel crosstalk C-R/C-G-B OUT Between the channel crosstalk R-G-B Between the channel crosstalk Vin=700mVpp , f=100kHz/6MHz Vin=700mVpp , (f=100kHz/14.3MHz) Vin=1.0Vpp , f=4.43MHz AMP0dB Vin=1.0Vpp , f=4.43MHz AMP6dB Vin=1.0Vpp , f=4.43MHz AMP6dB Vin=1.0Vpp , f=4.43MHz AMP6dB Vin=1.0Vpp , f=4.43MHz AMP6dB Vin=1.0Vpp , f=4.43MHz AMP6dB Vin=1.0Vpp , f=4.43MHz AMP6dB Vin=1.0Vpp , f=4.43MHz AMP6dB Vin=1.0Vpp , f=4.43MHz AMP0,6dB Vin=1.0Vpp , f=4.43MHz AMP6dB Vin=1.0Vpp , f=4.43MHz 㧨Scart connector part㧪 FB threshold 㧨ADR㧪 Input impedance 4/16 Pull down resister Item Symbol Limit MIN. TYP. MAX. Unit Conditions 㧨SCL, SDA㧪 Input voltage H VΤC-HI 2.0 㧙 VCC V Input voltage L VΤC-LOW 0 㧙 1.0 V Input bias current VΤC-BIAS 0 -1 -10 μA INT Output voltage H VINT-HI Vcc -0.5 Vcc-0.1 Vcc V Pull up 100kԈ INT Output voltage L VINT-LOW 0 0.3 0.5 V Iload=1mA ALL MUTE threshold VMUTE 1.0 1.5 2.0 V FS1, FS2 Input threshold H VFS-H 2.5 2.75 3 V FS1, FS2 Input threshold L VFS-L 0.83 1.08 1.33 V PARALLEL 1~4 Output voltage H VOPH Vcc -0.5 Vcc -0.1 Vcc V Pull up 100kԈ PARALLEL 1~4 Output voltage L VOPL 0 0.3 0.5 V Iload=1mA ASW1~4 Output voltage H VOSH 3.5 VCC0.1 VCC V No load ASW1~4 Output voltage L VOSL 0 0.1 1.0 V No load FSL1, FSAUX Output voltage H VOFSH 4.0 0.95 ×Vcc VCC V RL=200kԈ FSL1, FSAUX Output voltage M VOFSM 2.0 2.5 3.0 V RL=200kԈ FSL1, FSAUX Output voltage L VOFSL 0 0.1 0.75 V RL=200kԈ DGVPS0 - 0.1 - % 75Ԉterminating. 1Vpp output DGVPS6 - 0.1 - % 75Ԉterminating. 1Vpp output DGAD0 - 0.1 - % 75Ԉterminating. 1Vpp output DGAD2 - 0.1 - % 75Ԉterminating. 1Vpp output DGL1AU6 - 0.5 - % 75Ԉterminating. 1Vpp output DGL1AU8 - 0.5 - % 75Ԉterminating. 1Vpp output DGLCAUX - 1.0 - % 75Ԉterminating. 1Vpp output DGC-A6 - 1.0 - % 75Ԉterminating. 1Vpp output DGC-A8 - 1.0 - % 75Ԉterminating. 1Vpp output DGC-L6 - 1.0 - % 75Ԉterminating. 1Vpp output DGC-L8 - 1.0 - % 75Ԉterminating. 1Vpp output DGRGBL6 - 0.8 - % 75Ԉterminating. 1Vpp output DGRGBL8 - 0.8 - % 75Ԉterminating. 1Vpp output DGAUX-L - 0.2 - % 75Ԉterminating. 1Vpp output The span that input is possible. 0㨪VCC Maximum input voltage VCC (VCCr5%) Minimum input voltage 0V (VCCr5%) 㧨Guaranteed design parameters㧪 㧨SW part㧪 L1,AUX CVBS/Y ψ For VPS,PDC 0dB Differential Gain L1,AUX CVBS/Y ψ For VPS,PDC 6dB Differential Gain ENC CVBS,ENC Y ψ to INPUT AD 0dB Differential Gain ENC CVBS,ENC Y ψ to INPUT AD 2dB Differential Gain ENC CVBS,ENC Y ψ to L1&AUX 6dB Differential Gain ENC CVBS,ENC Y ψ to L1&AUX 8dB Differential Gain L1Cψto AUX 6dB Differential Gain ENC Cψto AUX 6dB Differential Gain ENC C ψto AUX 8dB Differential Gain ENC C ψto L1 6dB Differential Gain ENC C ψto L1 8dB Differential Gain ENC R,G,B ψto L1 6dB Differential Gain ENC R,G,B ψto L1 8dB Differential Gain AUX R,G,B ψto L1 Differential Gain 5/16 Item AUX R,G,B ψ R,G,B Differential Gain L1,AUX CVBS/Y ψFor VPS,PDC 0dB Differential Phase L1,AUX CVBS/Y ψFor VPS,PDC 6dB Differential Phase ENC CVBS,ENC Y ψto INPUT AD 6dB Differential Phase ENC CVBS,ENC Y ψto INPUT AD 8dB Differential Phase ENC CVBS,ENC Y ψto L1&AUX 6dB Differential Phase ENC CVBS,ENC Y ψto L1&AUX 8dB Differential Phase L1 C ψto AUX 6dB Differential Phase ENC C to AUX 6dB Differential Phase ENC C ψto AUX 8dB Differential Phase ENC C ψto L1 6dB Differential Phase ENC C ψto L1 8dB Differential Phase ENC R,G,B ψto L1 6dB Differential Phase ENC R,G,B ψto L1 8dB Differential Phase AUX R,G,B ψto L1 Differential Phase AUX R,G,B ψto R,G,B Differential Phase L1,AUX CVBS/Y ψ For VPS,PDC 0dB S/N ratio L1,AUX CVBS/Y ψ For VPS,PDC 6dB S/N ratio ENC CVBS,ENC Y ψ to INPUT AD 0dB S/N ratio ENC CVBS,ENC Y ψ to INPUT AD 2dB S/N ratio ENC CVBS,ENC Y ψ to L1&AUX 6dB S/N ratio ENC CVBS,ENC Y ψ to L1&AUX 8dB S/N ratio L1 C ψto AUX 6dB S/N ratio Symbol Limit Unit Conditions - % 75Ԉterminating. 1Vpp output 0.2 - deg 75Ԉterminating. 1Vpp output - 0.2 - deg 75Ԉterminating. 1Vpp output DPAD6 - 0.2 - deg 75Ԉterminating. 1Vpp output DPAD8 - 0.2 - deg 75Ԉterminating. 1Vpp output DPL1AU6 - 0.2 - deg 75Ԉterminating. 1Vpp output DPL1AU8 - 0.2 - deg 75Ԉterminating. 1Vpp output DPLCAU6 - 0.2 - deg 75Ԉterminating. 1Vpp output DPC-A6 - 0.4 - deg 75Ԉterminating. 1Vpp output DPC-A8 - 0.4 - deg 75Ԉterminating. 1Vpp output DPC-L6 - 0.4 - deg 75Ԉterminating. 1Vpp output DPC-L8 - 0.4 - deg 75Ԉterminating. 1Vpp output DPRGBL6 - 0.2 - deg 75Ԉterminating. 1Vpp output DPRGBL8 - 0.2 - deg 75Ԉterminating. 1Vpp output DPAUX-L - 0.2 - deg 75Ԉterminating. 1Vpp output DPAURB - 0.2 - deg 75Ԉterminating. 1Vpp output SNVPS0 - -70 - dB Standard 100% white signal SNVPS6 - -70 - dB Standard 100% white signal SNAD0 - -70 - dB Standard 100% white signal SNAD2 - -70 - dB Standard 100% white signal SNL1AU6 - -70 - dB Standard 100% white signal SNL1AU8 - -70 - dB Standard 100% white signal SNLCAU6 - -70 - dB Standard 100% white signal MIN. TYP. MAX. DGAURB - 0.2 DPVPS0 - DPVPS6 ENC C ψto AUX 6dB S/N ratio SNC-A6 - -70 - dB Standard 100% white signal ENC C ψto AUX 8dB S/N ratio SNC-A8 - -70 - dB Standard 100% white signal ENC C ψto L1 6dB S/N ratio SNC-L6 - -70 - dB Standard 100% white signal ENC C ψto L1 8dB S/N ratio SNC-L8 - -70 - dB Standard 100% white signal ENC R,G,B ψto L16dB S/N ratio SNRGBL6 - -70 - dB Standard 100% white signal ENC R,G,B ψto L18dB S/N ratio SNRGBL8 - -70 - dB Standard 100% white signal AUX R,G,B ψto L1 S/N ratio SNAUX-L - -70 - dB Standard 100% white signal AUX R,G,B ψto R,G,B S/N ratio SNAURB - -70 - dB Standard 100% white signal 6/16 ٨Block diagram Ǵ Ǵ Ǵ . %8$5; #7: %8$5; 67 %8$5; B CLAMP B CLAMP SW10 HQT 8252&% L1 CVBS/Y AUX CVBS/Y TU CVBS/Y ENC CVBS ENC Y B CLAMP 1 2 3 G% 1 2 3 4 5 SW1 %8$5; 176 VQ +0276 #& %8$5; 176 VQ . %8$5; 176 VQ #7: % 176 VQ #7: 4% 176 VQ . ) 176 VQ . $ 176 VQ . G% MUTE AUX CVBS/Y 1 ENC CVBS 2 ENC Y 3 SW2 G% Ǵ Ǵ '0% %8$5 '0% ; B CLAMP LPF B CLAMP LPF L1 CVBS/Y TU CVBS/Y ENC CVBS ENC Y 1 2 3 4 MUTE SW3 G% MUTE Ǵ Ǵ . % '0% % BIAS BIAS 1 2 LPF SW4 G% MUTE Ǵ Ǵ Ǵ Ǵ Ǵ Ǵ '0% 4 #7: 4% '0% ) #7: ) '0% $ #7: $ SW5 1 B CLAMP LPF 2 B CLAMP/BIAS B CLAMP LPF 1 SW6 2 MUTE 1 SW7 2 B CLAMP B CLAMP LPF B CLAMP MUTE 1 SW8 2 MUTE G% G% G% SW11 M M 4 ) $ (59 ($ +06 #.. /76' (5 (5 G% LPF G% LPF G% LPF 1 4V 2 0V 3 %8) 2 #59 #59 #59 #59 (5#7: ୯ REF (5. ୯ 2#4#..'. I C BUS 2#4#..'. #&4 7(67 INT 2#4#..'. 5%. 8%% 8&& )0& )0& &)0& . ($ 176 6'56 84'( SW9 FS IN MONI 2#4#..'. 5&# %8) M M 8%% Fig.1 Blocks inside the dotted line operate at a standby mode. 7/16 Ǵ ٨Equivalent circuit Pin No. Pin name (Input/Output) 1. 19. 39. DGND GND2 GND1 2. 6. 8. 10. 12. 24. 38. 42. 44. 48. ENCY ENCR ENCG ENCB TV CVBS/Y L1 CVBS/Y AUX CVBS/Y AUX G AUX B L1 C 4. 26. ENC C L1 C 40. AUX R/C 14. CVBS/Y OUT to INPUT AD for VPS PDC R G B Function Equivalent circuit No used INPUT range (V) Terminal voltage (V) GND terminal 㧙 0 Signal input terminal 1.4 The video signal input pins is a bottom clamp. Signal input terminal 2.9 The video signal input pins is a resistance bias. Signal input terminal 16. 18. 20. 22. 28. 29. 30. 32. 34. B OUT to L1 G OUT to L1 R/C OUT to L1 CVBS/Y OUT to AUX C OUT to AUX 1.4 AUX R input can be a bottom clamp or resistance bias. S-Video signal input distinction terminal 㧙 0.7 The state of each pin can be 2 read by I C-BUS. Signal output terminal 0.7 75ǡ driver output pin gain can be selected 6/8dB by 2 I C-BUS. 㧙 2.1 Signal output terminal 50. L1 FB OUT 52. FSW 51. FB This pin is an output terminal for scart connector. The drive of 75ǡis possible. 㧙 㧙 㧙 㧙 Signal output terminal The input from FB is outputted as is. Signal input terminal 㧙 The signal from scart connector input. Reference voltage terminal 9. VREF 2.8 A capacitor is connected to opposite GND. 8/16 7. 11. 13. 43. PARALLEL1 PARALLEL2 PARALLEL3 PARALLEL4 15. 17. 21. 23. ASW4 ASW3 ASW2 ASW1 Open collector output terminal 0 2 It can be set up by I C-BUS. LOW BD3825FS control terminal 0 The signal which switches SW of BD3825FS is output. It 2 can be set by I C-BUS. 㧙 HI 5 FS output terminal 3. 5. FS AUX FS L1 37. TEST1 Controls the FS output of BD3825FS. 2 It can be set up by I C-BUS. 㧙 0 TEST control terminal 0 Short to GND. ALL MUTE control terminal 41. ALL MUTE 5 It can set all 75ǡ driver outputs to mute mode. ADR control terminal 5. ADR 27. 31. FS1 FS2 Pin to set slave address which is 90H(91H) or 92H(93H). 0 FS monitor terminal 㧙 It acts as the monitor for the FS change. 2 I C-BUS Clock input terminal 46. SCL The pin is an input clock of 2 I C-BUS. It uses a resistor to pull up. 㧙 2 I C-BUS Data input terminal 47. SDA The pin is data of the 2 I C-BUS. It uses a resistor to pull up. 㧙 INT terminal 45. INT 0 When INT terminal changes FS pin, it outputs HiZ. 9/16 ٨Description of operations 2 عI C-BUS Control input specifications I2C -BUS Format (WRITE MODE) SLAVE S A DATA1 A ADDRESS DATA2 A DATA3 A DATA4 A DATA5 A DATA6 A P S : Start Condition A : Acknowledge P: Stop Condition Slave address DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 0 ADR R/W ADSW CAUVSW L1SW YAUXSW LASW CL/BI CRSW FBSW AMP0/6 AMP6/8 FILTERSW # SEL INT_EN OUTCTL1 OUTCTL2 Standby # # # # PARALLEL1 PARALLEL2 PARALLEL3 PARALLEL4 ASW1 ASW2 ASW3 ASW4 FSL FSA # # # # #㧔Don’t Care㧕When the power is turned on, the condition is as marked *. RSW GBSW Explanation Explanation ADR The slave address configured with the ADR terminal (write mode). 0 : When ADR terminal input is L. Address becomes “90H”. 1 : When ADR terminal input is H. Address becomes “92H”. YAUXSW SW3 input select. A signal to output in “CVBS/Y to AUX”, select. 000 :L1 CVBS/Y * 001 :TU CVBS/Y 010 : ENC CVBS 011 : ENC Y 1XX : MUTE R/W READ/WRITE mode setting 0 : WRITE 1 : READ CAUXSW SW4 input select. A signal to output in “C OUT to AUX”, select. 00 : L1 C * 01 : ENC C 1X : MUTE ADSW SW1 input select. A signal to output in “CVBS/Y to INPUT AD”, select. 000 : L1 CVBS/Y 001 : AUX CVBS/Y * 010 : TU CYBS/Y 011 : ENC CVBS 100 : ENC Y 101 : MUTE 110 : MUTE 111 : MUTE L1SW SW2 input select. A signal to output in “CVBS/Y to L1”, select. 00 : AUX CVBS/Y * 01 : ENC CVBS 10 : ENC Y 11 : MUTE RSW SW6 input select. A signal to output in “R/C OUT to L1”, select. 00 : ENC C or ENC R 01 : AUX R/C * 1X : MUTE GBSW CRSW A signal to input in RSW (SW5), select. 0 : ENC C * 1 : ENC FBSW AMP0/6 PARALLEL 1㨪4 for VPSޔPDC terminal AMP gain configuration. 0 : 0dB * 1 : 6dB The output configuration of the PARALLEL terminal. 0 : Low * 1 : Hi 10/16 CL/BI SEL SW7, SW8 input selects. Signals to output in “G OUT to L1” and “B OUT to L1”, select. 00 : ENC GޔENC B 01 : AUX GޔAUX B * 1X : MUTE The output of L1 FB OUT, select. 0X : FB (Through)* 10 : 0V 11 : 4V The configuration of AUX R/C input mode. 0 : B CLAMP * 1 : BIAS LASW AMP6/8 OUTCTL㧝 INT_EN INT signal output control. 0 : Enable * 1 : Disable Caution: When EnableψDisable change, INT signal is cleared. FILTERSW SW11 input select. Select the R, G and B each output signal are outputted through the filter, or not outputted through the filter. 0: There is no filter. * 1: There is a filter. SW10 input select. A signal to output in “for VPS, PDC”, select. 00 : AUX CVBS/Y * 01 : L1 CVBS/Y 1X : TU CVBS/Y When encoder input is chosen, the gain of AMP is configured. (Encoder input terminal :ENC CVBS, ENC Y, ENC C, ENC R, ENC G, ENC B) 0: 6dB 㧔0dB㧕* 1: 8dB 㧔2dB㧕 Caution : As for “CVBS/Y OUT to INPUT AD”, it is 0/2 dB switchover. “C OUT to AUX” output control. 0 : Normal * 1 : HI Z Standby normal/standby mode configuration. 0 : Normal * 1 : Standby Caution : Block diagram is referred for the actuation block at the time of Standby. ASW 1㨪4 FSL The output configuration of the FSL1. 00 : input mode * 01 : Low 10 : MID 11 : HI Caution : When input mode, the output of BD3825FS becomes HiZ(Low). FSA 2 I C-BUS format (READ MODE) SLAVE S A DATA1 A/N DATA2 ADDRESS A/N DATA3 “B OUT to L1” output control. 0 : Normal * 1 : HI Z The output configuration of the ASW terminal. 0 : Low 1 : Hi (Initial condition) ASW1:H ASW 2:L ASW 3:L ASW 4:H * The output configuration of the FSAUX. 00 : input mode * 01 : Low 10 : MID 11 : HI Caution : When input mode, the output of BD3825FS becomes HiZ(Low). OUTCTL2 A/N DATA4 A/N DATA5 A/N DATA6 A/N P S : Start Condition A/N : NO acknowledge P: Stop Condition Slave address DATA1 DATA2 b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 0 ADR R/W ADSW CAUVSW L1SW YAUXSW LASW CL/BI DATA3 CRSW FBSW AMP0/6 AMP6/8 FILTERSW HI SEL DATA4 INT_EN OUTCTL1 OUTCTL2 Standby HI HI HI HI DATA5 PARALLEL1 PARALLEL2 PARALLEL3 PARALLEL4 ASW1 ASW2 ASW3 ASW4 DATA6 FSL FSA FS1 FS2 #㧔Don’t Care㧕 In the read mode, 00h is output from DATA4 after power-on is reset to 09h. If a write movement occurs once, it is set to normal mode. RSW 11/16 GBSW Explanation Explanation ADR The slave address configured with the ADR terminal. (read mode) 0 : When ADR terminal input is L. Address becomes “91H”. 1 : When ADR terminal input is H. Address becomes “93H”. R/W READ/WRITE mode setting 0 : WRITE 1 : READ FS1 The state of FS1 is outputted. 00 : Low 10 : MID 11 : HI FS2 The state of FS2 is outputted. 00 : Low 10 : MID 11 : HI 䂓 INT signal (45pin) ż An INT signal outputs HI (high impedance) when the state of FS1, FS2 is monitored by I2C-BUS for transition stage, during input mode configuration. Mode Monitor FS1 FS2 Input mode Input mode Both Input mode Others Only FS1 Others Input mode Only FS2 Others Others No monitoring ż INT signal clearance occurs every time the read (read mode) of the data with I2C-BUS when slave address is sent. ż INT signal output control It can be controlled with I2C-BUS. INT signal is cleared at switching by EnableψDisable. 䂓 Standby mode ż Standby mode can be configured by I2C-BUS. Only the section marked in the dotted line, in the Figure 3, Block Diagram, is active during standby state. All others are off. 䂓 ALL MUTE ż CVBS/Y, C, R/C, G, B output (14pinޔ29pinޔ30pinޔ31pinޔ32pinޔ34pinޔ36pin) are all muted. Mute controls each output separately by I2C-BUS. ALL MUTE H L Mode Normal Mute 䂓 The bias of an AUX R/C As for CLAMP/BIAS change of AUX R/C (40pin), the output bias of R/C OUT to L1 (30pin) is synchronized. Setup “CL/BI SEL” by the I2C-BUS control, in accordance with the bias method of the input chosen when input from ENC C (4pin) and ENC R (6pin) is output. 12/16 ٨Reference data 10 CCSTBY[mA] 8 15 6 10 4 2 0 0 0 4.6 4.8 5.0 5.2 5.4 4.4 5.6 4.6 VCC [V] SUPPLY CURRENT : I 6 4 2 0 0 -25 0 25 50 TEMPERATURE [㷄] 75 100 Fig.5 VCC Circuit Current (Temperature dependence) 10 0 PHASE -45 -30 10 5 -50 -25 0 25 50 TEMPERATURE [㷄] 75 100 Fig.7 VCC Circuit Current (Standby) (Temperature dependence) 180 0 GAIN 135 5.25V 45 5.6 15 100 0 90 5.25V 5.0V -10 GAIN [dB] -20 5.4 10 90 PHASE [deg] 5.0V 4.75V 0 25 50 75 TEMPERATURE [㷄] 10 135 5.25V -10 -25 Fig.6 VDD Circuit Current (Temperature dependence) 180 GAIN 5.0 5.2 VCC [V] 0 -50 -10 4.75V GAIN [dB] -50 4.8 Fig.4 VCC Circuit Current (Standby) (Supply voltage dependence) CCSTBY[mA] [mA] 50 4.6 20 8 SUPPLY CURRENT : I 100 0 4.4 5.6 DD [mA] CC 5.4 10 150 SUPPLY CURRENT : I 5.0 5.2 VDD [V] Fig.3 VDD Circuit Current (Supply voltage dependence) Fig.2 VCC Circuit Current (Supply voltage dependence) GAIN [dB] 4.8 -20 5.0V 45 4.75V 0 -20 PHASE -30 -30 -40 -40 -45 -90 -90 -135 -50 -180 10E+04 1E+06 10E+06 FREQUENCY [Hz] 10E+04 180 135 GAIN GAIN [dB] -50C 45 PHASE -45 -30 1E+06 10E+06 FREQUENCY [Hz] 10 10 0 180 GAIN 100C 100C 25C -10 135 -10 -50C -20 25C -50C -20 -135 -50 10E+04 -180 1E+06 10E+06 FREQUENCY [Hz] 1E+08 Fig.11 Frequency Characteristics CVBS/Y OUT to L1 90 45 0 PHASE -30 -30 -40 -40 -45 -90 -40 1E+08 Fig.10 Frequency Characteristics G 90 0 -20 -180 10E+04 1E+08 Fig.9 Frequency Characteristics CVBS/Y OUT to L1 (with LPF) GAIN [dB] 25C -10 10E+06 0 100C PHASE [deg] 0 1E+06 FREQUENCY [Hz] Fig.8 Frequency Characteristics CVBS/Y OUT to L1 10 -135 -50 -50 1E+08 GAIN [dB] -40 PHASE [deg] 4.4 5 PHASE [deg] 50 20 SUPPLY CURRENT : I DD[mA] 100 SUPPLY CURRENT : I SUPPLY CURRENT : I CC[mA] 150 -90 -50 100E+03 01E+06 010E+06 FREQUENCY [Hz] 100E+06 Fig12 Frequency Characteristics CVBS/Y OUT to L1 (with LPF) 13/16 -135 -50 10E+04 -180 1E+06 10E+06 FREQUENCY [Hz] 1E+08 Fig.13 Frequency Characteristics G 10 10 0 5.25V 0 0 5.0V 25C 4.75V -20 -30 -30 -40 -40 -50 1E+06 10E+06 FREQUENCY [Hz] 1E+08 1E+06 10E+06 FREQUENCY [Hz] -50 1E+08 6dB 3 8dB 2 1 -50 -25 0 25 50 TEMPERATURE [㷄] 75 4 LPF OFF LPF ON 2 -50 -25 0 25 50 TEMPERATURE [㷄] 75 4.4 -50 -25 0 25 50 TEMPERATURE [㷄] 75 0.8 0.6 G 0.4 CVBS/Y OUT to L1 0.2 4.6 4.8 5.0 5.2 VCC [V] 5.4 G 0.2 CVBS/Y OUT to L1 -25 0 25 50 75 100 200 150 30 20 100 50 10 -80 G Fig.22 Differential Phase (Temperature dependence) IMPEDANCE [kȍ] IMPEDANCE [kȍ] -60 0.4 TEMPERATURE [㷄] 40 -40 5.6 0.6 -50 5.6 50 -20 5.4 0.8 Fig.21 Differential Phase (Supply voltage dependence) Fig.20 Differential Gain (Temperature dependence) 0 5.0 5.2 VCC [V] 0.0 4.4 100 4.8 1.0 0.0 0.0 4.6 Fig.19 Differential Gain (Supply voltage dependence) DIFFERENTIAL PHASE : DP [deg.] G G Fig.18 Maximum Output Level G DIFFERENTIAL PHASE : DP [deg.] 1.0 CVBS/Y OUT to L1 0.0 100 1.0 CVBS/Y OUT to L1 100 1.0 1 Fig.17 Maximum Output Level CVBS/Y OUT to L1 2.0 75 2.0 3 100 3.0 50 3.0 0 0 25 G DIFFERENTIAL GAIN : DG [%] MAXIMUM OUTPUT VOLTAGE :Vomax [Vpp] 4 0 Fig.16 MUTE Attenuation (Temperature dependence) 5 CVBS/Y OUT to L1 -25 TEMPERATURE [㷄] Fig.15 Frequency Characteristics G (with LPF) 5 MAXIMUM OUTPUT VOLTAGE :Vomax [Vpp] -100 10E+04 Fig.14 Frequency Characteristics G (with LPF) -60 -80 -50 10E+04 -40 GAIN [dB] GAIN [dB] GAIN [dB] -10 -20 DIFFERENTIAL GAIN : DG [%] -20 -50C -10 S/N [dB] CVBS/Y OUT to L1 100C CVBS/Y OUT to L1 0 -100 0 -50 -50 -25 0 25 50 TEMPERATURE [㷄] 75 100 Fig.23 S/N ratio (Temperature dependence) -25 0 25 50 TEMPERATURE [㷄] 75 100 Fig.24 BIAS input impedance (Temperature dependence) 14/16 -50 -25 0 25 50 TEMPERATURE [㷄] 75 100 Fig.25 AUX R BIAS input impedance (Temperature dependence) ٨Cautions on use 1. 2. Numbers and data in entries are representative design values and are not guaranteed values of the items. Although ROHM is confident that the example application circuit reflects the best possible recommendations, be sure to verify circuit characteristics for your particular application. Modification of constants for other externally connected circuits may cause variations in both static and transient characteristics for external components as well as this Rohm IC. Allow for sufficient margins when determining circuit constants. 3. Absolute maximum ratings Use of the IC in excess of absolute maximum ratings, such as the applied voltage or operating temperature range (Topr), may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure, such as a fuse, should be implemented when using the IC at times where the absolute maximum ratings may be exceeded. 4. GND potential Ensure a minimum GND pin potential in all operating conditions. Make sure that no pins are at a voltage below the GND at any time, regardless of whether it is a transient signal or not. 5. Thermal design Perform thermal design, in which there are adequate margins, by taking into account the permissible dissipation (Pd) in actual states of use. 6. Short circuit between terminals and erroneous mounting Pay attention to the assembly direction of the ICs. Wrong mounting direction or shorts between terminals, GND, or other components on the circuits, can damage the IC. 7. Operation in strong electromagnetic field Using the ICs in a strong electromagnetic field can cause operation malfunction. 8. Operating Voltage Range and Operating Temperature Range The circuit functional operations and electrical characteristics are guaranteed within the Operating Voltage Range and Operating Temperature Range. However, careful consideration must be taken in designing the circuit. 9. Supply voltage of operation Although basic circuit function is guaranteed under normal voltage operation (4.75V㨪5.25V), ensure each parameter complies with appropriate electrical characteristics, when using this device. 10. The first resistor of 75ǡ driver output must be layout nearest to the IC. 11. The coupling capacitor must be layout nearest to the IC and each pin. 2 12. I C BUS is compatible with fast mode of Version 2.0 but not compatible with Hs mode. ٨Thermal derating characteristics 㪧㪦㪮㪜㪩㩷㪛㪠㪪㪪㪠㪧㪘㪫㪠㪦㪥㩷㪑㩷㪧㪻㪲㫄㪮㪴 㪈㪋㪇㪇 㪈㪉㪇㪇 㪈㪇㪇㪇 㪏㪇㪇 㪍㪇㪇 㪋㪇㪇 㪉㪇㪇 㪇 㪄㪌㪇 㪄㪉㪌 㪇 㪉㪌 㪌㪇 㪎㪌 㪘㪤㪙㪠㪜㪥㪫㩷㪫㪜㪤㪧㪜㪩㪘㪫㪬㪩㪜㩷㪲㷄㪴 Fig.26 15/16 㪈㪇㪇 㪈㪉㪌 㪈㪌㪇 ٨Selection of order type B H 7 6 2 4 K S 2 TYPE BH7624KS2 SQFP-T52 <Dimension>! <Packing information>! 12.0 ± 0.3 10.0 ± 0.2 52 14 13 0.125 ± 0.1 1pin 0.1 ± 0.1 1.4 ± 0.1 1 1000pcs Direction of product is fixed in a tray. Direction of feed 27 26 40 Tray(with dry pack) Quantity 0.5 12.0 ± 0.3 10.0 ± 0.2 39 Container 0.65 0.3 ± 0.1 0.15 㧔Unit:mm) ̪Orders are available in complete units only. The contents described herein are correct as of October, 2005 The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD. Any part of this application note must not be duplicated or copied without our permission. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. The products described herein utilize silicon as the main material. The products described herein are not designed to be X ray proof. Published by Application Engineering Group Catalog NO.05T395Be '05.10 ROHM C 2000 TSU Appendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design. The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright © 2008 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev2.0