QCP-10G3A4EDR QSFP+ 40GBASE-SR4 Fiber Transceiver Preliminary Features RoHS-6 compliant High speed / high density: support up to 4X10 Gb/s bi-directional operation Compliant to industrial standard SFF-8436 QSFP+ standard Low power consumption : less than 1.5W Distance up to 100 meters by OM3 fiber and 150M by OM4 fiber Possible Interoperability with 10GBASE-SR SFP+ by break out cable Reliable VCSEL and PIN photonic devices I2C standard management interface Excellent high speed signal integrity Description Application The QCP-10G3A4EDR is a 40Gbps, hot pluggable fiber transceivers for Infiniband QDR and 40G Ethernet data transmission. It provides full duplex, parallel interconnects: 4 transmitting / 4 receiving data lanes and each lane at data rate up to 10.3125Gbps. 40G Ethernet (40GBASE-SR4) Proprietary high speed, high density data transmission. Switch and router high speed backplane interconnect High performance computing, server and data storage. Distance support could be up to 100 meters using OM3 fiber and 150 meters using OM4 fiber. Each lane could also be configured as independent 10G Ethernet transmission. Therefore facilitate higher port density at 10G Ethernet. QCP-10G3A4EDR is designed to meet the requirements of high speed, high density and low power consumption for applications in today’s data centers. 1 DELTA ELECTRONICS, INC. Revision: S0 4/8/2013 www.deltaww.com QCP-10G3A4EDR 1. Absolute Maximum Ratings Parameter Symbol Min Storage Temperature Storage Ambient Humidity TS HA VCC3 +3.3V Power Supply Typ Max Units -40 0 85 85 °C % 0 3.6 V Notes 2. General Operating Characteristics (V CC3=3.135V~3.465V, TC= 0 ºC to 70 ºC, Per End) Parameter Symbol Min Typ Max Units Notes Operating Case Temperature Ambient Humidity +3.3V Supply Voltage TC 0 70 °C [1] HA VCC3 5 3.135 85 3.465 % V [2] +3.3V Supply Current Total Power Dissipation Bit rate IVCC3 PD B 400 1.5 mA W Gb/s Module Turn-on Time Input Control Voltage- High Input Control Voltage - Low Digital Output Voltage- High ViH ViL VoH 2.0 -0.3 2.0 VoL 0 Digital Output Voltage- Low Clock Rate-I2C 10.3125 2000 Vcc+0.3 0.8 Vcc+0.3 0.8 400 ms V V [3] [4] [5] [5] [6] [6] [7] kHz Notes: 1. See ordering information. The position for measuring case temperature is shown as following 2. Non-condensing 31 -12 3. Tested with PRBS 2 -1, BER 1X10 4. Time from module power-on / insertion/ ResetL deassert to module full functional. 5. For all control input pins: LPMode, Reset and ModSelL 6. For all status output pins: ModPrsL , IntL 7. For management interface. Case temperature measuring point 2 DELTA ELECTRONICS, INC. Revision: S0 4/8/2013 www.deltaww.com QCP-10G3A4EDR 3. High Speed Characteristics- Transmitter (V CC3 = 3.135V ~ 3.465V, TC= 0 ºC to 70 ºC ) Parameter Reference Differential Input Impedance Central Wavelength Symbol Min Typ Zd λ Spectral Width σ Differential Data Input Swing Vin_pp Differential Data Input Threshold Average Launch Power Po OMA OMA difference Transmitter Dispersion Penalty TDP Extinction Ratio Optical Return Loss Tolerance ER ORL Encircled Flux Eye Mask Units Notes Ω 100 840 860 nm 180 0.65 600 2.4 nm mV mV dBm [1] Each lane [2] 4 -30 dBm dBm Each lane 0 dBm Each lane [2] 4 3.5 dB dB Any 2 lanes Each lane 50 -7.6 Peak Average Launch Power Average Launch Power at OFF Optical Modulation Amplitude Max -5.6 3 12 ≧86% in 38um diameter ≦30% in 9um diameter Meet IEEE802.3BA Tab 86-6 dB dB [3] Notes: 1. Input swing to trigger TX-squelch. 2. Further narrow down so that interoperability with 10GBASE-SR is possible 3. Hit ratio: 1X10 -5 3 DELTA ELECTRONICS, INC. Revision: S0 4/8/2013 www.deltaww.com QCP-10G3A4EDR 4. High Speed Characteristics- Receiver (V CC3 = 3.135V ~ 3.465V, TC= 0 ºC to 70 ºC) Parameter Reference Differential Input Impedance Differential Output Swing Differential Output Swing When Squelched Rise / Fall Time (20% ~80%) Central Wavelength Receiver Sensitivity (OMA) Receiver Overload (OMA) Damage Threshold LOS Assert LOS Deassert LOS Hysteresis Symbol Min Typ Zd 24 840 Notes 800 mV 50 mV 860 -5.6 ps nm dBm dBm Each lane [2] Each lane [2] dBm Each lane [2] 3 DT Units Ω 100 400 λ Max 4 -11 [1] -27 0.5 Notes: 1. Receiver output swing could be changed by I2C interface. 2. Measured with reference optical input with PRBS2^31-1 BER: 10E-12 at ER:4.75 dB 4 DELTA ELECTRONICS, INC. Revision: S0 4/8/2013 www.deltaww.com QCP-10G3A4EDR 5. Pin Description QSFP Module Pad Layout (Top View) Host PCB Layout (Top View) 5 DELTA ELECTRONICS, INC. Revision: S0 4/8/2013 www.deltaww.com QCP-10G3A4EDR Module Electrical Pin Function Definition Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Logic Symbol GND CML-I Tx2n CML-I Tx2p GND CML-I Tx4n CML-I Tx4p GND LVTTL-I ModSelL LVTTL-I ResetL Vcc Rx LVCMOS-I/O SCL LVCMOS-I/O SDA GND CML-O Rx3p CML-O Rx3n GND CML-O Rx1p CML-O Rx1n GND GND CML-O Rx2n CML-O Rx2p GND CML-O Rx4n CML-O Rx4p GND LVTTL-O ModPrsL LVTTL-O IntL Vcc Tx Vcc1 LVTTL-I LPMode GND CML-I Tx3p CML-I Tx3n GND CML-I Tx1p CML-I Tx1n GND Name/Description Ground Transmitter Inverted Data Input Transmitter Non-inverted Data Input Ground Transmitter Inverted Data Input Transmitter Non-inverted Data Input Ground Module Select Module Reset +3.3V Power Supply Receiver 2-Wire Serial Interface Clock 2-Wire Serial Interface Data Ground Receiver Non-Inverted Data Output Receiver Inverted Data Output Ground Receiver Non-Inverted Data Output Receiver Inverted Data Output Ground Ground Receiver Inverted Data Output Receiver Non-Inverted Data Output Ground Receiver Inverted Data Output Receiver Non-Inverted Data Output Ground Module Present Interrupt +3.3V Power Supply Transmitter +3.3V Power Supply Low Power Mode Ground Transmitter Non-inverted Data Input Transmitter Inverted Data Input Ground Transmitter Non-inverted Data Input Transmitter Inverted Data Input Ground Note [1] [1] [1] [2] [2] [1] [1] [1] [1] [1] [1] [2] [2] [1] [1] [1] Notes: 1. Module ground pins GND are isolated from the module case and chassis ground within the module. 2. Shall be pulled up with 4.7K-10Kohms to a voltage between 3.15V and 3.45V on the host board. 6 DELTA ELECTRONICS, INC. Revision: S0 4/8/2013 www.deltaww.com QCP-10G3A4EDR 6. Low Speed Electrical Hardware Pins In addition to 2-wire serial interface, QCP-10G3A4EDR module has the following low speed pins for control and status: ModPrsL, IntL, LPMode, ModSelL, ResetL 6.1 ModPrsL ModPrsL is an output pin. When “low”, indicates the module is present. The ModPrsL is asserted “Low” when inserted and deasserted “High” when the module is physically absent from the host connector. 6.2 IntL IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to the host system. The source of the interrupt could be identified by using the 2-wire serial interface. 6.3 LPMode LPMode is a control pin. When “High”, it could be used to set the module in low power mode (<1.5W). This pin, along with Power_overide bit and Power_set bit in management interface could be used to avoid system power crash. QCP-10G3A4EDR, however consumes less than 1.5W. Therefore this pin takes no effect. 6.4 ModSelL ModSelL is an input signal. When held low by the host, the module responds to two-wire serial communication commands. The ModSelL signal allows multiple QSFP modules to be on a single two-wire interface bus. When the ModSelL signal is “High”, the module will not respond to or acknowledge any two-wire interface communication from the host. The ModSelL signal input pin is biased to a “High” state in the module. In order to avoid conflicts, the host system must not attempt two-wire interface communications within the ModSelL deassert time after any QSFP modules are de-selected. Similarly, the host must wait for the period of the ModSelL assert time before communicating with the newly selected module. The assert and deassert periods of different modules may overlap as long as the above timing requirements are met. 6.5 ResetL The ResetL signal is pulled to Vcc in the QSFP+ module. A logic low level on the ResetL signal for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host will disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with the Data_Not_Ready bit negated. Note that on power-up (including hot insertion) the module will post this completion of reset interrupt without requiring a reset. 7 DELTA ELECTRONICS, INC. Revision: S0 4/8/2013 www.deltaww.com QCP-10G3A4EDR 7. Memory Map of Management Interface Abundant functions have been implemented in QCP-10G3A4EDR for the purpose of monitoring and control. QCP-10G3A4EDR is designed to be compliant to SFF-8436 rev. 3.6 “QSFP+ COPPER AND OPTICAL MODULES”. There are many registers and sophisticated behaviors associated to those functions. This could facilitate the flexible use of the module. 8. Mechanical Specification Parameter Symbol Min Module Retention Module Insertion Module Extraction 90 0 0 Insertion / Removal Cycles 50 Typ Max Units 40 30 N N N Notes cycles 9. Regulatory Compliance Feature Reference Electromagnetic Interference (EMI) FCC Part15 Class B Electrostatic Discharge (ESD) IEC/EN 61000-4-2 MIL-STD-883E EIA-JESD22-A115-A Laser Eye Safety EN 60825 FDA 21CFR 1040.10, 1040.11 Component Recognition IEC/EN 60950-1 UL60950 Version No. Date S0 2013-04-08 Description Initial draft release 8 DELTA ELECTRONICS, INC. Revision: S0 4/8/2013 www.deltaww.com