Active Optical Cable Assembly USER`S MANUAL

QSFP+
Active Optical Cable Assembly
USER’S MANUAL
COVERING:
QSFPO Series
JANUARY 2014
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2
Copyright © 2014 Samtec, Inc.
TABLE OF CONTENTS
INTRODUCTION
Product Features .............................................................................4
Applications .....................................................................................5
FUNCTIONAL DESCRIPTION
Transmitter Block ............................................................................6
Receiver Block .................................................................................7
Management Interface......................................................................7
SPECIFICATIONS
Common Electrical Characteristics...................................................8
High Speed Electrical Characteristics: QSFPO-40G Series.............10
High Speed Electrical Characteristics: QSFPO-56G Series.............12
Optical Characteristics....................................................................14
Interfaces........................................................................................15
Two-Wire Serial Interface...............................................................16
Control, Status and Monitor Interface............................................17
INITIALIZATION PROCEDURE
Memory Map
Introduction - EEPROM Virtual Addressing .........................18
SFF Memory Map.................................................................19
Page 00, Lower Memory .....................................................20
Page 00, Upper Memory......................................................21
Notes to Page 00 Implementation........................................22
Page 02................................................................................22
Page 03................................................................................22
Output Voltage and Pre-emphasis Settings..........................23
INTERFACE
Electrical.........................................................................................24
MECHANICAL CHARACTERISTICS
Connector Dimensions ..................................................................25
TECHNICAL INFORMATION
Regulatory and Compliance ..........................................................26
Ordering Information .....................................................................26
Definitions .....................................................................................27
Reference Documents ...................................................................27
Notice.............................................................................................27
Warning..........................................................................................27
FILE NO. E357212 I.T.E.
3
INTRODUCTION
Product Features
QSFPO Series Active Optical Cables (AOCs) are 4-channel bidirectional
optical assemblies for QSFP+ applications and are designed to meet
the requirements of modern optical based interconnects. Each AOC
offers 4 independent transmit and receive channels carrying 850 nm
signals across standard multi-mode fibers. Two different series are
available providing an aggregate bandwidth of up to 40 Gbps
(QSFPO-40G Series) or 56 Gbps (QSFPO-56G Series).
The electrical interface is a standard QSFP+ 38 contact edge type
connector and is electrically compliant with the SFI+ and PPI interface
supporting InfiniBand™, Ethernet, Fibre Channel and other protocols.
The connector is hot pluggable and provides I2C serial access via an
on-board microcontroller.
Figure 1:
QSFP+ Active Optical Cable Assembly
4
INTRODUCTION
Applications
The QSFP+ AOC comes pre-tested and can be used as a direct
replacement for traditional copper cables but with the added benefit
of a lighter weight and smaller diameter solution for cable lengths
from 1 to 100 m. It can also be used to replace a pair of transceivers
proving equivalent performance at a lower cost.
The QSFPO-40G Series AOC complies with the standard for
InfiniBand™ QDR and Ethernet 40 GbE (40 Gigabit Ethernet)
applications and is listed on the InfiniBand™ Trade Association’s
Approved Integrator’s List for lengths from 1 to 100 m.
The QSFPO-56G Series AOC provides the same capabilities as the
QSFPO-40G Series, but provides a higher data rate and the ability
to reconfigure the output voltage amplitude. It complies with the
InfiniBand™ FDR standard and is listed on the InfiniBand™ Trade
Association’s Approved Integrator’s List for lengths from 1 to 100 m.
5
FUNCTIONAL DESCRIPTION
The QSFP+ AOC has a miniature optical engine embedded into each
end of the cable assembly. The engines interconnect 4 independent
transmit / receive lanes. An on-board microcontroller provides control,
diagnostic and monitoring for the cable functions, as well as the
external I2C serial communication interface.
A functional block diagram of the engine is shown in Figure 2. The
transmitter section consists of a 4-channel VCSEL (Vertical Cavity
Surface Emitting Laser) array, a 4-channel input buffer and laser driver.
The receiver section consists of a 4-channel PIN photodiode array, a
4-channel TIA array, and a 4-channel output buffer.
X4
Laser
Driver
VCSEL
Array
SCL
Electrical
interface
SDA
ModSelL
Microcontroller
LPMode
Optical
interface
ModPrsL
ResetL
X4 TIA
PIN Diode
Array
Figure 2: Transceiver Functional Block Diagram
Transmitter Block
The optical transmit portion of the engine incorporates a 4-channel
VCSEL array, a 4-channel input buffer and laser driver, diagnostic
monitors, control and bias blocks. The transmit input buffer provides
CML compatible differential inputs presenting a nominal differential
input impedance of 100Ω. AC coupling capacitors are located on the
optical engine board and therefore are not required on the host board.
An LVTTL compatible Two-Wire Serial (or I2C) interface is provided for
module control and diagnostics. Status, alarm and fault information
are available via the TWS interface. To reduce the need for polling, a
hardware interrupt signal is provided to inform hosts of an assertion of
an alarm, Loss of Signal (LOS) and Transmitter (Tx) fault.
6
FUNCTIONAL DESCRIPTION
Receiver Block
The optical receiver portion of the engine incorporates a 4-channel
PIN photodiode array, a 4-channel TIA array, a 4-channel output buffer,
diagnostic monitors, control, and bias blocks. The Receiver Output
Buffer provides CML compatible differential outputs for the high
speed electrical interface presenting nominal single-ended output
impedances of 50Ω to AC ground and 100Ω differentially that should
be differentially terminated with 100Ω. Again, AC coupling capacitors
are located on the optical engine and are therefore not required on the
host board.
Management Interface
The internal optical engine provides digital diagnostics and control/
monitor functions, as specified in SFF-8436. A microcontroller, which
can be accessed through the Two-Wire interface, monitors and reports
this information. The functionality of the Two-Wire interface is specified
in the SFF-8436 specification.
The following module and channel digital diagnostic parameters are
provided for monitoring:
• Transceiver Temperature
• Transceiver Supply Voltage
The microcontroller will generate an Interrupt Flag, by asserting the
IntL signal, when an operational fault occurs. The host can identify the
source of the interrupt by reading the appropriate registers through the
Two-Wire interface. The following Interrupt Flags are provided:
• Rx LOS - Provided for each channel, which indicates that the
optical power input into the receiver has dropped below a
minimum allowed value
• Tx Fault - Provided for each channel, which indicates that a
fault condition relating to either the laser or one of the optical
modulators has occurred
• Transceiver Temperature High and Low Alarm, and, High
and Low Warning
• Transceiver Supply Voltage High and Low Alarm, and, High and
Low Warning
7
SPECIFICATIONS
Common Electrical Characteristics
The maximum operating and storage conditions are shown in Table 1.
Any stress beyond these maximum ratings may result in permanent
damage to the device.
Table 1: Absolute Maximum Rating
Specifications
Symbol
Unit
Min
Max
Notes
Storage Temperature Range
Tsto
°C
-40
85
Powered Case Temperature
Tcase
°C
0
70
Heat sink temperature
Operating Humidity
RH
%
5
90
Noncondensing
Supply Voltage Range
VCC1
V
0.5
4.0
Specifications listed in this documentation are only guaranteed
when the QSFP+ AOC is operated under the recommended operating
conditions listed in Table 2.
Table 2: Recommended Operating Conditions
Specifications
8
Symbol
Unit
Min
Max
Notes
Operating Case Temperature
Tcase
°C
0
70
Heat sink temperature
Power Supply Voltage
VCC1
V
3.15
3.45
DC Common Mode Voltage
VCM
V
0
3.6
Per Channel Data Rate (40G series)
Gbps
1
10.5
Per Channel Data Rate (56G series)
Gbps
1
14.1
SPECIFICATIONS
In addition to the recommended operating conditions, the power
supply requirements are shown in Table 3.
Table 3: Power Supply Requirements
Specifications
Symbol
Unit
Min
Max
Power Supply Voltage
VCC1
V
3.15
3.45
Power Supply Current
ICC1
mA
Notes
240 typical
Power Consumption
W
1.0
0.8 W typical
Power Supply Noise
including Ripple
mV
50
1 kHz to frequency of operation
measured at Vcc host
The QSFP+ specification recommends the use of a host board power
supply filter to reduce power supply noise. The recommended power
supply filter is shown in Figure 3.
Figure 3: QSFP+ Filtering Scheme
9
SPECIFICATIONS
High Speed Electrical Characteristics: QSFPO-40G Series
The electrical requirements for input signal into the QSFPO-40G Series
are defined for the transmit side in Table 4. With inputs into the AOC
that meet these requirements, the output parameters shown in Table 5
are guaranteed.
Table 4: QSFPO-40G Series Electrical Input Requirements
Specifications
Symbol
Data Rate per Channel
VDI
Differential Input Amplitude
Single-ended Voltage Tolerance
AC Common Mode Voltage
Unit
Min
Max
Gbps
1
10.5
mV
150
1600
V
-0.3
3.8
mV
15
SDD11
dB
Reflected Differential to Common
Mode Conversion
SCD11
dB
-10
TJ
UIp-p
0.28
DDJ
UIp-p
0.1
0.055
Data Dependent Jitter
Data Dependent Pulse Width Shrinkage
See Note 1
DDPWS
UIp-p
Uncorrelated Jitter
UJ
UIRMS
J2 Jitter Tolerance
J2
UI
0.17
J9 Jitter Tolerance
J9
UI
0.29
Eye Mask
Peak-to-peak differential
RMS
Differential Input S-Parameter
Total Jitter
Notes
10 MHz to 11.1 GHz
10 MHz to 11.1 GHz
0.023
See Note 2
Hit ratio = 5 x 10-5
Notes for Table 4:
1. Maximum SDD11 is defined by the formulas:
0.1 < f < 4.11 4.11 ≤ f < 11.1
2. The worst case electrical input is defined by the eye mask:
Normalized Time (UI)
10
SPECIFICATIONS
Table 5: QSFPO-40G Series Electrical Output Specification
Specifications
Symbol
Data Rate per Channel
DZM
Termination Mismatch at 1 MHz
Output AC Common Mode Voltage
Single-ended Output
Voltage Tolerance
Differential Output Amplitude
VDO
Differential Output Amplitude in
Squelched State
Unit
Min
Max
Gbps
1
10.5
%
15
mV
7.5
Notes
RMS
V
-0.3
3.8
mV
310
750
Peak-to-peak differential
50
Peak-to-peak differential
mV
0.1
0.6
Differential Unsigned Amplitude
Vdiffc
Common Mode Output
Reflection Coefficient
SCC22
dB
See Note 1
10 MHz to 11.1 GHz
Differential Output S-Parameter
SDD22
dB
See Note 2
10 MHz to 11.1 GHz
Output Transition Time
Tr, Tf
ps
28
Total Jitter
TJ
UIp-p
Deterministic Jitter
DJ
20% to 80%
0.7
UI
0.4
J2 Jitter
UIp-p
0.42
J9 Jitter
UIp-p
0.65
Eye Mask
See Note 3
Hit ratio = 5 x 10-5
Eye Mask
See Note 3
Hit ratio = 1 x 10-12
Notes for Table 5:
1. Maximum SCC22 is defined by the formulas:
0.1 < f < 2.5
2.5 ≤ f < 11.1
-3
2. Maximum SDD22 is defined by the formulas:
0.1 < f < 4.11
4.11 ≤ f < 11.1
3. Two eye masks are specified, but are considered to be identical due
to the differences in the hit ratio:
Normalized Time (UI)
Eye Mask for Hot Ratio
= 1 x 10-5
Normalized Time (UI)
Eye Mask for Hot Ratio
= 1 x 10-12
11
SPECIFICATIONS
High Speed Electrical Characteristics: QSFPO-56G Series
The electrical requirements for input signal into the QSFPO-56G Series
are defined for the transmit side in Table 6. With inputs into the AOC
that meet these requirements, the output parameters shown in Table 7
are guaranteed.
Table 6: QSFPO-56G Series Electrical Input Requirements
Specifications
Symbol
Data Rate per Channel
Differential Input Amplitude
VDI
Single-ended Voltage Tolerance
AC Common Mode Voltage
Unit
Min
Max
Gbps
1
14.2
mV
250
1600
V
-0.3
3.8
mV
15
SDD11
dB
Common Mode Input Return Loss
Common Mode to Differential
Reflection
SCC11
dB
SDC11
Reflected Differential to Common
Mode Conversion
SCD11
dB
-10
See Note 1
-2
TJ
UIp-p
0.28
UIp-p
0.1
DDPWS
UIp-p
0.11
J2 Jitter Tolerance
J2
UI
0.19
J9 Jitter Tolerance
J9
UI
0.34
Data Dependent Pulse Width
Shrinkage
Eye Mask
50 MHz to 14.1 GHz
See Note 2
DDJ
Data Dependent Jitter
Peak-to-peak differential
RMS
Differential Input Return Loss
Total Jitter
Notes
See Note 3
Hit ratio = 5 x 10-5
Notes for Table 6:
1. Maximum SDDxx is defined by the formula:
0.05 < f < 5.6 2. Maximum SDC11 is defined by the formula:
3. The worst case electrical input is defined by the eye mask:
Normalized Time (UI)
12
SPECIFICATIONS
Table 7: QSFPO-56G Series Electrical Output Specification
Specifications
Symbol
Data Rate per Channel
Termination Mismatch at 1MHz
Unit
Min
Max
Gbps
1
14.2
DZM
Output AC Common Mode Voltage
%
15
mV
Single-ended Output
Voltage Tolerance
20
V
Differential Output Amplitude in
Squelched State
-0.3
50
mV
Peak-to-peak differential
50, 225
Range 0
100, 350
Range 1
150, 450
Range 2
Common Mode Output Reflection
Coefficient
SCC22
dB
See Note 1
Differential Output S-Parameter
SDD22
dB
See Table 6, Note 2
Common Mode to
Differential Reflection
SDC22
Output Transition Time
Tr, Tf
ps
TJ
UIp-p
0.7
J2 Jitter
UIp-p
0.44
J9 Jitter
UIp-p
Total Jitter
RMS
3.8
mV
Differential Unsigned
Output Voltage
Notes
50 MHz to 15 GHz
See Table 6, Note 2
17
20% to 80%
0.69
Eye Mask
See Note 2
Hit ratio = 5 x 10-5
Notes for Table 7:
1. Maximum SCC22 is defined by the formulas:
0.01 < f < 4.1
11.1 ≤ f < 15
–2
2. The “InfiniBand Architecture Release 1.3” introduces the concept
of user selectable output voltage to enable interworking with linear
and limiting PHYs. By default, a QSFPO-56G Series cable will power
up with a voltage output range of 1. This can be changed to produce
a higher or lower output voltage swing by changing Bytes 238 and
239 within Page 03 of the memory map. For further information,
please refer to the aforementioned standard.
TM
The voltage mask is dependent on the Selected Voltage Range:
Normalized Time (UI)
13
SPECIFICATIONS
Optical Characteristics
QSFP+ Active Optical Cables are also available as half cable assemblies.
Half cables with MTP connectors are available for applications that
require connection to existing infrastructure. Breakout cables with four
Duplex LC connectors are available for connecting a QSFP+ port to
SFP+ or XFP transceivers.
Table 8: QSFPO-40G Series Optical Performance
Specifications
Unit
Min
Max
Center Wavelength
nm
840
860
RMS Spectral Width
nm
0.65
dB/Hz
RIN OMA
Encircled Flux
Fiber Length
dBm
0.1
100
dBm
-5.0
-1.2
dB
3
Average Receive Power
dBm
-9.9
Receiver Sensitivity in OMA
dBm
Extinction Ratio
At 19 µm
At 4.5 µm
-30
m
Average Launch Power per Lane
Defined as the standard
deviation of the spectrum
-128
≥86%
≥30%
Average Power of an Off Transmitter
Notes
Electrical connector to
optical connector
-1
-11.1
Table 9: QSFPO-56G Series Optical Performance
Specifications
Unit
Min
Max
Center Wavelength
nm
840
860
RMS Spectral Width
nm
RIN OMA
0.65
dB/Hz
Fiber Length
Average Launch Power per Lane
Extinction Ratio
14
Defined as the standard
deviation of the spectrum
-128
≥86%
≥30%
Encircled Flux
Average Power of an Off Transmitter
Notes
dBm
At 19 µm
At 4.5 µm
-30
m
0.1
100
dBm
-5.0
-1.2
dB
3
Average Receive Power
dBm
-9.9
Receiver Sensitivity in OMA
dBm
-1
-10.5
Electrical connector to
optical connector
SPECIFICATIONS
Interfaces
Control Interface
As described in the QSFP+ standard, the electrical interface has the
following low speed signals for control and status: ModSelL, LPMode,
ResetL, ModPrsL, IntL. Their operation is described below:
•ModSelL
The ModSelL signal allows multiple QSFP+ modules to be on a
standard I2C Serial control bus. By default, this pin is held low by
the host. In this state, the module will respond to the I2C interface.
When the ModSelL pin is pulled high by the host, the module will
not respond to or acknowledge any I2C query or command.
Care must be taken to ensure that the ModSelL pin is used to
toggle control of different modules, the assert and de-assert times
must be taken into account to prevent communication conflicts.
•LPMode
The LPMode pin is used by the host to set the maximum power
consumption by the module. This is intended to protect hosts that
are not designed to cool higher power modules that draw more
than 1.5 W.
Since the power consumption of a QSFP+ AOC is 0.8 W maximum,
this pin is not used and the module is always in a low power state.
•ResetL
The AOC can be reset to its default settings by pulling this control
pin to a low level for a period longer than the minimum pulse length
of the Two-Wire serial interface. While in this reset state, the host
should disregard all status bits.
•ModPrsL
ModPrsL is used to indicate to the host that the connector is populated by the AOC. In the absence of an AOC, this is pulled up to the
host Vcc. When the AOC is inserted, it completes the path to ground
through a resistor on the host and pulls ModPrsL to a low state.
•IntL
This control pin is used to indicate a possible module operation fault
or a status critical to the host system. The IntL pin is an open collector
output and must be pulled to the host Vcc voltage on the host board.
When pulled “low” by the AOC, the alarm is active and the AOC will
identify the source of the interrupt using the Two-Wire serial interface.
15
SPECIFICATIONS
In addition, there is an industry standard Two-Wire serial interface
scaled for 3.3 volt LVTTL. It is implemented as a slave device. Signal
and timing characteristics are further defined below:
Two-Wire Serial Interface
Table 10 and Figure 4 show the Two-Wire timing specifications as
defined by SFF-8436.
Table 10: Optical Engine Two-Wire Timing Specifications
Parameter
Symbol
Unit Min Typ Max
Conditions
Clock Frequency
fSCL
KHz
0
Clock Pulse Width Low
tLOW
µs
1.3
Clock Pulse Width High
tHIGH
µs
0.6
Time Bus Free Before New
Transmission Can Start
tBUF
µs
20
START Hold Time
tHD,STA
µs
0.6
START Setup Time
tSU,STA
µs
0.6
Data in Hold Time
tHD,DAT
us
0
Data in Setup Time
tSU,DAT
µs
0.1
Input Rise Time (400 kHz)
tR,400
ns
Input Fall Time (400 kHz)
tF,400
ns
STOP Setup Time
tSU,STO
µs
0.6
ModSelL Setup Time
HOST_select_setup
ms
2
Setup time on the select lines
before start of a host initiated
serial bus sequence
ModSelL Hold Time
Host_select_hold
µs
10
Delay from completion of a serial
bus sequence to changes of module select status
Deselect_abort
ms
2
Delay from a host de-asserting
ModSelL (at any point in a bus
sequence), to the module
releasing SCL and SDA
Abort Sequence –
Bus Release
400
400
Between STOP
and START
300
From VIL,MAX-0.15 to VIH,MIN + 0.15
300
From VIL,MAX-0.15 to VIH,MIN + 0.15
Figure 4: Two-Wire Timing Diagram (per SFF-8436)
16
SPECIFICATIONS
Control, Status and Monitor Interface
Table 11 and Table 12 provide the specifications of the control, status
and monitoring interface.
Table 11: I/O Timing for Control, Status and Monitoring
Specifications
Symbol Unit Min Max
Notes
tINIT
ms
2000
Time from power on, hot plug or rising edge of
reset until the module is fully functional
tRESET_INIT
μs
2.5
A reset is generated by a low level longer than the
minimum reset pulse time present on the ResetL pin
Serial Bus Hardware
Ready
tSERIAL
ms
2000
Time from power on until module responds to data
transmission over the Two-Wire serial bus
Monitor Data Ready
Time
tDATA
ms
2000
Time from power on to data not ready, bit 0 of
Byte 2, de-asserted and IntL asserted
Reset Assert Time
tRESET
ms
2000
Time from rising edge on the ResetL pin until the
module is fully functional3
IntL Assert Time
tON_INTL
ms
200
Time from occurrence of condition triggering IntL
until Vout:IntL = Vol
IntL De-assert Time
tOFF_INTL
μs
500
Time from operation4 of associated flag until
Vout:IntL = Voh. This includes de-assert times for Rx
LOS, Tx Fault and other flag bits
Rx LOS Assert Time
tON_LOS
ms
100
Time from Rx LOS state to Rx LOS bit set
(value = 1b) and IntL asserted
Tx Fault Assert Time
tON_TXFAULT
ms
200
Time from Tx Fault state to Tx Fault bit set
(value = 1b) and IntL asserted
Flag Assert Time
tON_FLAG
ms
200
Time from occurrence of condition triggering flag to
associated flag bit set (value = 1b) and IntL asserted
Mask Assert Time
tON_MASK
ms
100
Time from mask bit set (value = 1b)1 until associated
IntL assertion is inhibited
Mask De-assert Time
tOFF_MASK
ms
100
Time from mask bit cleared (value = 0b)1 until associated
IntlL operation resumes
Application or Rate
Select Change Time
tRATE_SEL
ms
100
Time from change of state of Application or Rate Select
bit1 until transmitter or receiver bandwidth is in
conformance with appropriate specification
ms
100
Time from P_Down bit set (value = 1b)1 until module
power consumption enters Power Level1
ms
300
Time from P_Down bit cleared (value = 0b)1 until the
module is fully functional3
Initialization Time
Reset init Assert Time
Power Over-ride or
tON_PDOWN
Power Set Assert Time
Power Over-ride or
t
Power Set De-assert Time OFF_PDOWN
Note 1. Measured from falling clock edge after stop bit of write transaction.
Note 2. Power is defined as the instant when supply voltages reach and remain at or above the minimum level specified in Table 3.
Note 3. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 Byte 2 de-asserted. The module should also meet
electrical specifications.
Note 4. Measured from falling edge after stop bit of read transaction.
Table 12: I/O Timing for Squelch
Specifications
Symbol
Unit Min Max
Rx Squelch Assert Time
tON_RXSQ
μs
80
Rx Squelch De-assert Time
tOFF_RXSQ
μs
80
Notes
Time from loss of Rx input signal until the
squelched output condition is reached
Time from resumption of Rx input signals until
normal Rx output condition is reached
17
INITIALIZATION PROCEDURE
Memory Map
Introduction – EEPROM Virtual Addressing
The SFF-8436 specification calls for a list of cable parameters to
be readable through an I2C interface, commonly referred as the
“EEPROM” parameters. When the first standard revision was written,
all the parameters were static and were stored in an on-board
EEPROM. As revisions evolved, some of the fields became dynamic
(such as temperature or optical power readings), while others (such
as interrupts and alarms) became Read/Write (R/W). As a result, an
EEPROM based implementation does not suffice anymore, although
the term is still used to refer to the Memory Map. We will refer to this
as the “SFF Memory Map.”
Consequently, the Samtec current implementation, although referred to as
an “EEPROM map,” does not use an actual direct EEPROM read or write.
Instead, each I2C read or write request is interpreted by the embedded
microprocessor in the optical engine. The microprocessor then reads or
stores data which could come from, or go to, different sources:
• The processor’s own internal EEPROM
• The processor’s static, dynamic RAM or register memory
• Sensors or internal chipset readings
• Internal processor calculations or registers
An important consequence is that EEPROM byte addresses used in I2C
requests are virtual – they will not always correspond to the physical
address in the processor internal EEPROM, or might not have a
physical EEPROM location at all.
This is invisible to the end user, who just reads and writes to the I2C
as if it were an actual EEPROM according to the standard SFF Memory
Map. The processor will take care of fetching and writing the data
internally from/to the correct physical location.
Instructions for modifying the EEPROM map can be found at
www.samtec.com.
18
INITIALIZATION PROCEDURE
SFF Memory Map
The structure of the SFF Memory Map as defined by SFF-8436 rev. 3.8
is shown in Figure 3.
For historical reasons, the SFF Memory Map is somewhat contrived. It
is divided into lower and upper memory:
The lower memory is a block or “page” of 128 bytes, and its bytes
address are numbered 0 to 127.
The upper memory is itself divided in four pages, numbered page
0 to page 3. Each page is also 128 bytes long block, but with byte
addresses numbered 128-255 for each page.
All QSFP+ AOCs are hard-wired at I2C device address A0h. The lower
page is accessed by using the A0h address as the device address, and
the 0 to 127 address as the byte address.
Upper pages are accessed by first writing the desired page number at
byte in address 127 (Page Select Byte). Any subsequent byte read or
write request in the address range 128-255 will be done from/to the
page that has been specified in the Page Select Byte. Samtec AOCs do
not use Page 02.
Figure 5: Structure of the SFF Memory Map (from the SFF specification)
19
INITIALIZATION PROCEDURE
Below is a summary description of the memory pages. For more
details, see pages 18-19 of this product specification:
• Lower memory, Page 00, bytes 0-127: contains status, interrupt and
monitoring information.
• Page 00, bytes 128-255: contains standardized Read-Only information
for the end-user. The data is physically mapped to the microprocessor
internal EEPROM bytes 128-255.
• Page 01, bytes 128-255 is optional and not supported in the Samtec AOC.
• Page 02, bytes 128-255 is available for the user to store and read his
own data.
• Page 03, bytes 128-255 contains module thresholds, channel thresholds
and masks, and optional channel controls.
Page 00, Lower Memory
Many of the lower memory bytes are optional or not applicable to
an AOC implementation. Table 13 lists the bytes and corresponding
features supported in our implementation. Full details about the bit
fields and usage can be found in the SFF-8436 specification.
Table 13: Supported Page 00 Lower Memory Fields
20
Page 00 Byte #
Description
Default Value
0
2
3
4
6
7
22
23
26
27
86
93
100
101
103
104
119
120
121
122
123
124
125
126
127
Identifier
Status – Flat or Paged Memory
Interrupt Flags – LOS
Interrupt Flags – Tx Fault
Interrupt Flags – Temp Alarm
Interrupt Flags – Voltage Alarm
Module Monitors – Temperature MSB
Module Monitors – Temperature LSB
Module Monitors – Supply Voltage MSB
Module Monitors – Supply Voltage LSB
Control – Transmitter Disable
Low Power Control
Interrupt Masks – Tx LOS Mask
Interrupt Masks – Tx Fault Mask
Interrupt Masks – Temperature Fault Mask
Interrupt Masks – Voltage Fault Mask
Password Change Entry Data
Password Change Entry Data
Password Change Entry Data
Password Change Entry Data
Password Entry Area
Password Entry Area
Password Entry Area
Password Entry Area
Page Select Byte
OD
0
1
2
3
Rx only. Tx LOS not supported
The engine always runs in low power mode, writing to this register has no effect
User settable password protection of page 02 not supported
0
0
0
0
Read-Only /
Read-Write
RO
RO
R0
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes
1
2
3
3
3
3
3
3
3
3
INITIALIZATION PROCEDURE
Page 00, Upper Memory
The values for the Page 00 Upper Memory bytes are shown in Table
14. Default factory-programmed values for InfiniBand™ are shown.
Some of the fields will need to be adjusted by the customer at
manufacturing time. Values can be uploaded using our software tool.
For details, please contact [email protected]. Please contact Samtec
for alternate default configurations.
Table 14: Page 00 Upper Memory Fields (factory default, InfiniBand™)
Byte #
Bit/s
Description
128
129
130
140
142
143
144
145
146
147
148-163
164
165-167
168-183
184-185
186
187
188
189
190
191
193
194
194
194
194
195
195
195
195
195
196-211
212-217
218-219
223
224-255
7:0
7:6
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:4
Identifier
Extended Identifier Values, Power Class
Connector
Nominal BR
Cable Length (SM fiber), in km
Cable Length (OM3 fiber), in 2 m Increments
Cable Length (OM2 fiber), in 1 m Increments
Cable Length (OM1 fiber), in 1 m Increments
Link Length Units of 1 m
Transmitter Technology
Vendor Name
Extended Module Codes (InfiniBand™ Data Rates)
Vendor OUI
Vendor Part Number
Vendor Revision
Wavelength (fiber)
Wavelength (fiber)
Wavelength Tolerance
Wavelength Tolerance
Max Case Temp
Check Sum
RX Output Amplitude Programming
RX Squelch Disable Implemented
RX Output Disable Capable
TX Squelch Disable Implemented
TX Squelch Implemented
Memory Page 02 Provided
Memory Page 01 Provided
TX Disable Implemented (also disables serial output)
TX Fault Reporting Implemented
LOS and Reporting Implemented
Vendor Serial Number
Date Code
Lot Code
Check Sum
Vendor Specific Information
3:0
7:0
7:0
7:0
7:0
7:0
7:0
0
3
2
1
0
7
6
4
3
1
All
All
All
7:0
All
Value
Meaning
0Dh
0
Power Class 1 Module
23h
AOC has no optical connector
Part Specific
0
0
0
0
Part Specific
0
Pass: 850 nm VCSEL
Samtec, Inc.
Part Specific
04C880h
Part Specific
0
42h
Wavelength = 850 nm
68h
Wavelength = 850 nm
0Fh
Wavelength Tolerance = 20 nm
A0h
Wavelength Tolerance = 20 nm
70
Max Temp Case = 70ºC
Part Specific
0
Not Implemented
0
Not Implemented
1
RX Output Disable Capable
0
Not Implemented
0
Not Implemented
1
Memory Provided
0
Not Implemented
1
TX Disable Implemented
1
TX Fault Reporting Implemented
0
Not Implemented
Part Specific
Part Specific
0
Optional - Value = 00
Part Specific
FF000110
21
INITIALIZATION PROCEDURE
Notes to Page 00 Implementation
Please see Table 15 for further clarification of our implementation of
Page 00 fields.
Table 14: Notes to the Memory Map Implementation
Type of Parameter
Address
Page
Byte
Name
Notes
Not Provided
Interrupt Flag
00
3
Tx_LOS
Interrupt Flag
00
9-10
L-Rx Power Alarm
Not Provided
Channel Monitoring
00
34-41
Rx Input Power
Rx Input Power is Not Supported
Channel Monitoring
00
42-49
Tx Bias
Tx Bias Monitoring is Not Supported
Channel Mask
00
100[7:4]
M-Tx LOS
Tx LOS is Not Supported
Optional Channel Controls
03
241[3:0]
Tx SQ Disable
Tx Squelch is Not Supported
Page 02
Page 02, bytes 128-255 are provided for end-customer’s own use. The
fields are initialized to 0 at the factory.
Page 03
Table 16: Supported Page 03 Fields
Page 03 Byte #
Description
128
Temp High Alarm MSB
129
Temp High Alarm LSB
130
Temp Low Alarm MSB
131
Temp Low Alarm LSB
132
Temp High Warning MSB
133
Temp High Warning LSB
134
Temp Low Warning MSB
135
Temp Low Warning LSB
144
Vcc High Alarm MSB
145
Vcc High Alarm LSB
146
Vcc Low Alarm MSB
147
Vcc Low Alarm LSB
148
Vcc High Warning MSB
149
Vcc High Warning LSB
150
Vcc Low Warning MSB
151
Vcc Low Warning LSB
Default Value
0ºC
70ºC
5ºC
3.465 V
3.135 V
3.3825 V
3.2175 V
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
176
Rx Power High Alarm MSB
RO
177
Rx Power High Alarm LSB
RO
238
FDR Voltage Select
Range 1
R/W
239
FDR Voltage Select
Range 1
R/W
240
Squelch Disable
R/W
241
Rx Output Disable
R/W
Note: Bytes 238 and 239 are only writeable for QSFPO-56G Series variants.
22
75ºC
Read-Only / Read-Write
INITIALIZATION PROCEDURE
Output Voltage and Pre-emphasis Settings
The Rx output amplitude swing and pre-emphasis settings are factory
adjustable. Four output voltage amplitude settings are available.
• 0 mV (Rx channel permanently disabled)
• 317 mV
• 422 mV
• 739 mV (factory default)
Four pre-emphasis settings are available:
• 0 mV (factory default)
• 125 mV
• 175 mV
• 325 mV
These settings will change the quality of the electrical output. In addition,
changing these settings also affect the power consumption of the optical
engine as shown on Table 17. Reducing voltage and pre-emphasis
results in the lowest power consumption available, while larger voltage
and pre-emphasis might be used in special non-standard applications
to overcome poor electrical traces or provide more design margin at
the expense of power consumption.
All QSFP+ AOC cables will default on power up to the 739 mV,
0 mV settings. As per the InfiniBand™ FDR specification, the memory
map can be used to change the output settings of the QSFPO-56G
Series. Changing the output to Range 0 will result in a drop in power
consumption, whereas changing to Range 2 will increase the power
consumption.
Table 17: Typical Power Consumption vs. Rx Settings
Voltage Swing Setting (mV)
Pre-emphasis Setting (mV)
Typical Power
Consumption (mW)
317
317
317
317
422
422
422
422
739
739
739
739
0
125
175
325
0
125
175
325
0
125
175
325
590
740
770
850
620
770
800
890
710
860
890
980
Notes
56G Range 0
Default Setting
56G Range 2
23
INTERFACE
Electrical
Figure 5 shows the contact numbering for the assembly connector.
The diagram shows the module from the bottom view. There are 38
pins intended for high speed low speed signals, power and ground
connections. These pins are described in Table 18.
Table 18: Edge Connector Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
24
Logic
CML-I
CML-I
CML-I
CML-I
LVTLL-I
LVTLL-I
LVCMOS-I/O
LVCMOS-I/O
CML-O
CML-O
CML-O
CML-O
CML-O
CML-O
CML-O
CML-O
LVTLL-O
LVTLL-O
LVTLL-I
CML-I
CML-I
CML-I
CML-I
Symbol
Description
Plug Sequence
Note
GND
Tx2n
Tx2p
GND
Tx4n
Tx4p
GND
ModSelL
ResetL
Vcc Rx
SCL
SDA
GND
Rx3p
Rx3n
GND
Rx1p
Rx1n
GND
GND
Rx2n
Rx2p
GND
Rx4n
Rx4p
GND
ModPrsL
IntL
Vcc Tx
Vcc1
LPMode
GND
Tx3p
Tx3n
GND
Tx1p
Tx1n
GND
Ground
Transmitter Inverted Data Input
Transmitter Non-Inverted Data Input
Ground
Transmitter Inverted Data Input
Transmitter Non-Inverted Data Input
Ground
Module Select
Module Reset
+3.3 V Power Supply Receiver
Two-Wire Serial Interface Clock
Two-Wire Serial Interface Data
Ground
Receiver Non-Inverted Data Output
Receiver Inverted Data Output
Ground
Receiver Non-Inverted Data Output
Receiver Inverted Data Output
Ground
Ground
Receiver Inverted Data Output
Receiver Non-Inverted Data Output
Ground
Receiver Inverted Data Output
Receiver Non-Inverted Data Output
Ground
Module Present
Interrupt
+3.3 V Power Supply Transmitter
+3.3 V Power Supply
Low Power Mode
Ground
Transmitter Non-Inverted Data Input
Transmitter Inverted Data Input
Ground
Transmitter Non-Inverted Data Input
Transmitter Inverted Data Input
Ground
1
3
3
1
3
3
1
3
3
2
3
3
1
3
3
1
3
3
1
1
3
3
1
3
3
1
3
3
2
2
3
1
3
3
1
3
3
1
1
1
1
2
1
1
1
1
1
1
2
2
1
1
1
Note 1: GND is the symbol for signal and supply (power) common for the optical engine. All are common within the optical engine
and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.
Note 2: Vcc Rx, Vcc1 and Vcc Tx are the receiver and transmitter power supplies and shall be applied concurrently. Requirements
defined for the host side of the Host Edge Card Connector are listed in Table 18. The connector pins are each rated for a maximum
current of 500 mA.
INTERFACE
Top Side
Viewed from Top
Bottom Side
Viewed from Bottom
Figure 5: Edge Card Connector Pinout
MECHANICAL CHARACTERISTICS
Connector Dimensions
OVERALL LENGTH = CABLE LENGTH + (47,00) 1.85 ±5%
(67,45) 2.66
(18,35)
.722
(8,50)
.335
(138,43) 5.45
Figure 6: Connector Dimensions
25
TECHNICAL INFORMATION
Regulatory and Compliance
Table 19: Regulatory and Compliance
Feature
Electrostatic Discharge (ESD)
to the Electrical Contact
Electrostatic Discharge (ESD)
to Module Case
Electromagnetic
Interference (EMI)
EMI Immunity
Laser Eye Safety
RoHS Compliance
Test Method
Performance
JEDEC Human Body Model (HBM)
(JESD22-A114-B)
1 kV
JEDEC Machine Model (MM)
(JESD22-A115-A)
TBD
Variation of IEC 61000-4-2
15 kV
FCC part 15 CENELEC EN55022
(CISPR 22A) VCCI class 1
Variation of IEC 61000-4-3
IEC 60825-1 amendment 2
CFR 21 section 1040
RoHS 6/6 directive 2002/95/EC
amendment 4054 (2005/747/EC)
TBD
10 V/m, 80 – 1000 Mz
Class 1
Class 1 LASER PRODUCT
per IEC 60825-1 Ed. 2 (2007)
Complies with FDA performance standards for laser products except for deviations pursuant to Laser Notice No. 50,
dated June 24, 2007
Manufacturing Location: Samtec, 520 Park East Blvd., New Albany, IN 47150
Caution - Use of controls or adjustments or performance of procedures other than those specified herein may result
in hazardous radiation exposure.
Ordering Information
QSFP+ Active Optical Cable
QSFPO - XXX - XXX.X - 01
Product Category
Speed
4 x 10G lanes
4 x 14G lanes
40G
56G
Type
Length in meters = 0.5 to 100.0
(500 mm to 100 m. See www.samtec.com?QSFPO-40G, www.samtec.com?QSFPO-56G)
MTP or Duplex LC end terminations also available. Call Samtec.
26
TECHNICAL INFORMATION
Definitions
This document uses the following conditions:
All voltages are referred to GND unless otherwise specifically noted.
Currents are defined positive out of the pin.
Reference Documents
SFF-8436: SFF-8431: InfiniBandTM IEEE802.3ba
QSFP+ Specifications Document
SFP+ Specifications Document
Architecture Release 1.3
Amendment 4: Media Access Control Parameters,
Physical Layers, and Management Parameters for
40 Gbps and 100 Gbps Operation
Notice
This document is made available subject to Samtec General Terms and
Conditions available at www.samtec.com and contains information about
a product which is currently under final development. The information
contained in this document is based on design targets, simulation results
or early prototype test results. Characteristics, data and other specifications
are subject to change without notice. Therefore the reader is cautioned that
this datasheet is preliminary. The reader is advised to obtain the most recent
datasheet before considering any purchase or use for design considerations.
Warning
Samtec products are not intended for use in life support applications
and any such use without written consent is therefore prohibited.
27
For more information visit
www.samtec.com/active-optics or contact
Samtec’s Optical Group at [email protected]
All designs, specifications and components are
preliminary and subject to change without notice.
JANUARY 2014