WM8778-EV1B Evaluation Board User Handbook

WM8778-EV1B
Evaluation Board User Handbook
Rev 1.1
WM8778-EV1M
TABLE OF CONTENTS
INTRODUCTION ............................................................................................. 3
GETTING STARTED ....................................................................................... 3
EVALUATION KIT CHECKLIST ............................................................................. 3
CUSTOMER REQUIREMENTS.............................................................................. 3
EVALUATION BOARD OPERATION.............................................................. 4
POWER SUPPLIES ............................................................................................... 4
BOARD FUNCTIONALITY ..................................................................................... 4
DIGITAL INPUT...................................................................................................... 5
ANALOGUE INPUT ................................................................................................ 5
DIGITAL OUTPUT.................................................................................................. 5
ANALOGUE OUTPUT ............................................................................................ 5
INTERFACES......................................................................................................... 6
HEADERS .............................................................................................................. 6
JUMPERS .............................................................................................................. 7
SWITCHES ............................................................................................................ 8
LINKS ..................................................................................................................... 8
HARDWARE CONTROL ................................................................................. 9
SOFTWARE CONTROL................................................................................ 11
SPI INTERFACE MODE....................................................................................... 11
TWO-WIRE MODE............................................................................................... 11
REGISTER MAP .................................................................................................. 12
SERIAL INTERFACE SOFTWARE DESCRIPTION...................................... 13
SOFTWARE DOWNLOAD ................................................................................... 13
SOFTWARE INSTALLATION............................................................................... 13
SOFTWARE OPERATION ................................................................................... 14
DAC SETUP ......................................................................................................... 19
ADC SETUP ......................................................................................................... 21
LINE SETUP ........................................................................................................ 23
SCHEMATIC LAYOUT .................................................................................. 25
WM8778-EV1B PCB LAYOUT...................................................................... 33
WM8778-EV1B BILL OF MATERIAL............................................................ 37
APPENDIX .................................................................................................... 39
DAC AND ADC ALTERNATIVE AUDIO INTERFACE CONFIGURATION............ 39
EXTERNAL DSP CONNECTION TO THE WM8778-EV1B .................................. 41
ADDITIONAL WM8778-EV1B SETUP RECOMMENDATIONS ............................ 45
EVALUATION SUPPORT ............................................................................. 47
IMPORTANT NOTICE ................................................................................... 48
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WM8778-EV1M
INTRODUCTION
The WM8778 is a high performance stereo audio CODEC, ideal for surround sound
processing applications for home hi-fi, DVD-RW and other audio visual equipment.
This evaluation platform and documentation should be used in conjunction with the latest
version of the WM8778 datasheet. The datasheet gives device functionality information as
well as timing and data format requirements.
This evaluation platform has been designed to allow the user ease of use and give optimum
performance in device measurement as well as providing the user with the ability to listen to
the excellent audio quality offered by the WM8778.
GETTING STARTED
EVALUATION KIT CHECKLIST
The following items are available from Wolfson:
•
WM8778-EV1B Evaluation Board (order from Wolfson)
•
WM8778-EV1S
.exe
file
http://www.wolfsonmicro.com/)
•
WM8778-EV1M User Handbook (download from http://www.wolfsonmicro.com/)
for
control
software
(download
from
CUSTOMER REQUIREMENTS
Minimum customer requirements are:
•
D.C. Power supply of +5V
•
D.C. Power supply of +2.7V to +5.5V
•
D.C. Power supply of +/-12.0V
•
PC and printer cable (for software control)
Minimum PC spec requirements are:
•
Win95/98/NT/2000/XP
•
486 Processor
DAC Signal Path Requires:
•
Digital coaxial or optical data source
•
1 set of active stereo speakers and/or 1 set of headphones
ADC Signal Path Requires:
•
Analogue coaxial signal source
•
Digital coaxial or optical data receiving unit
Analogue Signal Path Requires:
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•
Analogue coaxial signal source
•
1 set of active stereo speakers and/or 1 set of headphones
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EVALUATION BOARD OPERATION
POWER SUPPLIES
Using appropriate power leads with 4mm connectors, power supplies should be connected
as described in Table 1.
REF-DES
J1
SOCKET NAME
+5V
SUPPLY
+5V
J2
DGND
0V
J3
DVDD
+2.7V to +3.6V
J4
AVDD
+2.7V to +5.5V
J5
AGND
0V
J22
+12V
+12V
J23
-12V
-12V
Table 1 Power Supply Connections
The DGND and AGND connections may be connected to a common GND on the supply with
no reduction in performance.
Note: Refer to WM8778 datasheet for limitations on individual supply voltages.
Important: Exceeding the recommended maximum voltage can damage EVB
components. Under voltage may cause improper operation of some or all of the EVB
components.
BOARD FUNCTIONALITY
There are three options for inputting digital data into the WM8778 evaluation board. There is
a coaxial input (J7) via a standard phono connector or an optical input (U3) via a standard
optical receiver module. A direct digital input is also available via one side of a 2x8 pin
header (H1).
The analogue input signals are applied to the evaluation board via standard phono
connectors J13 (AINL) and J10 (AINR). The evaluation board provides the option to select an
active or passive anti-alias filter for the analogue input; this can be selected using SW3 and
SW4.
There are two options for outputting digital data from the WM8778 evaluation board. There is
a coaxial output (J6) via a standard phono connector. The digital signals may also be
accessed via one side of a 2x8 pin header (H2).
The line analogue outputs of the board are via phono connectors and can be output as active
external filtered or unfiltered outputs. J19 (UNFILT_VOUTL) and J15 (UNFILT_VOUTR)
provide the unfiltered outputs and J21 (FILT_VOUTL) and J20 (FILT_VOUTR) provide the
active filtered outputs.
All WM8778 device pins are accessible for easy measurement via the 1x14 pin headers (H3
and H4) running up each side of the device.
Level-shift IC’s (U5 and U8) are used to shift the fixed +5V digital input from the CS8427 (U4)
down to the same level as DVDD and vice-versa.
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DIGITAL INPUT
REF-DES
J7
SOCKET NAME
SPDIF_IN
SIGNAL
Digital (AES/EBU, UEC958, S/PDIF,
EIAJ CP340/1201) signal.
U3
DIGITAL_OPTICAL INPUT
Digital (AES/EBU, UEC958, S/PDIF,
EIAJ CP340/1201) optical signal.
Table 2 Digital Inputs
ANALOGUE INPUT
REF-DES
J10
SOCKET NAME
AINR
SIGNAL
Analogue Input signal
J13
AINL
Analogue Input signal
Analogue signals applied to these connectors can be selected for active or passive
anti-aliasing filtering and are also AC coupled before being input to the WM8778.
Table 3 Analogue Inputs
Note: When used in Slave Mode, an SPDIF signal must still be applied to phono connector
J7. This input signal is used to allow correct operation of the CS8427 as well as being used
to generate the MCLK for the WM8778.
DIGITAL OUTPUT
REF-DES
J6
SOCKET NAME
SPDIF_OUT
SIGNAL
Digital (AES/EBU, UEC958,
S/PDIF, EIAJ CP340/1201)
signal.
Table 4 Digital Output
ANALOGUE OUTPUT
REF-DES
J19
SOCKET NAME
UNFILT_VOUTL
SIGNAL
Analogue Line Output
J15
UNFILT_VOUTR
Analogue Line Output
J21
FILT_VOUTL
Analogue Line Output
J20
FILT_VOUTR
Analogue Line Output
Table 5 Analogue Outputs
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WM8778-EV1M
INTERFACES
Figure 1 Interfaces
HEADERS
H1
SIGNAL
H2
SIGNAL
1/2
DACDAT
16/15
GND
3/4
GND
14/13
ADCMCLK
5/6
DACLRC
12/11
GND
7/8
GND
10/9
ADCDOUT
9/10
DACBCLK
8/7
GND
11/12
GND
6/5
ADCBCLK
13/14
DACMCLK
4/3
GND
15/16
GND
2/1
ADCLRC
LNK1
SIGNAL
LNK2
SIGNAL
1
ZFLAGR
1
ZFLAGL
2
AGND
2
AGND
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WM8778-EV1M
H3
WM8778
PIN NAME
H4
WM8778
1
1
AINL
1
15
PIN NAME
CE/I2S
2
2
ZFLAGR
2
16
DI/DEEMPH
3
3
ZFLAGL
3
17
CL/IWL
4
4
DACBCLK
4
18
VOUTL
5
5
DACMCLK
5
19
VOUTR
6
6
DIN
6
20
VMIDDAC
7
7
DACLRC
7
21
DACREFN
DACREFP
8
8
ADCBCLK
8
22
9
9
ADCMCLK
9
23
VMIDADC
10
10
DOUT
10
24
ADCREFGND
11
11
ADCLRC
11
25
ADCREFP
12
12
DGND
12
26
AVDD
13
13
DVDD
13
27
AGND
14
14
MODE
14
2
AINR
Table 6 Headers
JUMPERS
JUMPERS
JUMPER STATUS
DESCRIPTION
J8
OPEN
SHORT
DAC Slave Mode (Level shift direction) [default setting]
DAC Master Mode
J9 (BCLK)
OPEN
SHORT
Separate ADC and DAC BCLK
Common ADC and DAC BCLK [default setting]
J11 (LRC)
OPEN
SHORT
Separate ADC and DAC LRC
Common ADC and DAC LRC [default setting]
J12
OPEN
SHORT
ADC Slave Mode (Level shift direction) [default setting]
ADC Master Mode
J14 (MCLK)
OPEN
SHORT
Separate ADC and DAC MCLK
Common ADC and DAC MCLK [default setting]
J16, J17
OPEN
SHORT
OUT Signals are AC coupled [default setting]
OUT Signals are not AC coupled
Table 7 Jumpers
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SWITCHES
SWITCHES
SWITCH STATUS
SW1
(DATA FORMAT)
DESCRIPTION
1
1
1
1
SW2
2
0
0
0
3
0
0
0
4
1
0
0
5
0
0
0
6
0
1
0
DATA FORMAT
I2S Compatible [default setting]
24-bit Right Justified
Left Justified
After an input data format change has been made using
SW1, the CS8427 will only latch the new settings after SW2
has been pressed and released.
SW3
(AINR Filter)
POS 1
POS 2
Active anti-alias filter selected
Passive anti-alias filter selected [default setting]
SW4
(AINL Filter)
POS 1
POS 2
Active anti-alias filter selected
Passive anti-alias filter selected [default setting]
SW5
(VOUTR Filter)
Pins 1 and 2 SHORT
Pins 2 and 3 SHORT
Centre Position
Unfiltered Output
Filtered Output [default setting]
Output Disconnected
SW6
(VOUL Filter)
Pins 1 and 2 SHORT
Pins 2 and 3 SHORT
Centre Position
Unfiltered Output
Filtered Output [default setting]
Output Disconnected
SW7
(Software Control)
POS 1
POS 2
POS 3
3-wire (SPI) Control Mode [default setting]
Hardware Mode
2-wire Control Mode
Table 8 Switches
LINKS
LINKS
LINK STATUS
DESCRIPTION
LNK3
(5V tolerant supply control)
Pins 1 and 2 SHORT
Pins 2 and 3 SHORT
Centre Position
DVDD Supply for S/W and mode control [default setting]
+5v Supply for S/W and mode control
No Supply for S/W and mode control
LNK4
(Hardware Mode – I2S Control)
Pins 1 and 2 SHORT
Pins 2 and 3 SHORT
24 Bit [default setting]
20/16 Bit
LNK5
(Hardware Mode – IWL Control)
Pins 1 and 2 SHORT
Pins 2 and 3 SHORT
I S Format [default setting]
Right Justified (RJ) Format
LNK6
(Hardware Mode – DEEMPH
Control)
Pins 1 and 2 SHORT
Pins 2 and 3 SHORT
DEEMPH ON
DEEMPH OFF [default setting]
LNK7
(DI Direction Control)
Pins 1 and 2 SHORT
Pins 2 and 3 SHORT
Select if using 2 wire control operation
Select if using 3 wire or hardware operation [default setting]
2
Table 9 Links
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WM8778-EV1M
HARDWARE CONTROL
To operate the WM8778 in hardware mode, the switch SW7 (MODE) must be set to position
2 and link LNK7 must be set to short pins 2 and 3. The 3-pin links on the board (LNK4, LNK5
and LNK6) then become the active source for changing the device functions. The diagram
shown in Figure 2 used with the settings specified in Table 10 will assist in setting the
WM8778-EV1B into a hardware configuration for DAC (slave mode) playback. This is to ease
the initial use of the WM8778 until the user becomes familiar with the device operation. For
ADC or bypass configuration please refer to the ADC and line setup sections.
+5v
DGND
DVDD
+2.7V
to
+3.6V
J1
J2
J3
SPDIF_
OUT
AVDD
+2.7V
to
+5.5V
AGND
J4
J5
-12v
+12v
J23
J22
OPEN
0
SW1
1
2
3
4
5
6
1
1
OPT
_IN
SW3
J8
SW2
AINR
1
H1
1
SW4
J9
1
1
SPDIF_
IN
J11
H2
AINL
H3
H4
1
J12
1
LNK3
1
SW7
LNK5
1
1
1
1
J16
1
1
1
PARALLEL PORT
J14
1
1
UNFILT_
VOUTR
J17
LNK6
LNK7 LNK4
SW6
SW5
UNFILT_
VOUTL
VOUTL
VOUTR
Figure 2 Recommended DAC Setup – Hardware Mode
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WM8778-EV1M
LINKS AND
JUMPERS
LINK / JUMPER /
SWITCH POSITION
DESCRIPTION
H1
Fit jumpers (1,2)
(5,6) (9,10) (13,14)
DAC clocks
H2
No jumpers
ADC Clocks
J8
OPEN
DAC Slave Mode
J9 (BCLK)
OPEN
DAC uses BCLK, no common BCLK for ADC
J11 (LRC)
OPEN
DAC uses LRCLK, no common LRCLK for ADC
J12
OPEN
ADC Slave Mode
J14 (MCLK)
OPEN
DAC uses MCLK, no common MCLK for ADC
J16 and J17
OPEN
Output Signals are AC Coupled
SW1
1
1
2
0
3
0
4
1
5
0
6
0
DATA FORMAT
I2S Compatible
SW3
POS 1
SW4
POS 1
Active anti-alias input filter selected
Active anti-alias input filter selected
SW5
Pins 2 and 3
SHORT
Filtered Output
SW6
Pins 2 and 3
SHORT
Filtered Output
SW7
POS 2
Hardware Mode Selected
LNK3
Pins 1 and 2
SHORT
DVDD Supply for S/W and mode control
LNK4
Pins 1 and 2
SHORT
24 Bit
LNK5
Pins 1 and 2
SHORT
I2S Format
LNK6
Pins 2 and 3
SHORT
DEEMPH OFF
LNK7
Pins 2 and 3
SHORT
Hardware Mode Selected
Table 10 DAC Hardware Mode Jumper Setup (Slave Mode)
Please refer to Table 7 and Table 8 of this document and the WM8778 datasheet for further
details on device configuration in hardware mode.
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WM8778-EV1M
SOFTWARE CONTROL
There are two possible serial software control modes that may be selected to operate the
WM8778. The standard SPI user interface is a 3-wire solution with the second option being
a two-wire solution.
SPI INTERFACE MODE
To operate the WM8778 in SPI (3-wire) mode, switch SW7 must be set to position 1,
selection of software mode will be indicated by D1 being OFF. The 3-wire serial interface
then becomes active on pins 15(CE), 16(DI) and 17(CL). The serial interface on the board
can be connected to a PC via the printer port or any other standard parallel port. The port
used can be selected through the software provided. The software supplied with this kit gives
the user access to all the possible features provided by the WM8778. The 3-wire latch, data
and clock lines may also be connected to the board via the test points TP12 (CE), TP9 (DI)
and TP10 (CL).
Please refer to the WM8778 datasheet for full details of the serial interface timing and all
register features.
latch
CE
CL
DI
B15
B14
B13
B12
B11
control register address
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
control register data bits
Figure 3 SPI Serial Interface
TWO-WIRE MODE
To operate the WM8778 in 2-wire mode, switch SW7 must be set to position 3, selection of
software mode will be indicated by D1 being OFF. Also LNK7 should be set to short positions
1-2, this is for the bi-directional direction of the control signal. The 2-wire serial interface
becomes active on pins 16(DI) and 17(CL). The serial interface on the board can be
connected to a PC via the printer port or any other standard parallel port. Note: a bidirectional parallel port is required for 2-wire operation1. The 2-wire data and clock lines
may also be connected to the board via the test points TP18 (DI) and TP4 (CL).
When used in 2-wire mode, the WM8778 has two possible addresses (0011010 [0x34h] or
0011011 [0x36h]) that are selectable by pulling CE low or high. If connecting a probe to the
Test Points it must be noted that the CE line is pulled high on the WM8778 evaluation board
selecting address 0011011. CE must be pulled low or driven low through the software writes
if address 0011010 is used (as is performed in the WM8778-EV1S software provided).
Figure 4 Two-Wire Serial Interface
1
Note: If the 2-wire mode is not reporting as expected then the most likely cause is that the parallel port being used is not
bi-directional. In most PC’s, the parallel port can be configured in the BIOS settings during initial power up.
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WM8778-EV1M
REGISTER MAP
REGISTER
ADDRESS (Bit
15 – 9)
Bit[8]
R3 (03h)
0000011
UPDATED
R4 (04h)
0000100
UPDATED
RDA[7:0]
R5 (05h)
0000101
UPDATED
MASTDA[7:0]
R6 (06h)
0000110
0
R7 (07h)
0000111
0
R8 (08h)
0001000
0
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
LDA[7:0]
0
0
0
0
PL[3:0]
0
0
0
0
R9 (09h)
0001001
0
0
0
R10 (0Ah)
0001010
0
0
0
R11 (0Bh)
0001011
ADCHPD
0
0
R12 (0Ch)
0001100
ADCMS
DACMS
0
R13 (0Dh)
0001101
0
R14 (0Eh)
0001110
ZCLA
R15 (0Fh)
0001111
ZCRA
R16 (10h)
0010000
R17 (11h)
0010001
LCEN
R18 (12h)
0010010
FDECAY
R19 (13h)
0010011
0
R20 (14h)
0010100
R21 (15h)
0010101
LRBOTH
MUTELA
R22 (16h)
0010110
0
0
R23 (17h)
0010111
0
0
0
IZD
ATC
DZCEN
0
0
0
DMUTE
PHASE[1:0]
0
DACWL[1:0]
ADCWL[1:0]
0
0
DACLRP
ADCBCP
ADCLRP
0
DEEMPH
DZFM[1:0]
DACBCP
DACFMT[1:0]
ADCFMT[1:0]
ADCOSR
DACRATE[2:0]
AINPD
0
TOD
ADCRATE[2:0]
DACPD
ADCPD
PDWN
0
NGAT
0
MXDAC
LAG[7:0]
RAG[7:0]
LCSEL[1:0]
MAXGAIN[2:0]
ALCZC
0
0
0
LCT[3:0]
0
0
HLD[3:0]
DCY[3:0]
ATK[3:0]
0
CHGPERZC[1:0]
NGTH[2:0]
TRANWIN[2:0]
MUTERA
MAXATTEN[3:0]
0
0
0
0
MXBYP
writing 000000000 to this register resets all registers to their default state
Table 11 Mapping of Program Registers
Please refer to the WM8778 datasheet for full details of the serial interface timing and all
register features.
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WM8778-EV1M
SERIAL INTERFACE SOFTWARE DESCRIPTION
The following section will detail the downloading and installation of evaluation software and
also the operation of the software and the functionality of each control button. Details the
main panel, hidden panels and details on the hardware setup required to use the main
functional buttons “DAC Setup”, “ADC Setup” and “Line Setup” will be provided.
SOFTWARE DOWNLOAD
The current evaluation board software should be downloaded from the Wolfson website
[www.wolfsonmicro.com].
From the homepage it is recommended that you do a search for ‘WM8778’ and select the
‘more’ button located under the ‘EVALUATION BOARDS’ heading. Select ‘DOWNLOAD’
from the right hand side of the screen under the ‘SOFTWARE’ heading. Once you have
accepted the licence agreement you can select the WM8778_EV1S_REVx.x.ZIP link and
download to your hard drive.
SOFTWARE INSTALLATION
Once the .zip file has been downloaded, to install the software:
•
Open the .zip file
•
Double click on the setup.exe file.
•
Follow the on-screen installation instructions and save to the desired location.
The software can then be opened by either running the extracted WM8778_EV1_REVx.x.exe
file from the saved location. Alternatively select: Start > Programs > WM8778-EV1S Revx.x >
WM8778-EV1S.
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WM8778-EV1M
SOFTWARE OPERATION
Due to the many features offered by the WM8778 the software has been split into 4 different
panels. This eases the complexity of the software making each panel less busy, the panels
have also been grouped so that it makes it simple to control each logical section of the
device.
The main menu panel shown in Figure 5 Software Menu Main Panel is used to call up the
other panels as well as offering a number of pull-down menus.
Figure 5 Software Menu Main Panel
SUBMIT ALL
The ‘Submit All’ button will submit the current panel settings, within each of the four main
panels to every register of the WM8778. This means changes within a number of different
panels can be made and then submitted at the same time using this button.
WM8778 RESET
The ‘Reset’ button writes to the reset register (R23) but does not reset the control panel
values. If the previous values are to be resubmitted then the ‘Submit All’ button should be
pressed.
RESET SOFTWARE PANEL SETTINGS
If the user would like to start afresh then the ‘Reset Software Panel Settings’ button should
also be pressed. Pressing this button does not write to the device, it only resets the panel
settings to their default state.
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WM8778-EV1M
WOLFSON LOGO
Left clicking on the Wolfson logo will open the PCs default web browser and go top the
Wolfson Microelectronics website (‘www.wolfsonmicro.com’).
On the main panel there are three buttons, “DAC Setup”, “ADC Setup” and “Line Setup”
which have been provided as a quick start approach. Pressing either of these buttons will
power up the DAC, ADC or Line signal paths in a known state as described in the following
pages.
Important: It must be noted that the CS8427 SPDIF decoder IC will only work at a rate of
256fs. This will limit the sample rates that may be set using the WM8778 unless an external
source is used supplying signals directly to the relevant pins of header H1 or taking the
signals from the relevant pins of header H2.
POWER MANAGEMENT CONTROL PANEL
Figure 6 Power and Interface Control
The Power Down and Interface Control panel is used to enable/disable the various sections
of the WM8778. It is also used to individually set the audio interface to the required data
format for both the ADC and DAC. Pressing the ‘Power Submit’ button will cause the settings
shown on this panel to be written to the WM8778. A full device register write is not sent using
the ‘Power Submit’ button.
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WM8778-EV1M
ADC, DAC AND OUTPUT CONTROL PANEL
Figure 7 ADC, DAC and Output Control
The ADC, DAC and Output Control panel is used to control the ADC, DAC and Output Mixer
related features of the WM8778. Pressing the ‘ADC, DAC and Output Submit’ button will
cause the settings shown on this panel to be written to the WM8778. A full device register
write is not sent using the ‘ADC, DAC and Output Submit’ button.
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WM8778-EV1M
VOLUME CONTROL PANEL
Figure 8 Volume Control
The Volume Control panel is used to control both analogue and digital volume settings of the
WM8778. The volume sliders update in ‘real’ time (i.e. the ‘Volume Submit’ button does not
have to be pressed to update the output volume level) but will only have an effect on the
output if the Volume Update bits are set. Once changes are made to the Volume Update bits
or any other settings excluding the volume sliders, the ‘Volume Submit’ button must be left
clicked for the change to take effect. Pressing the ‘Volume Submit’ button will cause the
settings shown on this panel to be written to the WM8778. A full device register write is not
sent using the ‘Volume Submit’ button.
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WM8778-EV1M
LIMITER/ALC CONTROL PANEL
Figure 9 Limiter/ALC Control
The Limiter/ALC Control panel is used to control the many options offered by the WM8778
for either ALC (Automatic Level Control) or Limiter operation. The default of the WM8778 is
for the operation to be disabled, this must firstly be enabled and then the correct limiter or
ALC function selected. Controls specific to ALC or limiter are dimmed and not controllable
depending on the operation selected. The following control sliders update in ‘real’ time’:
Maximum Gain of PGA, Noise Gate Threshold and Limiter Threshold/ALC Target Level (i.e.
the ‘Limiter/ALC Submit’ button does not have to be pressed to update these settings).
Pressing the ‘Limiter/ALC Submit’ button will cause the settings shown on this panel to be
written to the WM8778. A full device register write is not sent using the ‘Limiter/ALC Submit’
button.
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WM8778-EV1M
DAC SETUP
By pressing the ‘DAC Setup’ button, the software writes to the device setting the SPDIF_IN
through DAC to the VOUTL/R outputs; active in 24-bit, I2S input data format. Table 12 lists
the required board settings to allow this signal path to become active. This is to ease the
initial use of the WM8778 hardware and software until the user becomes familiar with both
device and software operation.
+5v
DGND
DVDD
+2.7V
to
+3.6V
J1
J2
J3
SPDIF_
OUT
AVDD
+2.7V
to
+5.5V
AGND
J4
J5
-12v
+12v
J23
J22
OPEN
0
SW1
1
2
3
4
5
6
1
1
OPT
_IN
SW3
J8
SW2
AINR
1
H1
1
SW4
J9
1
1
SPDIF_
IN
J11
H2
AINL
H3
H4
1
J12
1
LNK3
1
SW7
LNK5
1
1
1
1
J16
1
1
1
PARALLEL PORT
J14
1
1
UNFILT_
VOUTR
J17
LNK6
LNK7 LNK4
SW6
SW5
UNFILT_
VOUTL
VOUTL
VOUTR
Figure 10 Recommended DAC setup
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19
WM8778-EV1M
LINKS AND
JUMPERS
LINK / JUMPER /
SWITCH POSITION
DESCRIPTION
H1
Fit jumpers (1,2)
(5,6) (9,10) (13,14)
DAC clocks
H2
No jumpers
ADC Clocks
J8
OPEN
DAC Slave Mode
J9 (BCLK)
OPEN
DAC uses BCLK, no common BCLK for ADC
J11 (LRC)
OPEN
DAC uses LRCLK, no common LRCLK for ADC
J12
OPEN
ADC Slave Mode
J14 (MCLK)
OPEN
DAC uses MCLK, no common MCLK for ADC
J16 and J17
OPEN
Output Signals are AC Coupled
SW1
1
1
2
0
3
0
4
1
5
0
6
0
DATA FORMAT
I2S Compatible
SW3
POS 1
Active anti-alias input filter selected
SW4
POS 1
Active anti-alias input filter selected
SW5
Pins 2 and 3
SHORT
Filtered Output
SW6
Pins 2 and 3
SHORT
Filtered Output
SW7
POS 1
Software 3 Wire Mode Selected
LNK3
Pins 1 and 2
SHORT
DVDD Supply for S/W and mode control
LNK4
Pins 1 and 2
SHORT
24 Bit
LNK5
Pins 1 and 2
SHORT
I S Format
LNK6
Pins 2 and 3
SHORT
DEEMPH OFF
LNK7
Pins 2 and 3
SHORT
Hardware Mode DI Direction
2
Table 12 DAC Setup Jumper Settings (Slave Mode)
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Rev 1.1, February 2004
20
WM8778-EV1M
ADC SETUP
By pressing the ‘ADC Setup’ button, the software writes to the device setting the AINL/R
through ADC to SPDIF_OUT path active. As with the DAC setup described previously, this is
to ease the initial use of the WM8778 until the user becomes familiar with both device and
software operation. It should be noted that the SPDIF_IN connection is still required to
2
provide the necessary clocks to the WM8778 I S interface in this mode.
+5v
DGND
DVDD
+2.7V
to
+3.6V
J1
J2
J3
SPDIF_
OUT
AGND
J4
J5
-12v
+12v
J23
J22
OPEN
0
SW1
1
2
3
4
5
6
1
1
OPT
_IN
SW3
J8
SW2
AINR
1
H1
1
SW4
J9
1
SPDIF_
IN
1
The SPDIF input is
required to provide
clocks for the
WM8778 audio
interface.
AVDD
+2.7V
to
+5.5V
J11
H2
AINL
H3
H4
1
J12
1
LNK3
1
SW7
LNK5
1
1
1
1
J16
1
1
1
PARALLEL PORT
J14
1
1
UNFILT_
VOUTR
J17
LNK6
LNK7 LNK4
SW6
SW5
UNFILT_
VOUTL
VOUTL
VOUTR
Figure 11 Recommended ADC setup
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WM8778-EV1M
LINKS AND
JUMPERS
LINK / JUMPER /
SWITCH POSITION
DESCRIPTION
H1
Fit Jumpers (5,6)
(9,10) (13,14)
DAC clocks for ADC (Using J9, J11 and J14)
H2
Fit jumpers (1,2)
(5,6) (9,10)
ADC Clocks and data to Crystal
J8
OPEN
DAC Slave Mode
J9 (BCLK)
SHORT
Common BCLK for ADC
J11 (LRC)
SHORT
Common LRCLK for ADC
J12
OPEN
ADC Slave Mode
J14 (MCLK)
SHORT
Common MCLK for ADC
J16 and J17
OPEN
Output Signals are AC Coupled
SW1
1
1
2
0
3
0
4
1
5
0
6
0
DATA FORMAT
I2S Compatible
SW3
POS 1
SW4
POS 1
Active anti-alias input filter selected
Active anti-alias input filter selected
SW5
Pins 2 and 3
SHORT
Filtered Output
SW6
Pins 2 and 3
SHORT
Filtered Output
SW7
POS 1
Software 3 Wire Mode Selected
LNK3
Pins 1 and 2
SHORT
DVDD Supply for S/W and mode control
LNK4
Pins 1 and 2
SHORT
24 Bit (N/A)
LNK5
Pins 1 and 2
SHORT
I S Format (N/A)
LNK6
Pins 2 and 3
SHORT
DEEMPH OFF (N/A)
LNK7
Pins 2 and 3
SHORT
Hardware Mode DI Direction
2
Table 13 ADC Setup Jumper Setup (Slave Mode)
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Rev 1.1, February 2004
22
WM8778-EV1M
LINE SETUP
By pressing the ‘Line Setup’ button, the software writes to the device setting the AINL/R
through the analogue path to the VOUTL/R outputs. As with the previous configurations, this
is to ease the initial use of the WM8778 until the user becomes familiar with both device and
software operation.
Note: The WM8778 does not require an MCLK to operate in this mode. If the ADC or DAC
are used then the MCLK would be required.
+5v
DGND
DVDD
+2.7V
to
+3.6V
J1
J2
J3
SPDIF_
OUT
AVDD
+2.7V
to
+5.5V
AGND
J4
J5
-12v
+12v
J23
J22
OPEN
0
SW1
1
2
3
4
5
6
1
1
OPT
_IN
SW3
J8
SW2
AINR
1
H1
1
SW4
J9
1
1
SPDIF_
IN
J11
H2
AINL
H3
H4
1
J12
1
LNK3
1
SW7
LNK5
1
1
1
1
J16
1
1
1
PARALLEL PORT
J14
1
1
UNFILT_
VOUTR
J17
LNK6
LNK7 LNK4
SW6
SW5
UNFILT_
VOUTL
VOUTL
VOUTR
Figure 12 Recommended Line setup
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Rev 1.1, February 2004
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WM8778-EV1M
LINKS AND
JUMPERS
LINK / JUMPER /
SWITCH POSITION
DESCRIPTION
H1
No Jumpers
DAC clocks and data
H2
No Jumpers
ADC clocks and data
J8
OPEN
DAC Slave Mode
J9 (BCLK)
OPEN
Common BCLK for ADC
J11 (LRC)
OPEN
Common LRCLK for ADC
J12
OPEN
ADC Slave Mode
J14 (MCLK)
OPEN
Common MCLK for ADC
J16 and J17
OPEN
Output Signals are AC Coupled
SW1
1
1
2
0
3
0
4
1
5
0
6
0
DATA FORMAT
I2S Compatible
SW3
POS 1
SW4
POS 1
Active anti-alias input filter selected
Active anti-alias input filter selected
SW5
Pins 2 and 3
SHORT
Filtered Output
SW6
Pins 2 and 3
SHORT
Filtered Output
SW7
POS 1
Software 3 Wire Mode Selected
LNK3
Pins 1 and 2
SHORT
DVDD Supply for S/W and mode control
LNK4
Pins 1 and 2
SHORT
24 Bit
LNK5
Pins 1 and 2
SHORT
I2S Format
LNK6
Pins 2 and 3
SHORT
DEEMPH OFF
LNK7
Pins 2 and 3
SHORT
Hardware Mode DI Direction
Table 14 Line Setup Jumper Setup (Slave Mode)
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24
WM8778-EV1M
SCHEMATIC LAYOUT
Figure 13 Functional Diagram
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Rev 1.1, February 2004
25
WM8778-EV1M
Figure 14 Digital Input
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Rev 1.1, February 2004
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WM8778-EV1M
Figure 15 Software Control
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Rev 1.1, February 2004
27
WM8778-EV1M
Figure 16 Level Shift
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Rev 1.1, February 2004
28
WM8778-EV1M
Figure 17 Analogue Input and Output Mute
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Rev 1.1, February 2004
29
WM8778-EV1M
Figure 18 WM8778
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Rev 1.1, February 2004
30
WM8778-EV1M
Figure 19 Analogue Output
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WM8778-EV1M
Figure 20 Power
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32
WM8778-EV1M
WM8778-EV1B PCB LAYOUT
Figure 21 Top Layer Silkscreen
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33
WM8778-EV1M
Figure 22 Top Layer
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Rev 1.1, February 2004
34
WM8778-EV1M
Figure 23 Bottom Layer
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Rev 1.1, February 2004
35
WM8778-EV1M
Figure 24 Bottom Layer Silkscreen
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Rev 1.1, February 2004
36
WM8778-EV1M
WM8778-EV1B BILL OF MATERIAL
DESCRIPTION
0.1uF 0805 SMD Ceramic Capacitor 50V X7R
0.1uF 0603 SMD Ceramic Capacitor 16V X7R
REFERENCE DESIGNATOR
C1, C4, C5, C7, C8, C10, C13, C20, C23, C28, C30,
C32, C35, C42, C44, C45, C47, C49, C50, C51,
C52, C54, C55, C59, C60, C63, C66, C67, C71,
C72, C75
C11, C14
QTY
31
0.01uF 0805 SMD Ceramic Capacitor 50V X7R
C12
4.7nF 0603 SMD Ceramic Capacitor 50V X7R
C15, C18, C29
3
10uF 6.3 Dia 2.5 pitch Oscon Through Hole Cap. 25V 20%
C2, C3, C6, C39, C41, C46, C53, C57, C73, C74
10
820pF 0805 SMD Ceramic Capacitor 50V NPO
C21, C33
2
180pF 0805 SMD Ceramic Capacitor 50V NPO
C22, C34
2
220pF 0805 SMD Ceramic Capacitor 50V X7R
C27, C43
2
10uF 6.3 Dia 2.5 pitch Oscon Through Hole Cap. 16V 20%
C36, C37, C61, C62
4
100uF 8 Dia 3.5 pitch Oscon Through Hole Cap. 10V 20%
C48
1
220pF 0805 SMD Ceramic Capacitor 50V NPO
C58, C70, C76, C77
4
1nF 0805 SMD Ceramic Capacitor 50V NPO
C64, C69
2
680pF 0805 SMD Ceramic Capacitor 50V NPO
C65, C68
2
330uF M Series 10 Dia 5 pitch Through Hole Cap. 35V 20%
C78
1
10uF 10V SMD Tantalum Capacitor case A
C9
1
HSMY-C670 0805 SMD Chip LED YELLOW
D1
1
2x8 2.54mm pitch PCB Pin Header VERTICAL
H1, H2
2
1x14 2.54mm pitch PCB Pin Header VERTICAL
H3, H4
2
4mm Non-Insulated Panel Socket 16A
J1, J2, J3, J4, J5, J22, J23
7
Phono Socket PCB mount RED
J10, J15, J20
3
Phono Socket PCB mount WHITE
J13, J19, J21
3
36-way Centronics/IEE488 PCB mountable Connector
J18
1
2
1
Phono Socket PCB mount BLACK
J6
1
Phono Socket PCB mount YELLOW
J7
1
1x2 PCB Pin Header 0.1" VERTICAL
J8, J9, J11, J12, J14, J16, J17, LNK1, LNK2
9
0R 1206 Resistor on 1210 Inductor site
L1, L2, L3, L7, L8
5
47uH 1210 Surface Mount Inductor 'PA series'
L5
1
3.3uH 1210 Surface Mount Inductor '1210A series'
L6
1
JSK9-16-G0 PCB 1x3 Jumper Switch 0.1" Center-off
VERTICAL
LNK3, LNK4, LNK5, LNK6, LNK7, SW5, SW6
7
TN0200T N- Channel MOSFET SOT23
Q1, Q2, Q3
3
FMMT617 NPN Switching Transistor SOT23
Q4, Q5
2
MMBT3906 PNP Bipolar Transistor SOT23
Q6, Q7
2
680R 0805 SMD chip resistor 1% 0.1W
R10, R20, R26, R36
4
1K2 0805 SMD chip resistor 1% 0.1W
R11, R52, R58, R63
4
10K 0805 SMD chip resistor 1% 0.1W
R12, R13, R39, R40, R41, R42, R43, R45, R51,
R61, R62, R70, R71, R72, R79, R80
16
33R 0805 SMD chip resistor 1% 0.1W
R15, R19, R21, R22, R28, R31, R32, R34, R46, R48
10
8K2 0805 SMD chip resistor 1% 0.1W
R16, R17, R23, R29, R30, R35
6
0R 0805 SMD chip resistor 1% 0.1W
R2, R47, R49, R50, R55, R56, R59, R66, R81, R85
10
47k 1206 SMD chip 4 resistor array 5% 0.063W
R4, R5, R6
3
4K7 0805 SMD chip resistor 1% 0.1W
R53, R60, R67, R73, R75, R76, R77
7
560R 0805 SMD chip resistor 1% 0.1W
R54
1
1K8 0805 SMD chip resistor 1% 0.1W
R64, R65
2
7K5 0805 SMD chip resistor 1% 0.125W
R68, R69
2
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Rev 1.1, February 2004
37
WM8778-EV1M
DESCRIPTION
620R 0805 SMD chip resistor 1% 0.1W
REFERENCE DESIGNATOR
QTY
1
R7
49R9 0805 SMD chip resistor 1% 0.125W
R74,R78
2
100K 0805 SMD chip resistor 1% 0.1W
R8, R14, R25
3
3K 0805 SMD chip resistor 1% 0.1W
R82
1
1K 0805 SMD chip resistor 1% 0.1W
R83
1
75R 0805 SMD chip resistor 1% 0.125W
R9
1
Slotted Panhead Screw - M3 thread; 12mm long
SC1, SC2, SC3, SC4, SC6
5
Hexagonal brass M3 size spacer 20mm length
SPR1, SPR2, SPR3, SPR4, SPR6
5
DIL Switch 6-Way Rocker
SW1
1
B3F1000 SPNO PCB mount switch
SW2
1
DP2P PCB mount vertical slide switch
SW3, SW4, SW7
3
1.32mm PCB Test Terminal BLACK
10
1.32mm PCB Test Terminal RED
TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP11,
TP13
TP9, TP10, TP12
2:1 Ratio 96KHz SPDIF Digital Audio transformer SOIC
U1
1
DS1813 5V active Low Power-On-Reset chip SOT
U2
1
TORX176 Digirtal Audio Optical Receiver
U3
1
CS8427 96KHz Audio Transceiver
U4
1
74ALVC164245 16 Bit Dual Supply Bus Transceiver SSO
U5, U8
2
3
MC33078 Low Noise Dual Op-Amp SO
U6, U10
2
WM8778 24-bit 192kHz Stereo Codec
U7
1
74HCT157 Quad 2-Input Mux SO
U9
1
Plain M3 size washer
WSH1, WSH2, WSH3, WSH4, WSH6
5
Table 15 WM8778-EV1M Bill of Materials
1
Note: The audio transformer used on this board is manufactured by Scientific Conversion
Inc. (www.scientificonversion.com).
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Rev 1.1, February 2004
38
WM8778-EV1M
APPENDIX
DAC AND ADC ALTERNATIVE AUDIO INTERFACE CONFIGURATION
The DAC and ADC have separate left/right clocks, bit clocks, master clocks and data I/O’s.
The audio interface for each may be configured independently to operate as master or slave.
In slave mode ADCLRC, DACLRC, ADCBCLK and DACBCLK are all inputs. In master mode
ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs.
Previous configuration details (ADC, DAC and Line setup) have configured the WM8778 for
slave mode. Also the clocks for the audio interface have been generated from the SPDIF
crystal and for operation of the ADC common MCLK (short J9), LRC (short J16) and BCLK
(short J15) clocks were used. The following information details the configuration of the DAC
and ADC for master mode and also the configuration for independent DAC and ADC audio
interface.
MASTER/SLAVE MODE
The WM8778-EV1B has the ability to configure the WM8778 for independent DAC and ADC
in either master or slave mode. This means that there are four configurable options, the
following tables detail the recommended jumper settings to configure the audio interfaces for
the specified operation.
1. DAC and ADC = Slave. This configuration has been detailed during the software operation
explanation.
2. DAC and ADC = Master. The following switch and jumper settings should be made.
LINKS AND
JUMPERS
DESCRIPTION
H1
Fit Jumpers (1,2) (5,6)
(9,10) (13,14)
DAC clocks and data
H2
Fit jumpers (1,2) (5,6)
(9,10)
ADC Clocks and data
J8
SHORT
DAC Master Mode (Level Shift Direction)
J9 (BCLK)
OPEN
Separate BCLK
J11 (LRC)
OPEN
Separate LRCLK
J12
SHORT
ADC Master Mode (Level Shift Direction)
J14 (MCLK)
SHORT
Link MCLK (DAC MCLK to ADC)
SW1
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LINK / JUMPER /
SWITCH POSITION
1
0
2
0
3
0
4
1
5
0
6
0
DATA FORMAT
I2S Compatible
Rev 1.1, February 2004
39
WM8778-EV1M
3. DAC = Master ADC = Slave. The following switch and jumper settings should be made.
LINKS AND
JUMPERS
LINK / JUMPER /
SWITCH POSITION
DESCRIPTION
H1
Fit Jumpers (1,2) (5,6)
(9,10) (13,14)
DAC clocks and data
H2
Fit jumpers (1,2) (5,6)
(9,10)
ADC Clocks and data
J8
SHORT
DAC Master Mode (Level Shift Direction)
J9 (BCLK)
SHORT
Common BCLK from DAC
J11 (LRC)
SHORT
Common LRCLK from DAC
J12
OPEN
ADC Slave Mode (Level Shift Direction)
J14 (MCLK)
SHORT
Link MCLK (DAC MCLK to ADC)
SW1
1
0
2
0
3
0
4
1
5
0
6
0
DATA FORMAT
I2S Compatible
4. DAC = Slave ADC = Master. The following switch and jumper settings should be made.
LINKS AND
JUMPERS
LINK / JUMPER /
SWITCH POSITION
DESCRIPTION
H1
Fit Jumpers (1,2) (5,6)
(9,10) (13,14)
DAC clocks and data
H2
Fit jumpers (1,2) (5,6)
(9,10)
ADC Clocks and data
J8
OPEN
DAC Slave Mode (Level Shift Direction)
J9 (BCLK)
SHORT
Common BCLK from ADC
J11 (LRC)
SHORT
common LRCLK from ADC
J12
SHORT
ADC Master Mode (Level Shift Direction)
J14 (MCLK)
SHORT
Link MCLK (DAC MCLK to ADC)
SW1
1
1
2
0
3
0
4
1
5
0
6
0
DATA FORMAT
2
I S Compatible
Notes:
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1.
The WM8778-EV1B does not have the functionality to create a separate ADCMCLK.
There are two options for the ADCMCLK. One is to use the common DACMCLK by
fitting J9, as suggested in table above. The other is to apply an external MCLK to H2/13
and the ground to pin H2/15.
2.
When the WM8778 is configured for master mode the I2S interface to the SPDIF crystal
(U4) will only operate in slave mode.
3.
Software configuration of the WM8778 for master and slave mode can be found within
the “Power Down and General Audio” panel. It should be noted that the SPDIF crystal
(U4) has an MCLK output which is fixed at 256x the sample rate (Fs).
Rev 1.1, February 2004
40
WM8778-EV1M
EXTERNAL DSP CONNECTION TO THE WM8778-EV1B
The WM8778-EV1B evaluation board has been designed to allow it to be easily connected to
an external DSP platform with error free operation.
The following information is provided to ease the connection process and ensure that all
signals sent and received by the WM8778-EV1B are reliable and at the correct voltage
levels.
AUDIO INTERFACE CONNECTIONS
It is recommended that twisted pair (signal twisted with GND) or shielded wires are used to
make the audio interface connections between the DSP and WM8778-EV1B platforms. This
is to ensure that no interference or noise is picked up by the clocks or data lines, thus
reducing performance and reliability.
When the WM8778 is set in Slave Mode (both DAC and ADC), the jumpers on header H1
should be removed, disconnecting the digital input section of the evaluation board. The
audio interface timing and data signals from the DSP platform should then be connected as
shown in Figure 25 Connections from DSP Platform. The signals should be connected to H1
and not on the header strip H3 running up each side of the device. Connecting the signals on
the output side of the level-shift IC (U5) will cause drive contention between U5 and the DSP
and could result in damage to either or both devices. In most cases, the DSP supplies will be
set around 3V for low power portable applications. The inputs to the level-shift IC
(74ALVC164245) have a TTL threshold (i.e. Logic High = +2V(min); Logic Low = +0.8V(max))
and low input current requirements (i.e. 15uA max) allowing most DSP's to connect directly.
Figure 25 Connections from DSP Platform
The digital inputs to the WM8778 have a CMOS threshold (i.e. Logic High (min) = DVDDx0.7;
Logic Low (max) = DVDDx0.3). These are met directly by the level shift IC outputs.
The jumpers on H2 should also be removed, disconnecting the digital output section (ADC)
of the WM8778 evaluation board. The DOUT data from the WM8778 should then be
connected to the DSP via pin 10 of header strip H3 and the GND connection should be taken
from pin 12 of header strip H3.
The DOUT signal should be taken direct from the WM8778 digital output (H3) as the output
side of the level-shift IC (U5) from the WM8778 is pulled up to +5V which may overdrive and
cause damage to the DSP inputs. The digital output levels of the WM8778 are Logic High
(min) = DVDDx0.9; Logic Low (max) = DVDDx0.1 which should meet the input level
requirements of most DSPs running at +3V supplies. If the DSP is running with +5V supplies
then the connections to it should be made from the output side of the level-shift IC (U5),
connecting the signals as shown in Figure 26 Data Connection to the DSP Platform (+5V
tolerant input levels).
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Rev 1.1, February 2004
41
WM8778-EV1M
Figure 26 Data Connection to the DSP Platform (+5V tolerant input levels)
The connection in Figure 26 is applicable when links J9, J11 and J14 are fitted for common
DAC and ADC MCLK, BCLK and LRC clocks. If separate ADC clocks are required then
remove links J9, J11 and J14 and connect the separate clocks as shown in Figure 27. The
ADC data can then be connected to the point relevant for the DSP power supply, either H2
(5v tolerant) or H3 (direct to device).
GND
ADCMCLK
GND
ADCBCLK
GND
ADCLRC
H2
Figure 27 Connections to DSP Platform
When the WM8778 is set to Master mode (DAC and ADC), the jumpers on header H1
should be removed, disconnecting the digital input section of the evaluation board. If an
external MCLK signal is being used (i.e. supplied by the DSP) then the DSP platform should
be connected as shown in Figure 28 for MCLK and DIN. The signals should be connected to
H1 and not on the header strip H3 running up the side of the device. Connecting the signals
on the output side of the level-shift IC (U5) will cause drive contention between U5 and the
DSP and could result in damage to either or both devices. In most cases, the DSP supplies
will be set around +3V for low power portable applications. The inputs to the level-shift IC
(74ALVC164245) have a TTL threshold (i.e. Logic High = +2V(min); Logic Low = +0.8V(max))
and low input current requirements (i.e. 15uA max) allowing most DSPs to connect directly.
Figure 28 Timing Connections from DSP Platform
The digital inputs to the WM8778 have a CMOS threshold (i.e. Logic High (min) = DVDDx0.7;
Logic Low (max) = DVDDx0.3). These are met directly by the level shift IC outputs.
The DACBCLK and DACLRC signals can then be connected directly to the device on header
H3 pin 4 and pin 7 respectively.
The jumpers on H2 should also be removed, disconnecting the digital output section of the
WM8778 evaluation board.
The DOUT, ADCBCLK and ADCLRC signals should be taken direct from the WM8778 digital
output as the output side of the level-shift IC (U4) from the WM8778 is pulled up to +5V
which may overdrive and cause damage to the DSP inputs. The digital output levels of the
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WM8778-EV1M
WM8778 are Logic High (min) = DVDDx0.9; Logic Low (max) = DVDDx0.1 which should
meet the input level requirements of most DSPs running at +3V supplies. If the DSP is
running with +5V supplies (and +5V tolerant inputs) then the connections from the WM8778
evaluation board to the DSP should be made from H2 on the output side of the level-shift IC
from the WM8778 as shown in Figure 27. The ADCMCLK is only required as an input if a
separate MCLK is required. For a common MCLK then by fitting link J14 the DACMCLK will
be used.
If the DAC and ADC wish to be configured as separate master and slave then the details for
separate operation for either master or slave previous should be followed. Care should be
taken when connecting an external DSP to ensure that signal levels and device drive
direction (DSP, WM8778 or level shift) are configured correctly to save component damage.
This will ensure that the DSP input level specifications are met.
SOFTWARE INTERFACE
When using the WM8778-EV1B evaluation board with a DSP platform, the registers may be
set using the supplied software with a PC and parallel port cable as shown in Figure 29. The
example shown is for ADC and DAC in slave mode, interface connections to the board
depends on independent configuration for master or slave.
If the DSP is being used to write to the WM8778 registers as well as supplying/receiving the
audio interface timing and data signals, then it is recommended that twisted pair or shielded
wires are used to connect the DSP platform to the WM8778-EV1B. A direct connection can
be made to pin 1 (CE), pin 2 (DI) and pin 3 (CL) of header strip H4 for 3-wire software mode
as shown in Figure 30. This is applicable to a DSP with either 3v or 5v tolerant thresholds as
the software pins have 5v thresholds.
The same connections apply for controlling the WM8778 via 2-wire software mode (i.e. only
pin 2 (DI) and pin 3 (CL) of header strip H4 are used). Pin 1 (CE) can be pulled low on the
board if device address 0011010 [0x34h] is required or pulled high address 0011011 [0x36h]
is required.
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WM8778-EV1M
CONNECTION DIAGRAMS
Software
Control
WM8778-EV1B
DSP
Platform
Audio
Interface
H1
H3
H4
Figure 29 DSP Connection with PC Control using Wolfson Software
WM8778-EV1B
DSP
Platform
Audio
Interface
H1
H3
H4
DSP
Software Control
Figure 30 Full DSP Control
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WM8778-EV1M
ADDITIONAL WM8778-EV1B SETUP RECOMMENDATIONS
ADC TO DAC LOOPBACK
Setting the WM8778-EV1 into loopback mode allows an analogue signal to be applied to
AINL/R, passed through the ADC, looped into the DAC and output on the VOUTL/R outputs.
+5v
DGND
DVDD
+2.7V
to
+3.6V
J1
J2
J3
SPDIF_
OUT
AGND
J4
J5
-12v
+12v
J23
J22
OPEN
0
SW1
1
2
3
4
5
6
1
1
OPT
_IN
SW3
J8
SW2
AINR
1
H1
1
SW4
J9
1
SPDIF_
IN
1
The SPDIF input is
required to provide
clocks for the
WM8778 audio
interface.
AVDD
+2.7V
to
+5.5V
J11
H2
AINL
H3
H4
1
J12
1
LNK3
1
SW7
LNK5
1
1
1
1
J16
1
1
1
PARALLEL PORT
J14
1
1
UNFILT_
VOUTR
J17
LNK6
LNK7 LNK4
SW6
SW5
UNFILT_
VOUTL
VOUTL
VOUTR
Figure 31 Recommended ADC to DAC Loopback Setup
Note: Pin 2 of H1 (DIN) MUST be linked to pin 9 of H2 (DOUT). A digital input must also be
applied to U3 or J7 (SPDIF_IN) so that the correct clocks are supplied to the WM8778.
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WM8778-EV1M
LINKS AND
JUMPERS
LINK / JUMPER /
SWITCH POSITION
DESCRIPTION
H1
Fit jumpers (5,6)
(9,10) (13,14)
DAC clocks
H2
No jumpers
ADC Clocks
J8
OPEN
DAC Slave Mode
J9 (BCLK)
SHORT
Common BCLK
J11 (LRC)
SHORT
Common LRCLK
J12
OPEN
ADC Slave Mode
J14 (MCLK)
SHORT
Common MCLK
J16 and J17
OPEN
Output Signals are AC Coupled
SW1
1
1
2
0
3
0
4
1
5
0
6
0
DATA FORMAT
I2S Compatible
SW3
POS 1
SW4
POS 1
Active anti-alias input filter selected
Active anti-alias input filter selected
SW5
Pins 2 and 3
SHORT
Filtered Output
SW6
Pins 2 and 3
SHORT
Filtered Output
SW7
POS 1
Software 3 Wire Mode Selected
LNK3
Pins 1 and 2
SHORT
DVDD Supply for S/W and mode control
LNK4
Pins 1 and 2
SHORT
24 Bit
LNK5
Pins 1 and 2
SHORT
I2S Format
LNK6
Pins 2 and 3
SHORT
DEEMPH OFF
LNK7
Pins 2 and 3
SHORT
Hardware Mode DI Direction
Table 16 Loopback Setup Jumper Settings (Slave Mode)
Software Setup:
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1.
Press the ‘WM8778 Reset’ button. This ensures device is default.
2.
Press the ‘Reset Software Panel Settings’ button. This ensures panel buttons are set to
default.
3.
The ADC to DAC loopback path should function when the default register settings are
used.
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WM8778-EV1M
EVALUATION SUPPORT
The aim of this evaluation kit is to help you to become familiar with the functionality and
performance of the WM8778 CODEC.
If you require more information or require technical support please contact Wolfson
Microelectronics Applications group through the following channels:
Email:
[email protected]
Telephone Apps:
+44 (0)131 272 7070
Fax:
+44 (0)131 272 7001
Mail:
Applications Department at address on last page.
or contact your local Wolfson representative.
Additional information may be made available from time to time on our web site at
http://www.wolfsonmicro.com
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WM8778-EV1M
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
20 Bernard Terrace
Edinburgh
EH8 9NX
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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