DATASHEET 9DB106 Six Output Differential Buffer for PCIe Gen 2 Description Features/Benefits The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications. • • • • • CLKREQ# pin for outputs 1 and 4/ supports Express Card applications PLL or bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Recommended Applications 6 Output Differential Buffer for PCIe Gen 2 Key Specifications Output Features • • • Cycle-to-cycle jitter < 50ps Output-to-output skew < 50 ps 6 - 0.7V current mode differential output pairs (HCSL) Functional Block Diagram CLKREQ1# CLKREQ4# PCIEX1 CLK_INT C LK_INC SPREAD COMPATIBLE PLL PCIEX4 PCIEX(0,2,3,5) PLL_BW SMBDAT CONTROL LOGIC SMBCLK IREF IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 1 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 PLL_BW CLK_INT CLK_INC vCLKREQ1# PCIEXT0 PCIEXC0 VDD GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 9DB106 Pin Configuration 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDA GNDA IREF vCLKR EQ4# PCIEXT5 PCIEXC5 VDD GND PCIEXT4 PCIEXC4 PCIEXT3 PCIEXC3 VDD SMBCLK Note:Pins preceeded by ' v ' have internal 120K ohm pull down resistors 28-pin SSOP & TSSOP Power Groups Pin Number VDD GND 7, 13, 16, 22 8,21 TBD TBD N/A 27 28 27 Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 2 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 Pin Description PIN # PIN NAME PIN TYPE 1 PLL_BW IN 2 3 CLK_INT CLK_INC IN IN 4 vCLKREQ1# IN 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PCIEXT0 PCIEXC0 VDD GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 VDD SMBDAT SMBCLK VDD PCIEXC3 PCIEXT3 PCIEXC4 PCIEXT4 GND VDD PCIEXC5 PCIEXT5 25 vCLKREQ4# OUT OUT PWR IN OUT OUT OUT OUT PWR I/O IN PWR OUT OUT OUT OUT PWR PWR OUT OUT IN DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high True Input for differential reference clock. Complementary Input for differential reference clock. Output enable for PCI Express output pair 1. 0 = enabled, 1 =disabled True clock of differential PCI_Express pair. Complementary clock of differential PCI_Express pair. Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complementary clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complementary clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complementary clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complementary clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Complementary clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Output enable for PCI Express output pair 4. 0 = enabled, 1 =disabled 26 IREF OUT This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. 27 28 GNDA VDDA PWR PWR Ground pin for the PLL core. 3.3V power for the PLL core. Note: Pins preceeded by ' v ' have internal 120K ohm pull down resistors IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 3 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 Electrical Characteristics - Absolute Maximum Ratings 1 2 PARAMETER SYMBOL 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Input High Voltage VDDA VDD VIL VIH VIHSMB Storage Temperature Junction Temperature Input ESD protection Ts Tj ESD prot CONDITIONS MIN TYP MAX 4.6 4.6 GND-0.5 Except for SMBus interface SMBus clock and data pins VDD+0.5V 5.5V -65 Human Body Model 150 125 2000 UNITS NOTES V V V V V 1,2 1,2 1 1 1 1 1 1 ° C °C V Guaranteed by design and characterization, not 100% tested in production. Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Input/Supply/Common Output Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Ambient Operating Temperature TCOM TIND Commmercial range Industrial range 0 -40 70 85 °C °C 1 1 Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1,2 Input Low Voltage Input High Current VIL I IH 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all differential pairs tri-stated VDD = 3.3 V VSS - 0.3 -5 0.8 5 V uA 1,2 1,2 -5 uA 1,2 -200 uA 1,2 150 40 105 7 5 4.5 mA mA MHz nH pF pF 1 1 1 1 1 1.8 ms 1 30 33 kHz 1 2.7 5.5 0.4 V V 1 1 mA 1 1000 ns 1 300 ns 1 9DB106 REV K 04/20/11 IIL1 Input Low Current IIL2 Operating Supply Current I DD3.3OP Input Frequency Pin Inductance Fi Lpin CIN COUT Input Capacitance Clk Stabilization Input Spread Spectrum Modulation Frequency SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time 1 2 TSTAB VDD VOL 130 30 80 Logic Inputs Output pin capacitance From VDD reaching 3.1V and input clock stable Triangular Modulation @ IPULLUP I PULLUP TRI2C TFI2C TYP 100 MAX 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) UNITS Notes Guaranteed by design and characterization, not 100% tested in production. Except differential input clock IDT® Six Output Differential Buffer for PCIe Gen 2 4 9DB106 Six Output Differential Buffer for PCIe Gen 2 Electrical Characteristics - Clock Input Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Input High Voltage DIF_IN Input Low Voltage DIF_IN Input Common Mode Voltage - DIF_IN CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) VIHDIF VILDIF MIN TYP MAX UNITS NOTES 600 800 1150 mV 1 VSS - 300 0 300 mV 1 VCOM Common Mode Input Voltage 300 1000 mV 1 Input Amplitude - DIF_IN VSWING Peak to Peak value 300 1450 mV 1 Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2 Input Leakage Current I IN -5 5 uA 1 Input Duty Cycle dtin VIN = VDD , VIN = GND Measurement from differential wavefrom 45 55 % 1 Input Jitter - Cycle to Cycle J DIFIn 0 125 ps 1 1 2 Differential Measurement Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics - PLL Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% Group Parameter Description Min Typ Max Units Notes PLL Jitter Peaking jpeak-hibw (PLL_BW = 1) 0 1 2.5 dB 1,4 PLL Jitter Peaking jpeak-lobw (PLL_BW = 0) 0 1 2 dB 1,4 PLL Bandwidth PLL Bandwidth pllHIBW pllLOBW (PLL_BW = 1) (PLL_BW = 0) PCIe Gen 1 phase jitter (1.5 - 22 MHz) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=1) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=0) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz 2 0.4 2.5 0.5 3 1 MHz MHz 1,5 1,5 40 108 ps 1,2,3 2.7 3.1 ps rms 1,2,3 2.2 3.1 ps rms 1,2,3 1.3 3 ps rms 1,2,3 Jitter, Phase tjphasePLL NOTES: 1. Guaranteed by design and characterization, not 100% tested in production. 2. See http://www.pcisig.com for complete specs 3. Device driven by 932S421BGLF or equivalent 4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking. 5. Measured at 3 db dow n or half pow er point. IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 5 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 Electrical Characteristics - PCIEX 0.7V Current Mode Differential Outputs TA = TCOM or TIND; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, I REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN Current Source Output Impedance Zo1 VO = V x 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. 660 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Measurement on single ended signal using absolute value. Crossing Voltage (var) d-Vcross Variation of crossing over all edges Long Accuracy ppm Average period Tperiod Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Tabsmin tr tf d-tr d-tf tpd tpdbyp see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, V OH = 0.525V V OH = 0.525V VOL = 0.175V Input to Output Delay Duty Cycle dt3 Output-to-Output Skew tsk3 Jitter, Cycle to cycle t jcyc-cyc PLL Mode. Bypass mode Measurement from differential wavefrom VT = 50% PLL mode, Measurement from differential wavefrom BYPASS mode as additive jitter TYP MAX UNITS NOTES < 850 1 1,3 mV -150 150 1150 -300 250 9.9970 9.9970 9.8720 175 175 0 3.7 1,3 550 mV 1,3 1,3 1,3 140 mV 1,3 0 ppm 10.0030 ns 10.0533 ns ns 700 ps 700 ps 125 ps 125 ps 150 ps 4.2 ns 1,2 2 2 1,2 1 1 1 1 1 1 45 mV 55 % 1 40 50 ps 1 35 50 ps 1 35 50 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. The 9DB106 does not add a ppm error to the input clock. 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x I REF and VOH = 0.7V @ ZO=50Ω. 2 IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 6 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, route as non-coupled 50ohm trace 0.5 max L2 length, route as non-coupled 50ohm trace 0.2 max L3 length, route as non-coupled 50ohm trace 0.2 max Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' IDT® Six Output Differential Buffer for PCIe Gen 2 PCI Express Add-in Board REF_CLK Input L3 9DB106 7 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a R4 L4 L4' L2' L1' R1b R2a HCSL Output Buffer R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT® Six Output Differential Buffer for PCIe Gen 2 PCIe Device REF_CLK Input 9DB106 8 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 General SMBus serial interface information for the 9DB106 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D4 (h) IDT clock will acknowledge Controller (host) sends the begining byte location = N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1) • IDT clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D4(h) WRite WR Controller (host) will send start bit. Controller (host) sends the write address D4 (h) IDT clock will acknowledge Controller (host) sends the begining byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D5 (h) IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N + X -1 IDT clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address D4(h) WR WRite IDT (Slave/Receiver) IDT (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D5(h) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDT® Six Output Differential Buffer for PCIe Gen 2 Not acknowledge stoP bit 9DB106 9 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 SMBusTable: Device Control Register, READ/WRITE ADDRESS (D4/D5) Byte 0 Pin # Name Control Function Type 0 1 PWD Enables SMBus PLL controlled PLL controlled SW_EN Control of bits RW by SMBus 1 Bit 7 by device pins (1:0) registers RW X RESERVED Bit 6 RESERVED RW X Bit 5 RESERVED RW X Bit 4 RESERVED RW X Bit 3 RESERVED RW X Bit 2 Selects PLL PLL BW #adjust RW Low BW High BW 1 Bit 1 Bandwidth PLL bypassed PLL enabled Bypasses PLL for 1 RW PLL Enable Bit 0 (fan out mode) (ZDB mode) board test SMBusTable: Output Enable Register Byte 1 Pin # Name Control Function Type RESERVED RW Bit 7 RESERVED RW Bit 6 24,23 PCIEX5 Output Control RW Bit 5 RESERVED RW Bit 4 18,17 PCIEX3 Output Control RW Bit 3 11,12 PCIEX2 Output Control RW Bit 2 RW RESERVED Bit 1 5,6 PCIEX0 Output Control RW Bit 0 SMBusTable: Function Select Register Byte 2 Pin # Name Control Function Type RESERVED RW Bit 7 RESERVED RW Bit 6 RESERVED RW Bit 5 RESERVED RW Bit 4 RESERVED RW Bit 3 RW RESERVED Bit 2 RESERVED RW Bit 1 RW RESERVED Bit 0 SMBusTable: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type RID3 R Bit 7 RID2 R Bit 6 REVISION ID RID1 R Bit 5 RID0 R Bit 4 VID3 R Bit 3 VID2 R Bit 2 VENDOR ID VID1 R Bit 1 VID0 R Bit 0 IDT® Six Output Differential Buffer for PCIe Gen 2 0 1 - Disable Enable - Disable Disable Enable Enable - Disable Enable 0 1 PWD X X X X X X X X 1 - PWD 0 0 0 1 0 0 0 1 - 0 - PWD X X 1 X 1 1 X 1 9DB106 10 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 SMBusTable: DEVICE ID Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Control Function Type R R R Device ID R = 06 Hex R R R R 0 1 PWD 0 0 0 0 0 1 1 0 - SMBusTable: Byte Count Register Pin # Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name Control Function Type 0 1 PWD BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 0 1 1 0 IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 11 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 209 mil SSOP SYMBOL A A1 A2 b c D E E1 e L N a In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° VARIATIONS N 28 D mm. MIN 9.90 D (inch) MAX 10.50 MIN .390 MAX .413 Reference Doc.: JEDEC Publication 95, MO-150 10-0033 IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 12 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 4.40 mm. Body, 0.65 mm. Pitch TSSOP c N (173 mil) L E1 SYMBOL A A1 A2 b c D E E1 e L N a aaa E INDEX AREA 1 2 α D A A2 (25.6 mil) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS A1 N -C- 28 e SEATING PLANE b D mm. MIN 9.60 D (inch) MAX 9.80 MIN .378 MAX .386 Reference Doc.: JEDEC Publication 95, MO-153 aaa C 10-0035 Ordering Information Part / Order Number 9DB106BFLF 9DB106BFLFT 9DB106BGLF 9DB106BGLFT 9DB106BFILF 9DB106BFILFT 9DB106BGILF 9DB106BGILFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP Temperature 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C -40 to +85°C -40 to +85°C "LF" after the package code are the Pb-Free configuration and are RoHS compliant. "B" is the device revision designator (will not correlate to the datasheet revision). IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 13 REV K 04/20/11 9DB106 Six Output Differential Buffer for PCIe Gen 2 Revision History Rev. Originator B RDW Issue Date Description 1. Changed Output to Output skew from 30ps to 45ps. 2. Changed PLL mode jitter from 40ps to 35ps. 3. Changed Bypass mode additive jitter from 25ps to 35ps. 9/12/2005 4. Updated LF Ordering Information. C RDW 8/17/2006 Corrected Typo of SMBus Read/Write Address. 7 3/12/2007 Added SMBus Read/Write Table. 6 D RDW E F G RDW RDW H J K RDW RDW RDW Page # 5, 8-9 1. Added Phase Noise Parameters, Updated input to output delay values. 2. PLL BW moved to PLL parameters table. 8/6/2007 3. Added terminations tables. 12/14/2007 Updated SMBus serial Interface Information. 4/1/2010 Updated ordering info for Rev B 1. Updated DS to include I-temp specs and ordering information 2. Updated electrical tables to reflect common set of numbers for I-temp and C-temp 3. Converted all references of ICS to IDT 9/15/2010 4. Corrected placement of AC coupling caps in Figure 4 1/27/2011 Updated Termination Figure 4. 4/20/2011 1. Changed pull down indicator from '**" to " v " to correct pin description of CLKREQ# pins. 6-8 9 13 8 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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