DATASHEET ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Description Pin Configuration Dual DDR I/II fanout buffer for VIA Chipset AGND Output Features • • • • • • • • • Low skew, fanout buffer SMBus for functional and output control Single bank 1-6 differential clock distribution 1 pair of differential feedback pins for input to output synchronization Supports up to 2 DDR DIMMs 266MHz (DDRI 533) output frequency support 400MHz (DDRII 800) output frequency support Programmable skew through SMBus Individual output control programmable through SMBus BUF_INT BUF_INC DDRT0 DDRC0 DDRT1 DDRC1 GND VDDQ2.5/1.8 FB_OUTT FB_OUTC DDRT2 DDRC2 Key Specifications • • • • • OUTPUT - OUTPUT skew: <100ps Output Rise and Fall Time for DDR outputs: 650ps - 950ps DUTY CYCLE: 47% - 53% 28-pin SSOP/TSSOP package RoHS compliant packaging 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ICS9P936 AVDD2.5 GND VDDQ2.5/1.8 AVDD2.5 AGND DDRT5 DDRC5 GND VDDQ2.5/1.8 DDRT4 DDRC4 DDRT3 DDRC3 SDATA SCLK 28-SSOP & TSSOP Funtional Block Diagram BUF_INC BUF_INT SCLK SDATA Control Logic FB_OUTC FB_OUTT DDRC (5:0) DDRT (5:0) IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Pin Description PIN # 1 2 3 4 5 6 7 8 9 PIN NAME AVDD2.5 AGND BUF_INT BUF_INC DDRT0 DDRC0 DDRT1 DDRC1 GND PIN TYPE PWR PWR IN IN OUT OUT OUT OUT PWR DESCRIPTION 2.5V Analog Power pin for Core PLL Analog Ground pin for Core PLL True Buffer In signal for memory outputs. Complementary Buffer In signal for memory outputs. -40 "Complementary" Clock of differential pair output. "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Ground pin. 10 VDDQ2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively 11 FB_OUTT OUT 12 FB_OUTC OUT 13 14 15 16 17 18 19 20 DDRT2 DDRC2 SCLK SDATA DDRC3 DDRT3 DDRC4 DDRT4 OUT OUT IN I/O OUT OUT OUT OUT True single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs. Complementary single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs. "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. "Complementary" Clock of differential pair output. "True" Clock of differential pair output. "Complementary" Clock of differential pair output. "True" Clock of differential pair output. 21 VDDQ2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively 22 23 24 25 26 GND DDRC5 DDRT5 AGND AVDD2.5 PWR OUT OUT PWR PWR Ground pin. "Complementary" Clock of differential pair output. "True" Clock of differential pair output. Analog Ground pin for Core PLL 2.5V Analog Power pin for Core PLL 27 VDDQ2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively 28 GND PWR Ground pin. IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 2 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Absolute Max Supply Voltage Logic Inputs Ambient Operating Temperature Case Temperature Storage Temperature -0.5V to 3.6V GND –0.5 V to VDD +0.5 V or 3.6V, whichever is less 0°C to +70°C 115°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters (VDDQ2.5/1.8 = 1.8V +/- 0.1V) TA = 0 - 70°C; Supply Voltage AVDD = 2.5V +/- 0.2V(unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Input Clamp Voltage SYMBOL I IH I IL I DDAVDD2.5 CONDITIONS VI = VDDQ or GND VI = VDDQ or GND RL = 120Ω, CL = 12pf @ 266MHz RL = 120Ω, CL = 12pf @ 266MHz MIN -40 SPEC TYP MAX 23 164 I DDVDDQ2.5/1.8 VDDQ = 1.8V Iin = -18mA VIK High-level output voltage VOH I OH = -9 mA Low-level output voltage VOL I OL=9 mA Input Capacitance Output Capacitance CIN COUT VI = GND or VDDQ VOUT = GND or VDDQ 2 2 Input clock slew rate t sl(i) Input clock 1 10 26 180 -1.2 1.1 IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer UNITS µA µA mA mA V V 0.6 V 3 3 4 4 pF pF 2.5 4 V/ns 1084C 12/03/09 3 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Recommended Operating Condition (VDDQ2.5/1.8 = 1.8V +/- 0.1V) (see note1) TA = 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Low level input voltage VIL BUF_INT, BUF_INC High level input voltage VIH BUF_INT, BUF_INC DC input signal voltage (note 2) VIN Differential input signal voltage (note 3) VID Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) MIN SPECIFICATION TYP MAX UNITS 0.35 x V DDQ 0.65 x V DDQ V V -0.3 VDDQ + 0.3 V DC - BUF_INT, BUF_INC 0.3 VDDQ + 0.4 V AC - BUF_INT, BUF_INC 0.6 VDDQ + 0.4 V V OX V DDQ/2 - 0.1 VDDQ/2 + 0.1 V VIX V DDQ/2 - 0.15 VDDQ/2 + 0.15 V VDDQ/2 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allow able DC excursion of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for sw itching, w here VTR is the true input level and VCP is the complimentary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at w hich the differential signal must be changed. IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 4 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Timing Requirements VDDQ2.5/1.8 = 1.8 V +/- 0.1V TA = 0 - 70°C Supply Voltage AVDD2.5 = 2.5V+/-0.2V (unless otherwise stated) SPECIFICATION PARAMETER SYMBOL UNITS CONDITIONS -40 MAX Max clock frequency freqop 125 400 MHz Application Frequency Range Input clock duty cycle CLK stabilization freqApp dtin 160 40 TSTAB 400 60 MHz % 15 µs Switching Characteristics (VDDQ2.5/1.8 = 1.8V +/- 0.1V) (see note 1) TA = 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V, VDDQ2.5/1.8 = 1.8 V +/- 0.1V (unless otherwise stated) SPECIFICATION PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Period jitter -40 40 ps Period jitter Tjit (per) Half-period jitter T(jit_hper) Half period jitter -60 60 ps Cycle to Cycle Tcyc -Tcyc Cycle to Cycle jitter -40 40 ps Dynamic Phase Offset T(DPO) -50 50 ps -50 0 50 ps Static Phase Offset T(SPO) Output to Output Skew tskew DDR(0:5) 40 ps Output Duty Cycle tduty 47 53 ps Measured from 20% to 80% of Output clock slew rate tsl(i) 1.5 3 V/ns VDDQ 1. Switching characteristics guaranteed for operating frequency range IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 5 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Electrical Characteristics - Input/Supply/Common Output Parameters (VDDQ2.5/1.8 = 2.5V +/- 0.2V) TA = 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated) PARAMETER Input High Current SYMBOL I IH Input Low Current Operating Supply Current Input Clamp Voltage I IL CONDITIONS VI = VDD or GND MIN -10 VI = VDD or GND RL = 120Ω, CL = 12pf @ 200MHz RL = 120Ω, CL = 12pf @ 200MHz SPEC TYP MAX 20 220 IDDAVDD2.5 I DDVDDQ2.5/1.8 VIK VDDQ = 2.5V, Iin = -18mA High-level output voltage VOH IOH = -12 mA Low-level output voltage VOL IOL = 12 mA Input Capacitance Output Capacitance CIN COUT VI = GND or VDDQ VOUT = GND or VDDQ 2 2 Input clock slew rate tsl(i) Input clock 1 UNITS µA 10 µA 23 250 -1 mA mA V 1.7 V 0.6 V 3 3 4 4 pF pF 2.5 4 V/ns Recommended Operating Condition (VDDQ2.5/1.8 = 2.5V +/- 0.2V) (see note1) TA = 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated) PARAMETER Low level input voltage High level input voltage DC input signal voltage (note 2) SPECIFICATION TYP MAX UNITS V DDQ/2 - 0.18 V VDDQ/2 + 0.18 V SYMBOL CONDITIONS VIL BUF_INT, BUF_INC BUF_INT, BUF_INC VIH MIN VIN -0.3 VDDQ + 0.3 V DC - BUF_INT, BUF_INC 0.36 VDDQ + 0.6 V AC - BUF_INT, BUF_INC 0.7 VDDQ + 0.6 V VDDQ/2 + 0.15 V VDDQ/2 + 0.2 V Differential input signal voltage (note 3) VID Output differential crossvoltage (note 4) V OX V DDQ/2 - 0.15 Input differential crossvoltage (note 4) VIX V DDQ/2 - 0.2 VDDQ/2 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allow able DC excursion of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for sw itching, w here VTR is the true input level and VCP is the complimentary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at w hich the differential signal must be changed. IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 6 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Timing Requirements VDDQ2.5/1.8 = 2.5V +/- 0.2V TA = 0 - 70°C Supply Voltage AVDD2.5 = 2.5V+/-0.2V (unless otherwise stated) SPECIFICATION PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 45 500 MHz Max clock frequency freqop Application Frequency Range freqApp 95 233 MHz Input clock duty cycle dtin 40 60 % CLK stabilization TSTAB 15 µs Switching Characteristics (VDDQ2.5/1.8 = 2.5V +/- 0.2V ) (see note 1) TA = 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V, VDDQ2.5/1.8 = 2.5 V +/- 0.2V (unless otherwise stated) SPECIFICATION PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Period jitter -60 60 ps Period jitter Tjit (per) Half-period jitter T(jit_hper) Half period jitter -75 75 ps Cycle to Cycle Jitter Tcyc -Tcyc Cycle to Cycle jitter -60 60 ps Static Phase Offset T(SPO) -50 0 50 ps Output to Output Skew Tskew DDR(0:5) 40 ps Output Duty Cycle tduty 47 53 ps Measured from 20% to 80% of 1.5 4 V/ns Output clock slew rate t sl(o) VDDQ 1. Switching characteristics guaranteed for operating frequency range IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 7 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D4(H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 • Controller (host) will need to acknowledge each byte • Controller (host) will send a stop bit How to Read: How to Write: Controller (Host) Start Bit Address D4(H) Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver) ACK ICS (Slave/Receiver) ACK Byte Count Dummy Command Code ACK ACK Dummy Byte Count Byte 0 ACK ACK Byte 0 Byte 1 ACK ACK Byte 1 Byte 2 ACK ACK Byte 2 Byte 3 ACK ACK Byte 3 Byte 4 ACK Byte 4 ACK ACK Byte 5 Byte 5 ACK ACK Byte 6 Byte 6 ACK ACK Byte 7 Byte 7 Stop Bit ACK Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 8 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer 2 I C Table: Output Control Register Byte 7 Pin # Name Control Function Type 0 1 Bit 7 - BUFF_IN_T/C Frequency Detect RW OFF ON 1 Bit Bit Bit Bit Bit Bit Bit - FB_OUT_T/C DDR_T5/C5 DDR_T4/C4 DDR_T3/C3 DDR_T2/C2 DDR_T1/C1 DDR_T0/C0 FB_OUT Control Output Control Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 Control Function Type 0 1 Default 6 5 4 3 2 1 0 Default 2 I C Table: Byte Count Register Byte 8 Pin # Name Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 - BC7 RW BC6 BC5 BC4 BC3 BC2 BC1 BC0 RW RW RW RW RW RW RW Byte Count Programming b(7:0) 0 Writing to this register will configure how many bytes will be read back, default is 0h = 15 bytes 0 0 0 1 1 1 1 2 I C Table: Group Skew Control Register Pin # Name Byte 19 Bit 7 - Bit Bit Bit Bit Bit Bit Bit - 6 5 4 3 2 1 0 DDR_CSkw3 DDR_CSkw2 DDR_CSkw1 DDR_CSkw0 Reserved Reserved FBOUTSkw1 FBOUTSkw0 Control Function Type 0 1 Default Reserved Reserved FB_OUT Skew Control (also see table 2) RW RW RW RW RW RW RW RW 0000 = 0 0100 = 150 1000 = 300 1100 = 450 Reserved Reserved 00 = 0 01 = 250 1101 = 600 1110 = 750 1111 = 900 N/A Reserved Reserved 10 = 500 11 = 750 0 0 0 0 0 0 0 0 Control Function Type 0 1 Default RW RW RW RW RW RW RW RW 0000 = 0 0100 = 150 1000 = 300 1100 = 450 Reserved Reserved Reserved Reserved 1101 = 600 1110 = 750 1111 = 900 N/A Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 DDR_C Skew Control (also see table1) 2 I C Table: Group Skew Control Register Pin # Name Byte 20 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 - DDR_TSkw3 DDR_TSkw2 DDR_TSkw1 DDR_TSkw0 Reserved Reserved Reserved Reserved DDR_T Skew Control (also see table1) Reserved Reserved Reserved Reserved Note: Bytes not shown are reserved and should not be altered. IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 9 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer 28-pin SSOP Package Drawing and Dimensions c N L E1 INDEX AREA E 1 2 α D A A2 A1 -Ce b In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -2.00 -.079 A1 0.05 -.002 -A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 D SEE VARIATIONS SEE VARIATIONS E 7.40 8.20 .291 .323 E1 5.00 5.60 .197 .220 e 0.65 BASIC 0.0256 BASIC L 0.55 0.95 .022 .037 N SEE VARIATIONS SEE VARIATIONS α 0° 8° 0° 8° VARIATIONS N SEATING PLANE .10 (.004) C 28 D mm. MIN 9.90 D (inch) MAX 10.50 MIN .390 MAX .413 Reference Doc.: JEDEC Publication 95, MO-150 10-0033 209 mil SSOP IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 10 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer 28-pin TSSOP Package Drawing and Dimensions 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) SYMBOL A A1 A2 b c D E E1 e L N α aaa (25.6 mil) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS N 28 D mm. MIN 9.60 D (inch) MAX 9.80 MIN .378 MAX .386 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Ordering Information Part / Order Number 9P936AFLF 9P936AFLFT 9P936AGLF 9P936AGLFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP Temperature 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. "A" denotes the revision designator (will not correlate to datasheet revision). IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 11 ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Revision History Rev. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 A B C Issue Date 3/23/2005 4/1/2005 9/12/2005 9/14/2005 11/13/2006 4/5/2007 6/26/2007 4/8/2009 Description Updated Electrical Characteristics Updated Skew programming bytes and I2c programming address Updated LF Ordering Information Added TSSOP Ordering Information. Updated I2C. Updated Switching Characteristics. Updated Max Clock Frequency. Released to final. 1. Updated all electrical tables to specify VDDQ = 1.8V and 2.5V. 11/12/2009 2. Updated ordering information table 3. Updated pinout and pin descriptions 1.Corrected Byte 19/20 default to 00 hex. 12/2/2009 2.Corrected typos in electrical tables, made formatting improvements for readability. Page # 5-9 3, 10 11 12 3 6 1, 7, 10 Various Innovate with IDT and accelerate your future networks. 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