WM7211E Top Port Digital Silicon Microphone DESCRIPTION FEATURES The WM7211 is a low-profile silicon digital microphone. It offers high Signal-to-Noise Ratio (SNR) and low power consumption and is suited to a wide variety of consumer applications. The WM7211 incorporates Cirrus’s proprietary CMOS/MEMS membrane technology, offering high reliability and high performance in a miniature, low-profile package. The WM7211 is designed to withstand the high temperatures associated with automated flow solder assembly processes. (Note that conventional microphones can be damaged by this process.) The WM7211 incorporates a high performance ADC, which outputs a single-bit data stream using Pulse Density Modulation (PDM) encoding. The WM7211 supports selectable left/right channel assignment for a two-channel digital microphone interface, enabling efficient connection of multiple microphones in stereo/array configurations. The WM7211 offers tight tolerance on the microphone sensitivity, giving reduced variation between parts. This removes the need for in-line production calibration of partto-part microphone variations. BLOCK DIAGRAM High SNR (61dB) Low variation in sensitivity (±1dB tolerance) Low current consumption - 2μA (Sleep) - 735μA (Normal operation) PDM digital audio output Stereo/array operation Proprietary ADC technology - Reduced clock jitter sensitivity - Low noise floor - Stable in overload condition Top Port LGA Package 1.64V to 3.7V supply APPLICATIONS Mobile telephone handsets Portable computers Portable media players Digital still cameras Digital video cameras Bluetooth headsets Portable navigation devices 3D VIEW VDD WM7211 CLK CONTROL CHARGE PUMP AMP DAT LRSEL ADC CMOS MEMS Transducer GND 4.00mm x 3.00mm x 1.00mm LGA package http://www.cirrus.com Copyright Cirrus Logic, Inc., 2011–2016 (All Rights Reserved) Rev 4.0 MAR ‘16 WM7211E TABLE OF CONTENTS DESCRIPTION ................................................................................................................ 1 FEATURES ..................................................................................................................... 1 APPLICATIONS.............................................................................................................. 1 BLOCK DIAGRAM ......................................................................................................... 1 3D VIEW ......................................................................................................................... 1 TABLE OF CONTENTS .................................................................................................. 2 PIN CONFIGURATION ................................................................................................... 3 PIN DESCRIPTION ......................................................................................................... 3 ORDERING INFORMATION ........................................................................................... 3 ABSOLUTE MAXIMUM RATINGS ................................................................................. 4 IMPORTANT ASSEMBLY GUIDELINES ....................................................................... 4 RECOMMENDED OPERATING CONDITIONS .............................................................. 4 ACOUSTIC AND ELECTRICAL CHARACTERISTICS .................................................. 5 TERMINOLOGY ......................................................................................................................... 6 AUDIO INTERFACE TIMING ..................................................................................................... 7 TYPICAL PERFORMANCE ............................................................................................ 8 APPLICATIONS INFORMATION ................................................................................... 9 RECOMMENDED EXTERNAL COMPONENTS ........................................................................ 9 OPTIMISED SYSTEM RF DESIGN ........................................................................................... 9 CONNECTION TO A CIRRUS AUDIO CODEC ......................................................................... 9 PCB LAND PATTERN AND PASTE STENCIL ........................................................................ 10 PACKAGE DIMENSIONS ............................................................................................. 11 IMPORTANT NOTICE .................................................................................................. 12 REVISION HISTORY .................................................................................................... 13 2 Rev 4.0 WM7211E PIN CONFIGURATION 3 2 4 1 5 Top View PIN DESCRIPTION PIN NAME TYPE 1 VDD Supply 2 LRSEL Digital Input DESCRIPTION Power Supply Channel Select 0 = Data output following falling CLK edge 1 = Data output following rising CLK edge Internal pull-down holds this pin at logic 0 when not connected 3 CLK Digital Input 4 DAT Digital Output 5 GND Supply Clock input PDM Data Output Ground ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM7211IMSE/RV -40 to +100°C LGA (tape and reel) MSL2A +260°C Note: Reel Quantity = 4800 All devices are Pb-free and Halogen free. Rev 4.0 3 WM7211E ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Cirrus tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL2A = out of bag storage for 4 weeks at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Supply Voltage (VDD) -0.3V +4.2V GND - 0.3V VDD + 0.3V -40°C +100°C Voltage range digital inputs (LRSEL, CLK) Operating temperature range, TA Storage temperature prior to soldering 30°C max / 60% RH max Storage temperature after soldering -40°C +100°C IMPORTANT ASSEMBLY GUIDELINES Do not put a vacuum over the port hole of the microphone. Placing a vacuum over the port hole can damage the device. Do not board wash the microphone after a re-flow process. Board washing and the associated cleaning agents can damage the device. Do not expose to ultrasonic cleaning methods. Do not use vapour phase re-flow process. The vapour can damage the device. Please refer to application note WAN0273 (MEMS MIC Assembly and Handling Guidelines) for further assembly and handling guidelines. RECOMMENDED OPERATING CONDITIONS PARAMETER 4 SYMBOL MIN VDD Supply Range VDD 1.64 Ground GND Clock Frequency FCLK TYP MAX UNIT 3.7 V 3.25 MHz 0 1 V Rev 4.0 WM7211E ACOUSTIC AND ELECTRICAL CHARACTERISTICS Test Conditions: VDD=1.8V, 1kHz test signal, CLK=2.4MHz, TA = 25°C, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN Directivity Positive sound pressure S Acoustic Overload Total Harmonic Distortion MAX UNIT Omni-directional Polarity (see note) Sensitivity TYP THD 94dB SPL Decreasing density of 1s -27 -26 -25 dBFS No load, THD < 10% 120 dB SPL 94dB SPL 0.1 % 114dB SPL 0.5 117.5dB SPL 1 SNR A-weighted 61 DR A-weighted 84.5 dB Acoustic Noise Floor A-weighted 33 dB SPL Electrical Noise Floor A-weighted -87 dBFS Frequency Response +3dB high frequency Signal to Noise Ratio Dynamic Range Frequency Response Flatness Power Supply Rejection 200Hz to 8kHz PSR dB 17000 -1 217Hz Square Wave Hz +1 -75 dB dBFS 100mV (peak-peak) Digital Input / Output CLK Input HIGH Level VIH 0.65 x VDD CLK Input LOW Level VIL DAT Output HIGH Level VOH IOH = +1mA DAT Output LOW Level VOL IOL = -1mA Input capacitance (CLK) CIN V 0.35 x VDD 0.9 x VDD V CLOAD Short Circuit Output Current ISC 0.1 x VDD V 1 μA 100 pF 10 mA 0.5 Input Leakage Maximum load capacitance (DAT) V DAT connected to GND pF Miscellaneous Current Consumption Start-up Time CLK Sleep Frequency IVDD Active Mode 735 SLEEP Mode 2 From OFF 10 From SLEEP 10 μA 10 ms 1.0 kHz Note: The WM7211 generates a single-bit digital (PDM) output in response to the acoustic input. A positive sound pressure on the diaphragm generates a decreasing density of 1’s in the PDM stream (i.e. there is a phase inversion between the acoustic input and the digital output.) Rev 4.0 5 WM7211E TERMINOLOGY 1. Sensitivity (dBFS) – Sensitivity is a measure of the microphone output response to the acoustic pressure of a 1kHz 94dB SPL (1Pa RMS) sine wave. This is referenced to the output Full Scale Range (FSR) of the microphone. 2. Full Scale Range (FSR) - Sensitivity, Electrical Noise Floor and Power Supply Rejection are measured with reference to the output Full Scale Range (FSR) of the microphone. FSR is defined as the amplitude of a 1kHz sine wave output whose positive peak value reaches 100% density of logic 1s and whose negative peak value reaches 0% density of logic 1s. This is the largest 1kHz sine wave that will fit in the digital output range without clipping. Note that, because the definition of FSR is based on a sine wave, it is possible to support a square wave test signal output whose level is +3dBFS. 3. Total Harmonic Distortion (%) – THD is the ratio of the RMS sum of the harmonic distortion products in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output. 4. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the output response of a 1kHz 94dB SPL sine wave and the idle noise output. 5. Dynamic Range (dB) – DR is the ratio of the 1% THD microphone output level (in response to a sine wave input) and the idle noise output level. 6. All performance measurements are carried out within a 20Hz to 20kHz bandwidth and, where noted, an A-weighted filter. Failure to use these filters will result in higher THD and lower SNR values than are found in the Acoustic and Electrical Characteristics. The brick wall filter removes out of band noise. 7. Sleep Mode is enabled when the CLK input is below the CLK Sleep Frequency noted above. This is a power-saving mode. Normal operation resumes automatically when the CLK input is above the CLK Sleep Frequency. Note that the VDD supply is still required in Sleep mode. 6 Rev 4.0 WM7211E AUDIO INTERFACE TIMING tCY CLK (input) tL_DV DAT (LRSEL = 1) tL_DIS tL_EN tR_DV DAT (LRSEL = 0) tR_DIS tR_EN DAT is high-impedance (hi-z) when not outputting data Figure 1 Digital Microphone Interface Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT 308 1000 ns 60:40 40:60 Digital Microphone Interface Timing CLK cycle time tCY CLK duty cycle CLK rise/fall time DAT enable from rising CLK edge (LRSEL = 1) 6 tL_EN 14 DAT valid from rising CLK edge (LRSEL = 1) tL_DV 20 DAT disable from falling CLK edge (LRSEL = 1) tL_DIS DAT enable from falling CLK edge (LRSEL = 0) tR_EN 14 DAT valid from falling CLK edge (LRSEL = 0) tR_DV 20 DAT disable from rising CLK edge (LRSEL = 0) tR_DIS ns ns 90 ns 16 ns ns 90 ns 16 ns Notes: 1. The DAT output is high-impedance when not outputting data; this enables the outputs of two microphones to be connected together, with the data from one microphone interleaved with the data from the other. (The microphones must be configured to transmit on opposite channels in this case.) 2. In a typical configuration, the Left channel is transmitted following the rising CLK edge (LRSEL = 1). In this case, the Left channel should be sampled by the receiving device on the falling CLK edge. 3. Similarly, the Right channel is typically transmitted following the falling CLK edge (LRSEL = 0). In this case, the Right channel should be sampled by the receiving device on the rising CLK edge. 4. The WM7211 operating mode is selected according to the CLK frequency; see “Acoustic and Electrical Characteristics” for further details. Rev 4.0 7 WM7211E TYPICAL PERFORMANCE Sensitivity vs. Frequency PSR vs. Frequency Sensitivity vs. Supply Voltage Current Consumption vs. Supply Voltage THD vs. Sound Pressure Level 8 Rev 4.0 WM7211E APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS It is recommended to connect a 0.1µF decoupling capacitor between the VDD and GND pins of the WM7211. A ceramic 0.1µF capacitor with X7R dielectric or better is suitable. The capacitor should be placed as close to the WM7211 as possible. OPTIMISED SYSTEM RF DESIGN For optimised RF design please refer to document WAN0278 (Recommended PCB Layout for Microphone RF Immunity in Mobile Cell Phone Applications) for further information. CONNECTION TO A CIRRUS AUDIO CODEC Cirrus provides a range of audio CODECs incorporating a digital microphone input interface; these support direct connection to digital microphones such as the WM7211. Stereo connection of two WM7211 digital microphones is illustrated in Figure 2. Further information on Cirrus audio CODECs is provided in the respective product datasheet, which is available from the Cirrus website. VDD WM7211 VDD Audio CODEC CLK 0.1F DAT DMICCLK DMICDAT LRSEL GND VDD WM7211 VDD CLK 0.1F DAT LRSEL GND Figure 2 Stereo WM7211 Digital Microphone Connection Rev 4.0 9 WM7211E PCB LAND PATTERN AND PASTE STENCIL The recommended PCB Land Pattern and Paste Stencil Pattern for the WM7211 microphone are shown in Figure 3 and Figure 4. See also Application Note WAN0284 (General Design Considerations for MEMS Microphones) for further details of PCB footprint design. Full definition of the package dimensions is provided in the “Package Dimensions” section. Figure 3 DM96 - PCB Land Pattern, Top View Figure 4 DM096 - Paste Stencil Pattern, Top View 10 Rev 4.0 WM7211E PACKAGE DIMENSIONS Rev 4.0 11 WM7211E IMPORTANT NOTICE Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective. Copyright © 2011–2016 Cirrus Logic, Inc. All rights reserved. 12 Rev 4.0 WM7211E REVISION HISTORY DATE REV DESCRIPTION OF CHANGES 31/01/11 2.0 First Release 18/02/11 2.0 Confidential added to headers and footers 26/04/11 2.1 Updated the PSRR, sleep mode, start up time from off PAGE CHANGED BY PF JMacD KC Updated frequency response curve and the +3dB point to 17000hz Updated the THD % Updated all the LRSEL description , and figure 1 Added the notes on Updated reel quantity 27/04/11 2.1 Current consumption / Active Mode changed to 650 μA JMacD 02/05/11 2.2 Package Drawing updated. JMacD 20/12/11 2.3 Introduced E variant with sensitivity +/-1dB KC Added E variant ordering info Added voltage range digital input Updated the CODEC to WM8994 Added Reference to WAN_0273 19/01/12 2.3 Package Diagram updated to DM096C – formatting updates. JMacD 23/08/12 2.4 Package Diagram updated to DM096D JMacD 16/05/13 2.5 Package Diagram updated to DM096E JMacD 08/11/13 3.1 Product Status updated to Pre Production JMacD Updated CODEC reference to WM8280. 18/12/13 3.1 Acoustic and Electrical Characteristics updated: Polarity and Note added. MR 03/10/14 3.2 Updates throughout the whole document PH 16/03/15 3.3 Typical performance graphs updated 8 PCB Stencil and Land Pattern drawings updated 10 Package Outline Drawing updated 11 21/04/15 3.4 Package Outline Diagram updated 11 02/10/15 4.0 Updated to ‘Production’ status Rev 4.0 PH PH PH 13