IDT IDT54FCT833AEB


IDT54/74FCT833A
IDT54/74FCT833B
FAST CMOS
PARITY BUS
TRANSCEIVER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Equivalent to AMD’s Am29833 bipolar parity bus
transceiver in pinout/function, speed and output drive
over full temperature and voltage supply extremes
• High-speed bidirectional bus transceiver for processororganized devices
• IDT54/74FCT833A equivalent to Am29833A speed and
output drive
• IDT54/74FCT833B 30% faster than Am29833A
• Buffered direction and three-state controls
• Error flag with open-drain output
• IOL = 48mA (commercial) and 32mA (military)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Available in plastic DIP, CERDIP, LCC and SOIC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT833s are high-performance bus
transceivers designed for two-way communications. They
each contain an 8-bit data path from the R (port) to the T (port),
an 8-bit data path from the T (port) to the R (port), and a 9-bit
parity checker/generator. The error flag can be clocked and
stored in a register and read at the ERR output. The clear
(CLR) input is used to clear the error flag register.
The output enables OET and OER are used to force the
port outputs to the high-impedance state so that the device
can drive bus lines directly. In addition, OER and OET can be
used to force a parity error by enabling both lines
simultaneously. This transmission of inverted parity gives the
designer more system diagnostic capability. The devices are
specified at 48mA and 32mA output sink current over the
commercial and military temperature ranges, respectively.
FUNCTIONAL BLOCK DIAGRAM
RI
8
TI
8
PARITY
OE T
OE R
8
8
S
MUX
9
9-BIT
PARITY TREE
D
P
Q
ERR
Q
CP
CLR
CLK
2557 drw 01
CLR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1992 Integrated Device Technology, Inc.
7.21
MAY 1992
DSC-4621/2
1
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1
24
2
23
3
4
5
6
7
8
22
P24-1,
D24-1,
S024-2
&
E24-1
21
20
19
18
17
9
16
10
15
11
14
12
13
INDEX
Vcc
T0
T1
T2
T3
T4
T5
T6
T7
PARITY
OET
CLK
4
R2
R3
R4
NC
R5
R6
R7
DIP/SOIC/CERPACK
TOP VIEW
OER
I/O
I
Description
Inputs
RECEIVE enable input.
I/O
8-bit RECEIVE data input/output.
ERR
O
Output from fault registers. Register
detection of odd parity fault on rising clock
edge (CLK). A registered ERR output
remains LOW until cleared. Open drain
output, requires pull up resistor.
I
T2
T3
T4
NC
T5
T6
T7
25
6
24
7
L28-1
8
23
22
9
21
10
20
11
19
12 13 14 15 16 17 18
2557 drw 02
ERROR FLAG OUTPUT FUNCTION TABLE(1,2)
RI
CLR
28 27 26
1
LCC
TOP VIEW
PIN DESCRIPTION
Pin Name
3 2
5
ERR
CLR
GND
NC
CLK
OE T
PARITY
OER
R0
R1
R2
R3
R4
R5
R6
R7
ERR
CLR
GND
R1
R0
OER
NC
Vcc
T0
T1
PIN CONFIGURATIONS
I/O
8-bit TRANSMIT data input/output.
PARITY
I/O
1-bit PARITY output.
OET
I
TRANSMIT enable input.
CLK
I
External clock pulse input for fault register
flag.
CLR
CLK
Point “P”
ERRn–1
H
H
H
↑
↑
↑
H
—
L
L
—
—
Output
ERR
Function
H
L
—
H
L
L
Sample
(1’s
Capture)
—
H
Clear
NOTES:
1. OET is HIGH and OER is LOW.
2. H = HIGH
L = LOW
↑ = LOW-to-HIGH transition of clock
– = Don't Care or Irrelevant
Clears the fault register output.
TI
Internal
Output
To Device Pre-State
2557 tbl 02
2557 tbl 01
7.21
2
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(2)
Inputs
Outputs
TI Incl Parity
OET
OER
CLR
CLK
RI (∑ or H’s)
(∑ of H’s)
RI
TI
Parity
ERR(1)
L
L
L
L
H
H
H
H
H
H
H
H
↑
↑
↑
↑
H (Odd)
H (Even)
L (Odd)
L (Even)
NA
NA
NA
NA
NA
NA
NA
NA
H
H
L
L
L
H
L
H
H
L
H
L
Transmit data from R Port
to T Port with parity;
receiving path is disabled.
H
H
H
H
L
L
L
L
H
H
H
H
↑
↑
↑
↑
NA
NA
NA
NA
H (Odd)
H (Even)
L (Odd)
L (Even)
H
H
L
L
NA
NA
NA
NA
NA
NA
NA
NA
H
L
H
L
Receive data from T Port
to R Port with parity test
resulting in flag:
transmitting path is disabled.
—
—
L
—
—
—
NA
NA
NA
H
Clear the state of error flag
register.
H
H
H
H
H
H
H
H
H
L
H
H
H or L
—
↑
↑
—
—
H or L (Odd)
H or L (Even)
—
—
—
—
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
H
H
L
Both transmitting and
receiving paths are disabled.
Parity logic defaults to
transmit mode.
L
L
L
L
L
L
L
L
H
H
H
H
↑
↑
↑
↑
H (Odd)
H (Even)
L (Odd)
L (Even)
NA
NA
NA
NA
NA
NA
NA
NA
H
H
L
L
H
L
H
L
L
H
L
H
Forced-error checking.
NOTES:
1. Output state assumes HIGH output pre-state.
2. H
= HIGH
L
= LOW
↑
= LOW-to-HIGH transition of clock
*No change to stored Error State
Function
2557 tbl 03
Z =
NA =
– =
High Impedance
Not Applicable
Don’t Care or Irrelevant
7.21
Odd =
Even =
I
=
Odd number of logic one’s
Even number of logic one’s
0, 1, 2, 3, 4, 5, 6, 7
3
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
Military
Unit
VTERM(2)
Terminal Voltage
with Respect
to GND
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output Current
–0.5 to +7.0
–0.5 to +7.0
V
–0.5 to VCC
–0.5 to VCC
V
VTERM(3)
TA
TBIAS
TSTG
PT
IOUT
0 to +70
–55 to +125
°C
–55 to +125
–65 to +135
°C
–55 to +125
–65 to +150
°C
0.5
120
0.5
120
W
mA
Symbol Parameter(1)
Conditions
CIN
Input
Capacitance
CI/O
I/O
Capacitance
Typ.
Max.
Unit
VIN = 0V
6
10
pF
VOUT = 0V
8
12
pF
NOTE:
2557
1. This parameter is guaranteed by characterization but not tested.
tbl 05
NOTES:
2557 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Inputs and VCC terminals.
3. Outputs and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
VIL
IIH
IIL
IIH
IIL
VIK
IOS
VOH
VOL
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(Except I/O Pins)
Input LOW Current
(Except I/O Pins)
Input HIGH Current
(I/O Pins Only)
Input LOW Current
(I/O Pins Only)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
(Except ERR)
Output LOW Voltage
Test Conditions(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
VCC = Max.
VI =VCC
VI = 2.7V
VI = 0.5V
VI = GND
VCC = Max.
VI = VCC
VI = 2.7V
VI = 0.5V
VI = GND
Vcc = Min., IN = –18mA
Vcc = Max.(3), VO = GND
Vcc = 3V, VIN = VLC or VHC, IOH = –32µA
Vcc = Min.
IOH = –300µA
IOH = –15mA MIL.
VIN = VIH or VIL
IOH = –24mA COM’L.
Vcc = 3V, VIN = VLC or VHC, IOL = 300µA
Vcc = Min.
Except
IOL = 300µA
VIN = VIH
ERR
IOL = 32 mA MIL.
IOL = 48mA COM’L.
or VIL
ERR
IOL = 48mA
Min.
2.0
—
—
—
—
—
—
—
—
—
—
–60
VHC
VHC
2.4
2.4
—
—
—
—
—
Typ.(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
VCC
VCC
4.3
4.3
GND
GND
0.3
0.3
0.3
Max.
—
0.8
5
5(4)
–5(4)
–5
15
15(4)
–15(4)
–15
–1.2
—
—
—
—
—
VLC
VLC(4)
0.5
0.5
0.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.21
Unit
V
V
µA
µA
V
mA
V
V
2557 tbl 06
4
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC – 0.2V
Symbol
ICC
∆ICC
ICCD
IC
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current(4)
Outputs Open
Total Power Supply Current(6)
Test Conditions(1)
Vcc = Max.; VIN ≥ V HC, VIN ≤ VLC
Vcc = Max.
VIN = 3.4V(3)
Vcc = Max.
VIN ≥ VHC
VIN ≤ VLC
OET = OER = GND
One Input Toggling
50% Duty Cycle
Vcc = Max.
VIN ≥ VHC
Outputs Open
VIN ≤ VLC
fCP = 10MHz
(FCT)
50% Duty Cycle
OET = GND
VIN = 3.4V
OER = VCC
VIN = GND
fi = 2.5MHz
One Bit Toggling
Vcc = Max.
VIN ≥ VHC
Outputs Open
VIN ≤ VLC
fCP = 10MHz
(FCT)
50% Duty Cycle
OET = GND
VIN = 3.4V
fi = 2.5MHz
VIN = GND
OER = VCC
Eight Bits Toggling
Min.
—
—
Typ.(2)
0.2
0.5
Max.
1.5
2.0
Unit
mA
mA
—
0.15
0.25
mA/
MHz
—
1.4
3.4
mA
—
1.9
5.4
—
4.0
7.8(5)
—
6.2
16.8(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.21
2557 tbl 07
5
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT833A
Com’l.
Symbol
Parameter
Conditions(1)
IDT54/74FCT833B
Mil.
Com’l.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Mil.
Min.(2)
Max.
Unit
ns
tPLH
Propagation Delay
CL = 50pF
—
10.0
—
14.0
—
7.0
—
10.0
tPHL
RI to TI, TI to RI
CL = 300pF(3)
—
17.5
—
21.5
—
14.5
—
17.5
tPLH
Propagation Delay
CL = 50pF
—
15.0
—
20.0
—
10.5
—
14.0
—
22.5
—
27.5
—
18.0
—
21.5
—
12.0
—
16.0
—
8.5
—
11.0
(3)
ns
tPHL
RI to PARITY
CL = 300pF
tPZH
Output Enable Time
CL = 50pF
tPZL
OER, OET to RI, TI
—
19.5
—
23.5
—
16.0
—
18.5
tPHZ
Output Disable Time CL = 5pF(3)
—
10.7
—
14.7
—
7.2
—
9.8
tPLZ
OER, OET to RI, TI
CL = 50pF
—
12.0
—
16.0
—
8.5
—
11.0
CL = 50pF
12.0
—
16.0
—
8.5
—
11.0
—
ns
0
—
0
—
0
—
0
—
ns
CL = 300pF
(3)
ns
ns
tSU
TI, PARITY to CLK
Set-up Time
tH
TI, PARITY to CLK
Hold Time
tREM
Clear Recovery Time
CLR to CLK
15.0
—
20.0
—
10.5
—
14.0
—
ns
tW
Clock Pulse Width
HIGH or LOW
7.0
—
9.5
—
5.5
—
7.0
—
ns
tW
Clear Pulse Width
LOW
7.0
—
9.5
—
5.5
—
7.0
—
ns
tPHL
Propagation Delay
CLK to ERR
—
12.0
—
16.0
—
8.5
—
11.0
ns
tPLH
Propagation Delay
CLR to ERR
—
16.0
—
20.0
—
15.0
—
18.0
ns
tPLH
Propagation Delay
—
15.0
—
20.0
—
10.5
—
14.0
ns
tPHL
OER to PARITY
—
22.5
—
27.5
—
18.0
—
21.5
CL = 50pF
CL = 300pF
(3)
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
2557 tbl 08
7.21
6
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7.0V
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
SET-UP, HOLD AND RELEASE TIMES
Closed
All Other Tests
Open
3V
1.5V
0V
tH
TIMING
INPUT
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
tW
t REM
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
Open Drain
Disable Low
Enable Low
PULSE WIDTH
DATA
INPUT
ASYNCHRONOUS CONTROL
Switch
DEFINITIONS:
2557 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
CL
t SU
Test
t SU
1.5V
3V
1.5V
0V
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
1.5V
SAME PHASE
INPUT TRANSITION
t PLH
t PHL
CONTROL
INPUT
OUTPUT
NORMALLY SWITCH
LOW CLOSED
t PZH
VOL
t PLH
t PHL
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
t PLZ
t PZL
0V
VOH
1.5V
OUTPUT
1.5V
3.5V
1.5V
3.5V
0.3V
V OL
t PHZ
0.3V
1.5V
0V
V OH
0V
0V
NOTES
2557 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.21
7
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXX
Temperature
Range
FCT
X
X
X
Device
Type
Package
Process/
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°)
Compliant to MIL-STD-883, Class B
P
D
L
SO
E
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
833A
833B
Non-inverting Parity Bus Transceiver
Fast Non-inverting Parity Bus Transceiver
54
75
–55°C to +125°C
0°C to +70°C
2557 drw 03
7.21
8