WM0011 w General Purpose Low-Power Audio DSP DESCRIPTION FEATURES WM0011 Audio DSP provides Wolfson HD audio quality, with a power-budget targeted at handheld battery-powered audio devices. Tensilica HiFi EP™ 24-bit audio digital signal processor - C-programmable with advanced debugging and profiling tool set WM0011 combines the advanced Tensilica HiFi EP™ audio DSP with an I/O and peripheral set optimized for flexible integration into smartphones, tablets and other portable consumer electronics devices. WM0011 is ideal for extremely power-efficient implementations of advanced voice enhancement, telephony noise reduction, voice and music CODECs and general audio enhancement. - Local RAM memory - Instruction / Data cache memories - General-purpose system RAM - Flexible boot options supported within ROM - 32 Channel DMA - XTAL or CMOS clock input A very wide range of audio CODECs, voice CODECs and third-party algorithms from such companies as Waves Audio, SRS Labs and Dolby are available, providing a rich portfolio of audio-processing options that can be integrated into a device with no additional software development. - Low power programmable PLL WM0011 comes in a space-saving 3x3mm 49-ball W-CSP package with 0.4mm pitch. Security - Support for HW Authentication Random Number Generator (RNG) to assist security algorithms Peripherals - SPI Master / Slave interface - 3 x multi-channel serial digital interface (I S, TDM) APPLICATIONS - UART I C Master - Wireless audio devices – headsets, microphones, speakerphones - I C Slave Portable media devices - 3 x 32-bit general-purpose timer modules Automotive General purpose digital signal processor for consumer audio applications. - Watchdog timer - On-chip JTAG debug unit and trace buffer - GPIO Smartphones WOLFSON MICROELECTRONICS plc 2 2 2 Software-defined standby modes for extended battery life Product Brief, August 2013, Rev 4.1 Copyright 2013 Wolfson Microelectronics plc WM0011 Product Brief TDI TDO TMSDFT TCK TRST TDEBUG / TMSDEBUG UARTTX / SCLK1 / SCLK2 / GPIO23 UARTRX / SDA1 / SDA2 / GPIO22 PROGVDD AVDD DGND DGND DCVDD DBVDD1 DBVDD2 DBVDD3 BLOCK DIAGRAM MUX 2 (UART with I2CM and I2CS) 32kB Boot ROM 64kB Instruction RAM 1 I2C Module 1 (Slave) Timer Module I2C Module 2 (Master) UART JTAG Module Watchdog Module 64kB Instruction RAM 2 64kB Data RAM 2 RESET STANDBY IRQ DMA Module with SHA-256 Fuses TRAX Trace Buffer Module On-Chip Debug Module 12kB Instruction Cache 24kB Data Cache CLKOUT / GPIO28 RNG AIF2TXDAT AIF2RXDAT AIF2LRCLK AIF2BCLK Bypass AIF1TXDAT AIF1RXDAT AIF1LRCLK AIF1BCLK w AIF2 Module AIF3 Module SPI Module PLL XTI XTO PLLC GPIO MUX 1 (I2S and SPI) AIF3LRCLK / SPISS / GPIO17 AIF3TXDAT / SPIMOSI / GPIO18 AIF3RXDAT / SPIMISO / GPIO19 AIF3BCLK / SPISCLK AIF1 Module WM0011 Chip Config Module Tensilica Hi-Fi EP™ DSP Core PKA 384kB System RAM TOCDRST GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 64kB Data RAM 1 Product Brief, Rev 4.1, August 2013 2 WM0011 Product Brief PIN CONFIGURATION ORDERING INFORMATION DEVICE CUSTOM FUSES TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM0011ECS/R Un-programmed -40 to +85°C 49-ball W-CSP (Pb-free, Tape and reel) MSL1 260°C WM0011xxxECS/R CustomProgrammed -40 to +85°C 49-ball W-CSP (Pb-free, Tape and reel) MSL1 260°C Note: Reel quantity = 5000 * xxx = Unique Custom Fuse part number ** Custom programmed minimum order quantity 50,000. w Product Brief, Rev 4.1, August 2013 3 WM0011 Product Brief PACKAGE DIAGRAM B: 49 BALL W-CSP PACKAGE 3.055 X 3.055 X 0.636mm BODY, 0.40 mm BALL PITCH DM114.B 3 D A DETAIL 1 g 7 A2 5 6 4 3 1 2 A A1 CORNER 2 A B C e 4 D E1 E 3 E F G 2X ddd e DETAIL 2 M Z AB 2X 4 aaa B B aaa A TOP VIEW D1 BOTTOM VIEW f1 SOLDER BALL bbb Z f2 h 1 Z ccc Z A1 DETAIL 2 Symbols A A1 A2 D D1 E E1 e MIN 0.592 0.175 0.381 3.000 3.000 Dimensions (mm) NOM MAX 0.681 0.636 0.205 0.190 0.406 0.432 3.055 3.080 2.400 BSC 3.080 3.055 2.400 BSC 0.400 BSC 0.328 f1 0.300 f2 0.300 h g 0.216 0.270 0.324 0.036 0.040 0.10 0.10 0.044 aaa bbb ccc ddd 0.328 DETAIL 1 NOTE 4 Bump centre to die edge Bump centre to die edge 0.03 0.015 NOTES: 1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE. 3. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 4. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 6. FOLLOWS JEDEC DESIGN GUIDE MO-211-C. w Product Brief, Rev 4.1, August 2013 4 Product Brief WM0011 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. 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ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w Product Brief, Rev 4.1, August 2013 5 WM0011 Product Brief REVISION HISTORY DATE REV 17/07/12 1.1 First Release DESCRIPTION OF CHANGES 19/10/12 2.0 Pin G4 and E1 names updated PH 07/02/13 3.0 Change to document title, aligning with datasheet Block diagram updated (CLK DIV now labeled as Chip Config Module) PH 20/05/13 4.0 Pin Description updates (name changes only) PH 21/08/13 4.1 Front page description updated w PAGE CHANGED BY RR/RD JMacD Product Brief, Rev 4.1, August 2013 6