IDT49C465 IDT49C465A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT Integrated Device Technology, Inc. FEATURES DESCRIPTION • • • • • • • • • • • • • • The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC unit. The chip provides single-error correction and two and three bit error detection of both hard and soft memory errors. It can be expanded to 64-bit widths by cascading 2 units, without the need for additional external logic. The FlowthruEDC has been optimized for speed and simplicity of control. The EDC unit has been designed to be used in either of two configurations in an error correcting memory system. The bidirectional configuration is most appropriate for systems using bidirectional memory buses. A second system configuration utilizes external octal buffers, and is well suited for systems using memory with separate I/O buses. The IDT49C465/A supports partial word writes, pipelining and error diagnostics. It also provides parity protection for data on the system side. 32-bit wide Flow-thruEDC unit, cascadable to 64 bits Single-chip 64-bit Generate Mode Separate system and memory buses On-chip pipeline latch with external control Supports bidirectional and common I/O memories Corrects all single-bit errors Detects all double-bit errors, some multiple-bit errors Error Detection Time — 12ns Error Correction Time — 14ns On chip diagnostic registers. Parity generation and checking on system data bus Low power CMOS — 100mA typical at 20MHZ 144-pin PGA and PQFP packages Military product compliant to MIL-STD 883, Class B SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM MD0–31 Correct Logic Memory Checkbit Generator MLE Checkbit Latch CBI0–7 Mux Expansion Logic Syndrome Generator MD Latch Pipeline Latch PCBI0–7 SD0–31 SD Latch ERR Detect Logic MERR CONTROL CONTROL System Checkbit Generator Byte Mux Mux CBO0–7 SLE PLE 2552 drw 01 CONTROL CONTROL The IDT logo is a registered trademark and Flow-thruEDC is a trademarkof Integrated Device Technology Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1995 Integrated Device Technology, Inc. 11.7 AUGUST 1995 DSC-9028/7 1 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES MERR ERR SYO7 SYO6 SY05 SY04 GND SY03 SYO2 SYO1 SYO0 MD0 MD1 MD2 VCC SD2 SD1 SD0 PCBI7 PCBI6 PCBI5 PCBI4 PCBI3 PCBI2 PCBI1 PCBI0 CODE ID 1 CODE ID 0 GND GND MODE 1 MODE 0 SD3 72 73 37 36 49C465Y PQ144-2 108 109 1 VCC VCC MD3 MD4 MD5 MD6 MD7 MD8 MD9 GND MD10 MD11 MD12 MD13 MD14 MD15 MLE MOE GND MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 GND MD24 MD25 MD26 MD27 MD28 MD29 MD30 VCC SYNCLK SCLKEN CLEAR CBI0 CBI1 CBI2 CBI3 GND CBI4 CBI5 CBI6 CBI7 MD31 VCC P2 GND GND P1 P0 MODE 2 144 SD29 SD30 SD31 CBO0 CBO1 CBO2 CBO3 CBOE CBO4 CBO5 CBO6 CBO7 PSEL PERR P3 VCC VCC SD5 SD6 SD7 SD8 SD9 SD10 SD11 GND BE1 SD12 SD13 SD14 SD15 SLE PLE SOE GND SD16 SD17 SD18 SD19 BE2 SD20 SD21 SD22 GND SD23 SD24 SD25 SD26 SD27 BE3 SD28 VCC VCC SD4 BE0 VCC PIN CONFIGURATION 2552 drw 02 PQFP TOP VIEW 11.7 2 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATION CODE CODE MODE SD 2 PCBI 6 PCBI 5 PCBI 3 ID 1 MERR ERR SYO 5 SYO 3 SYO 1 MD 1 1 ID 0 VCC SD 6 SD 4 SD 1 PCBI 7 PCBI 4 PCBI 1 PCBI 0 MODE SYO 6 SYO 4 SYO 2 MD 0 MD 2 VCC MD 5 SD 9 SD 5 BE 0 MD 3 MD 6 MD 9 12 SD 11 SD 7 VCC MD 4 MD 8 11 SD 12 SD 10 SD 8 MD 7 MD 10 MD 11 10 SD 15 GND MD 12 MD 13 MD 15 9 SLE SD 13 SD 14 MOE MD 14 MLE 8 SOE 15 VCC 14 13 BE 1 PLE 0 SD 3 SD 0 PCBI 2 GND GND SYO 7 GND SYO 0 VCC G144-2 GND GND GND MD 17 MD 16 MD 20 MD 21 MD 18 7 SD 17 SD 19 SD 16 6 SD 18 BE 2 SD 20 GND MD 23 MD 19 5 SD 21 SD 22 SD 25 MD 27 MD 25 MD 22 4 GND SD 24 3 SD 23 SD 26 SD 28 2 SD 27 VCC SD 29 SD 31 CB0 2 CB0 4 CB0 6 P3 1 VCC SD 30 CB0 1 CB0 3 CB0 5 PSEL PERR P2 P1 H J A BE 3 B C NC* VCC D VCC MD 28 MD 24 SCLK GND CB1 6 CB1 7 MD 30 MD 26 EN MODE SYN2 CLK CB1 0 CB1 3 CB1 4 MD 31 MD 29 CB0 0 CBOE CB0 7 GND GND E F G P0 K CLEAR CB1 1 CB1 2 CB1 5 VCC L M N P R *Tied to Vcc internally PGA (CAVITY UP) 2552 drw 03 TOP VIEW 11.7 3 11.7 CODE ID 0,1 MODE0–2 SYNCLK SCLKEN CLEAR 4 3 2 SD LATCH MUX INTERNAL SYNCLK PARITY CHECK PARITY GEN CONTROL LOGIC /ERR 4 4 1 OF 4 BYTES 4 8 ERROR DETECT PIPE LATCH 8 8 MUX PERR P0–3 PSEL SLE SD0–31 BE0–3 SOE PLE SYO0–7 ERR MERR INTERNAL FINAL SYNDRO ME 8 8 8 MUX SYNDROME GENERATOR PCBI 0–7 SD CHECKBIT GENERATOR 8 8 MUX MD CHECKBIT GENERATOR 4 SD CHECKBIT GENERATOR BE 0–3 CLEAR MD LATCH CHECK BIT LATCH 8 8 8 8 INTERNAL SYNCLK BYTE MUX DIAGNOSTIC LATCHES ERROR DATA LATCH ERROR CORRECT 8 8 8 Dashed Line = Diagnostic path MUX 8 PCBI0–7 CBOE CBO0–7 MOE MD0–31 MLE CBI0–7 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES DETAILED FUNCTIONAL BLOCK DIAGRAM MUX MUX 2552 drw 04 4 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES SYSTEM CONFIGURATIONS The IDT49C465 EDC unit can be used in various configurations in an EDC system. The basic configurations are shown below. Figure 1 illustrates a bidirectional configuration, which is most appropriate for systems using bidirectional memory buses. It is the simplest configuration to understand and use. During a correction cycle, the corrected data word can be simultaneously output on both the system bus and memory bus. Logically, no other parts are required for the correction function. During partial-word-write operations, the new bytes are internally combined with the corrected old bytes for checkbit generation and writing to memory. Figure 3 illustrates a third configuration which utilizes external buffers and is also well suited for systems using memory with separate I/O buses. Since data from memory does not need to pass through the part on every cycle, the EDC system may operate in “bus-watch” mode. As in the separate I/O configuration, corrected data is output on the SD outputs. MEMORY INPUT BUS MEMORY OUTPUT BUS CHECKBIT I/O CBO CBI SD MD EDC CPU I/O SD MEMORY I/O MD EDC EXT. BUFFER EXT.BUFFER EXT. BUFFER CBI CPU BUS CHECKBITS CBO 2552 drw 07 2552 drw 05 Figure 3. Bypassed Separate I/O Configuration Figure 1. Common I/O Configuration Figure 2 illustrates a separate I/O configuration. This is appropriate for systems using separate I/O memory buses. This configuration allows separate input and output memory buses to be used. Corrected data is output on the SD outputs for the system and for re-write to memory. Partial word-write bytes are combined externally for writing and checkbit generation. CHECK BITS OUT EXT. BUFFER CPU Figure 4 illustrates the single-chip generate-only mode for very fast 64-bit checkbit generation in systems that use separate checkbit-generate and detect-correct units. If this is not desired, 64-bit checkbit generation and correction can be done with just 2 EDC units. 64-bit correction is also straightforward, fast and requires no extra hardware for the expansion. MEMORY INPUTS MEMORY INPUT BUS CHECK BITS IN MEMORY OUTPUT BUS MEMORY INPUT BUS CBO CBI 64-BIT GEN. ONLY LOWER DATA UPPER DATA EDC EDC EDC BUFFER BUFFER SD MD MEMORY OUTPUTS BUFFER BUFFER EDC CBI CHECKBITS CPU BUS 2552 drw 08 CBO 2552 drw 06 Figure 4. Separate Generate/Correction Units with 64-Bit Checkbit Generation Figure 2. Separate I/O Configuration 11.7 5 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTIONAL DESCRIPTION The error detection/correction codes consist of a modified Hamming code; it is identical to that used in the IDT49C460. 32-BIT MODE (CODE ID 1,0=00) VCC 8 CHECKBITS–OUT PCBI CBO 7 CBI7 CHECKBITS–IN 7 CBI0–6 SYO 7 SYNDROME–OUT EDC 2552 drw 09 Figure 5. 32-Bit Mode 64-BIT MODE (CODE ID 1,0=10 & 11) The expansion bus topology is shown in Figure 6. This topology allows the syndrome bits used by the correction logic to be generated simultaneously in both parts used in the expansion. During a 64-bit detection or correction operation, “Partial-Checkbit” data and “Partial-Syndrome” data is simultaneously exchanged between the two EDC units in opposite directions on dedicated expansion buses. This results in very short 64-bit detection and correction times. 8 PARTIAL–CHECKBITS–OUT (11) (CORRECTION ONLY) CHECKBITS–IN 8 PCBI CBO CBI SYO 8 PARTIAL–CHECKBITS–OUT (10) (GENERATE ONLY) 8 PARTIAL–SYNDROME (DETECT/CORRECT ONLY) PCBI CBO CBI SYO LOWER EDC ERR UPPER EDC (CODE ID 1,0 = 10) (CODE ID 1,0 = 11) 8 FINAL CHECKBITS–OUT (DETECT AND CORRECT) 2552 drw 10 Figure 6. 64-Bit Mode — 2 Cascaded IDT49C465 Devices 64-BIT GENERATE-ONLY MODE (CODE ID 1,0=01) If the Identity pins CODE ID 1,0 = 01, a single EDC is placed in the 64-bit “Generate-only” mode. In this mode, the lower 32 bits of the 64-bit data word enter the device on the MD0-31 inputs and the upper 32-bits of the 64 bit data word enter the device on the SD0-31 inputs. This provides the device with the full 64-bit word from memory. The resultant generated checkbits are output on the CBO0-7 outputs. The generate time is less than that resulting from using a 2-chip cascade. MD0–31 LOWER 32 BITS (0–31) CBO 8 32 CHECKBITS–OUT SD0–31 UPPER 32 BITS (32–63) 32 EDC 2552 drw 11 Figure 7. 64-Bit "Generate-Only" Mode (Single Chip) 11.7 6 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTIONS Symbol I/O Name and Function I/O Buses and Controls I/O System Data Bus: Data from MD0-31 appears at these pins corrected if MODE 2-0 = x11, or uncorrected in the other modes. The BEn inputs must be high and the SOE pin must be low to enable the SD output buffers during a read cycle. (Also, see diagnostic section.) Separate I/O memory systems: In a write or partial-write cycle, the byte not-to-be-modified is output on SDn to n+7 for re-writing to memory, if BEn is high and SOE is low. The new bytes to be written to memory are input on the SDn pins, for writing checkbits to memory, if BEn is low. Bi-directional memory systems: In a write or partial-write cycle, the byte not-to-be-modified is re-directed to the MD I/O pins, if BEn is high, for checkbit generation and rewriting to memory via the MD I/O pins. SOE must be high to avoid enabling the output drivers to the system bus in this mode. The new bytes to be written are input on the SDn pins for checkbit generation and writing to memory. BEn must be low to direct input data from the System Data bus to the MD I/O pins for checkbit generation and writing to the checkbit memory. SLE I System Latch Enable: SLE is an input used to latch data at the SD inputs. The latch is transparent when SLE is high; the data is latched when SLE is low. PLE I SOE I System Output Enable: When low, enables System output drivers and Parity output drivers if corresponding Byte Enable inputs are high. BE0-3 I Byte Enables: In systems using separate I/O memory buses, BEn is used to enable the SD and Parity outputs for byte n. The BEn pins also control the “Byte mux”. When BEn is high, the corrected or uncorrected data from the Memory Data latch is directed to the MD I/O pins and used for checkbit generation for byte n. This is used in partial-word-write operations or during correction cycles. When BEn is low, the data from the System Data latch is directed to the MD I/O pins and used for checkbit generation for byte n. BE0 controls SD0-7 BE2 controls SD16-23 BE1 controls SD8-15 BE3 controls SD24-31 I/O Memory Data Bus: These I/O pins accept a 32-bit data word from main memory for error detection and/ or correction. They also output corrected old data or new data to be written to main memory when the EDC unit is used in a bi-directional configuration. MLE I Memory Latch Enable: MLE is used to latch data from the MD inputs and checkbits from the CBI inputs. The latch is transparent when MLE is high; data is latched when MLE is low. When identified as the upper slice in a 64-bit cascade, the checkbit latch is bypassed. MOE I Memory Output Enable: P0-3 I/O SD0-7 SD8-15 SD16-23 SD24-31 MD0-31 PSEL Pipeline Latch Enable: PLE is an input which controls a pipeline latch, which controls data to be output on the SD bus and the MD bus during byte merges. Use of this latch is optional. The latch is transparent when PLE is low; the data is latched when PLE is high. MOE enables Memory Data Bus output drivers when low. Parity I/O: The parity I/O pins for Bytes 0 to 3. These pins output the parity of their respective bytes when that byte is being output on the SD bus. These pins also serve as parity inputs and are used in generating the Parity ERRor (PERR) signal under certain conditions (see Byte Enable definition). The parity is odd or even depending on the state of the Parity SELect pin (PSEL). I Parity SELect: If the Parity SELect pin is low, the parity is even. If the Parity SELect pin is high, the parity is odd. CBI0-7 I CheckBits-In (00) CheckBits-In-1 (10) Partial-Syndrome-In (11): In a single EDC system or in the lower slice of a cascaded EDC system, these inputs accept the checkbits from the checkbit memory. In the upper slice in a cascaded EDC system, these inputs accept the “PartialSyndrome” from the lower slice (Detect/Correct path). PCBI 0-7 I Partial-CheckBits-In (10) Partial-CheckBits-In (11): In a single EDC system, these inputs are unused but should not be allowed to float. In a cascaded EDC system, the “Partial-Checkbits” used by the lower slice are accepted by these inputs (Correction path only). In the upper slice of a cascaded EDC system, “Partial-Checkbits” generated by the lower slice are accepted by these inputs (Generate path). CODE ID1,0 I CODE IDentity: Inputs which identify the slice position/ functional mode of the IDT49C465. (00) Single 32-bit EDC unit (10) Lower slice of a 64-bit cascade (01) 64-bit “Checkbit-generate-only” unit (11) Upper slice of a 64-bit cascade Inputs 2552 tbl 01 11.7 7 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTIONS (Con’t.) Symbol I/O Name and Function Inputs (Con’t.) MODE 2-0 I MODE select: Selects one of four operating modes. (x11) (x10) (000) (x01) (100) CLEAR I SYNCLK I SCLKEN I “Normal” Mode: Normal EDC operation (Flow-thru correction and generation). “Generate-Detect” Mode: In this mode, error correction is disabled. Error generation and detection are normal. “Error-Data-Output” Mode: Allows the uncorrected data captured from an error event by the Error-Data Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by toggling CLEAR low. The Syndrome Register and Error-Data Register record the syndrome and uncorrected data from the first error that occurs after they are reset by the CLEAR pin. The Syndrome Register and Error-Data Register are updated when there is a positive edge on SYNCLK, an error condition is indicated (ERR = low), and the Error Counter indicates zero. All-Zero-Data Source: In Error-Data-Output Mode, clearing the Error-Data Register provides a source of all-zero-data for hardware initialization of memory, if this desired. Diagnostic-Output Mode: In this mode, the contents of the Syndrome Register , Error Counter and ErrorType Register are output on the SD bus. This allows the syndrome bytes for an indicated error to be read by the system for error-logging purposes. The Syndrome Register and the Error-Data Register are updated when there is a positive edge on SYNCLK, an error condition is indicated and the Error Counter indicates zero errors. Thus, the Syndrome Register saves the syndrome that was present when the first error occurred after the Error Counter was cleared. The Syndrome Register and the Error Counter are cleared by toggling CLEAR low. The Error Counter lets the system tell if more than one error has occurred since the last time the Syndrome Register or Error-Data Register was read. Checkbit-Injection Mode: In the “Checkbit-Injection” Mode, diagnostic checkbits may be input on System Data Bus bits 0-7 (see Diagnostic Features - Detailed Description). CLEAR: When the CLEAR pin is taken low, the Error-Data Register, the Syndrome Register, the Error Counter and the Error-Type Register are cleared. SYNdrome CLocK: If ERR is low, and the Error Counter indicates zero errors, syndrome bits are clocked into the Syndrome Register and data from the outputs of the Memory Data input latch are clocked into the Error-Data Register on the low-to-high edge of SYNCLK. If ERR is low, the Error Counter will increment on the low-to-high edge of SYNCLK, unless the Error Counter indicates fifteen errors. SynCLK ENable: The SCLKEN enables the SYNCLK signal. SYNCLK is ignored if SCLKEN is high. Outputs and Enables CBO0-7 O CheckBits-Out (00, 01) Partial-CheckBits-Out (10) Checkbits-Out (11): In a single EDC system, the checkbits are output to the checkbit memory on these outputs. In the lower slice in a cascaded EDC system, the “Partial-checkbits” used by the upper slice are output by these outputs (Generate path only). In the upper slice in a cascade, the “Final-Checkbits” appear at these outputs (Generate path only). CBOE I CheckBits Out Enable: Enables CheckBit Output drivers when low. SYO0-7 O SYndrome-Out (00) Partial-SYndrome-Out (10) Partial-Checkbits-Out (11): In a 32-bit EDC system, the syndrome bits are output on these pins. In the lower slice in a 64-bit cascaded system, the “Partial-Syndrome” bits appear at these outputs (Detect/ Correct path). In the upper slice in a cascaded EDC system, the “Partial-Checkbits” appear at these outputs (Correct path only). In a 64-bit cascaded system, the “Final-Syndrome” may be accessed in the “Diagnostic-Output” Mode from either the lower or the upper slice since the final syndrome is contained in both. ERR O MERR ERROR: When in “Normal” and “Detect only” modes, a low on this pin indicates that one or more errors have been detected. ERR is not gated or latched internally. O PERR O Multiple ERRor: When in “Normal” and “Detect only” modes, a low on this pin indicates that two or more errors have been detected. MERR is not gated or latched internally. Parity ERRor: A low on this pin indicates a parity error which has resulted from the active bytes defined by the 4 Byte Enable pins. Parity ERRor (PERR) is not gated or latched internally (see Byte Enable definition). Power Supply Pins Vcc 1- 10 GND1-12 P P +5 Volts Ground 2552 tbl 02 11.7 8 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES DIAGNOSTIC DATA FORMAT (SYSTEM BUS) Data Out (Unlatched) Latched Data Error ReType served Error Counter Syndrome bits Byte 3 S M 31 30 - - Byte 2 23 2 2 21 20 27 7 24 23 6 5 4 3 Checkbits Partial Checkbits Byte 1 2 1 0 7 6 5 4 3 Byte 0 2 1 16 15 0 7 6 5 4 3 2 1 0 8 7 0 2552 drw 12 DIAGNOSTIC FEATURES — DETAILED DESCRIPTION Mode 2-0 x11 “NORMAL” Mode In this mode, operation is “Normal” or non-diagnostic. x10 “GENERATE-DETECT” Mode When the EDC unit is in the “Generate-Detect” Mode, data is not corrected or altered by the error correction network. (Also referred to as the “Detect-only” Mode.) 000 “ERROR-DATA-OUTPUT” Mode In this mode, the 32-bit data from the Error-Data Register is output on the SD bus. Error Data Register: The uncorrected data from the Memory Data bus input latch is stored in the Error-Data Register if the error counter contents indicates “0” and there is a positive transition on the SYNCLK input when the ERR signal is low. Thus, the Error-Data Register contains memory data corresponding to the first error to occur since the register was cleared. This register is cleared by pulling the CLEAR input low. The register is read via the System Data bus by entering the “Error-Data-Output” Mode and enabling the System Data bus output drivers. All-Zero-Data: The Error-Data Register can be used as an “all-zero-data” data source for memory initialization in systems where the initialization process is to be done entirely by hardware. x01 “DIAGNOSTIC-OUTPUT” Mode In this mode, data from the diagnostic registers, the PCBI bus and the CBI bus is output on the SD bus. Direct Checkbit Readback: Internal data paths allow both the “Partial-CheckBit-Input” bus and the data in the “CheckBitInput” latch to be read directly by the system bus for diagnostic purposes. Both the Checkbit Input Bus and the Partial Checkbit Input Bus are read via the System Data bus by entering the “Diagnostic-Output” Mode and enabling the System Data bus output drivers. The checkbits are output on System Data bus bits 0-7; the Partial Checkbits are output on bits 8-15. Syndrome Register: After an error has been detected, the syndrome bits generated are clocked into the internal Syndrome Register if the error counter contents indicates “0” and there is a positive transition on the SYNCLK input when the ERR signal is low. This register is cleared by pulling the CLEAR input low. The register is read via the System Data bus by entering the “Diagnostic-Output” Mode and enabling the System Data bus outputs. This data is output on SD bits 16-23. Error Counter: The 4-bit on-board error counter is incremented if the error counter contents do not indicate FF HEX, which corresponds to a count of 15, and there is a positive transition on the SYNCLK input when the ERR signal is low. This counter is cleared by pulling the CLEAR input low. The counter is read via the System Data bus by entering the “Diagnostic-Output” Mode and enabling the System Data bus output drivers. This data is output on System Data bus bits 24-27. Test Register: These 2 bits are reserved for factory diagnostics only and must not be used by system software. This data is output on System Data bus bits 28-29. Error-Type Register: The Error-Type Register, clocked by the SYNCLK input, saves 2 bits which indicate whether a recorded error was a single or a multiple-bit error. This register holds only the first error type to occur after the last Clear operation. This data is output on System Data bus bits 30-31. 100 Direct Read-Path Checkbit Injection: In the “Checkbit-Injection” Mode, bits 0-7 of the System Data input latch are presented to the inputs of the Checkbit Input latch. If MLE is strobed, the checkbit latch will be loaded with this value in place of the checkbits from memory. By inserting various checkbit values, operation of the correction function of the EDC can be verified “on-board”. Except for the “Checkbit-Injection” function, operation in this mode is identical to “Normal” Mode operation. 2552 tbl 03 11.7 9 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES OPERATING MODE CHARTS SLICE IDENTIFICATION CODE ID 1 CODE ID 0 Slice Definition 0 0 1 1 0 1 0 1 32-bit Flow-Thru EDC 64-bit GENERATE Only EDC 64-bit EDC- Lower 32 bits (0-31) 64-bit EDC- Upper 32 bits (32-63) 2552 tbl 04 SLICE POSITION CONTROL Checkbit Buses Slice Position/ CODE Functional Operation ID 1 0 0 0 SOE SD Bus 32 Width = MOE MD Bus 32 PCBI PCBI Bus 8 CBI CBI Bus 8 CBO CBO Bus 8 SYO SYO Bus 8 P P Bus 4 PERR 1 Single 32-bit EDC unit Generate(1) Detect/Correct(2) 1 0 Sys. 0–31 Pipe. latch 0 1 Sys. Byte Mux MD 0–31 — — — CBs in CBs out — — Syn. out 0 1 “64-bit Generate-only” 1 Sys. 32–63 1 Sys. 0–31 — — CBs out — 1 0 Lower word, 64-bit bus Generate(1) Detect/Correct(2) 1 0 Sys. 0–31 Pipe. latch 0 1 MD 0–31 MD 0–31 — U-SYOout — CBs in Upper word, 64-bit bus Generate(1) Detect/Correct(2) 1 0 Sys. 32–63 Pipe. latch 0 1 MD 32–63 MD 32–63 L-CBOout — F.CBs out — P in active — L-SYOout — Par.Cbits P out — 1 1 P in active P out — — — PCBs out — P in active — Par.Synd P out — NOTES: 1. Checkbits generated from the data in the SD Latch. 2. Corrected data residing in the Pipe Latch. 2552 tbl 05 FUNCTIONAL MODE CONTROL Checkbit Buses Functional Mode of SD Bus SOE MODE SD Bus MOE CBI CBO SYO P Bus Bus Bus Bus Bus PERR 32 8 8 8 8 4 1 2 1 0 Width = x 1 1 “Normal” Generate Correct 1 0 CPU Data Pipe. latch 0 1 Pipe. latch RAM Data — — — CB in CB out — — — P in active P out — “Generate-Detect” Generate Detect 1 0 CPU Data Pipe. latch 0 1 Pipe. latch RAM Data — — — CB in CB out — — — P in active P out — 0 0 0 “Error-Data-Output” 0 Err. D. latch — — — — — — — — x 0 1 “Diagnostic-Output” 0 CBin latch PCBIin bus Syn. register Err. counter Er. type reg. — — PCBI in CB in — — — — 1 0 0 “Checkbit-Injection” Generate Inject Checkbits Correct 1 1 0 SDin latch SD0–7 in Pipe. latch 0 0 1 Pipe. latch Pipe. latch RAM Data — — — — — CB in CB out — — — — — x 1 0 32 PCBI MD Bus P in active — — P out — 2552 tbl 06 11.7 10 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES PRIMARY DATA PATH vs. MEMORY CONFIGURATION SEPARATE I/O MEMORIES: COMMON I/O MEMORIES: 1. Checkbit Generation Write New Word to Memory DIN BUFFER CPU 1. Checkbit Generation Write New Word to Memory CPU MAIN MEMORY SD MD P CBO IDT49C465 CBI BUFFER SD MD P CBO CBO IDT49C465 CHECKBIT MEMORY CBI DIN MAIN MEMORY BUFFER CORRECTED CBI MD I/O MAIN MEMORY P DOUT CBO IDT49C465 CHECKBIT MEMORY CHECKBIT MEMORY CBI 3. Memory Generation Re-write Corrected Word to Memory DIN MAIN MEMORY SD MD P CBO IDT49C465 CHECKBIT MEMORY CBI CORRECTED SD CPU 3. Memory Generation Re-write Corrected Word to Memory CPU I/O MAIN MEMORY 2. Data Correction Read Memory Word CORRECTED IDT49C465 MD P DOUT 2. Data Correction Read Memory Word CPU SD CORRECTED SD CPU CORRECTED MD P DOUT CBO IDT49C465 CHECKBIT MEMORY CBI I/O MAIN MEMORY CHECKBIT MEMORY 2552 drw 13 11.7 11 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES PARTIAL-WORD-WRITE OPERATIONS FOR COMMON I/O MEMORIES: MD LATCH CORRECTION BLOCK MD BUS B3 BYTE 3 PIPE LATCH SD BUS B2 BYTE 3 B1 BYTE 2 B0 BYTE 2 BYTE 1 BYTE MUX BYTE 1 MAIN MEMORY BYTE 0 BYTE 0 A3 8 SD LATCH A2 8 A1 8 CHECKBIT GENERATOR A0 8 CBO B3 = 1 B2 = 1 B1 = 1 B0 = 0 CBI IDT49C465 In order to perform a partial-word-write operation, the complete word in question must be read from memory. This must be done in order to correct any error which may have occurred in the old word. Once the complete, corrected word is available, with all the bytes verified, the new word may be assembled in the byte mux and the new checkbits generated. CHECKBIT MEMORY 2552 drw 14 The example shown above illustrates the case of combining 3 bytes from an old word with a new lower order byte to form a new word. The new word, along with the new checkbits, may now be written to memory. In the separate I/O memory configuration, the situation is similar except that the new word is output on the SD Bus instead of the MD Bus (refer to previous page). 11.7 12 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES 32-BIT DATA WORD CONFIGURATION A single IDT49C465 EDC unit, connected as shown below, provides all the logic needed for single-bit error correction, and double-bit error detection, of a 32-bit data field. The identification code (00) indicates 7 checkbits are required. The CBI7 pin should be tied high. The 39-bit data format for four bytes of data and 7 checkbits is indicated below. Syndrome bits are generated by an exclusive-OR of the generated checkbits with the checkbits read from memory. For example, Sn is the XOR of checkbits from those read with those generated. During Data Correction, the syndrome bits are used to complement (correct) single-bit errors in the data bits. 32-BIT DATA FORMAT CHECKBITS DATA BYTE 3 31 BYTE 2 24 23 BYTE 1 16 15 BYTE 0 8 7 C6 C5 C4 0 C3 C2 C1 C0 2552 drw 15 32-BIT HARDWARE CONFIGURATION VCC 8 PCBI0–7 CBO0–6 7 CHECKBITS–OUT 7 SYNDROME–OUT 32 MEMORY DATA I/O CBI7 CHECKBITS–IN CBI0–6 7 SYO0–6 ERR MERR P0–3 SYSTEM DATA I/O CODE ID 1,0 = 00 32 SD0–31 MD0–31 IDT49C465 11.7 2552 drw 16 13 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES 64-BIT DATA WORD CONFIGURATION Two IDT49C465 EDC units, connected as shown below, provide all the logic needed for single-bit error correction, and double-bit error detection, of a 64-bit data field. The “Slice Identification” Table gives the CODE ID1,0 values needed for distinguishing the upper 32 bits from the lower 32 bits. Final generated checkbits, ERR and MERR (indicates multiple errors) signals come from the upper slice, the IC with CODE ID1,0=11. Control signals not shown are connected to both units in parallel. Data-In bits 0 through 31 are connected to the same numbered inputs of the EDC with CODE ID1,0=10, while Data-In bits 32 through 63 are connected to data inputs 0 to 31, respectively, for the EDC unit with CODE ID1,0=11. The 72-bit data format of data and checkbits is indicated below. Correction of single-bit errors in the 64-bit configuration requires a simultaneous exchange of partial checkbits and partial syndrome bits between the upper and lower units. Syndrome bits are generated by an exclusive-OR of the generated checkbits with the checkbits read from memory. For example, Sn is the XOR of checkbits read and checkbits generated. During data correction, the syndrome bits are used to complement (correct) single-bit errors in the data bits. For double or multiple-bit error detection, the data available as output by the Pipeline Latch is not defined. Critical AC performance data is provided in the Table “Key AC Calculations”, which illustrates the delays that are critical to 64-bit cascaded performance. As indicated, a summation of propagation delays is required when cascading these units. 64-BIT DATA FORMAT DATA CHECKBITS BYTE 7 BYTE 6 BYTE 5 BYTE 4 BYTE 3 BYTE 2 BYTE 1 BYTE 0 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 C7 C6 C5 0 C4 C3 C2 C1 C0 2552 drw 17 64-BIT HARDWARE CONFIGURATION 8 CHECKBITS–IN 8 PCBI0–7 CBO0–7 CBI0–7 SYO0–7 PARTIAL–CHECKBITS (CORRECT ONLY) 8 PARTIAL–CHECKBITS (GENERATE ONLY) 8 PCBI0–7 CBO0–7 CBI0–7 SYO0–7 PARTIAL–SYNDROME (DETECT/CORRECT) 8 FINAL CHECKBITS (GENERATE ONLY) ERR (DETECT AND CORRECT) P0–3 P0–3 SD0–31 SD0–31 MERR SYSTEM DATA 0–31 MD0–31 MEMORY DATA 32–63 IDT49C465 IDT49C465 LOWER EDC (CODE ID 1,0 = 10) UPPER EDC (CODE ID 1,0 = 11) SYSTEM DATA 32–63 MEMORY DATA 0–31 2552 drw 18 11.7 14 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES DEFINITIONS OF TERMS: CMOS TESTING CONSIDERATIONS D0 – D31 CBI0 – CBI7 PCBI0 – PCBI7 FS0 – FS7 Special test board considerations must be taken into account when applying high-speed CMOS products to the automatic test environment. Large output currents are being switched in very short periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing results: 1) All input pins should be connected to a voltage potential during testing. If left floating, the device may oscillate, causing improper device operation and possible latchup. 2) Placement and value of decoupling capacitors is critical. Each physical set-up has different electrical characteristics and it is recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the minimum lead lengths. They should also be distributed to decouple power supply lines and be placed as close as possible to the DUT power pins. 3) Device grounding is extremely critical for proper device testing. The use of multi-layer performance boards with radial decoupling between power and ground planes is necessary. The ground plane must be sustained from the performance board to the DUT interface board and wiring unused interconnect pins to the ground plane is recommended. Heavy gauge stranded wire should be used for power wiring, with twisted pairs being recommended for minimized inductance. 4) To guarantee data sheet compliance, the input thresholds should be tested per input pin in a static environment. To allow for testing and hardware-induced noise, IDT recommends using VIL ≤ 0V and V IH ≥ 3V for AC tests. = = = = System Data and/or Memory Data Inputs Checkbit Inputs Partial Checkbit Inputs Final Internal Syndrome bits FUNCTIONAL EQUATIONS: The equations below describe the terms used in the IDT49C465 to determine the values of the partial checkbits, checkbits, partial syndromes and final internal syndromes. NOTE: All “⊕” symbols below represent the “EXCLUSIVEOR” function. PA = D0 ⊕ D1 ⊕ D2 ⊕ D4 ⊕ D6 ⊕ D8 ⊕ D10 ⊕ D12 ⊕ D16 ⊕ D17 ⊕ D18 ⊕ D20 ⊕ D22 ⊕ D24 ⊕ D26 ⊕ D28 PB = D0 ⊕ D3 ⊕ D4 ⊕ D7 ⊕ D9 ⊕ D10 ⊕ D13 ⊕ D15 ⊕ D16 ⊕ D19 ⊕ D20 ⊕ D23 ⊕ D25 ⊕ D26 ⊕ D29 ⊕ D31 PC = D0 ⊕ D1 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D16 ⊕ D17 ⊕ D21 ⊕ D22 ⊕ D23 ⊕ D27 ⊕ D28 ⊕ D29 PD = D2 ⊕ D3 ⊕ D4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D14 ⊕ D15 ⊕ D18 ⊕ D19 ⊕ D20 ⊕ D21 ⊕ D22 ⊕ D23 ⊕ D30 ⊕ D31 PE = D8 ⊕ D9 ⊕ D10 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D14 ⊕ D15 ⊕ D24 ⊕ D25 ⊕ D26 ⊕ D27 ⊕ D28 ⊕ D29 ⊕ D30 ⊕ D31 PF = D0 ⊕ D1 ⊕ D2 ⊕ D3 ⊕ D4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D24 ⊕ D25 ⊕ D26 ⊕ D27 ⊕ D28 ⊕ D29 ⊕ D30 ⊕ D31 PG = D8 ⊕ D9 ⊕ D10 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D14 ⊕ D15 ⊕ D16 ⊕ D17 ⊕ D18 ⊕ D19 ⊕ D20 ⊕ D21 ⊕ D22 ⊕ D23 PH0 = D0 ⊕ D4 ⊕ D6 ⊕ D7 ⊕ D8 ⊕ D9 ⊕ D11 ⊕ D14 ⊕ D17 ⊕ D18 ⊕ D19 ⊕ D21 ⊕ D26 ⊕ D28 ⊕ D29 ⊕ D31 PH1 = D1 ⊕ D2 ⊕ D3 ⊕ D5 ⊕ D8 ⊕ D9 ⊕ D11 ⊕ D14 ⊕ D17 ⊕ D18 ⊕ D19 ⊕ D21 ⊕ D24 ⊕ D25 ⊕ D27 ⊕ D30 PH2 = D0 ⊕ D4 ⊕ D6 ⊕ D7 ⊕ D10 ⊕ D12 ⊕ D13 ⊕ D15 ⊕ D16 ⊕ D20 ⊕ D22 ⊕ D23 ⊕ D26 ⊕ D28 ⊕ D29 ⊕ D31 11.7 15 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES 32-BIT SYNDROME DECODE TO BIT-IN-ERROR (1) DETAILED DESCRIPTION — CHECKBIT AND SYNDROME GENERATION vs. CODE ID HEX 0 1 2 3 4 5 6 7 S6 0 0 0 0 1 1 1 1 LOGIC EQUATIONS FOR THE CBO OUTPUTS Checkbit CODE ID 1,0 Syndrome S5 0 0 1 1 0 0 1 1 10 11 Bits S4 0 1 0 1 0 1 0 1 Partial Checkbits 00 Generation Final Chkbits Final Checkbits HEX CBO0 PH0 PH1 PH2 ⊕ PCBI0 0 0 0 0 * T C6 T T 30 PA PA PA ⊕ PCBI1 0 CBO1 PB PC PB ⊕ PCBI2 0 0 0 1 C0 T T 14 T M M T CBO3 PB PC 1 PC ⊕ PCBI3 2 0 0 1 0 C1 T T M T 2 24 T CBO4 PD PD PD ⊕ PCBI4 3 0 0 1 1 T 18 8 T M T T M CBO5 PE PE PE ⊕ PCBI5 4 0 1 0 0 C2 T T 15 T 3 25 T CBO6 PF PF PF ⊕ PCBI6 5 0 1 0 1 T 19 9 T M T T 31 CBO7 — PF PG ⊕ PCBI7 6 0 1 1 0 T 20 10 T M T T M 7 0 1 1 1 M T T M T 4 26 T 8 1 0 0 0 C3 T T M T 5 27 T 9 1 0 0 1 T 21 11 T M T T M A 1 0 1 0 T 22 12 T 1 T T M CBO2 2552 tbl 07 LOGIC EQUATIONS FOR THE SYO OUTPUTS Checkbit/ CODE ID 1,0 Syndrome Generation 00 10 11 Final Syndrome Partial Syndrome Partial Checkbits B 1 0 1 1 17 T T M T 6 28 T 1 1 0 0 T 23 13 T M T T M D 1 1 0 1 M T T M T 7 29 T PC E 1 1 1 0 16 T T M T M M T PD F 1 1 1 1 T M M T 0 T T M PH0 ⊕ CBI0 PH1 ⊕ CBI0 PH2 SYO1 PA ⊕ CBI1 PA ⊕ CBI1 PA SYO3 PB ⊕ CBI2 PC ⊕ CBI3 PB ⊕ CBI2 PC ⊕ CBI3 SYO4 PD ⊕ CBI4 PD ⊕ CBI4 SYO5 PE ⊕ CBI5 PE ⊕ CBI5 PE SYO6 PF ⊕ CBI6 PF ⊕ CBI6 PF SYO7 — PF ⊕ CBI7 PG PB 2552 tbl 08 LOGIC EQUATIONS FOR THE FINAL SYNDROME (FSn) Final CODE ID 1,0 Syndrome 00 10, 11 Generation Final Syndrome Final Internal Syndrome FS0 PH0 ⊕ CBI0 PH1 (L) ⊕ PH2 (U) ⊕ CBI0 FS1 PA ⊕ CBI1 PA (L) ⊕ PA (U) ⊕ CBI1 PB (L) ⊕ PB (U) ⊕ CBI2 FS3 PB ⊕ CBI2 PC ⊕ CBI3 FS4 PD ⊕ CBI4 PD (L)⊕ PD (U) ⊕ CBI4 FS5 PE ⊕ CBI5 PE (L) ⊕ PE (U) ⊕ CBI5 FS6 PF ⊕ CBI6 PF (L) ⊕ PF (U) ⊕ CBI6 FS7 — PF (L) ⊕ PG (U)⊕ CBI7 FS2 C4 C5 C SYO0 SYO2 S3 S2 S1 S0 NOTES: 2552 tbl 12 1. The table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. The all-zero case indicates no error detected. * = No errors detected # = The number of the single bit-in-error T = Two errors detected M = Three or more errors detected PC (L) ⊕ PC (U) ⊕ CBI3 2552 tbl 09 11.7 16 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES DETAILED DESCRIPTION — 32-BIT CONFIGURATION 32-BIT MODIFIED HAMMING CODE — CHECKBIT ENCODING CHART(1) Generated Checkbits Participating Data Bits Parity 0 CB0 Even (XOR) X CB1 Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) CB5 Even (XOR) CB6 Even (XOR) 1 2 X X 3 4 5 6 7 X X X X X 9 X X X X X X X X X X X X X X X X X X X X X 8 X X 11 13 15 X X X 14 X X X X 12 X X X X X 10 X X X X X X X X X X 2552 tbl 10 Generated Participating Data Bits Checkbits Parity CB0 Even (XOR) 16 17 18 19 X X X X X 20 21 22 23 24 25 X X 28 29 X X X X X X X X Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) CB5 Even (XOR) X X X X X CB6 Even (XOR) X X X X X X X X X X X 27 CB1 X X 26 X X X X X X X X X X X 30 31 X X X X X X X X X NOTE: 2552 tbl 11 1. The table indicates the data bits participating in the checkbit generation. For example, checkbit C0 is the Exclusive-OR function of the 16 data input bits marked with an X. 11.7 17 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES DETAILED DESCRIPTION — 64-BIT CONFIGURATION 64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART(1, 2) Generated Participating Data Bits Checkbits Parity 0 CB0 Even (XOR) CB1 Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) CB5 Even (XOR) CB6 Even (XOR) X CB7 Even (XOR) X 1 2 3 X X X X X 4 5 7 X X X 6 X X X 8 9 X X X X X X X X X X X X X X X X X X X X X X X X X X X 10 11 X 15 X X X 14 X X X X 13 X X X 12 X X X X X X X X X X 2552 tbl 13 Generated Participating Data Bits Checkbits Parity 16 17 18 19 X X X X X 20 CB0 Even (XOR) CB1 Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) 22 23 CB5 Even (XOR) X X X X X CB6 Even (XOR) X X X X X CB7 Even (XOR) X X X X X X X X X X X X X 21 X 24 25 X X X X X X X X X X 26 27 29 X X X 28 30 31 X X X X X X X X X X X X X X X X X X X 2552 tbl 14 Generated Participating Data Bits Checkbits Parity 32 CB0 Even (XOR) X CB1 Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) CB5 Even (XOR) CB6 Even (XOR) CB7 Even (XOR) X 33 X 34 35 X X 36 38 39 X X X X X X X X 37 40 41 X X X X X X X X X X X X X X X X X X 42 44 45 X 43 X X X X X X X X X X 46 47 X X X X X X X X X X X X X X X X X X X 2552 tbl 15 Generated Participating Data Bits Checkbits Parity 48 CB0 Even (XOR) X CB1 Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) CB5 Even (XOR) CB6 Even (XOR) CB7 Even (XOR) 49 50 X X 52 54 55 X X X X X X X X X X X X 51 X X X X 53 56 X X X X X X X X X X 57 X 58 59 60 61 X X X X X X X X X X X 62 63 X X X X X X X X X X X X X X X X X X X X NOTES: 2552 tbl 16 1. The table indicates the data bits participating in the checkbit generation. For example, checkbit C0 is the Exclusive-OR function of the 64 data input bits marked with an X. 2. The checkbit is generated as either an XOR or an XNOR of the 64 data bits noted by an “X” in the table. 11.7 18 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES DETAILED DESCRIPTION — 64-BIT CONFIGURATION (Con’t.) 64-BIT SYNDROME DECODE TO BIT-IN-ERROR(1) HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F S7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Syndrome S5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bits S4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX S3 S2 S1 S0 0 0 0 0 0 * C4 C5 T C6 T T 62 C7 T T 46 T M M T 1 0 0 0 1 C0 T T 14 T M M T T M M T M T T 30 2 0 0 1 0 C1 T T M T 34 56 T T 50 40 T M T T M 3 0 0 1 1 T 18 8 T M T T M M T T M T 2 24 T 4 0 1 0 0 C2 T T 15 T 35 57 T T 51 41 T M T T 31 5 0 1 0 1 T 19 9 T M T T 63 M T T 47 T 3 25 T 6 0 1 1 0 T 20 10 T M T T M M T T M T 4 26 T 7 0 1 1 1 M T T M T 36 58 T T 52 42 T M T T M 8 1 0 0 0 C3 T T M T 37 59 T T 53 43 T M T T M 9 1 0 0 1 T 21 11 T M T T M M T T M T 5 27 T A 1 0 1 0 T 22 12 T 33 T T M 49 T T M T 6 28 T B 1 0 1 1 17 T T M T 38 60 T T 54 44 T 1 T T M C 1 1 0 0 T 23 13 T M T T M M T T M T 7 29 T D 1 1 0 1 M T T M T 39 61 T T 55 45 T M T T M E 1 1 1 0 16 T T M T M M T T M M T 0 T T M F 1 1 1 1 T M M T 32 T T M 48 T T M T M M T NOTES: 2552 tbl 17 1. The table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. The all-zero case indicates no error detected. * = No errors detected # = The number of the single bit-in-error T = Two errors detected M = Three or more detected KEY AC CALCULATIONS — 64-BIT CASCADED CONFIGURATION 64-Bit Propagation Delay Mode Total AC Delay for IDT49C465 in 64-bit Mode From To Generate SD Bus Checkbits out Detect MD Bus ERR for 64-bits MD Bus MERR for 64-bits MD Bus Corrected data out Correct NOTE: 1. (or) = Whichever is worse. (L) = Lower slice (U) = Upper slice SD to CBO(L) t SC(L) + + PCBI to CBO(U) t PCC(U) MD to SYO(L) t MSY(L) MD to SYO(L) t MSY(L) + + + + CBI to ERR (U) t CE (U) CBI to M ERR t CME (U) MD to SYO(L) t MSY(L) (or) → MD to SYO(U) t MSY(U) + + + + CBI to SD(U) t CS (U) PCBI to SD(L) t PCS(L) 2552 tbl 18 11.7 19 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating VCC Power Supply Voltage VTERM Terminal Voltage with Respect to Ground TA Operating Temperature TBIAS Com’l. CAPACITANCE (TA = +25°C, f = 1.0MHz) Mil. –0.5 to +7.0 –0.5 to +7.0 Unit Symbol Parameter(1) Conditions Pkg. Typ. Unit V CIN Input Capacitance VIN = 0V PGA PQFP 10 5 pF COUT Output Capacitance VOUT = 0V PGA PQFP 12 7 pF –0.5 to VCC + 0.5 –0.5 to VCC + 0.5 V 0 to +70 –55 to +125 °C Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C IOUT DC Output Current 30 30 NOTE: 1. This parameter is sampled and not 100% tested. 2552 tbl 20 mA NOTE: 2552 tbl 19 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Ratings for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE The following conditions apply unless otherwise specified: Commercial: TA = 0°C to +70°C, V CC = 5.0V ± 5%; Military: TA = –55°C to +125°C, V CC = 5.0V ± 10% Symbol Test Conditions(1) Parameter (4) Min. Typ.(2) Max. Unit 2.0 — — V VIH Input HIGH Level Guaranteed Logic HIGH Normal Inputs 3.0 — — VIL Input LOW Level(4) Guaranteed Logic LOW — — 0.8 V IIH Input HIGH Current VCC = Max., VIN = VCC — — 5.0 µA IIL Input LOW Current VCC = Max., VIN = GND IOZ Off State (Hi-Z) VCC = Max. Hysteresis Inputs — — –5.0 µA VO = 0V — — –10 µA VO = 3V — — 10 (3) IOS Short Circuit Current VCC = Max. –20 — –150 mA VOH Output HIGH Voltage VCC = Min. IOH = –6mA COM’L. 2.4 — — V VIN = VIH or VIL IOH = –4mA MIL. 2.4 — — VCC = Min. IOL = 12mA COM’L. — — 0.5 VIN = VIH or VIL IOL = 6mA MIL. — — 0.5 — 200 — VOL VH Output LOW Voltage Hysteresis CLEAR, MLE, PLE, SLE, SYNCLK, SCLKEN NOTES: 1. For conditions shown as min. or max., use appropriate value specified above for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient temperature and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment. 11.7 V mV 2552 tbl 21 20 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Con’t.) The following conditions apply unless otherwise specified: Commercial: TA = 0°C to +70°C, V CC = 5.0V ± 5%; Military: TA = –55°C to +125°C, V CC = 5.0V ± 10% Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit ICCQ Quiescent Power Supply Current CMOS Input Levels VIN = VCC or GND VCC = Max. All Inputs Outputs Disabled — — 5 mA ICCQT Quiescent Power Supply Current TTL Input Levels VIH = 3.4V, VIL = 0V VCC = Max. All Inputs Outputs Disabled — — 1 mA/ input ICCD1 Dynamic Power Supply Current f = 10MHz fCP = 10MHz, 50% Duty Cycle VIH = VCC, VIL = GND Read Mode, Outputs Disabled COM'L. — — 100 mA MIL. — — 115 ICCD2 Dynamic Power Supply Current f = 20MHz fCP = 20MHz, 50% Duty Cycle VIH = VCC, VIL = GND Read Mode, Outputs Disabled COM'L. — — 200 MIL. — — 230 NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified above for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient temperature, and maximum loading. 3. Total supply current is the sum of the Quiescent current and the dynamic current and is calculated as follows: ICC = ICCQ + ICCQT (NT x DT) + ICCD (fOP) where: NT = Total # of quiescent TTL inputs DT = AC Duty cycle – % of time high (TTL) fOP = Operating frequency 11.7 mA 2552 tbl 22 21 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC PARAMETERS - 49C465A PROPAGATION DELAY TIMES 32-bit System Standalone Slice 64-bit “Generate only” Slice 64-bit System CODE ID=00 CODE ID=01 CODE ID=10 CODE ID=11 Lower Slice Upper Slice Parameter Description Com. Mil. Com. Mil. Com. Mil. Com. Mil. Number Parameter From To Name Input (edge) Output (edge) Max. Max. Max. Max. Max. Max. Max. Max. Unit Refer to Timing Diagram Figure GENERATE (WRITE) PARAMETERS 01 t BC BEN CBO 15 20 02 t BM BEN MDOUT 15 20 03 t MC MDIN CBO — — 04 t PCC PCBI CBO — — — PXIN PERR 12 18 — — 12 18 CBO 14 18 14 18 14 18 MDOUT 12 18 — — 12 18 PERR 12 18 — — 12 14 18 — — — 05 t PPE 06 t SC 07 t SM 08 tSPE SDIN — — 15 20 15 20 ns — — — 15 20 15 20 ns — 15 18 — — — — ns 10 — — — 12 18 ns 7 12 18 ns — 14 18 ns 7 12 18 ns 7 18 12 18 ns — — 12 18 ns 8,10 DETECT (READ) PARAMETERS 09 t CE 10 t CME 11 t CSY 12 t ME 13 t MME 14 t MSY CBI ERR Low MERR = Low SYO MDIN ERR MERR SYO 15 20 — — — — 15 20 ns 8,10 12 18 — — 12 18 — — ns 8,10 12 18 — — — — 12 18 ns 8,10 16 20 — — — — 16 20 ns 8,10 16 20 — — 12 18 12 18 ns 8,10 CORRECT (READ) PARAMETERS 15 t CS 16 t MP 17 t MS 18 t MSY 19 t PCS CBI MDIN PCBI SDOUT 16 20 — — — — 16 20 ns 8,11 Px 18 22 — — 18 22 18 22 ns 8,11 SDOUT 14 18 — — — — — — ns 8,11 SYO 16 20 — — 12 18 12 18 ns 8,11 SDOUT — — — — 13 18 — — ns 11 DIAGNOSTIC PARAMETERS 20 t CLR CLEAR = Low SDOUT 15 20 — — 15 20 15 20 ns 15 21 t MIS MODE ID 15 20 — — 15 20 15 20 ns 15 SDOUT 2552 tbl 24 NOTES: 1. Where “edge” is not specified, both HIGH and LOW edges are implied. 2. BOLD indicates critical system parameters. 11.7 22 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC PARAMETERS - 49C465A PROPAGATION DELAY TIMES FROM LATCH ENABLES Parameter Description Number Parameter Name From Input (edge) Mil. Refer to Max. Max. Unit Timing Diagram Figure Px SDOUT SYO * * * * * * 16 13 16 18 18 15 20 18 20 22 22 20 ns ns ns ns ns ns 13 8, 10, 11 8 8, 11 8, 10, 11 8, 10 To Output CBO Com.’l. (edge) 22 23 24 25 26 27 t MLC t MLE t MLME t MLP t MLS t MLSY 28 29 t PLS t PLP PLE = PLE = LOW LOW SDOUT Px * * 10 13 12 18 ns ns 8, 11 8, 11 30 31 t SLC t SLM SLE = SLE = HIGH HIGH CBO MDOUT * * 16 12 20 18 ns ns 7, 9 7, 9 MLE = HIGH ERR MERR NOTE: 2552 tbl 27 “*” = Both HIGH and LOW edges are implied. ENABLE AND DISABLE TIMES Parameter Description Mil. Refer to Number Parameter Name From Input 32 33 t BESZx t BESxZ BEN = HIGH LOW SDOUT * Hi – Z 2 2 13 11 2 2 16 14 ns ns 8, 10, 11 34 35 t BEPZx t BEPxZ BEN = HIGH LOW POUT * Hi – Z 2 2 13 11 2 2 16 14 ns ns 8, 11 36 37 t CECZx t CECxZ LOW HIGH CBO * Hi – Z 2 2 13 11 2 2 16 14 ns ns 7, 9 38 39 t MEMZx t MEMxZ LOW HIGH MDOUT * Hi – Z 2 2 13 11 2 2 16 14 ns ns 7, 9 8, 10 40 41 t SESZx t SESxZ LOW HIGH SDOUT * Hi – Z 2 2 13 11 2 2 16 14 ns ns 8, 10 7, 9 CBOE = MOE = SOE = (edge) To Output (edge) Com’l. Min. NOTE: “*” = Delay to both edges. Max. Min. Max. Unit Timing Diagram Figure 2552 tbl 28 11.7 23 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES SET-UP AND HOLD TIMES - 49C465A Parameter Description Number Parameter Name From Input To Output (edge) (edge) Com.’l. Mil. Refer to Min. Min. Unit Timing Diagram Figure 42 43 44 45 t SSLS t SSLH t MMLS t MMLH SDIN Set-up SDIN Hold MDIN Set-up MDIN Hold * * * * before SLE = LOW after SLE = LOW before MLE =LOW after MLE = LOW 3 3 3 3 4 4 4 4 ns ns ns ns 7, 9 7, 9 8, 10, 11 8, 10, 11 46 47 t CMLS t CMLH CBI Set-up CBI Hold * * before MLE = LOW after MLE = LOW 3 3 4 4 ns ns 8, 10, 11 8, 10, 11 48 49 50 51 52 53 t MPLS t MPLH t CPLS t CPLH t PCPLS t PCPLH MDIN Set-up MDIN Hold CBI Set-up CBI Hold PCBI Set-up PCBI Hold * * * * * * before PLE = HIGH after PLE = HIGH before PLE =HIGH after PLE = HIGH before PLE = HIGH after PLE = HIGH 10 0 10 0 10 0 12 0 12 0 12 0 ns ns ns ns ns ns — — — — — — 10 10 10 3 3 12 12 12 4 4 ns ns ns ns ns 15 15 15 15 15 DIAGNOSTIC SET-UP AND HOLD TIMES 54 55 56 57 58 t CSCS t MSCS t MLSCS t SESCS t SESCH CBI Set-up * MDIN Set-up * before SYNCLK=HIGH MLE Set-up =HIGH SCLKEN Set-up =LOW SCLKEN Hold =LOW after SYNCLK =HIGH NOTE: “*” = Where “edge” is not specified, both HIGH and LOW edges are implied. 2552 tbl 32 MINIMUM PULSE WIDTH Refer to Parameter Number 59 60 61 62 63 Minimum Pulse Width Name t CLEAR t MLE t PLE t SLE t SYNCLK Input Conditions Min. CLEAR LOW time Min. MLE HIGH time Min. PLE LOW time Min. SLE HIGH time Min. SYNCLK HIGH time to clear diag. registers to strobe new data to strobe new data to strobe new data to clock in new data Data = Valid MD, CBI = Valid SD = Valid SD = Valid SCKEN = LOW Com’l. Mil. Min. Min. 8 5 5 5 5 10 6 6 6 6 Timing Diagram Unit Figure ns ns ns ns ns 14 — — — 14 2552 tbl 33 Input Pulse Levels Input Rise/Fall Times GND to 3.0V 1V/ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 18 2552 tbl 34 11.7 24 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC PARAMETERS - 49C465 PROPAGATION DELAY TIMES 32-bit System Standalone Slice 64-bit “Generate only” Slice 64-bit System CODE ID=00 CODE ID=01 CODE ID=10 CODE ID=11 Lower Slice Upper Slice Parameter Description Com. Mil. Com. Mil. Com. Mil. Com. Mil. Number Parameter From To Name Input (edge) Output (edge) Max. Max. Max. Max. Max. Max. Max. Max. Unit Refer to Timing Diagram Figure GENERATE (WRITE) PARAMETERS 01 t BC BEN CBO 20 25 02 t BM BEN MDOUT 20 25 03 t MC MDIN CBO — — 04 t PCC PCBI CBO — — — PXIN PERR 15 20 — — 15 20 CBO 16 20 16 20 16 20 MDOUT 15 20 — — 15 20 PERR 15 20 — — 15 16 20 — — — 05 t PPE 06 t SC 07 t SM 08 tSPE SDIN — — 20 25 20 25 ns — — — 20 25 20 25 ns — 17 20 — — — — ns 10 — — — 15 20 ns 7 15 20 ns — 16 20 ns 7 15 20 ns 7 20 15 20 ns — — 15 20 ns 8,10 DETECT (READ) PARAMETERS 09 t CE 10 t CME 11 t CSY 12 t ME 13 t MME 14 t MSY CBI ERR = LOW MERR = LOW SYO MDIN ERR = LOW MERR = LOW SYO 20 24 — — — — 20 24 ns 8,10 15 20 — — 12 18 — — ns 8,10 15 20 — — — — 15 20 ns 8,10 20 24 — — — — 20 24 ns 8,10 18 22 — — 15 20 15 20 ns 8,10 CORRECT (READ) PARAMETERS 15 t CS 16 t MP 17 t MS 18 t MSY 19 t PCS CBI MDIN PCBI SDOUT 20 24 — — — — 20 24 ns 8,11 Px 20 26 — — 20 26 20 26 ns 8,11 SDOUT 16 20 — — — — — — ns 8,11 SYO 18 22 — — 15 20 15 20 ns 8,11 SDOUT — — — — 15 20 — — ns 11 DIAGNOSTIC PARAMETERS 20 t CLR CLEAR = LOW SDOUT 20 24 — — 20 24 20 24 ns 15 21 t MIS MODE ID SDOUT 20 24 — — 20 24 20 24 ns 15 NOTES: 1. Where “edge” is not specified, both HIGH and LOW edges are implied. 2. BOLD indicates critical system parameters. 11.7 2552 tbl 23 25 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC PARAMETERS - 49C465 PROPAGATION DELAY TIMES FROM LATCH ENABLES Parameter Description Number Parameter Name From Input (edge) Com.’l. Mil. Max. Max. Unit Timing Diagram Figure Px SDOUT SYO * * * * * * 20 15 20 20 20 18 24 20 24 25 25 22 ns ns ns ns ns ns 13 8, 10, 11 8 8, 11 8, 10, 11 8, 10 To Output (edge) CBO Refer to 22 23 24 25 26 27 t MLC t MLE t MLME t MLP t MLS t MLSY 28 29 t PLS t PLP PLE = PLE = LOW LOW SDOUT Px * * 12 16 16 20 ns ns 8, 11 8, 11 30 31 t SLC t SLM SLE = HIGH SLE = HIGH CBO MDOUT * * 20 15 24 20 ns ns 7, 9 7, 9 MLE = HIGH ERR MERR NOTE: 2552 tbl 25 “*” = Both HIGH and LOW edges are implied. ENABLE AND DISABLE TIMES Parameter Description Parameter Number Name From Input (edge) To Output Com’l. (edge) Min. Max. Mil. Min. Refer to Max. Unit Timing Diagram Figure 32 33 t BESZx t BESxZ BEN = HIGH LOW SDOUT * Hi – Z 2 2 15 13 2 2 18 16 ns ns 8, 10, 11 34 35 t BEPZx t BEPxZ BEN = HIGH LOW POUT * Hi – Z 2 2 15 13 2 2 18 16 ns ns 8, 11 36 37 t CECZx t CECxZ LOW HIGH CBO * Hi – Z 2 2 15 13 2 2 18 16 ns ns 7, 9 38 39 t MEMZx t MEMxZ LOW HIGH MDOUT * Hi – Z 2 2 15 13 2 2 18 16 ns ns 7, 9 8, 10 40 41 t SESZx t SESxZ LOW HIGH SDOUT * Hi – Z 2 2 15 13 2 2 18 16 ns ns 8, 10 7, 9 CBOE = MOE = SOE = NOTE: “*” = Delay to both edges. 2552 tbl 26 11.7 26 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES SET-UP AND HOLD TIMES - 49C465 Parameter Description Number Parameter Name From Input To (edge) Output Com.’l. (edge) Min. Mil. Refer to Min. Unit Timing Diagram Figure 42 43 44 45 t SSLS t SSLH t MMLS t MMLH SDIN Set-up SDIN Hold MDIN Set-up MDIN Hold * * * * before SLE =LOW after SLE = LOW before MLE =LOW after MLE = LOW 4 4 4 4 5 5 5 5 ns ns ns ns 7, 9 7, 9 8, 10, 11 8, 10, 11 46 47 t CMLS t CMLH CBI Set-up CBI Hold * * before MLE =LOW after MLE = LOW 4 4 5 5 ns ns 8, 10, 11 8, 10, 11 48 49 t MPLS t MPLH MDIN Set-up MDIN Hold * * before PLE =HIGH after PLE = HIGH 12 0 15 0 ns ns — — 50 51 52 53 t CPLS t CPLH t PCPLS t PCPLH CBI Set-up CBI Hold PCBI Set-up PCBI Hold * * * * 12 0 12 0 15 0 15 0 ns ns ns ns — — — — 12 12 12 4 4 15 15 15 5 5 ns ns ns ns ns 15 15 15 15 15 before PLE =HIGH after PLE = HIGH before PLE =HIGH after PLE = HIGH DIAGNOSTIC SET-UP AND HOLD TIMES 54 55 56 57 58 t CSCS t MSCS t MLSCS t SESCS t SESCH CBI Set-up * MDIN Set-up * before SYNCLK=HIGH MLE Set-up = HIGH SCLKEN Set-up = LOW SCLKEN Hold = LOW after SYNCLK =HIGH NOTE: “*” = Where “edge” is not specified, both HIGH and LOW edges are implied. 2552 tbl 29 MINIMUM PULSE WIDTH Refer to Parameter Number 59 60 61 62 63 Minimum Pulse Width Name t CLEAR t MLE t PLE t SLE t SYNCLK Input Conditions Min. CLEAR LOW time to clear diag. registers Min. MLE HIGH time to strobe new data Min. PLE LOW time to strobe new data Min. SLE HIGH time to strobe new data Min. SYNCLK HIGH time to clock in new data Data = Valid MD, CBI = Valid SD = Valid SD = Valid SCLKEN = LOW Com’l. Mil. Timing Diagram Min. Min. Unit Figure 8 5 5 5 5 10 6 6 6 6 ns ns ns ns ns 14 — — — 14 2552 tbl 30 Input Pulse Levels Input Rise/Fall Times GND to 3.0V 1V/ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 18 2552 tbl 31 11.7 27 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TIMING DIAGRAMS — 32-BIT CONFIGURATION to 1 2 3 4 5 Parameter Name Propagation Delay From To Min./ Max. BEN t BESxZ min. BEN = Low to SDOUT Disabled min. t BESxZ max. BEN = Low to SDOUT Disabled max. t SESxZ min. SOE = Low to SDOUT Disabled min. t SESxZ max. SOE = Low to SDOUT Disabled max. t SSLS SDIN Set-up to SLEIN = Low min. t SSLH SDIN Hold to SLEIN = Low min. t SPE t SPE SDIN to PERROUT max. t PPE t PPE Px to PERROUT max. SDIN to MDOUT SLE = High to MDOUT max. t MEMZx MOE = Low to MDOUT Enabled max. t SC SDIN to CBO SLE = High to CBO max. t BESxZ t BESxZ SOE t SESxZ t SESxZ SD0–31 (OUTPUT) DATAIN t SSLS t SSLH SLE PN PERR t SM t SM (1) t SLM t SLM (1) max. MOE tMEMZx MD0–31 (INPUT) M DATAOUT = S DATAIN t SC t SLC (1) t SLC (1) max. CBOE t CECZx t CECZx CBOE = Low to CBO Enable max. CBO to 1 2 3 4 5 NOTE: 1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH. 2552 drw 19 Figure 7. 32-Bit Generate Timing 11.7 28 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TIMING DIAGRAMS — 32-BIT CONFIGURATION to 1 2 3 4 5 Parameter Name Propagation Delay From To Min./ Max. MOE t MEMxZ MD 0–31 (OUTPUT) t MEMxZ MOE = High to MDOUT Disabled max. t MMLS MDIN Set-up to MLE = Low min. t MMLH MDIN Hold to MLE = Low min. t CMLS Checkbit Set-up to MLE = Low min. t CMLH Checkbit Hold to MLE = Low min. t MSY t MSY t CSY MDIN to SYOOUT Checkbits in to SYOOUT MLE = High to SYOOUT max. t CSY t MLSY (1) MDIN to ERR = Low Checkbits in to ERR = Low MLE = High to ERR = Low(1) max. Valid DATAIN t MMLS t MMLH Valid Checkbits In CBI t CMLS t CMLH MLE t MLSY (1) max. max. SYO t ME t ME t CE t MLEx (1) t CE t MLEx(1) max. max. ERR t MME t MME t CME t MLMEx (1) t CME (1) t MLEMx MDIN to MERR = Low Checkbits in to MERR = Low MLE = High to MERR = Low (1) max. max. max. MERR to 1 2 3 4 5 NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil,) before MLE goes HIGH. 2552 drw 20 Figure 8. 32-Bit Detect Timing 11.7 29 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TIMING DIAGRAMS — 32-BIT CONFIGURATION to Propagation Delay From To Min./ Max. t MEMxZ MOE = High to MDOUT Disabled max. t MMLS MDIN Set-up to MLE = Low min. t MMLH MDIN Hold to MLE = Low min. t CMLS Checkbit Set-up to MLE = Low min. t CMLH Checkbit Hold to MLE = Low min. t MLS (1) t MLS (1) MLEIN = High to SDOUT t PLS (1) t PLS(1) PLE = Low to SDOUT t BESZx BEN = High to SDOUT Enabled max. t SESZx SOE = Low to SDOUT Enabled CBI to Corrected SDOUT MDIN to Corrected SDOUT max. MDIN to Parity Out MLE = High to Parity Out PLE = Low to Parity Out BEN = High to Parity Out SOE = Low to Parity Out max. 1 2 3 4 5 Parameter Name MOE t MEMxZ MD 0–31 Valid DATAIN (OUTPUT) t MMLS t MMLH Valid Checkbits In CBI t CMLS t CMLH MLE (1) max. PLE (1) max. BEN t BESZx SOE t SESZx t CS t CS t MS t MS max. max. Corrected DATAOUT t MP t MP t MLP t MLP t PLP t PLP t BEPZx t BEPZx t SEP t SEP max. max. max. max. Parity Out P0–3 to 1 2 3 4 5 NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil.) before MLE goes HIGH. 2552 drw 21 Figure 9. 32-Bit Correct Timing 11.7 30 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TIMING DIAGRAMS — 64-BIT CONFIGURATION BOTH 465s to 1 2 3 5 Parameter Name 4 Propagation Delay From To Min./ Max. BEN SOE t SESxZ t SESxZ SD (L & U) t SESxZ min. SOE = High to SDOUT Disabled min. t SESxZ max. SOE = High to SDOUT Disabled max. t SSLS SDIN Set-up to SLEIN = Low min. t SSLH SDIN Hold to SLEIN = Low min. t PPE Px to PERR max. t SM SDIN to MDOUT max. t SLM (1) SLE = High to MDOUT MOE = Low to MDOUT Enabled BEN to MDOUT max. SD Lower In to CBO (1) SLEIN = High to CBO max. t SLC (1) t CECZx CBOE = Low to CBO Enabled max. DATAIN (OUTPUT) t SSLS t SSLH SLE Px Parity In t PPE PERR t SM MOE t SLM (1) t MEMZx t MEMZx t BEM MD (L & U) t BEM (INPUT) max. max. MD DATAOUT = SD DATAIN t SC t SC t SLC (1) max. CBOE t CECZx LOWER 465 Partial Checkbits Out CBO 3 Inter-chip delay (Design dependent) UPPER 465 Partial Checkbits In PCBI t PCC t PCC PCBI to CBO max. Final Checkbits Out CBO to 1 2 3 4 5 NOTE: 1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes HIGH. 2552 drw 22 Figure 10. 64-Bit Generate Timing — (64-Bit Cascading System) 11.7 31 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TIMING DIAGRAMS — 64-BIT CONFIGURATION BOTH 465s to 1 2 3 4 5 Parameter Name Propagation Delay From To Min./ Max. MOE t MEMxZ MD (L) t MEMxZ MOE = High to MDOUT Disabled max. t MMLS MDIN Set-up to MLE = Low min. t MMLH MDIN Hold to MLE = Low min. t CMLS CBI Set-up to MLE = Low min. t CMLH CBI Hold to MLE = Low min. t MLS(1) MLE = High to SDOUT t BESZx t BESZx BEN = High to SDOUT Enabled max. t SESZx t SESZx SOE = Low to SDOUT Enabled max. t MSY t MSY t CSY MD Lower In to SYOOUT CBI to SYO MLE = High to SYO max. t CSY Valid DATAIN (OUTPUT) t MMLS t MMLH Valid Checkbits In CBI t CMLS t CMLH MLE t MLS (1) (1) max. BEN SOE LOWER 465 Corrected DATAOUT SD0–31 t MLSY t MLSY max. max. Partial Syndrome Out SYO 3 UPPER 465 Inter-chip delay (Design dependent) Partial Syndrome In CBI t CME t MLME t CME (1) t MLME (1) CBI to MERR MLE = High to MERR max. CBI to ERR MLE = High to ERR max. MDIN to ERR MDIN to MERR max. max. MERR t CE t CE t MLE (1) t MLE (1) max. ERR t ME t ME t MME t MME MD (U) (OUTPUT) to max. Valid DATAIN 1 2 3 4 5 NOTE: 1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes HIGH. 2552 drw 23 Figure 11. 64-Bit Detect Timing 11.7 32 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TIMING DIAGRAMS — 64-BIT CONFIGURATION 64-BIT U/L Slice to 1 2 3 4 5 Parameter Name Propagation Delay From To Min./ Max. t MEMxZ MOE = High to MDOUT Disabled max. t MMLS MDIN Set-up to MLE = Low min. t MMLH MDIN Hold to MLE = Low min. t CMLS CBI Set-up to MLE = Low min. t CMLH CBI Hold to MLE = Low min. t MLS (1) MLEIN = High to SDOUT (1) max. MOE t MEMxZ MD 0–31 (OUTPUT) Valid DATAIN t MMLS t MMLH Valid Checkbits In CBI t CMLS t CMLH MLE (1) t MLS Partial checkbits in from Upper PCBI PLE t PLS (1) t PLS (1) (1) PLE = Low to SDOUT max. t BESZx BEN = High to SDOUT Enabled max. t SESZx SOE = Low to SDOUT Enabled CBI to Corrected SDOUT CBI to Syndrome MDIN to Corrected SDOUT max. CBI to Syndrome MDIN to Syndrome MDIN to Parity Out MLE = High to Parity Out PLE = Low to Parity Out BEN = High to Parity Out SOE = Low to Parity Out max. BEN t BESZx SOE t SESZx t CS t CS t CSY t CSY t MS t MS max. max. max. Corrected DATAOUT SD0–31 t CSY t CSY t MSY t MSY t MP t MP t MLP t MLP t PLP t PLP t BEPZx t BEPZx t SEP t SEP P0–3 Parity Out SYO Partial Syndrome Out to 1 2 3 4 max. max. max. max. max. max. 5 NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes HIGH. 2552 drw 24 Figure 12. 64-Bit Correct Timing (Lower Slice) 11.7 33 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TIMING DIAGRAMS — 64-BIT CONFIGURATION 64-BIT U/L Slice to 1 2 3 4 5 Parameter Name Propagation Delay From To Min./ Max. MOE t MEMxZ MD 0–31 (OUTPUT) t MEMxZ MOE = High to MDOUT Disabled max. t MMLS MDIN Set-up to MLE = Low min. t MMLH MDIN Hold to MLE = Low min. t CMLS CBI Set-up to MLE = Low min. t CMLH CBI Hold to MLE = Low min. t MLS(1) MLEIN = High to SDOUT t PLS(1) PLE = Low to SDOUT t BESZx BEN = High to SDOUT Enabled max. t SESZx max. Valid DATAIN t MMLS t MMLH Valid Checkbits In CBI t CMLS t CMLH MLE t MLS (1) (1) max. PLE t PLS (1) (1) max. BEN t BESZx SOE t SESZx t CS t CS t MS t MS t MSY t MSY SOE = Low to SDOUT Enabled CBI to Corrected SDOUT MDIN to Corrected SDOUT MDIN to Corrected SDOUT max. max. max. Corrected DATAOUT SD0–31 t MP MDIN to Parity Out max. t MLP t MP t MLP MLE = High to Parity Out max. t PLP t PLP PLE = Low to Parity Out BEN = High to Parity Out SOE = Low to Parity Out max. t BEPZx t BEPZx t SEP t SEP max. max. Parity Out P0–3 Partial Checkbits/ Syndrome Out SYO to 1 2 3 4 5 NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes HIGH. 2552 drw 25 Figure 13. 64-Bit Correct Timing (Upper Slice) 11.7 34 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TIMING DIAGRAMS — 64-BIT CONFIGURATION SINGLE 465 SOE to 1 2 3 4 5 Parameter Name Propagation Delay From To Min./ Max. (SOE = Tied high) Valid DATAIN SD Bus t SSLS t SSLH t SSLS SDIN Set-up to SLEIN = Low min. t SSLH SDIN Hold to SLEIN = Low min. t SLC(1) SLE = High to CBO t MMLS MDIN Set-up to MLEIN = Low MDIN Hold to MLEIN = Low min. max. t MLC(2) Bits 32–63 to CBO Bits 0–31 to CBO (2) MLEIN = High to CBO t CECZx CBOE = Low to CBO Enabled max. SLE (1) t SLC MOE (1) max. (MOE = Tied high) Valid DATAIN MD Bus t MMLS t MMLH t MMLH min. MLE t SC t SC t MC t MLC (2) t MC max. max. CBOE t CECZx Final Checkbits Out CBO to 1 2 3 4 5 NOTE: 1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH. 2. Assumes that Memory Data is valid at least 4ns (Com.) before MLE goes HIGH. 2552 drw 26 Figure 14. 64-Bit Single Chip "Generate Only" Timing 11.7 35 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TIMING DIAGRAMS — DIAGNOSTIC TIMING 465 to 1 2 3 4 5 Parameter Name Min./ Max. Propagation Delay From To Checkbits In CBI t CSCS CBI Set-up to SYNCLK = High t MSCS t MSCS MDIN Set-up to SYNCLK = High min. t MLSCS t MLSCS MLE = High Set-up to SYNCLK = High min. t SESCS SCLKEN Set-up to SYNCLK = High min. t SESCH SCLKEN = Hold After SYNCLK = High min. t CSCS Memory DataIN MD Bus MLE SCLKEN t SESCS t SESCH SYNCLK t SYNCLK t SYNCLK t SCS t SCS t CLEAR min. t CLEAR SCLKEN Pulse Width SCLKEN = High to SDOUT CLEAR Pulse Width t CLR CLEAR = Low to SDOUT max. max. min. CLEAR t CLR Valid DataOUT SD Bus to 1 2 3 4 5 2552 drw 27 Figure 15. 32-Bit Diagnostic Timing 11.7 36 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS V CC SWITCH POSITION 7.0V 500Ω Pulse Generator Switch Open Drain Disable Low Closed Enable Low V OUT VIN Test Open All Other Tests D.U.T. 50pF RT 2552 tbl 35 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 2552 drw 30 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 2552 drw 32 2552 drw 31 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED tPLZ 2552 drw 33 SWITCH OPEN 3.5V 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 1.5V 0V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V 2552 drw 34 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 11.7 37 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT 49C465 Device Type XX Speed XX Package X Process/ Temperature Range BLANK B Commercial (0°C to +70°C) Military (–55°C to +125°C) PQF G Plastic Quad Flatpack Pin Grid Array BLANK A Standard Speed High Speed 49C465 32-Bit Flow-thru EDC 2552 drw 35 11.7 38