TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 D Supply Current of 220 nA (Typ) D Precision Supply Voltage Supervision D D D D D D Applications Include – Applications Using Low-Power DSPs, Microcontrollers, or Microprocessors – Portable/Battery-Powered Equipment – Intelligent Instruments – Wireless Communication Systems – Notebook Computers – Automotive Systems Range: 1.8 V, 2.5 V, 3.0 V, 3.3 V Power-On Reset Generator With Selectable Delay Time of 10 ms or 200 ms Push/Pull RESET Output (TPS3836), RESET Output (TPS3837), or Open-Drain RESET Output (TPS3838) Manual Reset 5-Pin SOT-23 Package Temperature Range –40°C to 85°C TPS3836, TPS3838 DBV PACKAGE (TOP VIEW) CT 1 GND 2 MR 3 5 VDD 4 RESET description The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. TPS3837 DBV PACKAGE (TOP VIEW) During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage VIT. CT 1 GND 2 MR 3 5 VDD 4 RESET When CT is connected to GND a fixed delay time of typical 10 ms is asserted. When connected to VDD the delay time is typically 200 ms. When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. All the devices of this family have a fixed-sense threshold voltage VIT set by an internal voltage divider. The TPS3836 has an active-low push-pull RESET output. The TPS3837 has active-high push-pull RESET, and TPS3838 integrates an active-low open-drain RESET output. TPS3836K33 VDD MSP430 VCC CT Xin RESET RST MR T Xout GND VSS Quartz 32 kHz Lithium Battery 3.6 V TYPICAL OPERATING CIRCUIT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 description (continued) The product spectrum is designed for supply voltages of 1.8 V, 2.5 V, 3 V, and 3.3 V. The circuits are available in a 5-pin SOT-23 package. The TPS3836, TPS3837, TPS3838 families are characterized for operation over a temperature range of –40°C to 85°C. PACKAGE INFORMATION TA –40°C 40 C to 85 85°C C DEVICE NAME TPS3836E18DBVR† TPS3836E18DBVT‡ THRESHOLD VOLTAGE SYMBOL 1.71 V PDNI TPS3836J25DBVR† TPS3836H30DBVR† TPS3836J25DBVT‡ TPS3836H30DBVT‡ 2.25 V PDSI 2.79 V PHRI TPS3836L30DBVR† TPS3836K33DBVR† TPS3836L30DBVT‡ TPS3836K33DBVT‡ 2.64 V PCAI 2.93 V PDTI TPS3837E18DBVR† TPS3837J25DBVR† TPS3837E18DBVT‡ TPS3837J25DBVT‡ 1.71 V PDOI 2.25 V PDRI TPS3837L30DBVR† TPS3837K33DBVR† TPS3837L30DBVT‡ TPS3837K33DBVT‡ 2.64 V PCBI 2.93 V PDUI TPS3838E18DBVR† TPS3838J25DBVR† TPS3838E18DBVT‡ TPS3838J25DBVT‡ 1.71 V PDQI 2.25 V PDPI TPS3838L30DBVR† TPS3838K33DBVR† TPS3838L30DBVT‡ TPS3838K33DBVT‡ 2.64 V PCCI 2.93 V PDVI † The DBVR passive indicates tape and reel of 3000 parts. ‡ The DBVT passive indicates tape and reel of 250 parts. ORDERING INFORMATION TPS383 6 E 18 DBV R Reel Package Nominal Supply Voltage Typical Reset Threshold Voltage Functionality Family FUNCTION TABLE TPS3836, TPS3837, TPS3838 MR VDD > VIT RESET§ RESET¶ L 0 L H L 1 L H H 0 L H H L H 1 § TPS3836 and TPS3838 ¶ TPS3837 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 functional block diagram VDD CT R3 MR C1 R1 + S1 Reset Logic and Timer – Reset (TPS3837-Push-Pull) Reset (TPS3836-Push-Pull TPS3838-Open-Drain) R2 C2 S2 Band-Gap Reference S3 C3 Refresh Timer GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 timing diagram A B C D E F G VDD VIT < 1.1 V t MR t RESET t Undefined Output 4 td POST OFFICE BOX 655303 td • DALLAS, TEXAS 75265 td Undefined Output TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 mA Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t=1000 h continuously DISSIPATION RATING TABLE PACKAGE TA <25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DBV 437 mW 3.5 mW/ºC 280 mW 227 mW recommended operating conditions at specified temperature range MIN Supply voltage, VDD Input voltage, VI MAX UNIT 1.6 6 V 0 VDD + 0.3 V 0.7 × VDD High-level input voltage, VIH V 0.3 × VDD Low-level input voltage, VIL Input transition rise and fall rate at MR, ∆t/∆V Operating free-air temperature range, TA –40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 100 ns/V 85 °C 5 TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VOH VOL Vhys IIH RESET (TPS3836) IOH = –2 mA IOH = –3 mA RESET (TPS3837) VDD = 1.8 V, VDD = 3.3 V, IOH = –1 mA IOL = –2 mA RESET (TPS3836/8) VDD = 1.8 V, VDD = 3.3 V, IOL = 1 mA IOL = 2 mA RESET (TPS3837) VDD = 3.3 V, VDD = 6 V, IOL = 2 mA IOL = 3 mA TPS3836/8 VDD ≥ 1.1 V, IOL = 50 µA TPS3837 VDD ≥ 1.1 V, IOH = –50 µA High level output voltage High-level Low level output voltage Low-level Power-up Power up reset voltage (see Note 2) VIT TEST CONDITION VDD = 3.3 V, VDD = 6 V, Negative-going N ti i iinputt th threshold h ld voltage (see Note 3) IIL Low-level Low level in input ut current IOH High-level output current IDD Supply Su ly current Input capacitance at MR, CT MAX 0.8 × VDD 04 0.4 0.8 × VDD V 1.71 1.74 2.18 2.25 2.29 TPS383xH30 2.70 2.79 2.85 TPS383xL30 2.56 2.64 2.69 TPS383xK33 2.84 2.93 2.99 1.7 V < VIT < 2.5 V 30 2.5 V < VIT < 3.5 V 40 3.5 V < VIT < 5 V 50 MR (see Note 4) MR = 0.7 × VDD, CT CT = VDD = 6 V MR (see Note 4) MR = 0 V, VDD = 6 V CT CT = 0 V, TPS3838 VDD = VIT + 0.2 V, VDD > VIT, VDD = 6 V VOH = VDD VDD < 3 V VDD > VIT, VDD < VIT VDD = 6 V –40 –60 –25 VDD > 3 V VI = 0 V to VDD V 0.2 1.66 TA = –40°C 40 C to 85°C 85 C UNIT V TPS383xJ25 Internal pullup resistor at MR CI TYP TPS383xE18 Hysteresis at VDD input in ut High-level High level in input ut current MIN –130 –200 –25 V mV –100 µA 25 nA –340 µA 25 nA 25 nA 220 400 250 450 10 15 nA µA 30 kΩ 5 pF NOTES: 2. The lowest voltage at which RESET output becomes active. tr, VDD ≥ 15 µs/V 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal. 4. If manual reset is unused, MR should be connected to VDD to minimize current consumption. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25_C PARAMETER tw Pulse width TEST CONDITIONS MIN TYP MAX UNIT at VDD VIH = VIT + 0.2 V, VIL = VIT – 0.2 V 6 µs at MR VDD ≥ VIT + 0.2 V, VIH = 0.7 × VDD VIL = 0.3 × VDD, 1 µs switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25_C PARAMETER TEST CONDITIONS MIN VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = GND, See timing diagram td tPHL tPLH Delay time VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = VDD , See timing diagram Propagation Pro agation (delay) time, high high-to-low-level to low level out output ut Propagation Pro agation (delay) time, low low-to-high-level to high level out output ut VDD to RESET delay (TPS3836 TPS3838) (TPS3836, VDD to RESET delay (TPS3837) tPHL Propagation (delay) time, high-to-low-level output MR to RESET delay (TPS3836, TPS3838) tPLH Propagation (delay) time, low-to-high-level output MR to RESET delay (TPS3837) 5 TYP MAX 10 UNIT 15 ms 100 200 300 VIL = VIT – 0.2 V, VIH = VIT + 0.2 V 10 VIL = 1.6 V VIL = VIT – 0.2 V, VIH = VIT + 0.2 V 50 VIL = 1.6 V 50 10 VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIL = 0.7 × VDD µs µs 0.1 µs 0.1 µs TYPICAL CHARACTERISTICS Table of Graphs FIGURE IDD IMR Supply current vs Supply voltage 1 Manual reset current vs Manual reset voltage 2 VOL VOH Low-level output voltage vs Low-level output current 3 High-level output voltage vs High-level output current 4 Normalized reset threshold voltage vs Free-air temperature 5 Minimum pulse duration at VDD vs VDD Threshold overdrive 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE MANUAL RESET CURRENT vs MANUAL RESET VOLTAGE 10 100 MR = Open CT = GND VDD = 6 V CT = GND IMR – Manual Reset Current – µA TA = 85°C IDD – Supply Current – µA 8 TA = 25°C 6 TA = 0°C 4 TA = –40°C 2 0 0 TA = –40°C –100 TA = 0°C –200 TA = 25°C –300 TA = 85°C –400 –500 0 2 4 6 –2 0 VDD – Supply Voltage – V Figure 1 6 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.0 2.0 VDD = 2 V MR = OPEN CT = GND VOH – High-Level Output Voltage – V VOL – Low-Level Output Voltage – V 4 Figure 2 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 1.5 TA = 25°C 1.0 TA = 85°C TA = 0°C 0.5 TA = –40°C 0.0 VDD = 2 V MR = OPEN CT = GND 1.5 TA = 85°C TA = 25°C 1.0 TA = 0°C 0.5 TA = –40°C 0.0 0 1 2 3 4 5 6 7 IOL – Low-Level Output Current – mA Figure 3 8 2 VMR – Manual Reset Voltage – V POST OFFICE BOX 655303 0 1 2 3 4 IOH – High-Level Output Current – mA Figure 4 • DALLAS, TEXAS 75265 5 TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 TYPICAL CHARACTERISTICS NORMALIZED RESET THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE Normalized Reset Threshold Voltage – V 1.001 1 0.999 0.998 0.997 CT = GND, MR = Open 0.996 0.995 –40 –15 10 35 60 TA – Free-Air Temperature – °C 85 Figure 5 MINIMUM PULSE DURATION AT VDD vs VDD THRESHOLD OVERDRIVE 22 MR = Open CT = GND TA = 25°C Minimum Pulse Duration at VDD – µs 20 18 16 14 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VDD – Threshold Overdrive – V Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 MECHANICAL DATA DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE 0,50 0,30 0,95 5 0,20 M 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0°–8° 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/E 05/99 NOTES: A. B. C. D. 10 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-178 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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