WM8786 24-bit, 192kHz Stereo ADC DESCRIPTION FEATURES The WM8786 is a stereo audio ADC with differential inputs designed for high performance recordable media applications. Data is provided as a PCM output. Stereo 24-bit multi-bit sigma-delta ADCs are used with digital audio output word lengths of 16 to 32 bits, and sampling rates from 8kHz to 192kHz. The device also has a high pass filter to remove residual DC offsets. The device is hardware controlled. Pin programming provides access to all features including oversampling rate, audio format, powerdown, master/slave control and digital signal manipulation. The device is supplied in a 20-lead SSOP package. SNR 111dB (‘A’ weighted @ 48kHz) THD -102dB (at -0.1dB) Sampling Frequency: 8 – 192kHz Hardware Control Interface Master or Slave Clocking Mode Programmable Audio Data Interface Modes - I2S, Left, Right Justified or DSP - 24-Bit Word Length Supply Voltages - Analogue 4.5 to 5.5V - Digital core: 2.7V to 3.6V 20-lead SSOP package APPLICATIONS Recordable DVD Players Personal Video Recorders High End Sound Cards Studio Audio Processing Equipment BLOCK DIAGRAM VREF AINL+ ADC AINL- DIGITAL FILTER WM8786 DIGITAL FILTER CLOCK CIRCUITRY 50k VREFGND VREF MS0 AUDIOF0 AUDIOF1 OSR0 OSR1 CONTROL INTERFACE http://www.cirrus.com AUDIO INTERFACE ADC AINR- LRCLK BCLK DOUT MCLK 50k AGND AINR+ DVDD AVDD VMID DGND Copyright Cirrus Logic, Inc., 2004–2015 (All Rights Reserved) Rev 4.4 FEB ‘15 WM8786 TABLE OF CONTENTS DESCRIPTION ................................................................................................................ 1 FEATURES ..................................................................................................................... 1 APPLICATIONS .............................................................................................................. 1 BLOCK DIAGRAM.......................................................................................................... 1 TABLE OF CONTENTS .................................................................................................. 2 PIN CONFIGURATION ................................................................................................... 3 ORDERING INFORMATION ........................................................................................... 3 PIN DESCRIPTION ......................................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ................................................................................. 5 RECOMMENDED OPERATING CONDITIONS .............................................................. 5 ELECTRICAL CHARACTERISTICS ............................................................................... 6 TERMINOLOGY ..................................................................................................................... 7 SIGNAL TIMING REQUIREMENTS ............................................................................... 8 SYSTEM CLOCK TIMING ...................................................................................................... 8 AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA ............................................... 8 AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA ................................................... 9 POWER-ON RESET .............................................................................................................10 DIGITAL FILTER CHARACTERISTICS........................................................................ 11 TERMINOLOGY ....................................................................................................................11 HIGH PASS FILTER TRANSFER CHARACTERISTIC ..........................................................11 FILTER RESPONSES .................................................................................................. 12 SINGLE RATE 48K................................................................................................................12 DUAL RATE 96K ...................................................................................................................13 QUAD RATE 192K ................................................................................................................15 HIGH PASS FILTER ..............................................................................................................16 DEVICE DESCRIPTION ............................................................................................... 18 INTRODUCTION ...................................................................................................................18 DIGITAL AUDIO INTERFACE ...............................................................................................18 MASTER AND SLAVE MODE OPERATION ............................................................................................................................ 18 AUDIO DATA FORMATS ......................................................................................................................................................... 19 AUDIO INTERFACE CONTROL............................................................................................................................................... 21 OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY ....................21 MASTER CLOCK AND AUDIO SAMPLE RATES ..................................................................22 MLCK AND LRCLK PHASE RELATIONSHIP ........................................................................22 APPLICATIONS INFORMATION .................................................................................. 23 RECOMMENDED EXTERNAL COMPONENTS ....................................................................23 RECOMMENDED PCB LAYOUT ...........................................................................................24 PACKAGE DIMENSIONS ............................................................................................. 25 IMPORTANT NOTICE .................................................................................................. 26 REVISION HISTORY .................................................................................................... 27 2 Rev 4.4 WM8786 PIN CONFIGURATION 1 20 AINR+ AINL- 2 19 AINR- VREFGND 3 18 VREF AVDD 4 17 VMID AGND 5 16 DGND LRCLK 6 15 DVDD DOUT 7 14 OSR1 BCLK 8 13 OSR0 MCLK 9 12 AUDIOF1 10 11 AUDIOF0 AINL+ MS0 ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8786GEDS/V -40C to +85C 20-lead SSOP (Pb-free) MSL3 260oC WM8786GEDS/RV -40C to +85C 20-lead SSOP, (Pb-free, tape and reel) MSL3 260oC Note: Reel quantity = 2,000 Rev 4.4 3 WM8786 PIN DESCRIPTION 4 PIN NAME TYPE DESCRIPTION 1 AINL+ Analogue Input Left Channel Positive Input 2 AINL- Analogue Input Left Channel Negative Input 3 VREFGND Analogue Reference 4 AVDD Supply Analogue Supply 5 AGND Supply Analogue Ground (return path for AVDD) 6 LRCLK Digital Input / Output 7 DOUT Digital Output 8 BCLK Digital Input / Output 9 MCLK Digital Input Master Clock 10 MS0 (pull down pad) Digital Input Master/Slave Control 0 = Slave Mode Audio Interface 1 = Master Mode Audio Interface @ 256fs (or @128fs in quad rate) 11 AUDIOF0 Digital Input 12 AUDIOF1 Digital Input Audio Format Selection 00 = 24 bit right justified audio data format 01 = 24 bit left audio data format 10 = I2S audio data format 11 = DSP audio data format 13 OSR0 (pull down pad) Digital Input 14 OSR1 Digital Input 15 DVDD Supply Digital Supply 16 DGND Supply Digital Ground (return path for DVDD) Midrail Voltage Decoupling Capacitor Negative Reference Connection Audio Interface Left / Right Clock ADC Digital Audio Data Audio Interface Bit Clock Oversampling Rate Control 00 = Single rate (48kHz) 01 = Dual rate (96kHz) 10 = Quad rate (192kHz) 11 = Not valid 17 VMID Analogue Output 18 VREF Analogue Reference 19 AINR- Analogue Input Right Channel Negative Input 20 AINR+ Analogue Input Right Channel Positive Input Reference Voltage Decoupling Capacitor Rev 4.4 WM8786 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Cirrus tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage MIN MAX -0.3V +3.63V -0.3V +7V Voltage range digital inputs DGND -0.3V DVDD + 0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Master Clock Frequency 40MHz Operating temperature range, TA -40C +85C Storage temperature after soldering -65C +150C Notes 1. Analogue and digital grounds must always be within 0.3V of each other. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range DVDD 2.7 3.6 V Analogue supply range AVDD 4.5 5.5 V Ground Rev 4.4 DGND,AGND 0 V 5 WM8786 ELECTRICAL CHARACTERISTICS Test Conditions DVDD = 3.3V, AVDD = 5.0V, TA = +25°C, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ADC Performance Full Scale Input Signal Level (for ADC 0dB Input) 2.0 Vrms Input resistance 10 kΩ Input capacitance 10 pF 111 dB Signal to Noise Ratio Signal to Noise Ratio Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Dynamic Range SNR SNR SNR THD THD DNR Channel Level Matching Power Supply Rejection Ratio (AVDD, DVDD) PSRR A-weighted, @ fs = 48kHz 102 Unweighted, @ fs = 48kHz 108 A-weighted, @ fs = 96kHz 111 Unweighted, @ fs = 96kHz 108 A-weighted, @ fs = 192kHz 111 Unweighted, @ fs = 192kHz 108 1kHz, -0.1dB Full Scale @ fs = 48kHz -102 1kHz, -0.1dB Full Scale @ fs = 96kHz -102 1kHz, -0.1dB Full Scale @ fs = 192kHz -102 1kHz, -0.1dB Full Scale @ fs = 48kHz 0.0008 1kHz, -0.1dB Full Scale @ fs = 96kHz 0.0008 1kHz, -0.1dB Full Scale @ fs = 192kHz 0.0008 -60dBFS 102 dB dB -92 dB 0.0025 % 111 dB 20kHz signal 0.1 dB 100mV (peak-peak) 1kHz 50 dB 100mV (peak-peak) 20Hz to 20kHz 45 Digital Logic Levels (CMOS Levels) Input LOW level VIL Input HIGH level VIH 0.3 x DVDD V +1 µA 0.7 x DVDD Input leakage current -1 Input capacitance V ±0.2 5 Output LOW VOL IOL=-1mA Output HIGH VOH IOH= 1mA 0.9 x DVDD Midrail Reference Voltage VMID AVDD to VMID and VMID to VREFGND –3% Potential Divider Resistance RVMID AVDD to VMID and VMID to GND Buffered Reference Voltage VREF pF 0.1 x DVDD V V Analogue Reference Levels 6 AVDD/2 +3% 50 –3% 0.8 x AVDD V kΩ +3% V Rev 4.4 WM8786 Test Conditions DVDD = 3.3V, AVDD = 5.0V, TA = +25°C, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Supply Current Analogue supply current 27 mA Digital supply current 5 mA Power Down 22 uA Note: 1. The VMID and VREF pins should be decoupled with a 10µF electrolytic capacitor (ESR < 1.5Ω across all operating temperatures) and a 0.1µF ceramic capacitor. Device operation with other decoupling is not recommended, and may affect performance. TERMINOLOGY 1. 2. 3. 4. 5. Signal-to-noise ratio (dB) – Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter, except where noted. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible, it may affect dynamic specification values. Rev 4.4 7 WM8786 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK tMCLKY Figure 1 System Clock Timing Requirements Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25°C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT System Clock Timing Information MCLK System clock cycle time TMCLKY 25 MCLK duty cycle TMCLKDS 60:40 ns 40:60 AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA BCLK (Output) tDL LRCLK (Output) tDD A DOUT Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25°C, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN LRCLK propagation delay from BCLK falling edge tDL DOUT propagation delay from BCLK falling edge tDDA TYP MAX UNIT 0 10 ns 0 11 ns Audio Data Input Timing Information 8 Rev 4.4 WM8786 AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA BCLK tBCY LRCLK tLRSU tLRH tDD DOUT Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25°C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT BCLK cycle time tBCY 25 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 DOUT propagation delay from BCLK falling edge tDD 0 Audio Data Input Timing Information Rev 4.4 ns 11 ns 9 WM8786 POWER-ON RESET The WM8786 has an internal power-on reset circuit. The reset sequence is entered at power-on or power-up (DVDD). Until the internal reset is removed, DOUT is forced to zero. DOUT remains zero for a count equal to 32 sample clocks, after power up. (This count is driven by MCLK and is independent of any external LRCLK). MCLK 4 MCLK Periods INTERNAL RESET RELEASE POR Figure 4 POR Circuit DVDD 1.8V MCLK Power Supply Delay 4 Mclks POR 32/fs DOUT Valid Audio Data Figure 5 POR Timing 10 Rev 4.4 WM8786 DIGITAL FILTER CHARACTERISTICS The WM8786 digital filter characteristics scale with sample rate. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Sample Rate (Single Rate - 48Hz typically) Passband +/- 0.005dB 0 -6dB 0.454fs 0.5fs Passband Ripple +/- 0.005 Stopband Stopband Attenuation dB 0.546fs f > 0.546fs -85 Group Delay dB 32/fs s ADC Sample Rate (Dual Rate - 96kHz typically) Passband +/- 0.005dB 0 -6dB 0.454fs 0.5fs Passband Ripple +/- 0.005 Stopband Stopband Attenuation dB 0.546fs f > 0.546fs -85 Group Delay dB 32/fs s ADC Sample Rate (Quad Rate - 192kHz typically) Passband +/- 0.005dB 0 0.25fs -3dB 0.45fs -6dB 0.5fs Passband Ripple +/- 0.005 Stopband Stopband Attenuation dB 0.75fs f > 0.75fs -85 Group Delay dB 10/fs s Hz ADC High Pass Filter Corner Frequency -3dB 3.7 -0.5dB 10.4 -0.1dB 21.6 Table 1 Digital Filter Characteristics TERMINOLOGY 1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region HIGH PASS FILTER TRANSFER CHARACTERISTIC The high pass filter response is defined by the following polynomial: H(z) 1 - z -1 1 - (1 - )z -1 where α = 2-11 for single rate (48k) mode α = 2-12 for dual rate (96k) mode α = 2-13 for quad rate (192k) mode Rev 4.4 11 WM8786 FILTER RESPONSES SINGLE RATE 48K 0 Response (dB) -20 -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (Fs) Figure 6 Single Rate 48k Filter Response 0 Response (dB) -20 -40 -60 -80 -100 0.4 0.45 0.5 0.55 0.6 Frequency (Fs) Figure 7 Single Rate 48k Filter Response 12 Rev 4.4 WM8786 0.15 Response (dB) 0.1 0.05 0 -0.05 -0.1 -0.15 0 0.1 0.2 0.3 0.4 0.5 Frequency (Fs) Figure 8 Single Rate 48k Filter Response DUAL RATE 96K 0 Response (dB) -20 -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (Fs) Figure 9 Dual Rate 96k Filter Response Rev 4.4 13 WM8786 0 Response (dB) -20 -40 -60 -80 -100 0.4 0.45 0.5 0.55 0.6 Frequency (Fs) Figure 10 Dual Rate 96k Filter Response 0.15 Response (dB) 0.1 0.05 0 -0.05 -0.1 -0.15 0 0.1 0.2 0.3 0.4 0.5 Frequency (Fs) Figure 11 Dual Rate 96k Filter Response 14 Rev 4.4 WM8786 QUAD RATE 192K 0 Response (dB) -20 -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (Fs) Figure 12 Quad Rate 192k Filter Response 0 Response (dB) -20 -40 -60 -80 -100 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (Fs) Figure 13 Quad Rate 192k Filter Response Rev 4.4 15 WM8786 -2.5 -2.6 Response (dB) -2.7 -2.8 -2.9 -3 -3.1 -3.2 -3.3 -3.4 -3.5 0 0.1 0.2 0.3 0.4 0.5 Frequency (Fs) Figure 14 Quad Rate 192k Filter Response HIGH PASS FILTER 5 Response (dB) 0 -5 -10 -15 -20 0 0.0005 0.001 0.0015 0.002 Frequency (Fs) Figure 15 Single Rate 48k High Pass Filter Response 16 Rev 4.4 WM8786 5 Response (dB) 0 -5 -10 -15 -20 0 0.0005 0.001 0.0015 0.002 0.0015 0.002 Frequency (Fs) Figure 16 Dual Rate 96k High Pass Filter Response 5 Response (dB) 0 -5 -10 -15 -20 0 0.0005 0.001 Frequency (Fs) Figure 17 Quad Rate 192k High Pass Filter Response Rev 4.4 17 WM8786 DEVICE DESCRIPTION INTRODUCTION The WM8786 is a high performance stereo audio ADC designed for demanding recording applications such as DVD recorders, studio mixers, PVRs, and AV amplifiers. The WM8786 consists of stereo line level inputs, followed by a sigma-delta modulator and digital filtering. The WM8786 uses a multi-bit high-order oversampling architecture delivering high SNR operating at oversampling ratios from 128fs to 32fs according to the sample rate. Sample rates from 8kHz to 192kHz are supported. The WM8786 supports master clock rates from 128fs to 768fs. The digital filter is a high performance linear phase FIR filter. The digital filters are optimised for each sample rate. Also included is a high pass filter to remove residual DC offsets from the input signal. The output from the ADC is available on a configurable digital audio interface. It supports a number of audio data formats including I2S, Left justified and Right justified or DSP, and can operate in master or slave modes. The WM8786 functionality is controlled in hardware via specific pins. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. The WM8786 can be powered down to reduce system power consumption. DIGITAL AUDIO INTERFACE The digital audio interface uses three pins: DOUT: ADC data output LRCLK: ADC data alignment clock BCLK: Bit clock, for synchronisation The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always an output. BCLK and LRCLK may be inputs or outputs, depending whether the device is in Master or Slave mode (see Master and Slave Mode Operation, below). Four different audio data formats are supported: Left justified Right justified I2S DSP The data formats are described in Audio Data Formats, below. Refer to the Signal Timing Requirements section for timing information. MASTER AND SLAVE MODE OPERATION The WM8786 can be configured as either a master or slave mode device. As a master device the WM8786 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT. In slave mode, the WM8786 responds with data to clocks it receives over the digital audio interface. The mode can be selected using the MS0 pin. Master and slave modes are illustrated below. MS0 PIN STATUS INTERFACE FORMAT Low Slave High Master (@256fs in oversampling ratio = single or dual rate) High Master (@192fs in oversampling ratio = quad rate) Table 2 Control Interface Mode Selection 18 Rev 4.4 WM8786 BCLK WM8786 ADC BCLK DSP ENCODER/ DECODER LRCLK DOUT WM8786 ADC DSP ENCODER/ DECODER LRCLK DOUT Figure 18a Master Mode Figure 18b Slave Mode AUDIO DATA FORMATS In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DOUT 1 2 3 n-2 n-1 MSB n 1 LSB 2 3 n-2 n-1 MSB n LSB Figure 19 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DOUT 1 MSB 2 3 n-2 n-1 n LSB 1 2 3 MSB n-2 n-1 n LSB Figure 20 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Rev 4.4 19 WM8786 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK 1 BCLK 1 BCLK DOUT 1 2 3 n-2 n-1 n 1 LSB MSB 2 3 n-2 n-1 n LSB MSB Figure 21 I2S Justified Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on the 2nd rising edge of BCLK following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 22. In device slave mode, shown in Figure 23 it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. 1/fs 1 BCLK LRCLK BCLK LEFT CHANNEL DACDAT / ADCDAT 1 2 3 RIGHT CHANNEL n-2 n-1 MSB n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 22 DSP/PCM Mode Audio Interface (mode A, Master) 1/fs 1 BCLK 1 BCLK LRCLK falling edge can occur anywhere in this area BCLK LEFT CHANNEL DACDAT / ADCDAT 1 2 3 RIGHT CHANNEL n-2 n-1 MSB n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 23 DSP/PCM Mode Audio Interface (mode A, Slave) 20 Rev 4.4 WM8786 AUDIO INTERFACE CONTROL The audio interface is controlled using the AUDIOF0 and AUDIOF1 pins. Dynamically changing the audio format may cause erroneous operation of the interfaces and is therefore not recommended. All ADC data is signed 2’s complement. The length of the digital audio data is always 24 bits. AUDIOF1 PIN STATUS AUDIOF0 PIN STATUS AUDIO INTERFACE FORMAT Low Low 24-bit right justified Low High 24-bit left justified High Low 24-bit I2S High High 24-bit DSP Table 3 Audio Interface Format Selection OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY For correct operation of the device and optimal performance, the user must select the appropriate ADC modulator oversampling ratio. The oversampling ratio is selected using the OSR0 and OSR1 pins. OSR1 PIN STATUS OSR0 PIN STATUS OVERSAMPLING RATIO CONTROL Low Low Single Rate (128fs) Low High Dual Rate (64fs) High Low Quad Rate (32fs) High High Not Valid Table 4 Oversampling Ratio Selection The WM8786 can operate at sample rates from 8kHz to 192kHz. The WM8786 uses a sigma-delta modulator that operates at frequencies between 1.024MHz and 6.144MHz SAMPLING RATE (LRCLK) OVERSAMPLING RATIO SIGMA-DELTA MODULATOR FREQUENCY (MHZ) 1.024 8kHz Single Rate (128fs) 32kHz Single Rate (128fs) 4.096 44.1kHz Single Rate (128fs) 5.6448 48kHz Single Rate (128fs) 6.144 96kHz Dual Rate (64fs) 6.144 192kHz Quad Rate (32fs) 6.144 Table 5 Sigma-delta Modulator Frequency Rev 4.4 21 WM8786 MASTER CLOCK AND AUDIO SAMPLE RATES The Master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The WM8786 supports a wide range of master clock frequencies, and can generate many commonly used audio sample rates directly from the master clock. The following tables show the recommended Master clock frequencies for different sample rates. In Master Mode, with oversampling ratio = single rate or dual rate, Master clock frequency of 256 is supported. SAMPLING RATE (LRCLK) OVERSAMPLING RATIO MASTER CLOCK FREQUENCY (MHz) 32kHz Single Rate 8.192 44.1kHz Single Rate 11.2896 48kHz Single Rate 12.288 96kHz Dual Rate 24.576 256fs Table 6 Master Mode: Recommended Master Clock Frequency Selection In Master Mode, with oversampling ratio = quad rate, Master clock frequency of 192 is supported. SAMPLING RATE (LRCLK) OVERSAMPLING RATIO MASTER CLOCK FREQUENCY (MHz) 192kHz Quad Rate 24.576 128fs Table 7 Master Mode: Recommended Master Clock Frequency Selection In Slave Mode, Master clock frequencies of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs are supported. The WM8786 automatically detects the audio sample rate, in slave mode. SAMPLING RATE (LRCLK) OVERSAMPLING RATIO MASTER CLOCK FREQUENCY (MHz) 128fs 192fs 256fs 384fs 512fs 768fs 32kHz Single Rate - - 8.192 12.288 16.384 24.576 44.1kHz Single Rate - - 11.2896 16.9344 22.5792 33.8688 48kHz Single Rate - - 12.288 18.432 24.576 36.864 96kHz Dual Rate - - 24.576 36.864 - - 192kHz Quad Rate 24.576 36.864 - - - - Table 8 Slave Mode: Recommended Master Clock Frequency Selection MLCK AND LRCLK PHASE RELATIONSHIP The WM8786 does not require a specific phase relationship between MLCK and LRCLK. If the relationship between MCLK and LRCLK changes by more than +/-8 BCLKs in a 64 BLCK frame, the WM8786 will attempt to re-synchronise During re-synchronisation, data samples may be dropped or duplicated. 22 Rev 4.4 WM8786 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 24 External Component Diagram Rev 4.4 23 WM8786 RECOMMENDED PCB LAYOUT The WM8786 is sensitive to the routing of the ground return currents for VREF, VMID, and AVDD; care should be taken to ensure that these currents do not interfere. Figure 25 below shows a recommended PCB layout (with high frequency current paths) for the WM8786 that will demonstrate datasheet performance: To DVDD Supply VMID DGND AGND DVDD VREF VREFGND C5 C6 AVDD C2 + C4 + C3 C1 Top Layer Copper To AVDD Supply Bottom Layer Copper Via Figure 25 Recommended PCB Layout for VREF, VMID, AVDD and DVDD Decoupling Notes: 1. High frequency noise on VREF is decoupled through C5, and the return path should be directly to VREFGND. 2. The route from the negative terminal of C6 to C5 and then to VREFGND should be made on the top layer only and should not connect to the ground flood on the top layer. This ensures that the VREF return current is returned directly to VREFGND as shown by the black arrows. 3. The negative terminal of C6 should be connected to the ground plane on the underside of the board only. 4. High frequency noise on VMID is decoupled through C4, and the return path should be directly to AGND. 5. Via to bottom layer on VMID used to connect to bottom layer route to positive terminal of C3. 6. The route from C4 to AGND should be made on the top layer only. This ensures that the VMID return current is returned to AGND as shown by the white arrows. 7. AVDD is decoupled to AGND through C1. The ground return currents are not shown in this diagram. 8. DVDD is decoupled to DGND through C2. The ground return currents are not shown in this diagram. 9. DGND should not be connected directly to the ground flood on the top layer under the WM8786. This will ensure that noise in the digital ground does not interfere with the critical routing of VREF and VMID. 10. Bottom layer ground flood not shown for clarity. 11. See the WM8786 Evaluation Board for an example of this layout in use. 24 Rev 4.4 WM8786 PACKAGE DIMENSIONS DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) b DM0015.C e 20 11 E1 1 E GAUGE PLANE 10 D A A2 c A1 L 0.25 L1 -C0.10 C Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 o 0 Dimensions (mm) NOM --------1.75 0.30 ----7.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 SEATING PLANE MAX 2.0 ----1.85 0.38 0.25 7.50 8.20 5.60 0.95 o 8 JEDEC.95, MO -150 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. Rev 4.4 25 WM8786 IMPORTANT NOTICE Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (“Cirrus”) are sold subject to Cirrus’s terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus products. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or services does not constitute Cirrus’s approval, license, warranty or endorsement thereof. Cirrus gives consent for copies to be made of the information contained herein only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus, and only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design and SoundClear are among the trademarks of Cirrus. Other brand and product names may be trademarks or service marks of their respective owners. Copyright © 2004–2015 Cirrus Logic, Inc. All rights reserved. 26 Rev 4.4 WM8786 REVISION HISTORY DATE REV 26/01/15 4.4 Rev 4.4 DESCRIPTION OF CHANGES Clarifications to external component requirements PAGE CHANGED BY 7, 23 PH 27