WOLFSON WM8785_06

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WM8785
24-Bit, 192kHz Stereo ADC
DESCRIPTION
FEATURES
The WM8785 is a stereo audio ADC with differential inputs
designed for high performance recordable media applications.
Data is provided as a PCM output.
•
•
•
•
•
•
Stereo 24-bit multi-bit sigma-delta ADCs are used with digital
audio output word lengths of 16 to 32 bits, and sampling rates
from 8kHz to 192kHz. The device has a selectable high pass
filter to remove residual DC offsets. The device also supports a
TDM bus for data out.
The device is controlled via a 2 or 3 wire serial interface. The
interface provides access to all features including oversampling
rate, audio format, powerdown, master/slave control and digital
signal manipulation. The device is supplied in a 20-lead SSOP
package.
•
•
•
SNR 111dB (‘A’ weighted @ 48kHz)
THD -102dB (at -0.1dB)
Sampling Frequency: 8 – 192kHz
2 or 3 Wire Microprocessor Control Interface
Master or Slave Clocking Mode
Programmable Audio Data Interface Modes
- I2S, Left, Right Justified or DSP
- 16/20/24/32 bit Word Lengths
A TDM bus is supported for data out
Supply Voltages
- Analogue 4.5 to 5.5V
- Digital core: 2.7V to 3.6V
20-lead SSOP package
APPLICATIONS
•
•
•
•
Recordable DVD Players
Personal Video Recorders
High End Sound Cards
Studio Audio Processing Equipment
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, December 2006, Rev 4.1
Copyright ©2006 Wolfson Microelectronics plc
WM8785
Production Data
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 7
SIGNAL TIMING REQUIREMENTS .......................................................................8
SYSTEM CLOCK TIMING ............................................................................................. 8
AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA ...................................... 8
AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA ......................................... 9
CONTROL INTERFACE TIMING – 3-WIRE MODE ...................................................... 9
CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 10
POWER-ON RESET ................................................................................................... 11
DIGITAL FILTER CHARACTERISTICS ...............................................................12
TERMINOLOGY .......................................................................................................... 12
FILTER RESPONSES ..........................................................................................13
DEVICE DESCRIPTION.......................................................................................16
INTRODUCTION ......................................................................................................... 16
DIGITAL AUDIO INTERFACE ..................................................................................... 16
DIGITAL HIGH PASS .................................................................................................. 20
DATA OUT PIN DISABLE ........................................................................................... 21
CONTROL INTERFACE.............................................................................................. 21
TIME DIVISION MULTIPLEXED DATA OUT............................................................... 22
TDM SELECTION ....................................................................................................... 23
OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY.......... 26
MASTER CLOCK AND AUDIO SAMPLE RATES........................................................ 26
MLCK AND LRCLK PHASE RELATIONSHIP.............................................................. 27
POWER DOWN CONTROL ........................................................................................ 27
REGISTER MAP ......................................................................................................... 28
APPLICATIONS INFORMATION .........................................................................29
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 29
PACKAGE DIMENSIONS ....................................................................................30
IMPORTANT NOTICE ..........................................................................................31
ADDRESS: .................................................................................................................. 31
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PIN CONFIGURATION
AINL+
1
20
AINR+
AINL-
2
19
AINR-
VREFGND
3
18
VREF
AVDD
4
17
VMID
AGND
5
16
DGND
LRCLK
6
15
DVDD
DOUT
7
14
NC
BCLK
8
13
CSB
MCLK
9
12
SDIN
10
11
SCLK
NC
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
WM8785GEDS/V
-25°C to +85°C
20-lead SSOP
(Pb-free)
MSL3
260oC
WM8785GEDS/RV
-25°C to +85°C
20-lead SSOP
(Pb-free, tape and reel)
MSL3
260oC
Note:
Reel quantity = 2,000
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PIN DESCRIPTION
PIN
NAME
1
AINL+
Analogue Input
TYPE
Left Channel Positive Input
DESCRIPTION
2
AINL-
Analogue Input
Left Channel Negative Input
3
VREFGND
4
Analogue Reference
Negative Reference Connection
AVDD
Supply
Analogue Supply
5
AGND
Supply
Analogue Ground (return path for AVDD)
6
LRCLK
Digital Input / Output
Audio Interface Left / Right Clock
7
DOUT
Digital Output
ADC Digital Audio Data
8
BCLK
Digital Input / Output
Audio Interface Bit Clock
Digital Input
Master Clock
9
MCLK
10
NC
11
NC
No Connection
SCLK
Digital Input
Control Interface Clock Input / 2 wire output
12
SDIN
Digital Input / Output
Control Interface Data Input
13
CSB
Digital Input
Chip Select / Control Interface Format Selection / 3 wire address select
14
NC
NC
No connection
15
DVDD
Supply
Digital Supply
16
DGND
Supply
Digital Ground (return path for DVDD)
17
VMID
Analogue Output
Midrail Voltage Decoupling Capacitor
18
VREF
Analogue Reference
Reference Voltage Decoupling Capacitor
19
AINR-
Analogue Input
Right Channel Negative Input
20
AINR+
Analogue Input
Right Channel Positive Input
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
MIN
MAX
Digital supply voltage
CONDITION
-0.3V
+3.63V
Analogue supply voltage
-0.3V
+7V
Voltage range digital inputs
DGND -0.3V
DVDD + 0.3V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
Master Clock Frequency
40MHz
Operating temperature range, TA
-25°C
+85°C
Storage temperature after soldering
-65°C
+150°C
Note: Analogue and digital grounds must always be within 0.3V of each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range
DVDD
2.7
3.6
V
Analogue supply range
AVDD
4.5
5.5
V
Ground
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DGND,AGND
0
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ELECTRICAL CHARACTERISTICS
Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Performance
Full Scale Input Signal Level
(for ADC 0dB Input)
2.0
Vrms
Input resistance
10
kΩ
Input capacitance
10
pF
111
dB
Unweighted,
@ fs = 48kHz
108
dB
A-weighted,
@ fs = 96kHz
111
dB
Unweighted,
@ fs = 96kHz
108
dB
A-weighted,
@ fs = 192kHz
111
dB
Unweighted,
@ fs = 192kHz
108
dB
1kHz, -0.1dB Full Scale
@ fs = 48kHz
-102
1kHz, -0.1dB Full Scale
@ fs = 96kHz
-102
dB
1kHz, -0.1dB Full Scale
@ fs = 192kHz
-102
dB
1kHz, -0.1dB Full Scale
@ fs = 48kHz
0.0008
1kHz, -0.1dB Full Scale
@ fs = 96kHz
0.0008
%
1kHz, -0.1dB Full Scale
@ fs = 192kHz
0.0008
%
Signal to Noise Ratio (Note
1,2,4)
Signal to Noise Ratio (Note
1,2,4)
Signal to Noise Ratio (Note
1,2,4)
Total Harmonic Distortion
Total Harmonic Distortion
Dynamic Range
SNR
SNR
SNR
THD
THD
DNR
Channel Level Matching
Power Supply Rejection Ratio
PSRR
A-weighted,
@ fs = 48kHz
-60dBFS
102
102
-92
0.0025
dB
%
111
dB
20kHz signal
0.1
dB
1kHz 100mVpp, applied
to AVDD, DVDD
50
dB
20Hz to 20kHz
100mVpp
45
dB
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
Input HIGH level
VIH
0.3 x DVDD
0.7 x DVDD
Input leakage current
-1
Input capacitance
±0.2
+1
5
Output LOW
VOL
IOL=1mA
Output HIGH
VOH
IOH= -1mA
0.9 x DVDD
–3%
V
V
µA
pF
0.1 x DVDD
V
V
Analogue Reference Levels
Midrail Reference Voltage
VMID
AVDD to VMID and
VMID to VREFGND
Potential Divider Resistance
RVMID
AVDD to VMID and
VMID to GND
Buffered Reference Voltage
VREF
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AVDD/2
+3%
50
–3%
0.8 x AVDD
V
kΩ
+3%
V
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Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Current
Analogue supply current
27
mA
Digital supply current
5
mA
Power Down
22
uA
Note:
1.
VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce
performance.
TERMINOLOGY
1.
Signal-to-noise ratio (dB) – Ratio of output level with 1kHz full scale input, to the output level with all zeros into the
digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these
results).
2.
Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally
a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it.
(e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3.
THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4.
Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
5.
All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter, except
where noted. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than
are found in the Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible,
it may affect dynamic specification values
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock cycle time
TMCLKY
25
MCLK duty cycle
TMCLKDS
60:40
ns
40:60
AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
LRCLK propagation delay from BCLK falling edge
tDL
DOUT propagation delay from BCLK falling edge
tDDA
TYP
MAX
UNIT
0
10
ns
0
11
ns
Audio Data Input Timing Information
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AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
25
ns
LRCLK set-up time to BCLK rising edge
tLRSU
10
ns
LRCLK hold time from BCLK rising edge
tLRH
10
DOUT propagation delay from BCLK falling edge
tDD
0
ns
11
ns
CONTROL INTERFACE TIMING – 3-WIRE MODE
tCSL
tCSH
CSB
tCSS
tSCY
tSCH
tSCS
tSCL
SCLK
LSB
SDIN
tDSU
tDHO
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DVDD = 3.3V, DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise
stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
tSCS
80
ns
SCLK pulse cycle time
tSCY
200
ns
SCLK pulse width low
tSCL
80
ns
SCLK pulse width high
tSCH
80
ns
SDIN to SCLK set-up time
tDSU
40
ns
SCLK to SDIN hold time
tDHO
40
ns
CSB pulse width low
tCSL
40
ns
CSB pulse width high
tCSH
40
ns
CSB rising to SCLK rising
tCSS
40
tps
4
Pulse width of spikes that will be suppressed
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ns
6
ns
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CONTROL INTERFACE TIMING – 2-WIRE MODE
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t1
t9
t7
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DVDD = 3.3V, DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise
stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
SCLK Low Pulse-Width
t1
80
5
MHz
SCLK High Pulse-Width
t2
80
us
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
SDIN, SCLK Rise Time
t6
300
ns
SDIN, SCLK Fall Time
t7
300
ns
Setup Time (Stop Condition)
t8
Data Hold Time
t9
Pulse width of spikes that will be suppressed
tps
Program Register Input Information
SCLK Frequency
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0
ns
ns
600
4
ns
900
ns
6
ns
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POWER-ON RESET
The WM8785 has an internal power-on reset circuit. The reset sequence is entered at power-on or
power-up (DVDD). Until the internal reset is removed, DOUT is forced to zero. DOUT remains zero
for a count equal to 32 sample clocks, after power up. (This count is driven by MCLK and is
independent of any external LRCLK).
Figure 6 POR Circuit
Figure 7 POR Timing
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DIGITAL FILTER CHARACTERISTICS
The WM8785 digital filter characteristics scale with sample rate.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Sample Rate (Single Rate – 48KHz typically)
Passband
+/- 0.005dB
0
-6dB
0.454fs
0.5fs
Passband Ripple
+/- 0.005
Stopband
Stopband Attenuation
dB
0.546fs
f > 0.546fs
-85
Group Delay
dB
32/fs
s
ADC Sample Rate (Dual Rate - 96kHz typically)
Passband
+/- 0.005dB
0
-6dB
0.454fs
0.5fs
Passband Ripple
+/- 0.005
Stopband
Stopband Attenuation
dB
0.546fs
f > 0.546fs
-85
Group Delay
dB
32/fs
s
ADC Sample Rate (Quad Rate - 192kHz typically)
Passband
+/- 0.005dB
0
0.25fs
-3dB
0.45fs
-6dB
0.5fs
Passband Ripple
+/- 0.005
Stopband
Stopband Attenuation
f > 0.75fs
Group Delay
High Pass Filter Corner
Frequency
dB
0.75fs
-3dB
-85
dB
10/fs
s
3.7
Hz
-0.5dB
10.4
-0.1dB
21.6
TERMINOLOGY
1.
Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band)
2.
Pass-band Ripple – any variation of the frequency response in the pass-band region
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FILTER RESPONSES
SINGLE RATE 48k
0
Response (dB)
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (Fs)
Figure 8 Single Rate 48k Filter Response
0
Response (dB)
-20
-40
-60
-80
-100
0.4
0.45
0.5
0.55
0.6
Frequency (Fs)
Figure 9 Single Rate 48k Filter Response
0.15
Response (dB)
0.1
0.05
0
-0.05
-0.1
-0.15
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 10 Single Rate 48k Filter Response
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DUAL RATE 96k
0
Response (dB)
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (Fs)
Figure 11 Dual Rate 96k Filter Response
0
Response (dB)
-20
-40
-60
-80
-100
0.4
0.45
0.5
0.55
0.6
Frequency (Fs)
Figure 12 Dual Rate 96k Filter Response
0.15
Response (dB)
0.1
0.05
0
-0.05
-0.1
-0.15
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 13 Dual Rate 96k Filter Response
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QUAD RATE 192k
0
Response (dB)
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (Fs)
Figure 14 Quad Rate 192k Filter Response
0
Response (dB)
-20
-40
-60
-80
-100
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (Fs)
Figure 15 Quad Rate 192k Filter Response
-2.5
-2.6
-2.7
Response (dB)
-2.8
-2.9
-3
-3.1
-3.2
-3.3
-3.4
-3.5
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 16 Quad Rate 192k Filter Response
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DEVICE DESCRIPTION
INTRODUCTION
The WM8785 is a high performance stereo audio ADC designed for demanding recording
applications such as DVD recorders, studio mixers, PVRs, and AV amplifiers. The WM8785 consists
of stereo line level inputs, followed by a sigma-delta modulator and digital filtering.
The WM8785 uses a multi-bit high-order oversampling architecture delivering high SNR operating at
oversampling ratios from 128fs to 32fs according to the sample rate. Sample rates from 8kHz to
192kHz are supported. The WM8785 supports master clock rates from 128fs to 768fs.
The digital filter is a high performance linear phase FIR filter. The digital filters are optimised for each
sample rate. Also included is a selectable high pass filter to remove residual DC offsets from the
input signal.
The output from the ADC is available on a configurable digital audio interface. It supports a number
of audio data formats including I2S, Left justified and Right justified or DSP, and can operate in
master or slave modes.
The WM8785 can be controlled through a 2 wire or 3 wire MPU control interface. It is fully compatible
and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. A TDM
bus is supported for multiplexing data output.
The WM8785 can be powered down under software control to reduce system power consumption.
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
•
DOUT: ADC data output
•
•
LRCLK: ADC data alignment clock
BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT
and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with
left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left
or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the
BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always
an output. BCLK and LRCLK maybe inputs or outputs depending whether the device is in Master or
Slave mode, (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
•
Left justified
•
•
•
Right justified
I 2S
DSP
They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for
timing information.
MASTER AND SLAVE MODE OPERATION
The WM8785 can be configured as either a master or slave mode device. As a master device the
WM8785 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT.
In slave mode, the WM8785 responds with data to clocks it receives over the digital audio interface.
The mode can be selected by setting MCR=000 (see Table below). Master and slave modes are
illustrated below.
Figure 17a Master Mode
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Figure 17b Slave Mode
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AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 18 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 19 Right Justified Audio Interface (assuming n-bit word length)
2
In I S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 20 I2S Justified Audio Interface (assuming n-bit word length)
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In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 21 and Figure
22. In device slave mode, Figure 23 and Figure 24, it is possible to use any length of frame pulse
less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period
before the rising edge of the next frame pulse.
Figure 21 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
Figure 22 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)
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Figure 23 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)
Figure 24 DSP/PCM Mode Audio Interface (mode B, LRP=1, Slave)
AUDIO INTERFACE CONTROL
The register bits controlling the audio interface are summarised below. Note that dynamically
changing the software format may cause erroneous operation of the interfaces and is therefore not
recommended.
All ADC data is 2’s complement. The length of the digital audio data is programmable at 16/20/24 or
32 bits, as shown below. The ADC digital filters process data using 24 bits. If the WM8785 is
programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data. If the device is
programmed to output 32 bits then it packs the LSBs with zeros.
In master mode LRCLK and BCLK are generated on chip. In slave mode they are received from an
external source.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R0 (00h)
Sample Rate
and Digital Audio
Interface Format
6:5
FORMAT
10
Audio Data Format Select
11: DSP Format
10: I2S Format
01: Left justified
00: Right justified
R1 (01h)
Digital Audio
Interface Format
and TDM
1:0
WL
10
Audio Data Word Length
11: 32 bits (see Note)
10: 24 bits
01: 20 bits
00: 16 bits
2
LRP
0
right, left and I S modes –
LRCLK polarity
1 = invert LRCLK polarity
0 = normal LRCLK polarity
2
DSP Mode – A/B select
1 = MSB is available on 1st
BCLK rising edge after LRC
rising edge (mode B)
0 = MSB is available on 2nd
BCLK rising edge after LRC
rising edge (mode A)
3
BCLKINV
0
BCLK invert bit (for master and
slave modes)
0 = BCLK not inverted
1 = BCLK inverted
4
LRSWAP
0
Left/Right channel swap
1 = swap left and right DAC
data in audio interface
0 = output left and right data as
normal
Table 1 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual
word length is 24 bits.
DIGITAL HIGH PASS
The high pass filter can be enabled using the HPFL and HPFR bits (see digital filter characteristics)
REGISTER
ADDRESS
R2(02h)
HPfilter ,
Output
disable,
Power down,
Mono mode
BIT
LABEL
DEFAULT
DESCRIPTION
0
HPFR
1
Digital High Pass Filter, Right Channel
0 = HPF Off
1 = HPF On
1
HPFL
1
Digital High Pass Filter, Left Channel
0 = HPF Off
1 = HPF On
Table 2 Oversampling Ratio Selection
The high pass filter should only be disabled for procedures such as DC offset calibration. It should be
noted that the output range of the ADC with a DC level applied and HPF disabled is as follows:
Maximum code: 7FDFB0
Minimum code: 802033
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DATA OUT PIN DISABLE
To prevent any communication problems on the Audio Interface, the interface can be disabled
(DOUT tristated and floating) using the SDODIS bit.
REGISTER
ADDRESS
R2(02h)
HP Filter ,
Output
disable,
Power down,
Mono mode
BIT
2
LABEL
DEFAULT
SDODIS
0
DESCRIPTION
DOUT serial data pin disable
0 = DOUT pin enabled
1 = DOUT pin off (high impedance)
Table 3 Oversampling Ratio Selection
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8785 is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each
control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The
CSB pin is sampled at power-up and selects the interface format. After power-up the pin is available
to latch in control data in 3-wire interface mode.
Figure 25 Control Interface Mode Selection
CSB PIN STATUS
INTERFACE FORMAT
Low
2 wire
High
3 wire
Table 4 Control Interface Mode Selection
SETUP/HOLD
TIME
tpusetup
250us
tpuhold
250us
Table 5 Control Interface Mode Selection
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3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.
latch
CSB
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
control register address
B5
B4
B3
B2
B1
B0
control register data bits
Figure 26 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8785 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address
of each register in the WM8785).
The WM8785 operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8785 and the R/W bit is ‘0’, indicating a write, then the WM8785 responds by
pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’,
the WM8785 returns to the idle condition and wait for a new start condition and valid address.
Once the WM8785 has acknowledged a correct address, the controller sends the first byte of control
data (B15 to B8, i.e. the WM8785 register address plus the first bit of register data). The WM8785
then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then
sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the
WM8785 acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8785 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
DEVICE ADDRESS
(7 BITS)
SDIN
RD / WR
BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
SCLK
START
register address and
1st register data bit
remaining 8 bits of
register data
STOP
Figure 27 2-Wire Serial Control Interface
The WM8785 device address is 0011010.
TIME DIVISION MULTIPLEXED DATA OUT
The WM8785 can be used to time division multiplex several data channels at once. For example, the
diagram below illustrates 4 devices connected to the same TDM bus. While one DOUT pin is driving
data, the others will be tri-stated.
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Figure 28 WM8785 in Time Division Multiplexing Setup
Note:
1.
TDM is only available in slave mode.
2.
Right justified mode is not supported
TDM SELECTION
The figure below indicates how data is multiplexed onto the TDM bus, in left justified mode. This
assumes we have 4 devices, and each device has 2 data channels:
•
LCHAN = left channel
•
RCHAN = right channel
Each channel is allocated 32 BCLKs
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Figure 29 WM8785 in Time Division Multiplexing Left Justified Mode
Up to 4 devices (8 channels) can be supported, which would require 256 BCLKs per sample.
(whereas 128 BCLKs will allow only 2 devices, or 4 channels). The table below shows the range of
BCLK frequencies required.
BCLK RATE
DEVICES THAT CAN BE SUPPORTED
OVER-SAMPLE RATIOS
SUPPORTED (SET BY OSR)
64 fs
128 fs
192 fs
1
1, 2
1, 2
Single/dual/quad rates all supported
256 fs
1, 2, 3, 4
Single rate only supported
Table 6 Range of BCLK Frequencies Required
Note: MCLK frequency must always be greater or equal to BCLK frequency
To avoid bus contention all chips on the TDM should be programmed before DOUT is released after
power up (DOUT is held at vss for 32 samples after power-up). Alternatively SDODIS should be set
while devices are programmed (to tri-state DOUT).
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Two registers must be set to enter TDM mode:
•
DEVNO[2:0] sets the number of devices which are on the bus
•
TDM[2:0] allocates a TDM slot to the device
REGISTER
ADDRESS
R1(h01)
Clocking, Sample
Rates,
Oversampling and
Signal Control
BIT
7:5
LABEL
DEFAULT
DEVNO[2:0]
000
DESCRIPTION
Number of TDM Devices
000 = 1 Device
001 = 2 Devices
010 = 3 Devices
011 = 4 Devices
Table 7 DEVNO
REGISTER
ADDRESS
R2(h02)
Clocking, Sample
Rates,
Oversampling and
Signal Control
BIT
8:6
LABEL
TDM[2:0]
DEFAULT
000
DESCRIPTION
Time Division Multiplexing
Device Select
000 = Device 0 (no delay)
001 = Device 1 (64 BCLK delay)
010 = Device 2 (128 BCLK
delay)
011 = Device 3 (192 BCLK
delay)
Table 8 TDM
Note: When TDM is not required, the register will default to 000 (normal operation)
The figures below indicate TDM mode for I2S and DSP mode A.
Figure 30 TDM Bus I2S Mode
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OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY
For correct operation of the device and optimal performance, the user must select the appropriate
ADC modulator oversampling ratio. The oversampling ratio is selected using the OSR[1:0] bits.
REGISTER
ADDRESS
R0(h00)
Signal Control
BIT
4:3
LABEL
OSR[1:0]
DEFAULT
00
DESCRIPTION
Oversampling Ratio
Control
00: Single Rate (128fs)
01: Dual Rate (64fs)
10: Quad Rate (32fs)
11: Not Valid
Table 9 Oversampling Ratio Selection
The WM8785 can operate at sample rates from 8kHz to 192kHz. The WM8785 uses a sigma-delta
modulator that operates at frequencies between 1.024MHz and 6.144MHz
SAMPLING RATE
(LRCLK)
OVERSAMPLING RATIO
SIGMA-DELTA
MODULATOR
FREQUENCY (MHZ)
8kHz
Single Rate (128fs)
1.024
32kHz
Single Rate (128fs)
4.096
44.1kHz
Single Rate (128fs)
5.6448
48kHz
Single Rate (128fs)
6.144
96kHz
Dual Rate (64fs)
6.144
192kHz
Quad Rate (32fs)
6.144
Table 10 Sigma-delta Modulator Frequency
MASTER CLOCK AND AUDIO SAMPLE RATES
Master clock frequencies of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs are supported. In slave mode
the WM8785 automatically detects the audio sample rate. In Master mode the master clock
frequency is selected using MCR[2:0] bits. This is described in table below.
REGISTER
ADDRESS
R0(h00)
Clocking, Sample
Rates,
BIT
2:0
LABEL
MCR[2:0]
DEFAULT
000
DESCRIPTION
Master/Slave Selection
000: Slave Mode
001: Master Mode, 128fs
010: Master Mode, 192fs
011: Master Mode, 256fs
100: Master Mode, 384fs
101: Master Mode, 512fs
110: Master Mode, 768fs
Table 11 Master Clock Frequency
The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The
WM8785 supports a wide range of master clock frequencies, and can generate many commonly
used audio sample rates directly from the master clock. Table 1 shows the recommended master
clock frequencies for different sample rates
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SAMPLING RATE
(LRCLK)
OVERSAMPLING
RATIO
MASTER CLOCK FREQUENCY (MHZ)
128fs
192fs
256fs
384fs
512fs
768fs
32kHz
Single Rate
-
-
8.192
12.288
16.384
24.576
44.1kHz
Single Rate
-
-
11.2896
16.9344
22.5792
33.8688
48kHz
Single Rate
-
-
12.288
18.432
24.576
36.864
96kHz
Dual Rate
-
-
24.576
36.864
-
-
192kHz
Quad Rate
24.576
36.864
-
-
-
-
Table 12 Slave Mode: Recommended Master Clock Frequency Selection
MLCK AND LRCLK PHASE RELATIONSHIP
The WM8785 does not require a specific phase relationship between MLCK and LRCLK. If the
relationship between MCLK and LRCLK changes by more than +/-8 BCLKs in a 64 BLCK frame, the
WM8785 will attempt to re-synchronise. During re-synchronisation, data samples may be dropped or
duplicated.
POWER DOWN CONTROL
The WM8785 can be powered down by setting the PWRDNL and PWRDNR bits. This is described in
the table below.
REGISTER
ADDRESS
R2(02h)
Signal control
BIT
LABEL
DEFAULT
DESCRIPTION
3
PWRDNR
0
Power Down Right Channel
0 = Power On
1 = Power Off
4
PWRDNL
0
Power Down Left Channel
0 = Power On
1 = Power Off
Table 13 Power Down Control
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REGISTER MAP
REGISTER ADDRESS REMARK BIT8 BIT7 BIT6 BIT5
FORMAT
BIT4
BIT3
R0(00h)
00_0000
Sample
Rate
And
Audio IF
Format
0
0
R1(01h)
00_0001
Audio IF
Format
And
TDM
0
DEVNO
R2(02h)
00_0010
Signal
Control
TDM
R7(07h)
00_0111
Reset
Writing to reg 7 will cause software reset
0
OSR
BIT2
BIT1
BIT0
MCR
DEFAULT
0_0000_0011
LRSWP
BCLKINV
LRP
WL
0_0000_1010
PWRDNL
PWRDNR
SDODIS
HPFL
HPFR
0_0000_0011
0_0000_0000
Table 14 Register Map for Control Interface
Notes:
1.
All unused register bits should be set to zero
2.
The interface will initiate SWRB whenever R7 is addressed, regardless of the data input.
3.
SWRB is released on the next register write or after 4 MCLK cycles (which ever occurs first).
4.
Until the SWRB is released, DOUT is forced to zero.
5.
DOUT remains zero for a count of 32 sample clocks SWRB is released, this count is driven by MCLK and is
independent of any external LRCLK.
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WM8785
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Notes:
1.
2.
3.
4.
AGND and DGND should be connected as close to the WM8785 as possible.
C1 to C6 should be placed as close to the WM8785 device as possible.
Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum performance, such as X7R. VMID and VREF decoupling
capacitors must be high quality electrolytic capacitors to achieve datasheet performance; ceramic capacitors are not acceptable.
An active input filter is required to achieve datasheet performance. The circuit shown is a tested inverting reference example.
Figure 31 External Component Diagram
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PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
b
DM0015.C
e
20
11
E1
1
E
GAUGE
PLANE
10
Θ
D
A A2
c
A1
L
0.25
L1
-C0.10 C
Symbols
A
A1
A2
b
c
D
e
E
E1
L
L1
θ
MIN
----0.05
1.65
0.22
0.09
6.90
7.40
5.00
0.55
o
0
REF:
Dimensions
(mm)
NOM
--------1.75
0.30
----7.20
0.65 BSC
7.80
5.30
0.75
1.25 REF
o
4
SEATING PLANE
MAX
2.0
----1.85
0.38
0.25
7.50
8.20
5.60
0.95
o
8
JEDEC.95, MO -150
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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