WM8711L w Internet Audio DAC with Integrated Headphone Amplifier DESCRIPTION FEATURES The WM8711L is a low power stereo DAC with an integrated headphone driver. The WM8711L is designed specifically for portable MP3 audio and speech players. The WM8711L is also ideal for MD, CD machines and DAT players. Stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8KHz to 96KHz are supported. Stereo audio outputs are buffered for driving headphones from a programmable volume control, line level outputs are also provided along with anti-thump mute and power up/down circuitry. The device is controlled via a 2 or 3 wire serial interface. The interface provides access to all features including volume controls, mutes, de-emphasis and extensive power management facilities. The device is available in a small 28lead QFN (5x5x0.9 mm body) package. A USB mode is provided where all audio rates can be derived from a single 12MHz or 24MHz MCLK, saving on the need for a PLL or multiple crystals. Audio Performance - DAC SNR 90dB (‘A’ weighted) at AVDD = 1.8V Low Power Headphone Playback - Down to 6mW at 1.8V - 1.42 – 3.6V Digital Supply Operation - 1.8 – 3.6 V Analogue Supply Operation DAC Sampling Frequency: 8KHz – 96KHz 2 or 3-Wire MPU Serial Control Interface Programmable Audio Data Interface Modes 2 - I S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths - Master or Slave Clocking Mode Stereo Audio Outputs Output Volume and Mute Controls Highly Efficient Headphone Driver 28-lead QFN (5x5x0.85 mm) package APPLICATIONS Portable MP3 Players CD and Minidisc Players BLOCK DIAGRAM WOLFSON MICROELECTRONICS plc Production Data, February 2013, Rev 4.6 Copyright 2013 Wolfson Microelectronics plc WM8711L Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS .................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 TABLE OF CONTENTS......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... 6 TERMINOLOGY ............................................................................................................... 7 POWER CONSUMPTION ...................................................................................... 8 HEADPHONE SNR VS AVDD ............................................................................... 9 ANALOGUE SUPPLY CURRENT VS AVDD ........................................................ 9 MASTER CLOCK TIMING ................................................................................... 10 DIGITAL AUDIO INTERFACE – MASTER MODE ......................................................... 10 DIGITAL AUDIO INTERFACE – SLAVE MODE ............................................................ 11 MPU INTERFACE TIMING ............................................................................................ 11 DEVICE DESCRIPTION ...................................................................................... 13 INTRODUCTION ............................................................................................................ 13 AUDIO SIGNAL PATH ................................................................................................... 14 DEVICE OPERATION .................................................................................................... 19 AUDIO DATA SAMPLING RATES ................................................................................. 27 ACTIVATING DSP AND DIGITAL AUDIO INTERFACE ................................................ 30 SOFTWARE CONTROL INTERFACE ........................................................................... 30 POWER DOWN MODES ............................................................................................... 32 REGISTER MAP .................................................................................................. 34 DIGITAL FILTER CHARACTERISTICS .............................................................. 38 DAC FILTER RESPONSES ........................................................................................... 38 DIGITAL DE-EMPHASIS CHARACTERISTICS ............................................................. 40 RECOMMENDED EXTERNAL COMPONENTS ................................................. 41 PACKAGE DIMENSIONS .................................................................................... 42 IMPORTANT NOTICE ......................................................................................... 43 ADDRESS: ..................................................................................................................... 43 REVISION HISTORY ........................................................................................... 44 w PD, Rev 4.6, February 2013 2 WM8711L Production Data 21 20 19 18 17 HPGND LOUT ROUT AVDD AGND VMID NC PIN CONFIGURATION 16 15 NC 22 14 RHPOUT RLINEIN 23 13 LHPOUT LLINEIN 24 12 HPVDD MODE 25 11 NC CSB 26 10 NC 9 DACLRC SDIN 27 8 DACDAT DCVDD 5 6 7 BCLK XTO 4 CLKOUT 3 DGND 2 DBVDD 1 XTI/MCLK SCLK 28 ORDERING INFORMATION DEVICE TEMPERATURE AVDD RANGE RANGE o WM8711CLGEFL -25 to 85 C WM8711CLGEFL/R -25 to 85 C 1.8 to 3.6V PACKAGE 28 QFN (Pb free) MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE MSL 1 260°C MSL 1 260°C 28 QFN o 1.8 to 3.6V (Pb free, tape and reel) Note: Reel quantity = 3,500 w PD, Rev 4.6, February 2013 3 WM8711L Production Data PIN DESCRIPTION 28 LEAD NAME TYPE DESCRIPTION QFN 5 DBVDD Supply 6 CLKOUT Digital Output 7 BCLK Digital Input/Output 8 DACDAT Digital Input 9 DACLRC Digital Input/Output Digital Buffers VDD Buffered Clock Output Digital Audio Bit Clock, Pull Down (see Note 1) DAC Digital Audio Data Input DAC Sample Rate Left/Right Clock, Pull Down (see Note 1) 10 NC No Connection 11 NC No Connection Headphone VDD 12 HPVDD Supply 13 LHPOUT Analogue Output Left Channel Headphone Output 14 RHPOUT Analogue Output Right Channel Headphone Output 15 HPGND Ground 16 LOUT Analogue Output Left Channel Line Output 17 ROUT Analogue Output Right Channel Line Output 18 AVDD Supply Analogue VDD 19 AGND Ground Analogue GND 20 VMID Analogue Output Headphone GND Mid-rail reference decoupling point 21 NC No Connection 22 NC No Connection 23 RLINEIN Analogue Input Right Channel Line Input (AC coupled) 24 LLINEIN Analogue Input Left Channel Line Input (AC coupled) 25 MODE Digital Input Control Interface Selection, Pull up (see Note 1) 26 CSB Digital Input 3-Wire MPU Chip Select/ 2-Wire MPU interface address selection, active low, Pull up (see Note 1) 27 SDIN Digital Input/Output 28 SCLK Digital Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input 1 XTI/MCLK Digital Input Crystal Input or Master Clock Input (MCLK) 2 XTO Digital Output 3 DCVDD Supply Digital Core VDD 4 DGND Ground Digital GND 3-Wire MPU Data Input / 2-Wire MPU Data Input Crystal Output Note: 1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power. 2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB. w PD, Rev 4.6, February 2013 4 WM8711L Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION MIN MAX Digital supply voltage -0.3V +3.63V Analogue supply voltage -0.3V +3.63V Voltage range digital inputs DGND -0.3V DVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Operating temperature range, TA -25C +85C Storage temperature after soldering -65C +150C Notes: 1. Analogue and digital grounds must always be within 0.3V of each other. 2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD). 3. DCVDD must always be less than or equal to DBVDD RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Digital supply range (Core) Digital supply range (Buffer) Analogue supply range Ground w MIN TYP DCVDD 1.42 1.5 DBVDD 1.8 3.6 V AVDD, HPVDD 1.8 3.6 V DGND,AGND,HPGND TEST CONDITIONS 0 MAX UNIT 3.6 V V PD, Rev 4.6, February 2013 5 WM8711L Production Data ELECTRICAL CHARACTERISTICS Test Conditions o AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (CMOS Levels) Input LOW level VIL Input HIGH level VIH Output LOW VOL IOL = 1mA Output HIGH VOH IOH = -1mA 0.3 x DBVDD 0.7 x DBVDD V V 0.10 x DBVDD 0.9 x DBVDD V V Power On Reset Threshold (DCVDD) DCVDD Threshold On -> Off 0.9 V Hysteresis 0.3 V DCVDD Threshold Off -> On 0.6 V Analogue Reference Levels Reference voltage (VMID) VVMID AVDD/2 V Potential divider resistance RVMID 50k Line Output for DAC Playback Only (Load = 10K. 50pF) 0dBFs Full scale output voltage At LINE outputs 1.0 x Vrms AVDD/3.3 Signal to Noise Ratio SNR (Note 1,2) A-weighted, 85 90 dB @ fs = 48kHz A-weighted 90 @ fs = 96kHz Dynamic Range (Note 2) DR Total Harmonic Distortion THD Power Supply Rejection Ratio PSRR DAC channel separation A-weighted, -60dB full scale input 85 90 1kHz, 0dBFs -81 1kHz, -3dBFs -88 1kHz 100mVpp 50 20Hz to 20kHz 100mVpp 45 1kHz, 0dB signal 100 dB -75 dB dB dB Analogue Line Input to Line Output (Load = 10k. 50pF, No Gain on Input ) Bypass Mode 0dB Full scale output voltage 1.0 x Vrms AVDD/3.3 Signal to Noise Ratio SNR 90 101 dB (Note 1,2) Total Harmonic Distortion THD 1kHz, 0dB -93 -85 dB Stereo Headphone Output 0dB Full scale output voltage 1.0 x Vrms AVDD/3.3 Max Output Power Signal to Noise Ratio PO SNR RL = 32 9 RL = 16 18 A-weighted 80 86 mW dB (Note 1,2) w PD, Rev 4.6, February 2013 6 WM8711L Production Data Test Conditions o AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Total Harmonic Distortion Power Supply Rejection Ratio SYMBOL TEST CONDITIONS THD 1kHz, RL = 32 @ PO = 5mW rms PSRR MIN TYP 1kHz 100mVpp 50 20Hz to 20kHz 100mVpp 45 MAX UNIT 0.18 % -55 dB dB Programmable Gain 1kHz Programmable Gain Step Size 1kHz 1 dB 1kHz, 0dB 80 dB Mute attenuation -73 6 6 dB TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). 5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. 6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region. w PD, Rev 4.6, February 2013 7 WM8711L Production Data CLKOUTPD OSCPD DAC Playback, oscillator and CLKOUT enabled 0 0 0 0 0 1.7 0.5 1.2 0.8 mA DAC Playback, using external MCLK 0 1 1 0 0 1.7 0.5 1.2 0.03 mA Standby 0 1 1 1 1 9 0.1 0.4 - A Power Down 1 1 1 1 1 - - 0.3 - A CURRENT CONSUMPTION DACPD MODE DESCRIPTION OUTPD POWEROFF POWER CONSUMPTION TYPICAL AVDD (1.8V) HPVDD (1.8V) DCVDD (1.5V) DBVDD (1.8V) UNITS Table 1 Powerdown Mode Current Consumption Examples Notes: o 1. TA = +25 C. Slave Mode, fs = 48kHz, MCLK = 256fs (12.288MHz). 2. All figures are quiescent, with no signal. 3. The power dissipation in the headphone itself not included in the above table. w PD, Rev 4.6, February 2013 8 WM8711L Production Data HEADPHONE SNR VS AVDD 24-bit data; DCVDD=1.5V; DBVDD=1.8V; Load=32Ohm; fs=44.1kHz; Output=-5dBFS (sine) SNR (dB) SNR vs AVDD (DAC Playback to Headphone) 99 98 97 96 95 94 93 92 91 90 1.5 2 2.5 3 3.5 4 AVDD = HPVDD (V) ANALOGUE SUPPLY CURRENT VS AVDD 24-bit data; DCVDD=1.5V; DBVDD=1.8V; Load=16Ohm; fs=44.1kHz; Output=quiescent Supply Current vs AVDD (DAC Playback to Headphone) 4 IAVDD (mA) 3.5 3 2.5 2 1.5 1 w 1.5 2 2.5 AVDD = HPVDD (V) 3 3.5 4 PD, Rev 4.6, February 2013 9 WM8711L Production Data MASTER CLOCK TIMING tXTIL MCLK tXTIH tXTIY Figure 1 System Clock Timing Requirements Test Conditions o AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 C, Slave Mode fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high tXTIH 18 ns MCLK System clock pulse width low tXTIL 18 ns MCLK System clock cycle time tXTIY 54 MCLK Duty cycle ns 40:60 60:40 DIGITAL AUDIO INTERFACE – MASTER MODE BCLK (Output) tDL DACLRC (Output) tDLT tDHT DACDAT Figure 2 Digital Audio Data Timing - Master Mode Test Conditions o AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 C, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 10 ns Audio Data Input Timing Information DACLRC propagation delay from BCLK falling edge tDL 0 DACDAT setup time to BCLCK rising edge tDST 10 ns DACDAT hold time from BCLK rising edge tDHT 10 ns w PD, Rev 4.6, February 2013 10 WM8711L Production Data DIGITAL AUDIO INTERFACE – SLAVE MODE tBCH BCLK (Input) tBCL tBCY DACLRC (Input) tDS tLRH tLRSU DACDAT Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions o AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 C, slave mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns DACLRC set-up time to BCLK rising edge tLRSU 10 ns DACLRC hold time from BCLK rising edge tLRH 10 ns DACDAT set-up time to BCLK rising edge tDS 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns MPU INTERFACE TIMING tCSL tCSH CSB tCSS tSCY tSCH tSCL tSCS SCLK LSB SDIN tDSU tDHO Figure 4 Program Register Input Timing - 3-Wire MPU interface Timing w PD, Rev 4.6, February 2013 11 WM8711L Production Data Test Conditions o AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 60 ns SCLK pulse cycle time tSCY 80 ns SCLK pulse width low tSCL 20 ns SCLK pulse width high tSCH 20 ns SDIN to SCLK set-up time tDSU 20 ns SCLK to SDIN hold time tDHO 20 ns CSB pulse width low tCSL 20 ns CSB pulse width high tCSH 20 ns CSB rising to SCLK rising tCSS 20 ns t3 t3 t5 SDIN t4 t6 t2 t8 SCLK t1 t10 t7 Figure 5 Program Register Input Timing – 2-Wire MPU Interface Timing Test Conditions o AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 526 kHz Program Register Input Information SCLK Frequency 0 SCLK Low Pulsewidth t1 1.3 us SCLK High Pulsewidth t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 SDIN, SCLK Rise Time t6 SDIN, SCLK Fall Time t7 Setup Time (Stop Condition) t8 Data Hold Time t10 w ns 300 ns 300 ns 600 ns 900 ns PD, Rev 4.6, February 2013 12 WM8711L Production Data DEVICE DESCRIPTION INTRODUCTION The WM8711L is a low power audio DAC designed specifically for portable audio products. Its features, performance and low power consumption make it ideal for portable MP3, CD and mini-disc players. The WM8711L includes line and headphone outputs from the on-board DAC, configurable digital audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data under software control. The DAC employs a high quality multi-bit high-order oversampling architecture to again deliver optimum performance with low power consumption. The DAC outputs and Line Inputs (BYPASS) are available both at line level and through a headphone amplifier capable of efficiently driving low impedance headphones. The headphone output volume is adjustable in the analogue domain over a range of +6dB to –73dB and can be muted. The design of the WM8711L minimises power consumption without compromising performance. It includes the ability to power off selective parts of the circuitry under software control, thus conserving power. Separate power save modes can be configured under software control including a standby and power off mode. Special techniques allow the audio to be muted and the device safely placed into standby, sections of the device powered off, volume levels adjusted without any audible clicks, pops or zipper noises. Therefore standby and power off modes may be used dynamically under software control, whenever playback is not required. The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz. The WM8711L has two schemes to support the programmable sample rates: Normal industry standard 256/384fs sampling mode may be used. A special USB mode is included, where all audio sampling rates can be generated from a 12.00MHz USB clock. The digital filters used for playback are optimised for each sampling rate used. The digital audio interface can support a range of audio data formats including I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified. The digital audio interface can operate in both master or slave modes. The software control uses either a 2 or 3-wire MPU interface. w PD, Rev 4.6, February 2013 13 WM8711L Production Data AUDIO SIGNAL PATH DAC FILTERS The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by the analogue DAC. Figure 6 illustrates the DAC digital filter path. FROM DIGITAL AUDIO INTERFACE DIGITAL DE_EMPHASIS DEEMP MUTE DIGITAL INTERPOLATION FILTER TO LINE OUTPUTS DACMU Figure 6 DAC Filter Schematic The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 2. The DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This removes any abrupt step changes in the audio that might otherwise result in audible clicks in the audio outputs. REGISTER ADDRESS 0000101 BIT 2:1 LABEL DEEMP[1:0] DEFAULT 00 Digital Audio Path Control DESCRIPTION De-emphasis Control (Digital) 11 = 48kHz 10 = 44.1kHz 01 = 32kHz 00 = Disable 3 DACMU 1 DAC Soft Mute Control (Digital) 1 = Enable soft mute 0 = Disable soft mute Note 1 Table 2 DAC Software Control Note 1: Not valid when SR[3:0] = 1111 or 0111. To ensure correct DACMU operation at fs = 88.2kHz, set SR[3:0] = 1000. To ensure correct DACMU operation at fs = 96kHz, set SR[3:0] = 0000. w PD, Rev 4.6, February 2013 14 WM8711L Production Data DAC The WM8711L employs a multi-bit sigma delta oversampling digital to analogue converter. The scheme for the converter is illustrated in Figure 7. FROM DAC DIGITAL FILTERS TO LINE OUTPUT Figure 7 Multi-Bit Oversampling Sigma Delta Schematic The DAC converts the multi-level digital audio data stream from the DAC digital filters into high quality analogue audio. LINE OUTPUTS The WM8711L provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for driving typical line loads of impedance 10K and capacitance 50pF. The LLINEOUT and RLINEOUT outputs are only available at a line output level and are not level adjustable in the analogue domain, having a fixed gain of 0dB. The level is fixed such that at the DAC full scale level the output level is Vrms at AVDD = 3.3 volts. Note that the DAC full scale level tracks directly with AVDD. The scheme is shown in Figure 8. The line output includes a low order audio low pass filter for removing out-of band components from the sigma-delta DAC. Therefore no further external filtering is required in most applications. BYPASS FROM LINE INPUTS DACSEL FROM DAC LINEOUT VMID TO HEADPHONE AMP Figure 8 Line Output Schematic The line output is muted by either muting the DAC (analogue) or Soft Muting (digital) and disabling the BYPASS path. Refer to the DAC section for more details. Whenever the DAC is muted or the device placed into standby mode the DC voltage is maintained at the line outputs to prevent any audible clicks from being present. w PD, Rev 4.6, February 2013 15 WM8711L Production Data The software control for the line outputs is shown in Table 3. REGISTER ADDRESS 0000100 Analogue Audio Path Control BIT LABEL DEFAULT 3 BYPASS 1 DESCRIPTION Bypass Switch 1 = Enable Bypass 0 = Disable Bypass 4 DACSEL DAC Select 0 1 = Select DAC 0 = Don’t select DAC Table 3 Output Software Control The recommended external components are shown in Figure 9. R2 LINEOUT C1 R1 AGND AGND Figure 9 Line Outputs Application Drawing Recommended values are C1 = 10F, R1 = 47k, R2 = 100 C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can have dramatic effects on the measured signal distortion at the output. HEADPHONE AMPLIFIER The WM8711L has a stereo headphone output available on LHPOUT and RHPOUT. The output is designed specifically for driving 16 or 32 ohm headphones with maximum efficiency and low power consumption. The headphone output includes a high quality volume level adjustment and mute function. w PD, Rev 4.6, February 2013 16 WM8711L Production Data The scheme of the circuit is shown in Figure 10. FROM DAC VIA LINEOUT HPOUT VMID Figure 10 Headphone Amplifier Schematic LHPOUT and RHPOUT volumes can be independently adjusted under software control using the LHPVOL[6:0] and RHPVOL[6:0] bits respectively of the headphone output control registers. The adjustment is logarithmic with an 80dB range in 1dB steps from +6dB to –73dB. The headphone outputs can be separately muted by writing codes less than 0110000 to LHPVOL[6:0] or RHPVO[6:0]L bits. Whenever the headphone outputs are muted or the device placed into standby mode, the DC voltage is maintained at the line outputs to prevent any audible clicks from being present. A zero cross detect circuit is provided at the input to the headphones under the control of the LZCEN and RZCEN bits of the headphone output control register. Using these controls the volume control values are only updated when the input signal to the gain stage is close to the analogue ground level. This minimises and audible clicks and zipper noise as the gain values are changed or the device muted. Note that this circuit has no time out so if only DC levels are being applied to the gain stage input of more than approximately 20mV, then the gain will not be updated. This zero cross function is enabled when the LZCEN and RZCEN bit is set high during a volume register write. If there is concern that a DC level may have blocked a volume change (one made with LZCEN or RZCEN set high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low will force a volume update, regardless of the DC level. LHPOUT and RHPOUT volume and zero-cross setting can be changed independently. Alternatively, the user can lock the two channels together, allowing both to be updated simultaneously, halving the number of serial writes required, provided that the same gain is needed for both channels. This is achieved through writing to the HPBOTH bit of the control register. Setting LRHPBOTH whilst writing to LHPVOL and LZCEN will simultaneously update the Right Headphone controls similarly. The corresponding effect on updating RLHPBOTH is also achieved. w PD, Rev 4.6, February 2013 17 WM8711L Production Data The software control is given in Table 4. REGISTER ADDRESS 0000010 BIT 6:0 LABEL LHPVOL[6:0] Left Headphone Out DEFAULT 1111001 ( 0dB ) DESCRIPTION Left Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE 7 LZCEN 0 Left Channel Zero Cross detect Enable 1 = Enable 0 = Disable 8 LRHPBOTH 0 Left to Right Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN 0 = Disable Simultaneous Load 0000011 6:0 RHPVOL[7:0] Right Headphone Out 1111001 ( 0dB ) Right Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE 7 RZCEN 0 Right Channel Zero Cross Detect Enable 1 = Enable 0 = Disable 8 RLHPBOTH 0 Right to Left Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of RHPVOL[6:0] and RZCEN to LHPVOL[6:0] and LZCEN 0 = Disable Simultaneous Load Table 4 Headphone Output Software Control w PD, Rev 4.6, February 2013 18 WM8711L Production Data The recommended external components required to complete the application are shown in Figure 11. HPOUT C1 AGND R1 AGND Figure 11 Headphone Output Application Drawing Recommended values are C1 = 220uF (10V electrolytic), R1 = 47k C1 forms a DC blocking capacitor to isolate the dc of the HPOUT from the headphones. R1 form a pull down resistor to discharge C1 to prevent the voltage at the connection to the headphones from rising to a level that may damage the headphones. DEVICE OPERATION DEVICE RESETTING The WM8711L contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on threshold voltage then the power on reset is re-applied. The threshold voltages and associated hysteresis are shown in the Electrical Characteristics table. The user also has the ability to reset the device to a known state under software control as shown in the table below. REGISTER ADDRESS 0001111 BIT 8:0 LABEL RESET Reset Register DEFAULT not reset DESCRIPTION Reset Register Writing 00000000 to register resets device Table 5 Software Control of Reset When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the ACK signal (approximately 1 SCLK period, refer to Figure 21). w PD, Rev 4.6, February 2013 19 WM8711L Production Data CLOCKING SCHEMES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. To allow WM8711L to be used in a centrally clocked system, the WM8711L is capable of either generating this system clock itself or receiving it from an external source as will be discussed. For applications where it is desirable that the WM8711L is the system clock source, then clock generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input and XTO output pins (see CRYSTAL OSCILLATOR section). For applications where a component other than the WM8711L will generate the reference clock, the external system Master Clock can be applied directly through the XTI/MCLK input pin with no software configuration necessary. Note that in this situation, the oscillator circuit of the WM8711L can be safely powered down to conserve power (see POWER DOWN section) CORE CLOCK The WM8711L DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by software as shown in Table 6 below. REGISTER ADDRESS 0001000 BIT 6 LABEL DEFAULT CLKIDIV2 0 Sampling Control DESCRIPTION Core Clock divider select 1 = Core Clock is MCLK divides by 2 0 = Core Clock is MCLK Table 6 Software Control of Core Clock Having a programmable MCLK divider allows the device to be used in applications where higher frequency master Clocks are available. For example the device can support 512fs master clocks whilst fundamentally operating in a 256fs mode. CRYSTAL OSCILLATOR The WM8711L includes a crystal oscillator circuit that allows the audio system’s reference clock to be generated on the device. This is available to the rest of the audio system in buffered form on CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application circuit is shown Figure 12. XTI/MCLK XTO Cp Cp DGND DGND Figure 12 Crystal Oscillator Application Circuit The WM8711L crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a requirement for high quality audio DACs, regardless of the converter architecture. The WM8711L architecture is less susceptible than most converter techniques but still requires clocks with less than approximately 1ns of jitter to maintain performance. In applications where there is more than one source for the master clock, it is recommended that the clock is generated by the WM8711L to minimise such problems. w PD, Rev 4.6, February 2013 20 WM8711L Production Data CLOCKOUT The Core Clock is internally buffered and made available externally to the audio system on the CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for driving external loads. There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to Electrical Characteristics. CLKOUT can also be divided by 2 under software control, refer to Table 7. Note that if CLKOUT is not required then the CLKOUT buffer on the WM8711L can be safely powered down to conserve power (see POWER DOWN section). If the system architect has the choice between using FCLKOUT = FMCLK or FCLKOUT = FMCLK/2 in the interface, the latter is recommended to conserve power. When the divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical Characteristics for timing information. REGISTER ADDRESS 0001000 BIT 7 LABEL CLKODIV2 Sampling Control DEFAULT 0 DESCRIPTION CLKOUT divider select 1 = CLOCKOUT is Core Clock divides by 2 0 = CLOCKOUT is Core Clock Table 7 Programming CLKOUT CLKOUT is disabled and set low whenever the device is in reset. DIGITAL AUDIO INTERFACES WM8711L may be operated in either one of the 4 offered audio interface modes. These are: Right justified Left justified IS DSP mode 2 All four of these modes are MSB first and operate with data 16 to 32 bits, except in right justified mode where 32 bit data is not supported. The digital audio interface receives the digital audio data for the internal DAC digital filters on the DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section w PD, Rev 4.6, February 2013 21 WM8711L Production Data There are four digital audio interface formats accommodated by the WM8711L. These are shown in the figures below. Refer to the Electrical Characteristic section for timing information. Left Justified mode is where the MSB is available on the first rising edge of BCLK following a DACLRC transition. 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC BCLK DACDAT 1 2 3 n-2 n-1 MSB n 1 LSB 2 3 n-2 n-1 MSB n LSB Figure 13 Left Justified Mode 2 I S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC transition. 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC BCLK 1 BCLK 1 BCLK DACDAT 1 MSB 2 3 n-2 n-1 n LSB 1 MSB 2 3 n-2 n-1 n LSB 2 Figure 14 I S Mode w PD, Rev 4.6, February 2013 22 WM8711L Production Data Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC transition, yet MSB is still transmitted first. 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC BCLK DACDAT 1 2 3 n-2 n-1 MSB n LSB 1 2 3 n n-2 n-1 MSB LSB Figure 15 Right Justified Mode st nd In DSP/PCM mode, the left channel MSB is available on either the 1 (mode B) or 2 (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. Figure 16 DSP/PCM Mode Audio Interface (mode A, LRP=1) w PD, Rev 4.6, February 2013 23 WM8711L Production Data Figure 17 DSP/PCM Mode Audio Interface (mode B, LRP=0) In all modes DACLRC must always change on the falling edge of BCLK, refer to Figures 13,14,15 and 16. Operating the digital audio interface in DSP mode allows ease of use for supporting the various sample rates and word lengths. The only requirement is that all data is transferred within the correct number of BCLK cycles to suit the chosen word length. In order for the digital audio interface to offer similar support in the three other modes (Left Justified, 2 I S and Right Justified), the DACLRC and BCLK frequencies, continuity and mark-space ratios need more careful consideration. In Slave mode, DACLRC inputs are not required to have a 50:50 mark-space ratio. BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC transition to clock the chosen data word length. The non-50:50 requirement on the LRC is of use in some situations such as with a USB 12MHZ clock. Here simply dividing down a 12MHz clock within the DSP to generate LRC and BCLK will not generate the appropriate DACLRC since it will no longer change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are 375 MCLK per LRC. In these situations DACLRC can be made non 50:50. In Master mode, DACLRC will be output with a 50:50 mark-space ratio with BCLK output at 64fs x Base Frequency (ie 48kHz). The exception is in 96/88.2k mode where BCLK is MCLK and in USB mode where BCLK is always 12MHz. So for example in 12MHz/32k fs mode there are 375 master clocks per LRC period. Therefore the DACLRC output will have a mark space ratio of 187:188. The DAC digital audio interface modes are software configurable as indicated in Table 7. Note that dynamically changing the software format may result in erroneous operation of the interfaces and is therefore not recommended. The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software control table below. The data is signed 2’s complement. The DAC digital filters process data using 24 bits. If the DAC is programmed to receive 16 or 20 bit data, the WM8711L packs the LSBs with zeros. If the DAC is programmed to receive 32 bit data, then it strips the LSBs. The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in Table 8. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the order so that a Left sample goes to the right DAC output and a Right sample goes to the left DAC output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the correct channel phase difference, except in DSP mode, where LRP controls the positioning of the MSB relative to the rising edge of DACLRC. w PD, Rev 4.6, February 2013 24 WM8711L Production Data To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is controlled via the software shown in Table 8. This is especially appropriate for DSP mode. REGISTER ADDRESS 0000111 BIT LABEL 1:0 FORMAT[1:0] DEFAULT 10 Digital Audio Interface Format DESCRIPTION Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 2 10 = I S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified 3:2 IWL[1:0] 10 Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 4 LRP 0 DACLRC phase control (in left, right 2 or I S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low 2 (opposite phasing in I S mode) or DSP mode A/B select ( in DSP mode only) nd 1 = MSB is available on 2 BCLK rising edge after DACLRC rising edge 0 = MSB is available on 1st BCLK rising edge after DACLRC rising edge 5 LRSWAP 0 DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right 6 MS 0 Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode 7 BCLKINV 0 Bit Clock Invert 1 = Invert BCLK 0 = Don’t invert BCLK Table 8 Digital Audio Interface Control Note: If right justified 32 bit mode is selected then the WM8711L defaults to 24 bits. w PD, Rev 4.6, February 2013 25 WM8711L Production Data MASTER AND SLAVE MODE OPERATION The WM8711L can be configured as either a master or slave mode device. As a master mode device the WM8711L controls sequencing of the data and clocks on the digital audio interface. As a slave device the WM8711L responds with data to the clocks it receives over the digital audio interface. The mode is set with the MS bit of the control register as shown in Table 9. REGISTER ADDRESS 0000111 BIT 6 LABEL MS Digital Audio Interface Format DEFAULT 0 DESCRIPTION Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Table 9 Programming Master/Slave Modes As a master mode device the WM8711L controls the sequencing of data transfer (DACDAT) and output of clocks (BCLK, DACLRC) over the digital audio interface. It uses the timing generated from the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 18. DACDAT is always an input to the WM8711L independent of master or slave mode. BCLK WM8711 DACLRC DAC DSP DECODER DACDAT Figure 18 Master Mode As a slave device the WM8711L sequences the data transfer (DACDAT) over the digital audio interface in response to the external applied clocks (BCLK, DACLRC). This is illustrated in Figure 19. BCLK WM8711 DACLRC DAC DSP DECODER DACDAT Figure 19 Slave Mode Note that the WM8711L relies on controlled phase relationships between audio interface BCLK, DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section for detailed information. w PD, Rev 4.6, February 2013 26 WM8711L Production Data AUDIO DATA SAMPLING RATES The WM8711L provides for two modes of operation (normal and USB) to generate the required DAC sampling rates. Normal and USB modes are programmed under software control according to the table below. In Normal mode, the user controls the sample rate by using an appropriate MCLK frequency and the sample rate control register setting. The WM8711L can support sample rates from 8ks/s up to 96ks/s. In USB mode, the user must use a fixed MLCK frequency of 12MHz to generate sample rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at 12MHz and the WM8711L can be directly used within such systems. WM8711L can generate all the normal audio sample rates from this one Master Clock frequency, removing the need for different master clocks or PLL circuits. REGISTER ADDRESS 0001000 BIT 0 Sampling Control LABEL DEFAULT USB/ NORMAL 0 BOSR 0 DESCRIPTION Mode Select 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) 1 Base Over-Sampling Rate USB Mode 0 = 250fs Normal Mode 96/88.2 kHz 1 = 272fs 0 = 256fs 0 = 128fs 1 = 384fs 1 = 192fs 5:2 SR[3:0] 0000 DAC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation Table 10 Sample Rate Control NORMAL MODE SAMPLE RATES In normal mode MCLK is set up according to the desired sample rates of the DAC. For DAC sampling rates of 8, 32, 48 or 96kHz, MCLK frequencies of either 12.288MHz (256fs) or 18.432MHz (384fs) can be used. DAC sampling rates of 8, 44.1 or 88.2kHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used. w PD, Rev 4.6, February 2013 27 WM8711L Production Data The table below should be used to set up the device to work with the various sample rate combinations. Refer to Digital Filter Characteristics section for an explanation of the different filter types. SAMPLING RATE DAC MCLK FREQUENCY kHz MHz 48 8 32 DIGITAL FILTER TYPE SAMPLE RATE REGISTER SETTINGS BOSR SR3 SR2 SR1 SR0 12.288 0 (256fs) 0 0 0 0 18.432 1 (384fs) 0 0 0 0 12.288 0 (256fs) 0 0 0 1 18.432 1 (384fs) 0 0 0 1 12.288 0 (256fs) 0 1 1 0 18.432 1 (384fs) 0 1 1 0 96 12.288 0 (128fs) 0 1 1 1 18.432 1 (192fs) 0 1 1 1 44.1 11.2896 0 (256fs) 1 0 0 0 16.9344 1 (384fs) 1 0 0 0 8 11.2896 0 (256fs) 1 0 0 1 (Note 1) 16.9344 1 (384fs) 1 0 0 1 88.2 11.2896 0 (128fs) 1 1 1 1 16.9344 1 (192fs) 1 1 1 1 1 1 1 2 1 1 2 Table 11 Normal Mode Sample Rate Look-up Table Notes: 1. 8k not exact, actual = 8.018kHz 2. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711L digital signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at 256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the actual audio data rate required by the DAC. The exact sample rates achieved are defined by the relationships in Table 12 below. TARGET ACTUAL SAMPLING RATE SAMPLING RATE MCLK=12.288 MCLK=11.2896 MCLK=18.432 MCLK=16.9344 kHz kHz kHz kHz kHz 8 32 BOSR=0 BOSR=1 8 8.018 8 8.018 (12.288MHz/256) x 1/6 (11.2896MHz/256) x 2/11 (18.432MHz/384) x 1/6 (16.9344MHz/384) x 2/11 32 not available 32 not available (12.288MHz/256) x 2/3 44.1 not available (18.432MHz/384) x 2/3 44.1 not available 11.2896MHz/256 48 48 not available 48 88.2 not available 12.288MHz/256 88.2 not available 96 not available 18.432MHz/384 (11.2896MHz/256) x 2 96 44.1 16.9344MHz /384 not available (12.288MHz/256) x 2 88.2 (16.9344MHz /384) x 2 96 not available (18.432MHz/384) x 2 Table 12 Normal Mode Actual Sample Rates w PD, Rev 4.6, February 2013 28 WM8711L Production Data 128/192FS NORMAL MODE The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the WM8711L is also capable of being clocked from a 128/192fs MCLK for application over limited sampling rates as shown in the table below. SAMPLING RATE DAC MCLK FREQUENCY DIGITAL FILTER TYPE SAMPLE RATE REGISTER SETTINGS kHz MHz BOSR SR3 SR2 SR1 SR0 48 6.144 0 0 1 1 1 9.216 1 0 1 1 1 5.6448 0 1 1 1 1 8.4672 1 1 1 1 1 44.1 2 2 Table 13 128/192fs Normal Mode Sample Rate Look-up Table 512/768FS NORMAL MODE 512fs and 768fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384fs internally and the device otherwise operates as in Table 9 but with MCLK at twice the specified rate. USB MODE SAMPLE RATES In USB mode the MCLK input is 12MHz only. SAMPLING RATE DIGITAL FILTER TYPE DAC MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS kHz MHz BOSR SR3 SR2 SR1 SR0 48 12.000 0 0 0 0 0 0 44.1 12.000 1 1 0 0 0 1 (Note 2) 8 12.000 0 0 0 0 1 0 8 12.000 1 1 0 0 1 1 (Note 1) 32 12.000 0 0 1 1 0 0 96 12.000 0 0 1 1 1 3 88.2 12.000 1 1 1 1 1 2 (Note 3) Table 14 USB Mode Sample Rate Look-Up Table Notes: 1. 8k not exact, actual = 8.021kHz 2. 44.1k not exact, actual = 44.118kHz 3. 88.1k not exact, actual = 88.235kHz 4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711L digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode, with BOSR = 0, the base over-sampling rate is defined at 250Fs, with BOSR = 1, the base over-sampling rate is defined at 272Fs. This can be used to determine the actual audio sampling rate required by the DAC. w PD, Rev 4.6, February 2013 29 WM8711L Production Data The exact sample rates supported for all combinations are defined by the relationships in Table 15 below. ACTUAL SAMPLING RATE TARGET SAMPLING RATE BOSR=0 BOSR=1 ( 250FS) (272FS) kHz kHz 8 32 kHz 8 8.021 12MHz/(250 x 48/8) 12MHz/(272 x 11/2) 32 not available 12MHz/(250 x 48/32) 44.1 not available 48 48 44.117 12MHz/272 not available 12MHz/250 88.2 not available 96 96 88.235 12MHz/136 not available 12MHz/125 Table 15 USB Mode Actual Sample Rates ACTIVATING DSP AND DIGITAL AUDIO INTERFACE To prevent any communication problems from arising across the Digital Audio Interface is disabled (tristate with weak 100k pulldown) at power on. Once the Audio Interface and the Sampling Control has been programmed it is activated by setting the ACTIVE bit under Software Control. REGISTER ADDRESS BIT 0001001 0 LABEL ACTIVE DEFAULT 0 Active Control DESCRIPTION Activate Interface 1 = Active 0 = Inactive Table 16 Activating DSP and Digital Audio Interface It is recommended that between changing any content of Digital Audio Interface or Sampling Control Register that the active bit is reset then set. SOFTWARE CONTROL INTERFACE The software control interface may be operated using either a 3-wire or 2-wire MPU interface. Selection of interface format is achieved by setting the state of the MODE pin. In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two addresses. SELECTION OF SERIAL CONTROL MODE The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved by setting the state of the MODE pin. MODE INTERFACE FORMAT 0 2 wire 1 3 wire Table 17 Control Interface Mode Selection w PD, Rev 4.6, February 2013 30 WM8711L Production Data 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE The WM8711L can be controlled using a 3-wire serial interface. SDIN is used for the program data, SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire interface protocol is shown in Figure 20. CSB SCLK SDIN B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Figure 20 3-Wire Serial Interface Notes: 1. B[15:9] are Control Address Bits 2. B[8:0] are Control Data Bits 3. CSB is edge sensitive not level sensitive. The data is latched on the rising edge of CSB. 2-WIRE SERIAL CONTROL MODE The WM8711L supports a 2-wire MPU serial interface. The device operates as a slave device only. The WM8711L has one of two slave addresses that are selected by setting the state of pin 26 (CSB). R ADDR SDIN R/W ACK DATA B15-8 ACK DATA B7-0 ACK SCLK START STOP Figure 21 2-Wire Serial Interface Notes: 1. B[15:9] are Control Address Bits 2. B[8:0] are Control Data Bits CSB STATE ADDRESS 0 0011010 1 0011011 Table 18 2-Wire MPU Interface Address Selection To control the WM8711L on the 2-wire bus the master control device must initiate a data transfer by establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high. This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of two available addresses for this device (see Table 18). If the correct address is received and the R/W bit is ‘0’, indicating a write, then the WM8711L will respond by pulling SDIN low on the next clock pulse (ACK). The WM8711L is a write only device and will only respond to the R/W bit indicating a write. If the address is not recognised the device will return to the idle condition and wait for a new start condition and valid address. w PD, Rev 4.6, February 2013 31 WM8711L Production Data Once the WM8711L has acknowledged a correct address, the controller will send eight data bits (bits B[15]-B[8]). WM8711L will then acknowledge the sent data by pulling SDIN low for one clock pulse. The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8711L will then acknowledge again by pulling SDIN low. A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition. After receiving a complete address and data sequence the WM8711L returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address and R/W bit followed by the 16 register address and data bits. POWER DOWN MODES The WM8711L contains power conservation modes in which various circuit blocks may be safely powered down in order to conserve power. This is software programmable as shown in the table below. REGISTER ADDRESS 0000110 BIT 3 LABEL DACPD DEFAULT 1 Power Down Control DESCRIPTION DAC Power Down 1 = Enable Power Down 0 = Disable Power Down 4 OUTPD 1 Line Output Power Down 1 = Enable Power Down 0 = Disable Power Down 5 OSCPD 0 Oscillator Power Down 1 = Enable Power Down 0 = Disable Power Down 6 CLKOUTPD 0 CLKOUT Power Down 1 = Enable Power Down 0 = Disable Power Down 7 POWEROFF 1 Power Off Device 1 = Device Power Off 0 = Device Power On Table 19 Power Conservation Modes Software Control The power down control can be used to either a) permanently disable functions when not required in certain applications or b) to dynamically power up and down functions depending on the operating mode, e.g.: during playback or record. Please follow the special instructions below if dynamic implementations are being used. w PD, Rev 4.6, February 2013 32 WM8711L Production Data DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops will result unless the following guidelines are followed. In order to prevent pops, the DAC should first be soft-muted (DACMU), the output should then be de-selected from the line and headphone output (DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Pause or Stop modes. During DACPD the digital audio interface is remains active. OUTPD: Powers down the Line and Headphone Outputs. If this is done dynamically then audible pops may result unless the DAC is first soft-muted (DACMU). This is of use when the device enters Record, Pause or Stop modes. POWER OFF CLKOUTPD OSCPD OUTPD DACPD The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry under software control as shown in Table 19. 0 0 0 1 1 STANDBY, but with Crystal Oscillator OS and CLKOUT available 0 1 0 1 1 STANDBY, but with Crystal Oscillator OS available, CLKOUT not-available 0 1 1 1 1 STANDBY, Crystal oscillator and CLKOUT not-available. DESCRIPTION Table 20 Standby Mode In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue circuitry remain active. The active analogue includes the analogue VMID reference so that the analogue line outputs and headphone outputs remain biased to VMID. This reduces any audible effects caused by DC glitches when entering or leaving STANDBY mode. POWER OFF CLKOUTPD OSCPD OUTPD DACPD The device can be powered off by writing to the POWEROFF bit of the Power Down register. In POWEROFF mode the Control Interface and a small portion of the digital remain active. The analogue VMID reference is disabled. Refer to Table 21. 1 0 0 X 1 POWEROFF, but with Crystal Oscillator OS and CLKOUT available 1 1 0 X 1 POWEROFF, but with Crystal Oscillator OS available, CLKOUT not-available 1 1 1 X 1 POWEROFF, Crystal oscillator and CLKOUT not-available. DESCRIPTION Table 21 Poweroff Mode w PD, Rev 4.6, February 2013 33 WM8711L Production Data REGISTER MAP The complete register map is shown in Table 23. The detailed description can be found in the relevant text of the device description. There are 8 registers with 9 bits per register. These can be controlled using either the 2 wire or 3 wire MPU interface. REGISTER B B B B B B B 15 14 13 12 11 10 9 B8 R2 (04h) 0 0 0 0 0 1 0 R3 (06h) 0 0 0 0 0 1 1 R4 (08h) 0 0 0 0 1 0 0 0 0 0 0 R5 (0Ah) 0 0 0 0 1 0 1 0 0 0 0 0 DAC MU R6 (0Ch) 0 0 0 0 1 1 0 0 OSCPD OUTPD DACPD R7 (0Eh) 0 0 0 0 1 1 1 0 LR SWAP LRP R8 (10h) 0 0 0 1 0 0 0 0 R9 (12h) 0 0 0 1 0 0 1 0 R15(1Eh) 0 0 0 1 1 1 1 LRHP BOTH RLHP BOTH B7 B6 B5 B4 B3 LZCEN LHPVOL RZCEN RHPVOL POWER CLK OFF OUTPD BCLK MS INV CLK0 CLKI DIV2 DIV2 0 0 DAC SEL BYPASS B2 B1 0 0 1 0 1 IWL 0 0 DEEMPH 1 FORMAT SR 0 B0 USB/ BOSR 0 0 0 NORM ACTIVE RESET ADDRESS DATA Table 22 Mapping of Program Registers REGISTER ADDRESS 0000010 BIT 6:0 Left Headphone Out LABEL LHPVOL [6:0] DEFAULT 1111001 ( 0dB ) DESCRIPTION Left Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE 7 LZCEN 0 Left Channel Zero Cross detect Enable 1 = Enable 0 = Disable 8 LRHPBOTH 0 Left to Right Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN 0 = Disable Simultaneous Load w PD, Rev 4.6, February 2013 34 WM8711L Production Data REGISTER ADDRESS 0000011 BIT 6:0 Right Headphone Out LABEL RHPVOL [6:0] DEFAULT 1111001 ( 0dB ) DESCRIPTION Right Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE 7 RZCEN 0 Right Channel Zero Cross detect Enable 1 = Enable 0 = Disable 8 RLHPBOTH 0 Right to Left Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of RHPVOL[60] and RZCEN to LHPVOL[6:0] and LZCEN 0 = Disable Simultaneous Load 0000100 Audio Path Control 3 BYPASS 1 Bypass Switch DAC Select (Analogue) 1 = Enable Bypass 0 = Disable Bypass 4 DACSEL 0 2:1 DEEMP[1:0] 00 1 =Select DAC 0 = Don’t select DAC 0000101 Digital Audio Path Control De-emphasis Control (Digital) 11 = 48kHz 10 = 44.1kHz 01 = 32kHz 00 = Disable 3 DACMU 1 DAC Soft Mute Control (Digital) 1 = Enable soft mute 0 = Disable soft mute See note 1, page 14 0000110 3 DACPD 1 Power Down Control DAC Power Down 1 = Enable Power Down 0 = Disable Power Down 4 OUTPD 1 Outputs Power Down 1 = Enable Power Down 0 = Disable Power Down 5 OSCPD 0 Oscillator Power Down 1 = Enable Power Down 0 = Disable Power Down 6 CLKOUTPD 0 CLKOUT Power Down 1 = Enable Power Down 0 = Disable Power Down 7 POWEROFF 1 POWEROFF mode 1 = Enable POWEROFF 0 = Disable POWEROFF w PD, Rev 4.6, February 2013 35 WM8711L Production Data REGISTER ADDRESS 0000111 BIT LABEL 1:0 FORMAT[1:0] DEFAULT 10 Digital Audio Interface Format DESCRIPTION Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified 3:2 IWL[1:0] 10 Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 4 LRP 0 DACLRC phase control (in left, right or 2 I S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low 2 (opposite phasing in I S mode) or DSP mode A/B select ( in DSP mode only) nd 1 = MSB is available on 2 BCLK rising edge after DACLRC rising edge 0 = MSB is available on 1st BCLK rising edge after DACLRC rising edge 5 LRSWAP 0 DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right 6 MS 0 Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode 7 BCLKINV 0 Bit Clock Invert 1 = Invert BCLK 0 = Don’t invert BCLK w PD, Rev 4.6, February 2013 36 WM8711L Production Data REGISTER ADDRESS 0001000 BIT 0 Sampling Control LABEL USB/ NORMAL DEFAULT 0 DESCRIPTION Mode Select 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) 1 BOSR 0 Base Over-Sampling Rate USB Mode 0 = 250fs 1 = 272fs 5:2 6 SR[3:0] CLKIDIV2 0000 0 DAC sample rate control; Normal Mode See USB Mode and Normal Mode Sample Rate sections for operation 1 = 384fs 0 = 256fs Core Clock divider select 1 = Core Clock is MCLK divide by 2 0 = Core Clock is MCLK 7 CLKODIV2 0 CLKOUT divider select 1 = CLOCKOUT is MCLK divide by 2 0 = CLOCKOUT is MCLK 0001001 0 ACTIVE 0 Active Control Activate Interface 1 = Active 0 = Inactive 0001111 8:0 RESET Reset Register not reset Reset Register Writing 00000000 to register resets device Table 23 Register Map Description Note: All other bits not explicitly defined in the register table should be set to zero unless specified otherwise. w PD, Rev 4.6, February 2013 37 WM8711L Production Data DIGITAL FILTER CHARACTERISTICS The DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Filter Type 0 (USB mode, 250fs operation) Passband +/- 0.03dB 0 0.416fs -6dB 0.5fs Passband Ripple +/-0.03 Stopband dB 0.584fs Stopband Attenuation f > 0.584fs -50 dB DAC Filter Type 1 (USB mode, 272fs or Normal mode operation) Passband +/- 0.03dB 0 0.4535fs -6dB 0.5fs Passband Ripple +/- 0.03 Stopband dB 0.5465fs Stopband Attenuation f > 0.5465fs -50 dB Table 24 Digital Filter Characteristics DAC FILTERS Mode Group Delay 0 11/FS 1 18/FS 2 5/FS 3 5/FS Table 25 DAC Digital Filters Group Delay DAC FILTER RESPONSES 0.04 0 0.03 0.02 Response (dB) Response (dB) -20 -40 -60 0.01 0 -0.01 -0.02 -80 -0.03 -100 -0.04 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 22 DAC Digital Filter Frequency Response–Type 0 w 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 23 DAC Digital Filter Ripple–Type 0 PD, Rev 4.6, February 2013 38 WM8711L Production Data 0.04 0 0.03 0.02 Response (dB) Response (dB) -20 -40 -60 0.01 0 -0.01 -0.02 -80 -0.03 -100 -0.04 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 24 DAC Digital Filter Frequency Response–Type 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 25 DAC Digital Filter Ripple–Type 1 0.02 0 0.01 0 Response (dB) Response (dB) -20 -40 -60 -0.01 -0.02 -0.03 -0.04 -80 -0.05 -100 -0.06 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 -20 0 -40 -60 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 0.2 0.25 Figure 27 DAC Digital Filter Ripple–Type 2 Response (dB) Response (dB) Figure 26 DAC Digital Filter Frequency Response–Type 2 0 -0.05 -0.1 -0.15 -80 -0.2 -100 -0.25 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 28 DAC Digital Filter Frequency Response–Type 3 w 0 0.05 0.1 0.15 Frequency (Fs) Figure 29 DAC Digital Filter Ripple–Type 3 PD, Rev 4.6, February 2013 39 WM8711L Production Data DIGITAL DE-EMPHASIS CHARACTERISTICS 0 0.4 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -10 -0.4 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 Figure 30 De-Emphasis Frequency Response (32kHz) 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 Figure 31 De-Emphasis Error (32kHz) 0 0.4 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -10 -0.4 0 5000 10000 Frequency (Fs) 15000 20000 Figure 32 De-Emphasis Frequency Response (44.1kHz) 0 5000 10000 Frequency (Fs) 15000 20000 Figure 33 De-Emphasis Error (44.1kHz) 0 0.4 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -10 -0.4 0 5000 10000 15000 Frequency (Fs) 20000 Figure 34 De-Emphasis Frequency Response (48kHz) w 0 5000 10000 15000 Frequency (Fs) 20000 Figure 35 De-Emphasis Error (48kHz) PD, Rev 4.6, February 2013 40 WM8711L Production Data 5.6k 220pF 1M 5.6k 220pF 1M RECOMMENDED EXTERNAL COMPONENTS Figure 36 External Components Diagram w PD, Rev 4.6, February 2013 41 WM8711L Production Data PACKAGE DIMENSIONS FL: 28 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.85 mm BODY, 0.50 mm LEAD PITCH DM109.A D2 0.10 C A B B D2/2 27 22 D 28 INDEX AREA (D/2 X E/2) L 21 1 EXPOSED GROUND 6 PADDLE 2 E2/2 A A 15 E2 E 7 SEE DETAIL A 13 8 2X b aaa C ccc M C A B B e 2X BOTTOM VIEW aaa C TOP VIEW 0.10 C 0.08 C SEATING PLANE SIDE VIEW A1 R e C DETAIL A A DATUM (A3) 1 1 e/2 TERMINAL TIP 14 Symbols A A1 A3 b D D2 E E2 e L R MIN 0.80 0 0.20 3.00 3.00 Dimensions (mm) NOM MAX 0.85 0.90 0.035 0.05 0.203 REF 0.25 0.30 5.00 BSC 3.10 3.20 5.00 BSC 3.10 3.20 0.5 BSC 0.55 0.60 0.50 b(min)/2 Tolerances of Form and Position aaa 1 2 2 2 0.10 0.10 0.10 bbb ccc REF: NOTE JEDEC, MO-220, VARIATION VHHD-3 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2 AND L: D2,E2: SMALLER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION, L IS SLIGHTLY LARGER THAN JEDEC SPEC. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. w PD, Rev 4.6, February 2013 42 WM8711L Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. 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ADDRESS: Wolfson Microelectronics plc 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w PD, Rev 4.6, February 2013 43 WM8711L Production Data REVISION HISTORY DATE REV ORIGINATOR CHANGES 30/08/10 4.5 SS 23/02/11 4.5 JMacD WM8711SEDS and WM8711SEDS/R obsolete. SSOP removed from datasheet. 05/05/11 4.5 JMacD WM8711GEFL and WM8711GEFL/R obsolete. All references to GEFL and WM8711 removed from datasheet. Part now referred to as WM8711L. 05/11/12 4.6 JMacD Order Added Table 26 Digital Filter Group Delays Code WM8711LGEFL and All references to SEDS and WM8711LGEFL/R changed to WM8711CLGEFL and WM8711CLGEFL/R to reflect change to copper wire bonding. 05/11/12 4.6 JMacD Package Diagram changed to DM109.A. 14/02/13 4.6 JMacD Package dimension updated in Features on front page. w PD, Rev 4.6, February 2013 44