Datasheet

AOZ3010PI
EZBuck™ 2 A Synchronous Buck Regulator
General Description
Features
The AOZ3010PI is a high efficiency, simple to use, 2 A
synchronous buck regulator. The AOZ3010PI operates
from a 4.5 V to 18 V input voltage range, and provides up
to 2 A of continuous output current with an output voltage
adjustable down to 0.8 V.
 4.5 V to 18 V operating input voltage range
The AOZ3010PI comes in an exposed pad SO-8
package and is rated over a -40 °C to +85 °C operating
ambient temperature range.
 Output voltage adjustable down to 0.8 V
 80 mΩ internal high-side switch and 50 mΩ internal
low-side switch (at 12 V)
 Up to 95 % efficiency
 External soft start
 2 A continuous output current
 500 kHz PWM operation
 Cycle-by-cycle current limit
 Pre-bias start-up
 Short-circuit protection
 Thermal shutdown
 Exposed pad SO-8 package
Applications
 Point of load DC/DC conversion
 LCD TVs
 Set top boxes
 DVD and Blu-ray players/recorders
 Cable modems
Typical Application
VIN
C1
10µF
Css
VIN
SS
L1 4.7µH
EN
AOZ3010PI
COMP
Rc
AGND
VOUT
LX
R1
C2, C3
22µF
FB
PGND
R2
Cc
Figure 1. 3.3 V, 2 A Synchronous Buck Regulator, Fs = 500 kHz
Rev. 0.5 December 2012
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Page 1 of 14
AOZ3010PI
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ3010PI
-40 °C to +85 °C
EPAD SO-8
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
PGND
1
VIN
2
AGND
3
FB
4
PAD
(LX)
8
LX
7
SS
6
EN
5
COMP
Exposed Pad SO-8
(Top View)
Pin Description
Pin Number
Pin Name
Pin Function
1
PGND
2
VIN
3
AGND
Analog ground. AGND is the reference point for the controller section. AGND needs to be
electrically connected to PGND.
4
FB
Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider
between the output and AGND.
5
COMP
6
EN
Power ground. PGND needs to be electrically connected to AGND.
Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high,
the device starts up.
External loop compensation pin. Connect a RC network between COMP and AGND to
compensate the control loop.
Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the
device. If on/off control is not needed, connect it to VIN and do not leave it open.
7
SS
8
LX (Sense)
Switching node. This pin has to be externally connected to exposed pad LX through PCB.
Exposed Pad
LX
Switching node. LX is the drain of the internal PFET. LX is used as the thermal pad of the
power stage.
Rev. 0.5 December 2012
Soft-start pin. 5 µA charging current.
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Page 2 of 14
AOZ3010PI
Block Diagram
VIN
UVLO
& POR
EN
Internal
+5V
5V LDO
Regulator
OTP
+
ISen
Reference
& Bias
Softstart
–
Q1
ILimit
SS
SS
5µA
0.8V
FB
+
+
EAmp
–
–
PWM
Comp
PWM
Control
Logic
+
Level
Shifter
+
FET
Driver
LX
Q2
COMP
Over-Voltage
Protection
Comparator
500kHz
Oscillator
+
0.96V
–
AGND
PGND
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum Ratings may damage the
device.
The device is not guaranteed to operate beyond the
Recommended Operating Conditions.
Parameter
Supply Voltage (VIN)
LX to AGND
LX to AGND (20ns)
EN to AGND
FB, SS, COMP to AGND
PGND to AGND
Rating
Parameter
20 V
-0.7 V to VVIN+ 0.3 V
-0.5 V to 22 V
-0.3 V to VVIN+ 0.3 V
-0.3 V to 6 V
4.5 V to 18 V
Output Voltage Range
0.8 V to 0.85*VIN
Ambient Temperature (TA)
-40 °C to +85 °C
Package Thermal Resistance
Exposed Pad SO-8 (JA)
50 °C/W
-0.3 V to + 0.3 V
Junction Temperature (TJ)
+150 °C
Storage Temperature (TS)
-65 °C to +150 °C
ESD Rating(1)
Supply Voltage (VIN)
Rating
2 kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5 kΩ in series with 100 pF.
Rev. 0.5 December 2012
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Page 3 of 14
AOZ3010PI
Electrical Characteristics
TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified(2)
Symbol
VIN
Parameter
Conditions
Supply Voltage
Min.
Typ.
4.5
Max.
Units
18
V
Input Under-Voltage Lockout Threshold
VIN Rising
VIN Falling
4.1
3.7
Supply Current (Quiescent)
IOUT = 0, VFB = 1.2 V, VEN > 2 V
1.6
2.5
mA
IOFF
Shutdown Supply Current
VEN = 0 V
1
10
A
VFB
Feedback Voltage
TA = 25 ºC
0.8
0.812
VUVLO
IIN
0.788
Load Regulation
IFB
V
V
0.5
%
1
%
Feedback Voltage Input Current
200
nA
ENABLE
VEN_OFF
VEN_ON
EN Input Threshold
VEN_HYS
EN Input Hysteresis
Off Threshold
On Threshold
0.6
2
200
Enable Leakage Current
SS Time
mV
A
1
CSS = 16 nF
V
2
ms
MODULATOR
fO
Frequency
400
DMAX
Maximum Duty Cycle
85
TMIN
Controllable Minimum On Time
500
600
kHz
%
150
ns
Current Sense Transconductance
7
A/V
Error Amplifier Transconductance
200
A / V
PROTECTION
ILIM
VOVP
Current Limit
3.5
A
Over-Voltage Protection
Off Threshold
On Threshold
2.5
960
800
mV
Over-Temperature Shutdown Limit
TJ Rising
TJ Falling
150
100
°C
High-Side Switch On-Resistance
VIN = 12 V
VIN = 5 V
80
120
mΩ
Low-Side Switch On-Resistance
VIN = 12 V
VIN = 5 V
50
60
mΩ
OUTPUT STATE
Note:
2. Specification in BOLD indicate an ambient temperature range of -40 °C to +85 °C. These specifications are guaranteed by design.
Rev. 0.5 December 2012
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Page 4 of 14
AOZ3010PI
Typical Performance Characteristics
Circuit of Figure 1. TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified.
Full Load Operation
Light Load Operation
Vin ripple
0.2V/div
Vin ripple
0.5V/div
Vo ripple
0.2V/div
Vo ripple
0.2V/div
VLX
10V/div
VLX
10V/div
IL
2A/div
IL
2A/div
2µs/div
2µs/div
Start Up to Full Load
Short Circuit Protection
Vin
5V/div
Vo
2V/div
VLX
10V/div
Vo
2V/div
IL
2A/div
1ms/div
10ms/div
50% to 100% Load Transient
Short Circuit Recovery
Vo
2V/div
VLX
10V/div
Vo ripple
0.2V/div
IL
2A/div
Io
2A/div
100µs/div
Rev. 0.5 December 2012
10ms/div
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Page 5 of 14
AOZ3010PI
Efficiency
Efficiency (VIN = 12V, L = 4.7µH) vs. Load Current
100
95
90
Efficiency (%)
85
80
75
5V OUTPUT
3.3V OUTPUT
1.8V OUTPUT
70
65
1.2V OUTPUT
60
55
50
0
0.5
1.0
1.5
2.0
Load Current (A)
Detailed Description
The AOZ3010PI is a current-mode step down regulator
with integrated high-side PMOS switch and low-side
NMOS switch. The AOZ3010PI operates from a 4.5 V to
18 V input voltage range and supplies up to 2 A of load
current. Features include enable control, power-on reset,
input under voltage lockout, output over voltage
protection, external soft-start, and thermal shut down.
The AOZ3010PI is available in an exposed pad SO-8
package.
Enable and Soft Start
The AOZ3010PI has an external soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1 V and voltage
on EN pin is HIGH. In soft start process, the FB voltage is
ramped to follow the voltage of soft start pin until it
reaches 0.8 V. The voltage of soft-start pin is charged by
internally 5 µA current.
The EN pin of the AOZ3010PI is active high. Connect the
EN pin to VIN if enable function is not used. Pulling EN to
ground will disable the AOZ3010PI. Do not leave EN
open. The voltage on EN pin must be above 2 V to
enable the AOZ3010PI. When the EN pin voltage falls
below 0.6 V, the AOZ3010PI is disabled.
Rev. 0.5 December 2012
Steady-State Operation
Under heavy load steady-state conditions, the converter
operates in fixed frequency and Continuous-Conduction
Mode (CCM).
The AOZ3010PI integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of inductor
current signal and ramp compensation signal, at PWM
comparator input. If the current signal is less than the
error voltage, the internal high-side switch is on. The
inductor current flows from the input through the inductor
to the output. When the current signal exceeds the error
voltage, the high-side switch is off. The inductor current is
freewheeling through the internal low-side N-MOSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and lowside switch.
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AOZ3010PI
Compared with regulators using freewheeling Schottky
diodes, the AOZ3010PI uses freewheeling NMOSFET to
realize synchronous rectification. This greatly improves
the converter efficiency and reduces power loss in the
low-side switch.
The AOZ3010PI uses a P-Channel MOSFET as the highside switch. This saves the bootstrap capacitor normally
seen in a circuit which is using an NMOS switch. It allows
100 % turn-on of the high-side switch to achieve linear
regulation mode of operation. The minimum voltage drop
from VIN to VO is the load current times DC resistance of
MOSFET plus DC resistance of buck inductor. It can be
calculated by equation below:
V O_MAX = V IN – I O  R DS  ON 
where;
VO_MAX is the maximum output voltage,
VIN is the input voltage from 4.5 V to 18 V,
IO is the output current from 0 A to 2 A, and
RDS(ON) is the on resistance of the internal MOSFET.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin with a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below.
R 1

V O = 0.8   1 + -------
R 2

R1 (kΩ)
R2 (kΩ)
0.8
1.0
Open
1.2
4.99
10
10
11.5
12.7
10.2
2.5
21.5
10
3.3
31.1
10
5.0
52.3
10
The AOZ3010PI has multiple protection features to
prevent system circuit damage under abnormal
conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ3010PI employs peak
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4 V and 2.5 V
internally. The peak inductor current is automatically
limited cycle by cycle.
When the output is shorted to ground under fault
conditions, the inductor current decays very slow during
a switching cycle because the output voltage is 0 V. To
prevent catastrophic failure, a secondary current limit is
designed inside the AOZ3010PI. The measured inductor
current is compared against a preset voltage which
represents the current limit. When the output current is
more than current limit, the high side switch will be turned
off. The converter will initiate a soft start once the overcurrent condition disappears.
Power-On Reset (POR)
Thermal Protection
Vo (V)
1.8
Protection Features
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds 4.1 V, the converter starts
operation. When input voltage falls below 3.7 V, the
converter will be shut down.
Some standard values of R1 and R2 for the most
commonly used output voltage values are listed in
Table 1.
1.5
Since the switch duty cycle can be as high as 100 %, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
An internal temperature sensor monitors the junction
temperature. The sensor shuts down the internal control
circuit and high side PMOS if the junction temperature
exceeds 150 °C. The regulator will restart automatically
under the control of soft-start circuit when the junction
temperature decreases to 100 °C.
Table 1.
Combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Rev. 0.5 December 2012
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Page 7 of 14
AOZ3010PI
Application Information
The basic AOZ3010PI application circuit is shown in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor must be connected to the VIN pin and
the GND pin of the AOZ3010PI to maintain steady input
voltage and filter out the pulsing input current. The
voltage rating of the input capacitor must be greater than
maximum input voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
For reliable operation and best performance, the input
capacitors must have a current rating higher than
ICIN_RMS at the worst operating conditions. Ceramic
capacitors are preferred for use as input capacitors
because of their low ESR and high ripple current rating.
Depending on the application circuits, other low ESR
tantalum capacitor or aluminum electrolytic capacitor
may be used. When selecting ceramic capacitors,
X5R or X7R type dielectric ceramic capacitors are
preferred for their better temperature and voltage
characteristics.
Note that the ripple current rating from capacitor
manufactures are based on a fixed life time. Further derating may be necessary for practical design
requirement.
VO  VO
IO

V IN = -----------------   1 – ---------  --------f  C IN 
V IN V IN
Inductor
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a
buck circuit, the RMS value of input capacitor current can
be calculated by:
VO 
VO 
-  1 – --------
I CIN_RMS = I O  -------V IN 
V IN
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
VO 
VO 
-
I L = -----------   1 – -------fL 
V IN
The peak inductor current is:
I L
I Lpeak = I O + -------2
if we let m equal the conversion ratio:
VO
-------- = m
V IN
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2. It can be seen that when VO is half of
VIN, CIN is under the worst current stress. The worst
current stress on CIN is 0.5 x IO.
High inductance provides a low inductor ripple current
but requires larger size inductor to avoid saturation.
Low ripple current reduces inductor core losses and also
reduces RMS current through inductor and switches.
This results in less conduction loss. Usually, peak to peak
ripple current on the inductor is designed to be
20 % to 40 % of output current.
0.4
When selecting the inductor, make sure it is able to
handle the peak current without saturation at the highest
operating temperature.
ICIN_RMS(m) 0.3
IO
0.2
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked for
thermal and efficiency requirements.
0.1
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise but cost
more than unshielded inductors. The choice depends on
EMI requirement, price and size.
0.5
0
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
Rev. 0.5 December 2012
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Page 8 of 14
AOZ3010PI
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
V O = I L   ESR CO + -------------------------

8fC 
where,
CO is output capacitor value, and
The AOZ3010PI employs peak current mode control for
ease of use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output L&C filter. It also greatly simplifies the
compensation loop design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
The zero is a ESR zero due to the output capacitor and
its ESR. It is can be calculated by:
ESRCO is the equivalent series resistance of the output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
f Z1 = -----------------------------------------------2  C O  ESR CO
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
1
V O = I L   -------------------------
8  f  C 
O
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
V O = I L  ESR CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used as
output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current.
It can be calculated by:
Rev. 0.5 December 2012
Loop Compensation
1
f P1 = ----------------------------------2  C O  R L
O
I L
I CO_RMS = ---------12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
The compensation design shapes the converter control
loop transfer function for the desired gain and phase.
Several different types of compensation networks can be
used with the AOZ3010PI. For most cases, a series
capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ3010PI, FB and COMP are the inverting input
and the output of the internal error amplifier. A series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
G EA
f P2 = ------------------------------------------2  C C  G VEA
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is the compensation capacitor in Figure 1.
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AOZ3010PI
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
1
f Z2 = ----------------------------------2  C C  R C
To design the compensation circuit, a target crossover
frequency fC to close the loop must be selected. The
system crossover frequency is where the control loop
has unity gain. The crossover is the also called the
converter bandwidth. Generally a higher bandwidth
means faster response to load transients. However, the
bandwidth should not be too high because of system
stability concern. When designing the compensation
loop, converter stability under all line and load condition
must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of the switching frequency.
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
VO
2  C C
R C = f C  ----------  ----------------------------V
G G
FB
EA
Thermal Management and Layout
Consideration
In the AOZ3010PI buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pad, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the low side NMOSFET.
Current flows in the second loop when the low side
NMOSFET is on.
In PCB layout, minimizing the area of the two loops will
reduce the noise of this circuit and improves efficiency.
A ground plane is strongly recommended to connect the
input capacitor, the output capacitor, and the PGND pin
of the AOZ3010PI.
In the AOZ3010PI buck regulator circuit, the major power
dissipating components are the AOZ3010PI and the
output inductor. The total power dissipation of converter
circuit can be measured by input power minus output
power:
P total_loss =  V IN  I IN  –  V O  I O 
CS
where;
fC is the desired crossover frequency. For best performance,
fC is set to be about 1/10 of the switching frequency;
VFB is 0.8V,
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V, and
GCS is the current sense circuit transconductance, which is
7 A/V
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of the selected
crossover frequency. CC can is selected by:
1.5
C C = ----------------------------------2  R C  f P1
The power dissipation of inductor can be approximately
calculated by output current and DCR value of the
inductor:
P inductor_loss = IO2  R inductor  1.1
The actual junction temperature can be calculated by the
power dissipation in the AOZ3010PI and the thermal
impedance from junction to ambient:
T junction =  P total_loss – P inductor_loss    JA
The maximum junction temperature of the AOZ3010PI is
150 ºC, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ3010PI under different ambient
temperature.
The thermal performance of the AOZ3010PI is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
The above equation can be simplified to:
CO  RL
C C = --------------------RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Rev. 0.5 December 2012
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Page 10 of 14
AOZ3010PI
Layout Considerations
The AOZ3010PI is an exposed pad SO-8 package.
Several layout tips are listed below for the best electric
and thermal performance.
1. The exposed pad (LX) is connected to internal PFET
and NFET drains. Connected a large copper plane to
LX pin to help thermal dissipation.
2. Do not use thermal relief connection to the VIN and
the PGND pin. Pour a maximized copper area to the
PGND pin and the VIN pin to help thermal dissipation.
3. Input capacitor should be connected to the VIN pin
and the PGND pin as close as possible.
4. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect them
only at one point to avoid the PGND pin noise coupling to the AGND pin.
5. Make the current trace from LX pins to L to Co to the
PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
7. Keep sensitive signal trace far away form the LX pad.
Rev. 0.5 December 2012
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Page 11 of 14
AOZ3010PI
Package Dimensions, SO-8 EP1
Gauge plane
0.2500
D0
C
L
L1
E2
E1
E3
E
L1'
D1
Note 5
D
θ
7 (4x)
A2
e
B
A
A1
Dimensions in millimeters
RECOMMENDED LAND PATTERN
3.70
2.20
5.74
2.71
2.87
0.80
1.27
0.635
UNIT: mm
Symbols
A
Min.
1.40
Nom.
1.55
A1
A2
B
0.00
1.40
0.31
0.05
1.50
0.406
C
D
0.17
4.80
—
4.96
D0
D1
E
e
E1
E2
E3
L
y
θ
| L1–L1' |
L1
3.20
3.10
5.80
—
3.80
2.21
Max.
1.70
0.10
1.60
0.51
0.25
5.00
3.60
3.50
6.20
—
4.00
2.61
3.40
3.30
6.00
1.27
3.90
2.41
0.40 REF
1.27
0.40
0.95
0.10
—
—
0°
—
8°
3°
0.04
0.12
1.04 REF
Dimensions in inches
Symbols
A
A1
A2
B
C
D
D0
D1
E
e
E1
E2
E3
L
y
θ
| L1–L1' |
L1
Min.
0.055
0.000
0.055
0.012
0.007
0.189
Nom.
0.061
0.002
Max.
0.067
0.004
0.059
0.016
—
0.063
0.020
0.010
0.195 0.197
0.134 0.142
0.130 0.138
0.236 0.244
0.050
—
0.153 0.157
0.095 0.103
0.016 REF
0.016 0.037 0.050
—
0.004
—
0.126
0.122
0.228
—
0.150
0.087
0°
—
3°
8°
0.002 0.005
0.041 REF
Notes:
1. Package body sizes exclude mold flash and gate burrs.
2. Dimension L is measured in gauge plane.
3. Tolerance 0.10mm unless otherwise specified.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Followed from JEDEC MS-012
Rev. 0.5 December 2012
www.aosmd.com
Page 12 of 14
AOZ3010PI
Tape and Reel Dimensions, SO-8 EP1
Carrier Tape
P1
D1
P2
T
E1
E2
E
B0
K0
A0
D0
P0
Feeding Direction
UNIT: mm
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
Reel
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.25
±0.10
W1
S
G
N
M
K
V
R
H
W
UNIT: mm
W
N
Tape Size Reel Size
M
12mm
ø330
ø330.00 ø97.00 13.00
±0.10 ±0.30
±0.50
W1
17.40
±1.00
H
K
ø13.00
10.60
+0.50/-0.20
S
2.00
±0.50
G
—
R
—
V
—
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 0.5 December 2012
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min. or
125 empty pockets
Page 13 of 14
AOZ3010PI
Part Marking
Z3010PI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 0.5 December 2012
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 14 of 14