Datasheet

AOZ3054DI
EZBuck™ 6A Synchronous Buck Regulator
General Description
Features
The AOZ3054DI is a high efficiency, easy to use, 6A
synchronous buck regulator with a smart mode adoption
function. The AOZ3054DI works from 4.5V to 18V input
voltage range, and provides up to 6 A of continuous
output current with an output voltage adjustable down to
0.8V.
 4.5V to 18V operating input voltage range
The AOZ3054DI comes in a DFN5x6 package and is
rated over a -40°C to +85°C operating ambient
temperature range.
 Internal soft start
 Synchronous Buck: 30mΩ internal high-side switch
and 12mΩ internal low-side switch (at 12V)
 PEM (pulse energy mode) enables 80% plus efficiency
with IO = 10mA (VIN = 12V, VO = 5V)
 Up to 95% efficiency
 Output voltage adjustable to 0.8 V
 6A continuous output current
 500kHz PWM operation at heavy load
 Cycle-by-cycle current limit
 Pre-bias start-up
 Short-circuit protection
 Thermal shutdown
 DFN5x6 package
Applications
 LCD TV
 Set top boxes
 DVD and Blu-ray players/recorders
 Cable modems
Typical Application
VIN
COS
10nF
C1
10μF
VIN
EN
VOS
AOZ3054
LX
COMP
ROS
10Ω
VOUT
L1
6.8μH
R1
FB
RC
AGND
PGND
C2, C3
22μF
R2
CC
Figure 1. 5V, 6A Synchronous Buck Regulator, Fs = 500kHz
Rev. 1.0 December 2015
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Page 1 of 14
AOZ3054DI
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ3054DI
-40 °C to +85 °C
DFN5x6-8L
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
VIN
1
8
PGND
AGND
2
7
LX
FB
3
6
VOS
COMP
4
5
EN
LX
DFN5x6-8
(Top View)
Pin Description
Pin Number
Pin Name
1
VIN
Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high,
the device starts up.
2
AGND
Analog ground. AGND is the reference point for controller section. AGND needs to be
electrically connected to PGND.
3
FB
Feedback input. The pin is used to set the output voltage via a resistive voltage divider
between the output and AGND.
4
COMP
External loop compensation pin. Connect a RC network between COMP and AGND to
compensate the control loop.
5
EN
6
VOS
7
LX
8
PGND
Exposed Pad
LX
Rev. 1.0 December 2015
Pin Function
Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the
device. If on/off control in not needed, connect EN to VIN and do not leave it open.
VO Sense pin for protection purpose and smart mode change adoption.
Switching node.
Power ground. PGND needs to be electrically connected to AGND.
Switching node. LX is the drain of the internal power PFET. LX is used as the thermal pad
of the power stage.
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AOZ3054DI
Block Diagram
VIN
UVLO
& POR
EN
LDO
Regulator
OTP
+
Reference
& Bias
ISen
Iinfo
Softstart
–
Q1
ILimit
+
+
EAmp
FB
–
–
PWM
Control
Logic
PWM
Comp
+
VOS
PWM/PEM
Logic
+
FET
Driver
LX
Q2
500kHz
Oscillator
COMP
+
Protection
0.96V
PWM/PEM
Master Control
Over-Voltage
Protection
Comparator
–
PEM
Control
Logic
Vref
Iinfo
Iinfo
AGND
PGND
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum Ratings may damage the
device.
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Parameter
Supply Voltage (VIN)
LX to AGND
LX to AGND (20 ns)
EN to AGND
VFB, VOS, COMP to AGND
PGND to AGND
Rating
Parameter
20V
-0.7V to VIN +0.3V
-5V to 22V
-0.3V to VIN +0.3V
-0.3V to 6V
Output Voltage Range
Ambient Temperature (TA)
Package Thermal Resistance
DFN5x6 (ΘJA)
4.5V to 18V
0.8V to 0.85*VIN
-40°C to +85°C
40°C/W
-0.3V to +0.3V
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
ESD Rating(1)
Supply Voltage (VIN)
Rating
2.0kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5 kΩ in series with 100 pF.
Rev. 1.0 December 2015
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AOZ3054DI
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 5V unless otherwise specified(2)
Symbol
VIN
VUVLO
IIN
Parameter
Conditions
Supply Voltage
Input Under-Voltage Lockout
Threshold
Supply Current (Quiescent)
Min.
Typ.
4.5
Max.
Units
18
V
VIN Rising
4.0
V
VIN Falling
3.7
V
VIN = 12V, VFB = 1.2 V, IOUT = 0A
0.35
0.5
mA
1
2
µA
0.8
0.812
V
IOFF
Shutdown Supply Current
VEN = 0 V
VFB
Feedback Voltage
TA = 25 °C
RO
Load Regulation
0.5
%
SV
Line Regulation
1
%
IFB
Feedback Voltage Input Current
VEN
EN Input Threshold
0.788
10
Off Threshold
On Threshold
200
nA
0.6
V
V
2
VHYS
EN Input Hysteresis
200
IEN
EN Leakage Current
0.1
tSS
SS Time
mV
µA
1
6
ms
MODULATOR
fO
Frequency
DMAX
Maximum Duty Cycle
TMIN
Controllable Minimum On-Time
Heavy Load
400
Heavy Load
500
600
kHz
85
%
120
ns
gm_CS
Current Sense Transconductance
8
A/ V
gm_EA
Error Amplifier Transconductance
200
µA / V
7.5
A
TJ Rising
150
°C
TJ Falling
100
°C
Off Threshold
960
mV
On Threshold
860
mV
PROTECTION
ILIM
TOTP
VOVP
Current Limit
Over-Temperature Shutdown Limit
Over-Voltage Protection
6.5
OUTPUT STAGE
RH
High-Side Switch On-Resistance
VIN = 12 V
30
mΩ
RL
Low-Side Switch On-Resistance
VIN = 12 V
15
mΩ
Note:
2. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are not guaranteed to operate beyond the
Maximum Operating ratings.
Rev. 1.0 December 2015
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AOZ3054DI
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3 V unless otherwise specified.
Light Load Operation
Full Load Operation
VLX
5V/div
VLX
5V/div
Vo ripple
50mV/div
IL
2A/div
Vo ripple
50mV/div
IL
1A/div
Vin ripple
200mV/div
Vin ripple
500mV/div
1μs/div
2μs/div
Light Load to Heavy Load Operation
Heavy Load to Light Load Operation
VLX
5V/div
VLX
5V/div
Vo ripple
200mV/div
Vo ripple
200mV/div
IL
2A/div
IL
2A/div
20μs/div
20μs/div
Short Circuit Protection
Short Circuit Recovery
VLX
5V/div
VLX
5V/div
Vo
1V/div
Vo
1V/div
IL
2A/div
IL
2A/div
20ms/div
Rev. 1.0 December 2015
20ms/div
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AOZ3054DI
Typical Performance Characteristics (Continued)
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3 V unless otherwise specified.
50 % to 100 % Load Transient
Start Up to Full Load
Vin
5V/div
Vo ripple
200mV/div
Vo
1V/div
Io
2A/div
Io
2A/div
100μs/div
5ms/div
Efficiency
Efficiency (VIN = 12V) vs. Load Current
Derating at 5V Input (VOS = 0V) vs. Temperature
100
6.0
5.5
5.0
Output Current (A)
Efficiency (%)
90
80
70
5V OUTPUT, L=6.8μH
3.3V OUTPUT, L=4.7μH
2.5V OUTPUT, L=4.7μH
60
1.8V OUTPUT, L=2.2μH
1.2V OUTPUT, L=2.2μH
50
0.01
4.5
4.0
3.5
3.0
2.5
2.0
VOUT = 3.3V
VOUT = 1.8V
1.5
VOUT = 1.0V
1.0
0.1
1
10
Load Current (A)
Rev. 1.0 December 2015
20
30
40
50
60
70
80
90
Ambient Temperature (ºC)
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AOZ3054DI
Detailed Description
The AOZ3054DI is a current-mode step down regulator
with an integrated high-side PMOS switch and a low-side
NMOS switch. The AOZ3054DI operates from a 4.5V to
18V input voltage range and supplies up to 6A of load
current. Features include enable control, power-on reset,
input under voltage lockout, output over voltage
protection, external soft start and thermal shut down.
The AOZ3054DI is available in a DFN5x6 package.
Enable and Soft Start
The AOZ3054DI has an internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. The soft start process
begins when the input voltage rises to 4.1V and voltage
on the EN pin is HIGH. In the soft start process, the
output voltage is typically ramped to regulation voltage in
6ms. The 6ms soft start time is set internally.
The EN pin of the AOZ3054DI is active high. Connect the
EN pin to VIN if the enable function is not used. Pulling
EN to ground will disable the AOZ3054DI. Do not leave
EN open. The voltage on the EN pin must be above 2V to
enable the AOZ3054DI. When the EN pin voltage falls
below 0.6V, the AOZ3054DI is disabled.
VOS Setting
VO Sense pin can be set for protection purpose. COMP
protection is active when VOS > 2.4V, or else COMP
protection will be disabled. VO Sense pin can also be set
for 2nd UVLO. When VIN > 8.3V and VOS > 2.4V, the
UVLO will be set to 7.2V rising and 6.5V falling, or else
the UVLO is default to 4V rising and 3.7V falling.
The VO Sense pin is suggested to connect to output or
GND.
PEM Operation
When VOS > 2.4V, AOZ3054DI will operate with pulse
energy mode at light load to obtain high efficiency. When
VOS < 2.4V, PEM is active only when VIN > 8.3V. In pulse
energy mode, the PWM will not turn off until the inductor
current reaches to 800mA and the current signal exceeds
the error voltage.
of the FB pin voltage and reference voltage is amplified
by the internal transconductance error amplifier. The
error voltage, which shows on the COMP pin, is
compared against the current signal, which is the sum of
inductor current signal and ramp compensation signal, at
the PWM comparator input. If the current signal is less
than the error voltage, the internal high-side switch is on.
The inductor current flows from the input through the
inductor to the output. When the current signal exceeds
the error voltage, the high-side switch is off. The inductor
current is freewheeling through the internal low-side
NMOS switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both the
high-side and the low-side switch.
Compared with regulators using freewheeling Schottky
diodes, the AOZ3054DI uses a freewheeling NMOS to
realize synchronous rectification. This greatly improves
the converter efficiency and reduces power loss in the
low-side switch.
The AOZ3054DI uses a P-Channel MOSFET as the
high-side switch. This saves the bootstrap capacitor
normally seen in a circuit using an NMOS switch.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin using a resistor divider network as shown in
Figure 1. The resistor divider network includes R1 and
R2. Usually, a design is started by picking a fixed R2
value and calculating the required R1 with the equation
below:
R 1

V O = 0.8 ×  1 + -------
R 2

Some standard value of R1 and R2 for the most common
output voltages are listed in Table 1.
Table 1.
VO (V)
R1 (kΩ)
R2 (kΩ)
0.8
1.0
Open
1.2
4.99
10
1.5
10
11.5
PWM Operation
1.8
12.7
10.2
When VIN < 7V and VOS < 2.4V, or under heavy load
steady-state conditions, the converter operates in fixed
frequency and Continuous Conduction Mode (CCM).
2.5
21.5
10
3.3
31.1
10
5.0
52.3
10
The AOZ3054DI integrates an internal PMOS as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the highside power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
Rev. 1.0 December 2015
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
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AOZ3054DI
Protection Features
Application Information
The AOZ3054DI has multiple protection features to
prevent system circuit damage under abnormal
conditions.
The basic AOZ3054DI application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ3054DI employs peak
current mode control, the peak inductor current is
automatically limited
cycle-by-cycle.
AOZ3054DI also has internal short-circuit protection to
prevent catastrophic failure under output short
conditions. When the FB pin voltage is below 0.2V after
half soft start time, the short-circuit protection circuit is
triggered and device will stop switching. The AOZ3054DI
will enter hiccup mode if the over current or output short
conditions continue.
AOZ3054DI. The measured inductor current is compared
against a preset voltage which represents the current
limit. When the output current is greater than the current
limit, the high-side switch will be turned off. The converter
will initiate a soft start once the over-current condition is
resolved.
The input capacitor must be connected to the VIN and
the PGND pins of AOZ3054DI to maintain steady input
voltage and filter out the pulsing input current. The
voltage rating of input capacitor must be greater than
maximum input voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
VO  VO
IO

ΔV IN = ----------------- ×  1 – --------- × --------f × C IN 
V IN V IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
VO 
VO 
-  1 – --------
I CIN_RMS = I O × -------V IN 
V IN
Power-On Reset (POR)
if we let m equal the conversion ratio:
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds UVLO rising point, the
converter starts operation. When input voltage falls below
UVLO falling point, the converter will be shut down.
VO
-------- = m
V IN
AOZ3054DI provides two kinds of UVLO threshold.
When VIN > 8.2V and VOS > 2.4V, the UVLO will be set to
7.2V rising and 6.5V falling, or else the UVLO is default
to 4V rising and 3.7V falling.
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2 below. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
worst current stress on CIN is 0.5 x IO.
Thermal Protection
0.5
An internal temperature sensor monitors the junction
temperature. The sensor shuts down the internal control
circuit and high-side PMOS if the junction temperature
exceeds 150 ºC. The regulator will restart automatically
under the control of the soft-start circuit when the junction
temperature decreases to 100 ºC.
0.4
ICIN_RMS(m) 0.3
IO
0.2
0.1
0
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
Rev. 1.0 December 2015
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Page 8 of 14
AOZ3054DI
For reliable operation and best performance, the input
capacitors must have a current rating higher than
ICIN_RMS at the worst operating conditions. Ceramic
capacitors are preferred for input capacitors because of
their low ESR and high current rating. Depending on the
application circuits, other low ESR tantalum capacitors
may be used. When selecting ceramic capacitors, X5R or
X7R type dielectric ceramic capacitors should be used
for their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor
manufactures are based on a certain operating life time.
Further de-rating may be necessary for practical design.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For a given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
ΔV O = ΔI L ×  ESR CO + -------------------------

8×f×C 
O
VO 
VO 
-
ΔI L = ----------- ×  1 – -------f×L 
V IN
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
The peak inductor current is:
ΔI L
I Lpeak = I O + -------2
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on the inductor is designed to be 20%
to 40% of output current.
When selecting the inductor, confirm it is able to handle
the peak current without saturation at the highest
operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on the inductor needs to be checked
for thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. However,
they cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
When a low ESR ceramic capacitor is used as the output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
ΔV O = ΔI L × ------------------------8×f×C
O
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔV O = ΔI L × ESR CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitors are
recommended as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
ΔI L
I CO_RMS = ---------12
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Page 9 of 14
AOZ3054DI
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, the output capacitor could
be overstressed.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
Loop Compensation
To design the compensation circuit, a target crossover
frequency fC to close the loop must be selected. The
system crossover frequency is where the control loop
has unity gain. The crossover is the also called the
converter bandwidth. Generally a higher bandwidth
means faster response to load transients. However, the
bandwidth should not be too high because of system
stability concern. When designing the compensation
loop, converter stability under all line and load condition
must be considered.
The AOZ3054DI employs peak current mode control for
ease of use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output L&C filter. It also greatly simplifies the
compensation loop design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of the switching frequency.
1
f P1 = ----------------------------------2π × C O × R L
The zero is a ESR zero due to the output capacitor and
its ESR. It is can be calculated by:
1
f Z1 = -----------------------------------------------2π × C O × ESR CO
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
VO
2π × C C
R C = f C × ---------- × ----------------------------V
G ×G
where;
FB
CO is the output filter capacitor, RL is load resistor value,
and ESRCO is the equivalent series resistance of output
capacitor.
The compensation design shapes the converter control
loop transfer function for the desired gain and phase.
Several different types of compensation networks can be
used with the AOZ3054DI. For most cases, a series
capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ3054DI, FB and COMP are the inverting input
and the output of the internal error amplifier. A series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
G EA
f P2 = ------------------------------------------2π × C C × G VEA
EA
CS
where;
fC is the desired crossover frequency. For best
performance, fC is set to be about 1/10 of the switching
frequency, VFB is 0.8V, GEA is the error amplifier
transconductance, which is 200 x 10-6 A/V, and GCS is
the current sense circuit transconductance, which is 8 A/
V.
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of the selected
crossover frequency. CC can is selected by:
1.5
C C = ----------------------------------2π × R C × f P1
The above equation can be simplified to:
where;
GEA is the error amplifier transconductance, which is 200
x 10-6 A/V, GVEA is the error amplifier voltage gain, which
is 500 V/V, and CC is the compensation capacitor in
Figure 1.
Rev. 1.0 December 2015
1
f Z2 = ----------------------------------2π × C C × R C
CO × RL
C C = --------------------RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
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AOZ3054DI
Thermal Management and Layout
Considerations
Layout Considerations
In the AOZ3054DI buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pad, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high-side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the low-side NMOS. Current flows in the second loop when the low-side NMOS is
on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capacitor, output capacitor, and PGND pin of the AOZ3054DI.
In the AOZ3054DI buck regulator circuit, the major power
dissipating components are the AOZ3054DI and the output inductor. The total power dissipation of converter circuit can be measured by input power minus output
power.
P total_loss = V IN × I IN – V O × I O
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
The AOZ3054DI is a DFN5x6 package. Layout tips are
listed below for the best electric and thermal performance.
1. The exposed pad (LX) is connected to internal PFET
and NFET drains. Connect a large copper plane to
the LX pin to help thermal dissipation.
2. Do not use thermal relief connection to the VIN and
the PGND pins. Pour a maximized copper area to the
PGND and the VIN pins to help thermal dissipation.
3. Input capacitor should be connected as close as possible to the VIN and the PGND pins.
4. A ground plane is suggested. If a ground plane is not
used, separate PGND from AGND and connect them
only at one point to avoid the PGND pin noise coupling to the AGND pin.
5. Make the current trace from the LX pin to L to CO to
the PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
7. Keep sensitive signal traces far away from the LX
pad.
P inductor_loss = IO2 × R inductor × 1.1
The actual junction temperature can be calculated with
power dissipation in the AOZ3054DI and thermal impedance from junction to ambient.
T junction = ( P total_loss – P inductor_loss ) × Θ JA
The maximum junction temperature of AOZ3054DI is
150ºC, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ3054DI under different ambient
temperatures.
The thermal performance of the AOZ3054DI is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental conditions.
Rev. 1.0 December 2015
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Page 11 of 14
AOZ3054DI
Package Dimensions, DFN5x6, 8L, EP1_P
0.05
b
c
θ
E
E1
VIEW ‘A’
A
e
TOP VIEW
SIDE VIEW
D
D1
L1
A1
L
E3
E2
VIEW 'A'
(SCALE 5:1)
BOTTOM VIEW
Dimensions in millimeters
RECOMMENDED LAND PATTERN
0.5000
0.6500
1.6750
3.3500
4.6000
2.7500
Symbols
Min.
Nom.
Max.
Symbols
Min.
Nom.
Max.
A
A1
0.85
0.00
0.95
—
1.00
0.05
A
A1
0.033
0.000
0.037
—
0.039
0.002
b
0.30
0.40
0.016
0.020
c
D
0.15
0.50
b
0.012
0.20
0.25
5.20 BSC
c
D
0.006
D1
E
E1
4.35 BSC
5.55 BSC
6.05 BSC
D1
E
E1
0.171 BSC
0.219 BSC
0.238 BSC
E2
E3
3.15 BSC
1.575 BSC
E2
E3
0.124 BSC
0.062 BSC
e
1.2700
UNIT: mm
Dimensions in inches
L
L1
θ
1.27 BSC
0.45
0
0°
0.55
—
—
e
0.65
0.15
10°
L
L1
θ
0.008 0.010
0.205 BSC
0.050 BSC
0.018
0
0°
0.022
—
—
0.026
0.006
10°
Notes:
1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils each.
2. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
Rev. 1.0 December 2015
www.aosmd.com
Page 12 of 14
AOZ3054DI
Tape and Reel Dimensions, DFN5x6
Carrier Tape
P1
D1
T
P2
Y
E1
E2
E
C
L
B0
Y
K0
D0
P0
A0
Feeding Direction
UNIT: MM
Package
A0
B0
K0
D0
D1
DFN 5x6
(12mm)
6.30
±0.10
5.45
±0.10
1.30
±0.10
1.50
Min.
1.55
±0.05
Reel
E
E1
12.00 1.75
±0.30 ±0.10
E2
P0
P1
P2
T
5.50
±0.10
8.00
±0.10
4.00
±0.10
2.00
±0.10
0.30
±0.05
W1
S
G
N
M
K
V
R
H
W
UNIT: MM
Tape Size
Reel Size
12 mm
ø330
M
N
ø330.0 ø97.00
±0.50
±0.10
W
W1
H
K
S
G
R
V
13.00
±0.30
17.40
±1.00
ø13.0
10.60
2.0
±0.5
—
—
—
+0.50/-0.20
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 1.0 December 2015
Components Tape
Orientation in Pocket
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Leader Tape
500mm min. or
125 empty pockets
Page 13 of 14
AOZ3054DI
Part Marking
AOZ3054DI
(DFN5x6, 8L)
Z3054DI
Part Number Code
FAY W LT
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.0 December 2015
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 14 of 14