IDT71V124 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description 128K x 8 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/GND) for reduced noise Commercial (0°C to +70°C) and Industrial (–40°C to +85°C) temperature options Equal access and cycle times — Industrial and Commercial: 15/20ns One Chip Select plus one Output Enable pin Bidirectional inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Available in 32-pin 400 mil Plastic SOJ. The IDT71V124 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using IDT’s high-performance, highreliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a costeffective solution for high-speed memory needs. The JEDEC center power/GND pinout reduces noise generation and improves system performance. The IDT71V124 has an output enable pin which operates as fast as 7ns, with address access times as fast as 15ns available. All bidirectional inputs and outputs of the IDT71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. The IDT71V124 is packaged in 32-pin 400 mil Plastic SOJ. E C N I N A T CE 4S NS R S 12 IG A V E P L 71 DES O ER W S D E B R N Functional Block Diagram A0 • • • • • • ADDRESS 1,048,576-BIT MEMORY ARRAY DECODER A16 O I/O0 - I/O7 O R O F 8 I/O CONTROL 8 8 WE OE CS CONTROL LOGIC 3484 drw 01 AUGUST 2000 1 ©2000 Integrated Device Technology, Inc. DSC-3484/05 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Pin Configuration A0 A1 A2 A3 CS I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7 3484 drw 02 WE L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Output Disabled X X High-Z Deselected – Standby (I SB) X X High-Z Deselected – Standby (ISB1 ) VHC I/O NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VDD –0.2V. 3. Other inputs ≥VHC or ≤VLC. Capacitance O Function Parameter(1) CIN Input Capacitance CI/O I/O Capacitance TA Operating Temperature –0.5 to +4.1 V 0 to +70 o C C C TBIAS Temperature Under Bias –55 to +125 o TSTG Storage Temperature –55 to +125 o PT Power Dissipation IOUT DC Output Current 0.5 E W 50 mA 3484 tbl 02 Grade Temperature GND VDD Commercial 0°C to +70°C 0V See Below Industrial –40°C to +85°C 0V See Below 3484 tb l 02a 3484 tbl 01 Recommended DC Operating Conditions (TA = +25°C, f = 1.0MHz, SOJ package) Symbol Terminal Voltage with Respect to GND Unit (2) Recommended Operating Temperature and Supply Voltage OE (3) VTERM Value NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. VTERM must not exceed VDD + 0.5V. CS H Rating (2) C N I N A T CE 4S NS R S 12 IG A V E P L 71 DES O ER W S D E B R N SOJ Top View Truth Table(1,2) Symbol A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8 1 32 2 31 3 30 4 29 28 5 6 SO32-3 27 26 7 25 8 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Symbol O R O F Conditions Max. Unit VIN = 3dV 8 pF VOUT = 3dV 8 pF 3484 tbl 03 NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested. Parameter Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V VDD Supply Voltage GND Ground VIH Input High Voltage 2.0 ____ VDD +0.3 V VIL Input Low Voltage –0.3(1) ____ 0.8 V 3484 tbl 04 NOTE: 1. VIL (min.) = –1V for pulse width less than 5ns, once per cycle. DC Electrical Characteristics (VDD = 3.3V ± 10%, Commercial and Industrial Temperature Ranges) IDT71V124 Symbol |ILI| |ILO| VOL VOH Parameter Test Condition Min. Max. Unit Input Leakage Current VDD = Max., VIN = GND to VDD ___ 5 µA Output Leakage Current VDD = Max., CS = VIH, VOUT = GND to VDD ___ 5 µA IOL = 8mA, VDD = Min. ___ 0.4 V 2.4 ___ V Output Low Voltage Output High Voltage IOH = –8mA, VDD = Min. 3484 tbl 05 6.42 2 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges DC Electrical Characteristics(1) (VDD = 3.3V ± 10%, VLC = 0.2V, VHC = VDD – 0.2V) 71V124S15 Symbol Parameter 71V124S20 Com'l. Ind. Com'l. Ind. Unit ICC Dynamic Operating Current CS < VIL, Outputs Open, VDD = Max., f = f MAX(2) 100 120 95 115 mA ISB Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VDD = Max., f = f MAX(2) 35 40 30 35 mA ISB1 Full Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VDD = Max., f = 0(2) VIN < VLC or VIN > VHC 5 7 5 7 mA E C N I N A T CE 4S NS R S 12 IG A V E P L 71 DES O ER W S D E B R N NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 3484 tbl 06 AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels Output Reference Levels 1.5V 1.5V AC Test Load See Figure 1 and 2 3484 tbl 07 3.3V DATA OUT 30pF O 3.3V O R O F 298Ω 298Ω DATAOUT 5pF* 216Ω 216Ω 3484 drw 04 3484 drw 03 *Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 6.42 3 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 3.3V ± 10%, Commercial and Industrial Ranges) 71V124S15 Symbol Parameter 71V124S20 Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 ____ 20 ____ ns tAA Address Access Time ____ 15 ____ 20 ns tACS Chip Select Access Time ____ 15 ____ 20 ns tCLZ(1) Chip Select to Output in Low-Z 3 ____ 3 ____ ns tCHZ(1) Chip Deselect to Output in High-Z 0 0 8 ns tOE Output Enable to Output Valid ____ 8 ns tOLZ(1) Output Enable to Output in Low-Z 0 ____ 0 ____ ns tOHZ(1) Output Disable to Output in High-Z 0 5 0 7 ns tOH Output Hold from Address Change 4 ____ 4 ____ ns tPU(1) Chip Select to Power-Up Time 0 ____ 0 ____ ns tPD(1) Chip Deselect to Power-Down Time ____ 15 ____ 20 ns tWC Write Cycle Time 15 ____ 20 ____ ns tAW Address Valid to End of Write 12 ____ 15 ____ ns 15 ____ ns WRITE CYCLE C 7 E IN N A T CE 4S NS R S 12 IG A V E P L 71 DES O ER W S D E B R N ____ 7 tCW Chip Select to End of Write 12 ____ tAS Address Set-up Time 0 ____ 0 ____ ns tWP Write Pulse Width 12 ____ 15 ____ ns 0 ____ 0 ____ ns 8 ____ 9 ____ ns 0 ____ 0 ____ ns tWR Write Recovery Time tDW Data Valid to End of Write tDH Data Hold Time tOW(1) Output Active from End of Write 3 ____ 4 ____ ns tWHZ(1) Write Enable to Output in High-Z 0 5 0 8 ns O O R O F NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 6.42 4 3484 tbl 08 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1 (1) tRC ADDRESS tAA OE tOE tOLZ CS tCLZ (5) (5) tACS (3) C HIGH IMPEDANCE DATAOUT (5) tOHZ (5) DATAOUT VALID IN N A T CE 4S NS R S 12 IG A V E P L 71 DES O ER W S D E B R N tPD tPU VCC SUPPLY ICC CURRENT ISB E tCHZ 3484 drw 05 Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATAOUT VALID DATAOUT VALID NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. O O R O F 6.42 5 3484 drw 06 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No.1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tWR tAS WE tWP (2) (5) HIGH IMPEDANCE tDW DATAIN C tOW (3) DATAOUT E IN N A T CE 4S NS R S 12 IG A V E P L 71 DES O ER W S D E B R N tWHZ (5) tCHZ (5) (3) tDH DATAIN VALID 3484 drw 07 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS WE DATAIN O tAS (3) tCW O R O F tWR tDW tDH DATAIN VALID 3484 drw 08 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured ±200mV from steady state. 6.42 6 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges Ordering Information IDT 71V124 Device Type S XX X X Power Speed Package Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Y 400-mil SOJ (SO32-3) E C N I N A T CE 4S NS R S 12 IG A V E P L 71 DES O ER W S D E B R N 15 20 Speed in nanoseconds 3484 drw 09 O O R O F 6.42 7 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges Datasheet Document History 11/1/99 Updated to new format Expressed commercial and industrial temperature ranges on DC Electrical table Added Recommended Operating Temperature and Supply Voltage table Expressed commercial and industrial ranges on AC Electrical table Revised footnotes and notes on AC Electrical table Revised footnotes on Write Cycle No. 1 diagram Added datasheet document history Part in obsolescence; order part 71V124SA. See PDN# S-0004 Pg. 2 Pg. 2 Pg. 4 Pg. 4 Pg. 6 Pg. 8 08/30/00 E O C N I N A T CE 4S NS R S 12 IG A P LE 71VDES O ER W S D E B R N O R O F CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 8 for Tech Support: [email protected] 800-544-7726, x4033