IDT71V016SA 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description 64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times — Commercial: 10/12/15/20ns — Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Single 3.3V power supply Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71V016 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA. Functional Block Diagram OE A0 – A15 Output Enable Buffer Address Buffers Row / Column Decoders I/O15 CS 8 Chip Enable Buffer High Byte I/O Buffer 8 I/O8 WE Write Enable Buffer 16 64K x 16 Memory Array Sense Amps and Write Drivers I/O7 8 Low Byte I/O Buffer 8 I/O0 BHE Byte Enable Buffers BLE 3834 drw 01 OCTOBER 2011 1 ©2011 Integrated Device Technology, Inc. DSC-3834/11 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Pin Configurations A4 1 44 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE A0 5 40 BHE CS 6 39 BLE I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 34 VSS 33 VDD SO44-1 SO44-2 A5 VDD 11 VSS 12 I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A15 18 27 A8 A14 19 26 A9 A13 20 25 A10 A12 21 24 A11 NC 22 23 NC 1 2 3 4 5 6 A BLE OE A0 A1 A2 NC B I/O8 BHE A3 A4 CS I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 3834 tbl 02a FBGA (BF48-1) Top View Pin Description 3834 drw 02 SOJ/TSOP Top View A0 – A15 Address Inputs Input CS Chip Select Input WE Write Enable Input OE Output Enable Input BHE High Byte Enable Input BLE Low Byte Enable Input I/O0 – I/O15 Data Input/Output I/O VDD 3.3V Power VSS Ground Power Gnd 3834 tbl 01 Truth Table(1) CS OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 H X X X X High-Z High-Z Deselected – Standby L L H L H DATAOUT High-Z Low Byte Read L L H H L High-Z DATAOUT High Byte Read L L H L L DATAOUT DATAOUT Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled Function 3834 tbl 02 NOTE: 1. H = VIH, L = VIL, X = Don't care. 6.42 2 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Symbol Rating Value Unit VDD Supply Voltage Relative to VSS –0.5 to +4.6 V VIN, VOUT Terminal Voltage Relative to VSS –0.5 to VDD+0.5 V TBIAS Temperature Under Bias –55 to +125 o TSTG Storage Temperature –55 to +125 o PT Power Dissipation 1.25 W IOUT DC Output Current 50 mA Recommended Operating Temperature and Supply Voltage Grade Temperature VSS VDD Commercial 0°C to +70°C 0V See Below Industrial -40°C to +85°C 0V See Below 3834 tbl 04 C Recommended DC Operating Conditions C Symbol 3834 tbl 03 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VDD (1) VDD (2) Capacitance (TA = +25°C, f = 1.0MHz, SOJ package) (1) Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = 3dV 6 pF CI/O I/O Capacitance VOUT = 3dV 7 pF Parameter Min. Typ. Max. Unit Supply Voltage 3.15 3.3 3.6 V Supply Voltage 3.0 3.3 3.6 V 0 0 0 V Vss Ground VIH Input High Voltage 2.0 ____ VDD+0.3(3) V VIL Input Low Voltage –0.3(4) ____ 0.8 V NOTES: 1. For 71V016SA10 only. 2. For all speed grades except 71V016SA10. 3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 4. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. 3834 tbl 05 3834 tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. DC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) IDT71V016SA Symbol Parameter Test Condition Min. Max. Unit 5 µA |ILI| Input Leakage Current VDD = Max., VIN = VSS to VDD ___ |ILO| Output Leakage Current VDD = Max., CS = VIH, VOUT = VSS to VDD ___ 5 µA VOL Output Low Voltage IOL = 8mA, VDD = Min. ___ 0.4 V VOH Output High Voltage IOH = –4mA, VDD = Min. 2.4 ___ V DC Electrical Characteristics(1,2) 3834 tbl 07 (VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V) 71V016SA10 Symbol ICC Parameter Dynamic Operating Current CS ≤ VLC, Outputs Open, VDD = Max., f = fMAX(3) ISB Dynamic Standby Power Supply Current CS ≥ VHC, Outputs Open, VDD = Max., f = fMAX(3) ISB1 Full Standby Power Supply Current (static) CS ≥ VHC, Outputs Open, VDD = Max., f = 0(3) Max. Typ. (5) (4) 71V016SA12 71V016SA15 71V016SA20 Com'l Only Com'l Ind Com'l Ind Com'l Ind 160 150 160 130 130 120 120 65 60 -- 55 -- 50 -- 45 40 45 35 35 30 30 10 10 10 10 10 10 10 NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD – 0.2V (High). 3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 4. Typical values are based on characterization data for H step only measured at 3.3V, 25°C and with equal read and write cycles. 6.42 3 Unit mA mA mA 3834 tbl 08 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges AC Test Conditions GND to 3.0V Input Pulse Levels Input Rise/Fall Times 1.5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V See Figure 1, 2 and 3 AC Test Load 3834 tbl 09 AC Test Loads 3.3V +1.5V 320Ω 50Ω I/O DATA OUT Z0 = 50Ω 5pF* 350Ω 30pF 3834 drw 03 3834 drw 04 *Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 7 • 6 ΔtAA, tACS (Typical, ns) 5 4 • 3 • 2 • 1 • • • 8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) Figure 3. Output Capacitive Derating 6.42 4 3834 drw 05 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) 71V016SA10(2) Symbol Parameter 71V016SA12 71V016SA15 71V016SA20 Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 10 ____ 12 ____ 15 ____ 20 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ____ 20 ns tACS Chip Select Access Time ____ 10 ____ 12 ____ 15 ____ 20 ns tCLZ(1) Chip Select Low to Output in Low-Z 4 ____ 4 ____ 5 ____ 5 ____ ns tCHZ(1) Chip Select High to Output in High-Z ____ 5 ____ 6 ____ 6 ____ 8 ns tOE Outp ut Enable Low to Output Valid ____ 5 ____ 6 ____ 7 ____ 8 ns tOLZ(1) Output Enable Low to Output in Low-Z 0 ____ 0 ____ 0 ____ 0 ____ ns tOHZ(1) Output Enable High to Output in High-Z ____ 5 ____ 6 ____ 6 ____ 8 ns tOH Output Hold from Address Change 4 — 4 — 4 — 4 — ns tBE Byte Enable Low to Output Valid — 5 — 6 — 7 ____ 8 ns tBLZ(1) Byte Enable Low to Output in Low-Z 0 ____ 0 ____ 0 ____ 0 ____ ns tBHZ(1) Byte Enable High to Output in High-Z ____ 5 ____ 6 ____ 6 ____ 8 ns WRITE CYCLE tWC Write Cycle Time 10 ____ 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End of Write 7 ____ 8 ____ 10 ____ 12 ____ ns tCW Chip Select Lo w to End of Write 7 ____ 8 ____ 10 ____ 12 ____ ns tBW Byte Enable Low to End of Write 7 ____ 8 ____ 10 ____ 12 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tWR Ad dress Hold from End of Write 0 ____ 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 7 ____ 8 ____ 10 ____ 12 ____ ns tDW Data Valid to End of Write 5 ____ 6 ____ 7 ____ 9 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ 0 ____ ns tOW(1) Write Enable High to Output in Low-Z 3 ____ 3 ____ 3 ____ 3 ____ ns tWHZ(1) Write Enable Low to Output in High-Z ____ 5 ____ 6 ____ 6 ____ 8 ns NOTES: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2. 0°C to +70°C temperature range only. 3834 tbl 10 Timing Waveform of Read Cycle No. 1(1,2,3) tRC ADDRESS tAA tOH tOH DATAOUT DATAOUT VALID PREVIOUS DATAOUT VALID NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW. 3834 drw 06 6.42 5 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2(1) tRC ADDRESS tAA tOH OE tOHZ tOE (3) tOLZ CS tCLZ (3) (3) tACS (2) tCHZ (3) BHE, BLE tBE tBLZ (2) tBHZ (3) (3) DATAOUT DATA OUT VALID 3834 drw 07 NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured ±200mV from steady state. Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tCW (2) tCHZ (5) tBW BHE , BLE tWR (5) tWP WE tAS (5) tWHZ tOW DATAOUT tBHZ PREVIOUS DATA VALID (3) (5) DATA VALID tDW DATAIN tDH DATAIN VALID 3834 drw 08 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6.42 6 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tCW (2) tAS tBW BHE, BLE tWP tWR WE DATAOUT tDW DATAIN tDH DATAIN VALID 3834 drw 09 Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4) tWC ADDRESS tAW CS tCW (2) tAS tBW BHE, BLE tWP tWR WE DATAOUT tDW DATAIN tDH DATAIN VALID 3834 drw 10 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6.42 7 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Ordering Information 71V016 Device Type SA XX Power Speed XXX Package X X Process/ Temperature Range X Blank 8 Tube or Tray Tape and Reel Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Restricted hazardous substance device Y PH BF 400-mil SOJ (SO44-1) 400-mil TSOP Type II (SO44-2) 7.0 x 7.0 mm FBGA (BF48-1) 10** 12 15 20 Speed in nanoseconds ** Commercial temperature range only. 3834 drw 11 6.42 8 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Datasheet Document History 1/7/00 08/30/00 08/22/01 06/20/02 01/30/04 09/27/06 02/14/07 06/26/07 10/13/08 10/11/11 Pp. 1, 3, 5, 8 Pg. 2 Pg. 6 Pg. 7 Pg. 9 Pg. 3 Pg. 5 Pg. 8 Pg. 8 Pg. 8 Pg. 8 Pg.8 Pg.3 Pg.8 Pg.1,8 Updated to new format Added Industrial Temperature range offerings Numbered I/Os and address pins on FBGA Top View Revised footnotes on Write Cycle No. 1 diagram Revised footnotes on Write Cycle No. 2 and No. 3 diagrams Added Datasheet Document History Tighten ICC and ISB. Tighten tCLZ, tCHZ, tOHZ, tBHZ and tWHZ Removed footnote "available in 15ns and 20ns only" Added tape and reel field to ordering information Added "Restricted hazardous substance device" to ordering information. Corrected ordering information, changed position of I and G. Added H step generation to data sheet ordering information. Changed typical parameters for ICC, DC electrical characteristics table. Removed "IDT" from orderable part number Updated datasheet with removal of Obsolete HSA part number. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 9 for Tech Support: [email protected] 800-345-7015