2016 D8259 IP Core Programmable Interrupt Controller v. 1.04 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. IP CORE OVERVIEW The D8259 is a soft Core of Programmable Interrupt Controller. It is fully compatible with the 82C59A device. The D8259 Core manages up to 8-vectored priority interrupts for the processor. Programming it to cascade allows up to 64 vectored interrupts. More than 64 vectored interrupts can be accomplished, by programming to Poll Command Mode. The D8259 can operate in all 82C59A modes and it supports all 82C59A features: ● ● ● ● ● ● ● ● ● ● ● ● MCS-80/85 and 8088/8086 processor modes Fully nested mode and special fully nested mode Special mask mode Buffered mode Pool command mode Cascade mode with master or slave selection Automatic end-of-interrupt mode Specific and non-specific end-of-interrupt commands Automatic and Specific Rotation Edge and level triggered interrupt input modes Reading of interrupt request register (IIR) and inservice register (ISR) through data bus. Writing and reading of interrupt mask register (IMR) through data bus ● Fully synthesizable, static design, with no internal tri-states DELIVERABLES ♦ ♦ ♦ ♦ ♦ ♦ Source code: ● VHDL Source Code or/and ● VERILOG Source Code or/and ● Encrypted, or plain text EDIF VHDL & VERILOG test bench environment ● Active-HDL automatic simulation macros ● ModelSim automatic simulation macros ● Tests with reference responses Technical documentation ● Installation notes ● HDL core specification ● Datasheet Synthesis scripts Example application Technical support ● IP Core implementation support ● 3 months maintenance ● ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license – dedicated to small and middle sized companies running business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: KEY FEATURES ● ● ● 8 vectored priority interrupts Up to sixty-four vectored priority interrupts with cascading Support for all 82C59A modes features ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ MCS-80/85 and 8088/8086 processor modes Fully nested mode and special fully nested mode Special mask mode Buffered mode Pool command mode Cascade mode with master or slave selection Automatic end-of-interrupt mode Specific and non-specific end-of-interrupt commands Automatic and Specific Rotation Edge and level triggered interrupt input modes Reading of interrupt request register (IIR) and inservice register (ISR) through data bus VHDL or Verilog RTL synthesizable source code FPGA EDIF/NGO/NGD/QXP/VQM (Netlist) SYMBOL rst datai(7:0) a0 cs rd wr ir(7:0) inta casi(2:0) sp datao(7:0) dbe int caso(2:0) case en 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. BLOCK DIAGRAM rst a0 wr rd cs inta Control logic Read/Write Logic datai(7:0) datao(7:0) dbe Data Bus Buffer casi(2:0) caso(2:0) case sp en Cascade Controller Interrupt Mask Register int Priority Resolver – PR block resolve, which interrupt request has the highest priority, and will be served as first. In Service Register– ISR register stores information about interrupts that are being serviced. PINS DESCRIPTION Interrupt Request Register ir7 ir6 ir5 ir4 ir3 ir2 ir1 ir0 Priority Resolver In Service Register PIN rst datai(7:0) a0 cs rd wr ir(7:0) inta casi(2:0) sp datao(7:0) dbe int caso(2:0) case en DESCRIPTION Power-up reset Data bus (input) Processor address line Chip select Read strobe Write strobe Interrupt request lines Interrupt acknowledge Cascade input lines Slave program input Data bus (output) Data bus output enable Interrupt request output Cascade output lines Cascade output enable Buffer transceiver enable PERFORMANCE UNITS SUMMARY Read Write Logic - The Read/Write Logic accepts inputs from the system bus and generates control signals, for other functional blocks of the D8259. A “low'' on the RD input tells the D8259, that the CPU is reading contents of IRR and ISR registers. A “low'' on the WR input, tells the D8254, that the CPU is writing a Command Words to D8259. Both, RD and WR, are qualified by CS; RD and WR are ignored, unless the D8259 has been selected by holding CS low. Data Bus Buffer 8-bit buffer is used to interface the D8259 to the system bus. Cascade Controller - The Cascade Controller stores and compares Identifiers of all 8259 devices in the system. Block manages direction of CAS input/output buses, depending on device status: Master or Slave. When operating as a master, the D8259 drives onto the CAS bus address of interrupting 8259 device, then the addressed 8259 slave, during the next one or two consecutive INTA pulses send to the Data Bus preprogrammed address of subroutine. Interrupt Mask Register – IMR register stores the information, which interrupt request to be masked. Control Logic – CL block checks for INTA pulses, which cause the D8259 to release vectoring information onto the Data Bus. Format of drive data, depends on mode of operation. CL also manages the state of INT output. Interrupt Request Register – IIR register stores information about states of all IR lines. It saves information about all interrupt requests to be serviced. TYPE input input input input input input input input input input output output output output output output The following table gives a survey about the Core area and performance in XILINX ® devices after Place & Route: Device ARTIX 7 KINTEX 7 ZYNQ SPARTAN 6 SPARTAN 3 VIRTEX 7 VIRTEX 6 VIRTEX 5 VIRTEX 4 Slices 128/267 128/288 128/288 132/283 134/283 128/288 130/260 130/272 130/252 Core performance in XILINX® devices Fmax 320 MHz 340 MHz 218 MHz 140 MHz 104 MHz 340 MHz 231 MHz 247 MHz 203 MHz CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.