2016 DSPI IP Core Serial Peripheral Interface – Master/Slave v. 2.09 KEY FEATURES COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. ● SPI Master ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ● SPI Slave ○ ○ ○ ○ ○ IP CORE OVERVIEW The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of a serial clock signal (SCK). It allows the microcontroller to communicate with serial peripheral devices and is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines. DSPI data is simultaneously transmitted and received. What's most important, it's a technology independent design, which can be implemented in a variety of process technologies. The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. It can be configured as a master or a slave device, with data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of eight different bit rates for the serial clock. The DSPI automatically drives selected by SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and address SPI slave device, to exchange serially shifted data. Error-detection logic is included, to support interprocessor communications. A write collision detector indicates when an attempt is made to write data to the serial shift register, while transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI devices simultaneously attempts to become a bus master. The DSPI is fully customizable and can be tailored to your configuration and requirements. It includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. Master and Multi-master operations 8 SPI slave select lines System error detection Mode fault error Write collision error Interrupt generation Supports speeds up ¼ of system clock Bit rates generated 1/4 - 1/512 of system clock. Four transfer formats supported Simple interface allows easy connection to microcontrollers Slave operation System error detection Interrupt generation Supports speeds up ¼ of system clock Simple interface allows easy connection to microcontrollers Four transfer formats supported ○ ● Fully synthesizable, static synchronous design, with no internal tri-states BLOCK DIAGRAM MSB mo so 8-Bit Shift Register LSB mi si Read Data Buffer clk rst SPI Clock Logic Divider 4 - 512 addr cs we rd SPR scko scki CPHA CPOL SPI Control Reg. datao SPI Status Reg. datai SPI Controller SS Control Reg. scken soen ss en ss7o ss6o ss5o ss4o ss3o ss2o ss1o ss0o DELIVERABLES ♦ Source code: ● ● ● ♦ VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test bench environment ● ● ● ♦ Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation ● ● ● ♦ ♦ ♦ Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support ● ● IP Core implementation support 3 months maintenance ● ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. TRANSFER FORMATS The software can select any of four combinations of serial clock (SCK) phase and polarity, using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit, selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow a master device to communicate with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral. SCK CYCLE# 1 2 MSB 6 6 3 4 5 6 7 8 5 4 3 2 1 LSB 5 4 3 2 1 4 5 6 7 8 LSB SCK (CPOL=0) SCK (CPOL=1) MOSI MISO MSB LSB SS SCK CYCLE# 1 3 2 SCK (CPOL=0) SCK (CPOL=1) MSB MOSI MISO MSB 6 5 4 3 2 1 6 5 4 3 2 1 LSB SS TYPICAL uC / BUS CONNECTION The figure below shows a typical connection the DSPI Core with microcontroller and other SPI Master/Slave devices. VDD RP RP RP MISO MOSI SCK RS NOR data RS RS 8 addr cs rd wr irq RS RS Slave Device tri-state buffer 2 uC RS datao mi datai addr so cs rd we irq miso Tris mosi soen si DSPI sck mo Tris scken ss scki system clk clk scko system rst rst scken tris DSPI ASIC/FPGA chip ss7o-ss0o ss 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code FPGA EDIF/NGO/NGD/QXP/VQM (Netlist) UNITS SUMMARY Shift register and Read Data Buffer – Central element in the SPI system. The system is single buffered in the transmit direction and double buffered in the receive direction. This fact means that the new data for transmission cannot be written to the shifter, until the previous transaction is complete; however, received data is transferred into a parallel read data buffer, so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition will occur. When an SPI transfer occurs, an 8-bit character is shifted out on data pin, while a different 8-bit character is simultaneously shifted in a second data pin. Another way to view this transfer is that an 8-bit shift register in the master and another 8-bit shift register in the slave is connected as a circular 16-bit shift register. When the transfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in the master and slave are effectively exchanged. Control Register may be read or written at any time, it is used to configure the DSPI System. This register controls the mode of transmission (Master, Slave), polarity and phase of SPI Clock and transmission speed. Status Register (SPSR) contains flags, indicating the completion of transfer or occurrence of system errors. All flags are set automatically when the corresponding event occur and cleared by software sequence. Slave Select Control Register configures which slave select output should be driven while SPI master transfer. Contents of SSCR register is automatically assigned on SS7O-SS0O pins when DSPI master transmission starts. SPI Clock Logic - Software can select any from four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow master device communication with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral. PINS DESCRIPTION PIN clk rst datai(7:0) addr(1:0) cs rd we scki mi si ss datao(7:0) irq scko scken mo so soen ss7o-ss0o TYPE input input input input input input input input input input input output output output output output output output output DESCRIPTION Global clock Global reset Data bus input Processor address lines Chip select Processor read strobe Processor write strobe SPI clock input Master serial data input Slave serial data input Slave select Data bus output Interrupt request SPI clock output SPI clock output enable Master serial data output Slave serial data output Slave data output enable Slave select outputs PERFORMANCE The following table gives a survey about the Core area and performance in XILINX® devices, after Place & Route: Device LUTs/Slices ZYNQ 7000 241 ZYNQ 243/134 KINTEX Ultra Scale 232 KINTEX 7 243/107 ARTIX 7 273/118 VIRTEX Ultra Scale 232 VIRTEX7 247/115 VIRTEX 6 199/95 VIRTEX 5 208/105 VIRTEX 4 280/188 SPARTAN 6 282/106 SPARTAN 3E 337/220 SPARTAN 3 338/217 Core performance in XILINX® devices Fmax MHz 330 297 330 457 275 330 369 243 255 172 186 138 137 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales 4 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.