XILINX Datasheet

2016
D85C30 IP Core
UART Core with SDLC Function v. 1.04
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
IP CORE OVERVIEW
The D85C30 - (Serial Communication Controller) is
a dual channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) device
designed for use with 8 and 16-bit microprocessors. It functions as a serial-to-parallel, parallel-toserial converter/controller and can be softwareconfigured to satisfy a wide variety of serial communications applications. The device contains a
variety of new, sophisticated internal functions
including on-chip baud rate generators. The
D85C30 handles asynchronous formats, synchronous byte-oriented protocols such as IBM® Bisync,
and synchronous bit-oriented protocols such as
HDLC and IBM SDLC. This versatile device supports
virtually any serial data transfer application (telecommunication, LAN, etc.). The device can generate and check CRC codes in any synchronous mode
and can be programmed to check data integrity in
various modes. The D85C30 also has facilities for
modem control in both channels. In applications
where these controls are not needed, the modem
controls can be used for general-purpose I/O. The
user can configure the D85C30 to handle all synchronous formats regardless of data size, number
of stop bits, or parity requirements. D85C30 control is done through access to 14 Write registers
and 7 Read registers per channel (the number of
the registers varies depending on the version).
Within each operating mode, the D85C30 also
allows for protocol variations by checking odd or
even parity bits, character insertion or deletion,
CRC generation, checking break and abort generation and detection, and many other protocoldependent features.
KEY FEATURES
♦
♦
♦
♦
Software compatible with Z85C30
Dual Channel: A, B
Configuration capability
Asynchronous mode:
◊
◊
♦
Character-Oriented mode:
◊
◊
◊
♦
NRZ, NRZI
FM0, FM1
Manchester (require external logic)
Line break generation and detection.
Internal diagnostic capabilities:
◊
◊
◊
♦
SDLC/HDLC
SDLC/HDLC Loop
Complete status reporting capabilities
Receiver data FIFO and Error FIFO
SDLC Frame FIFO
Data encoder\decoder:
◊
◊
◊
♦
♦
Monosynchronous
Bisynchronous
External Synchronous
Bit-Oriented mode:
◊
◊
♦
♦
♦
♦
Asynchronous (x16, x32, or x64 clock
Isochronous (x1 clock)
Loop-back controls for communications link fault isolation
Auto Echo
Break, parity, overrun, framing error simulation
Fully synchronous design with no internal tri-state
buffers
Transmission modes:
♦
Synchronous Byte (Bisync) features
◊
◊
◊
◊
◊
◊
♦
Asynchronous Features
◊
◊
◊
◊
◊
♦
◊
1-8 Bits character (transmitter)
5-8 Bits receiver character
Hardware address recognition
Automatic zero insertion and deletion
I-Field residue handling
Automatic flag insertion between messages
Hardware CRC generation and reception
Interrupt system features
◊
◊
◊
♦
CTS, DSR, DCD and RI lines, usable for modem control
or user defined input
DTR and RTS usable for modem control or user defined output
Synchronous SDLC features
◊
◊
◊
◊
◊
◊
◊
♦
5-8 Bits per character
1, 1,5 and 2 stop bits
Break generation and detection
Parity, overrun and framing error detection
Even, Odd or no parity
Modem controls and indicators
◊
♦
5 to 8 Bit characters
Programmable Sync character
Transparent text mode operation
Automatic Sync insertion during Idle
Hardware CRC generation and detection
CRC-16 or CRC-CCITT polynomials
Channel functions and timers internally prioritized
Channel functions and timers generate unique interrupt mode
Prioritized Daisy-chain.
LOOPBACK test mode
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
DELIVERABLES
♦
Source code:
●
●
●
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF Netlist
♦
VHDL & VERILOG test bench environment
● Active-HDL automatic simulation macros
● ModelSim automatic simulation macros
♦
Technical documentation
●
Tests with reference responses
●
●
●
♦
♦
♦
SYMBOL
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
●
●
IP Core implementation support
3 months maintenance
●
Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
●
PINS DESCRIPTION
PIN
rst
clk
PCLK
TYPE
input
input
input
PCLKEN
input
datai[7:0]
datao[7:0]
dataen
addr[3:0]
input
output
output
input
directaddr
input
wr
rd
cs
ab
dc
intack
int
iei
ieo
rxd (a,b)
txd (a, b)
trxci (a,b)
trxco (a,b) *
trxcen (a,b)
rtxc (a, b) *
synci (a, b)
synco (a, b)
syncen (a, b)
wreq (a, b)
dtrreq (a, b)
rts (a, b)
cts (a, b)
dcd (a, b)
input
input
input
input
input
input
output
input
output
input
output
input
output
output
input
input
output
output
output
output
output
input
input
DESCRIPTION
Global reset
Global clock
Baud generator clock
Baud generator clock enable - 1 enable
the PCLK
Parallel data input
Parallel data output
Parallel data output enable
Address bus (optional)
Configuration pin, when high enable the
address bus
Write input
Read input
Chip select input
Channel A/Channel B input
Data/Command
Interrupt acknowledge
Interrupt request
Interrupt enable input
Interrupt enable output
Serial data input
Serial data output
TRXC Clock input
TRXC Clock output
TRXC Clock output enable
RTXC Clock input
SYNC Pin input
SYNC Pin output
SYNC Buffer output enable
WAIT Request
Data Terminal Rready Request
Request To Send pin
Clear to send input
Data carrier detect input
rst
clk
pclk
pclken
datai(7:0)
address(3:0)*
directaddr*
wr
rd
cs
ab
dc
D85C30
rxd
cts
dcd
dtr
rts
Channels
Pins
Same set for
A and B
waireq
datao(7:0)
dataen
int
intack
ieo
iei
txd
trxci
trxco
trxcen
synci
synco
syncen
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
DCD’S UART FAMILY OVERVIEW
-
-
-
-
-
-
Half-Duplex RS485
Internal diagnostic
Complete status report
False START detection
MODEM Control
RTS/CTS Flow Control
-
-
-
*
1284 Parallel Port
-
IRDA Port
-
Break gen. and detect
2*8
2* 16
2* 64
2* 16
2* 64
2* 128
4
Soft Flow Control –
Xon/Xoff
-
Prioritized interrupts
DUART
D2692
D16450
D16550
D16750
D16552
D16752
D16950
D85C30
Separate BAUD Clock l
Synchronous Transmission
-
Design
FIFO Size (Bytes)
SDLC
The family of DCD’s UART IP Cores combines high performance, low cost and a small compact size, offering best
price/performance ratio in the IP Market. DCD’s Cores are designed to be used in cost-sensitive consumer
products, such as computer peripherals, office automation, automotive control systems, security and telecommunication applications. Our Cores are written in pure VHDL/VERILOG HDL languages, which makes them
technologically independent. All DCD’s UART IP Cores can be fully customized according to the customer’s
needs.
-*
-*
*
-*
-*
*
*
*
*
-
-
*
-
-
*-Optional
BLOCK DIAGRAM
addr
directaddr
datai
datao
dataen
rd
wr
cs
ab
dc
wreq
rtsa/b
ctsa/b
dtra/b
dcda/b
syncia/b
syncoa/b
syncena/b
clk
rst
pclk
pclken
Data Bus
Buffer
Receiver
Control
&
Shift Register
PERFORMANCE
rxda/b
rtxca/b
RCVR Buffer
&
RCVR FIFO
Modem
Control
Logic
Transmitter
Control
&
Shift Register
txda/b
trxcia/b
trxcoa/b
trxcena/b
TX Buffer
Baud
Generator
Interrupt
Controller
intr
intack
iei
ieo
The following table gives a survey about the Core
area and performance in XILINX® devices after
Place & Route:
Mem.
Blocks
Artix 7
1785/797
2
Kintex Ultra Scale
1754
2
Kintex 7
1877/676
2
Zynq 7000
1816
2
Zynq
1868/774
2
Virtex Ultra Scale
1752
2
Virtex 7
1869/878
2
Virtex 6
1801/850
2
Virtex 5
1861/846
2
Virtex 4
2533/1598
2
Spartan 6
1815/681
2
Spartan 3E
2647/1655
2
Spartan 3
2625/1645
2
Core performance in XILINX® devices
Device
LUTs /Slices
Fmax
MHz
165
330
239
330
171
330
194
144
161
121
122
75
72
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.