2016 DµART IP Core Tiny UART v. 1.02 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. ● Line break generation and detection. Internal diagnostic capabilities: ○ ○ ● Full prioritized interrupt system controls ● Technology independent HDL Source Code ● Fully synthesizable static design with no internal tristate buffers DELIVERABLES ♦ ● Majority Voting Logic ● Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data ● In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data ● Independently controlled transmit, receive, line status, and data set interrupts ● 16 bit programmable baud generator ● False start bit detection VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test bench environment ● ● ● IP CORE OVERVIEW KEY FEATURES Source code: ● ● ● ♦ The DµART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (overrun, framing). The DµART includes a programmable baud rate generator that is capable of dividing the timing reference 16 clock input by divisors of 1 to (2 -1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The DµART has processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link. The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Loop-back controls for communications link fault isolation Overrun, framing error detection ♦ Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation ● ● ● ♦ ♦ ♦ Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support ● ● IP Core implementation support 3 months maintenance ● ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code called HDL Source code FPGA EDIF/NGO/NGD/QXP/VQM called Netlist 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. DCD’S UART FAMILY OVERVIEW - - - Half-Duplex RS485 Internal diagnostic Complete status report - - - * 1284 Parallel Port - - False START detection MODEM Control RTS/CTS Flow Control - IRDA Port - - Break gen. and detect 2*8 2* 16 2* 64 2* 16 2* 64 2* 128 4 Soft Flow Control – Xon/Xoff - Prioritized interrupts DUART D2692 D16450 D16550 D16750 D16552 D16752 D16950 D85C30 Separate BAUD Clock l Synchronous Transmission - Design FIFO Size (Bytes) SDLC The family of DCD’s UART IP Cores combines high performance, low cost and a small compact size, offering best price/performance ratio in the IP Market. DCD’s Cores are designed to be used in cost-sensitive consumer products, such as computer peripherals, office automation, automotive control systems, security and telecommunication applications. Our Cores are written in pure VHDL/VERILOG HDL languages, which makes them technologically independent. All DCD’s UART IP Cores can be fully customized according to customer’s needs. -* -* * -* -* * * * * - - * - - *-Optional TYPICAL APPLICATION addr CPU ale addr latch datao(7:0) datai(7:0) we rd cs int addr(2:0) DUART datai(7:0) datao(7:0) wr rd cs intr txd rxd BLOCK DIAGRAM addr(2:0) datai(7:0) datao(7:0) EIA rd Drivers wr cs Data Bus Buffer clk rst temt PINS DESCRIPTION PIN rst clk datai[7:0] addr[2:0] wr rd cs rxd intr temt datao[7:0] txd TYPE input input input input input input input input output output output output ACTIVE high rising low low low high high - DESCRIPTION Global reset Global clock Parallel data input Address bus Write input Read input Chip select input Serial data input Interrupt request output Transmitter empty Parallel data output Serial data output clk rst Receiver Control & Shift Register rxd Transmitter Control & Shift Register txd temt Interrupt Controller intr 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. UNITS SUMMARY PERFORMANCE RST - Global Reset. When this input is high, it clears all the registers (except the Receiver Buffer, Transmitter Holding, and Divisor Latches), and the control logic of the UART. The states of various output signals (SO, INTR, OUT 1, OUT 2, RTS, DTR) are affected by an active RST input. The following table gives a survey about the Core area and performance in ALTERA® devices, after Place & Route: DATAI(7:0), DATAO(7:0) - Data Busses, the bus provides communications between the UART and CPU. Data, control words, and status information are transferred via the Data Bus. ADDR(2:0), Address Bus - selects a UART register for the CPU to read from or write to during data transfer. A table of registers and their addresses is shown in figure below. Note that the state of the Divisor Latch Access Bit (DLAB), which is the most significant bit of the Line Control Register, affects the selection of certain UART registers. The DLAB must be set high by the system software to access the Baud Generator Divisor Latches. RD - Read. When RD is low and chip is selected, the CPU can read status information or data from the selected UART register. WR – Write, When WR is low while the chip is selected, the CPU can write control words or data into the selected UART register. CS - Chip Select, When CS is low, the chip is selected. This enables communication between the UART and CPU. RXD - Serial Input. Serial data input from the communications link (peripheral device, MODEM, or data set). Speed Logic MEMORY grade Cells Bits ARIA GX -6 143/130 ARIA V -6 100/141 CYCLONE -6 218 CYCLONE2 -6 218 CYCLONE3 -6 227 CYCLONE4 -6 223 CYCLONE5 -6 102/141 STRATIX -5 218 STRATIX2 -3 144/131 STRATIX3 -2 146/130 STRATIX4 -2 146/130 STRATIX5 -2 95/148 STRATIX GX -5 218 STRATIX2 GX -3 218 MAX II -4 218 Core performance in ALTERA® devices Device Fmax 267 MHz 315 MHz 226 MHz 297 MHz 335 MHz 317 MHz 265 MHz 244 MHz 404 MHz 542 MHz 605 MHz 637 MHz 242 MHz 176 MHz 91 MHz CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales INTR - Interrupt pin goes high whenever any one of the following interrupt types has an active high condition and is enabled via the IER: Receiver Error Flag; Received Data Available: timeout (FIFO Mode only); Transmitter Holding Register Empty; and MODEM Status. The INTR signal is reset low upon the appropriate interrupt service or a Master Reset operation. TEMT – Transmitter Empty. This pin can be used in RS485 systems to control three state output buffer. When in low state, the output buffer should be enabled, to allow transmission from DUART. High state on TEMT informs that transmitter in IDLE state, or reception is in progress (in Half Duplex mode, transmission is disabled as long as the reception is in progress). TXD - Serial Output. Composite serial data output to the communications link (peripheral, MODEM or data set). The TXD signal is set to the logic 1 state upon a Master Reset operation. 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.