IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS IDT74ALVC162836 FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in SSOP and TSSOP packages This 20-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVC162836 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. DRIVE FEATURES: APPLICATIONS: • Light Balanced Output Drivers: ±12mA • Minimal switching noise • SDRAM Modules • PC Motherboards • Workstations FUNCTIONAL BLOCK DIAGRAM OE CLK LE A1 1 56 29 55 1D C1 2 Y1 CLK TO 19 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 © 2004 Integrated Device Technology, Inc. DSC-4900/5 IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION OE 1 56 CLK Y1 2 55 A1 Y2 3 54 A2 GND 4 53 GND Y3 5 52 Y4 6 51 VCC 7 50 VCC Y5 8 49 A5 Y6 9 48 A6 Y7 10 47 A7 GND 11 46 GND Y8 12 45 A8 Y9 13 44 A9 Description VTERM(2) Max Unit Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C –50 to +50 mA ±50 mA IOUT DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC A3 IOK Continuous Clamp Current, VO < 0 –50 mA A4 ICC ISS Continuous Current through each VCC or GND ±100 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. Y10 14 43 A10 Y11 15 42 A11 Y12 16 41 A12 Symbol Y13 17 40 A13 CIN Input Capacitance VIN = 0V 3.3 5 6 pF GND 18 39 GND COUT Output Capacitance VOUT = 0V — 7 9 pF Y14 19 38 A14 CI/O I/O Port Capacitance VIN = 0V — 7 9 pF Y15 20 37 A15 Y16 21 36 A16 VCC 22 35 VCC Y17 23 34 A17 Y18 24 33 A18 GND 25 32 GND Y19 26 31 A19 OE LE Y20 27 30 A20 H NC 28 29 LE L CAPACITANCE (TA = +25°C, F = 1.0MHz) Pin Names Data Inputs Yx 3-State Outputs NC No Internal Connection Outputs CLK Ax Yx X X X Z L X L L L L X H H L H ↑ L L L H ↑ H H L H H X Y0 L H L X Y0 (2) (2) NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance ↑ = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. Register Input Clock Ax Min Typ. Max. Unit Inputs 3-State Output Enable Inputs (Active LOW) Latch Enable (Active LOW) Conditions FUNCTION TABLE(1) Description LE Parameter(1) NOTE: 1. As applicable to the device type. PIN DESCRIPTION OE Symbol IIK SSOP/ TSSOP TOP VIEW CLK INDUSTRIAL TEMPERATURE RANGE 2 IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Unit V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — VCC = 3V Output LOW Voltage Max. VCC = 2.3V to 3.6V VCC = 2.7V VOL Min. VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = – 4mA 2.2 — IOH = – 8mA 2 — IOH = – 6mA 2.4 — IOH = – 12mA 2 — IOL = 0.1mA — 0.2 IOL = 4mA — 0.4 IOL = 6mA — 0.55 IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 31 36 pF 7 11 SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter fMAX VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit 150 — 150 — 150 — MHz 1 4.4 — 4.6 1.2 4 ns 1.1 5.8 — 6.1 1.4 5.1 ns 1 5.2 — 5.5 1.9 4.5 ns 1.1 6.4 — 6.5 1.2 5.5 ns 1 4.7 — 5.2 1.7 5.1 ns tPLH Propagation Delay tPHL Ax to Yx tPLH Propagation Delay tPHL LE to Yx tPLH Propagation Delay tPHL CLK to Yx tPZH Output Enable Time tPZL OE to Yx tPHZ Output Disable Time tPLZ OE to Yx tW Pulse Duration, LE LOW 3.3 — 3.3 — 3.3 — ns tW Pulse Duration, CLK HIGH or LOW 3.3 — 3.3 — 3.3 — ns tSU Set-up Time, data before CLK↑ 1.4 — 1.7 — 1.5 — ns tSU Set-up Time, data before LE↑, CLK HIGH 1.2 — 1.6 — 1.3 — ns tSU Set-up Time, data before LE↑, CLK LOW 1.4 — 1.5 — 1.2 — ns tH Hold Time, data after CLK↑ 0.7 — 0.7 — 0.7 — ns tH Hold Time, data after LE↑, CLK HIGH or LOW 1.1 — 1.1 — 1.1 — ns Output Skew(2) — — — — — 500 ps tSK(O) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. SWITCHING CHARACTERISTICS FROM 0°C TO 65°C, CL = 5pF VCC = 3.3V ± 0.15V Symbol tPLH tPHL Parameter Propagation Delay CLK to xYx 4 Min. Max. Unit 1.9 4.5 ns IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF tPLH tPHL tPLH tPHL OUTPUT VIH VT 0V OPPOSITE PHASE INPUT TRANSITION ALVC Link Propagation Delay VLOAD VCC Open 500Ω (1, 2) VIN CONTROL INPUT VOUT Pulse Generator DISABLE ENABLE GND D.U.T. tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω RT CL ALVC Link Test Circuit for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Switch Open Drain Disable Low Enable Low TIMING INPUT VLOAD ASYNCHRONOUS CONTROL Open tPHZ VOH VOH - VHZ 0V VT 0V NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION All Other Tests VLOAD/2 VOL + VLZ VOL ALVC Link DATA INPUT GND VLOAD/2 VT Enable and Disable Times NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. Disable High Enable High tPLZ VIH VT 0V SYNCHRONOUS CONTROL tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V tH tREM tSU tH ALVC Link INPUT OUTPUT 1 VIH VT 0V tPHL1 tPLH1 tSK (x) tSK (x) OUTPUT 2 tPLH2 Set-up, Hold, and Release Times VOH VT VOL LOW-HIGH-LOW PULSE VOH VT VOL HIGH-LOW-HIGH PULSE tW VT ALVC Link Pulse Width tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) VT ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT ALVC X XX Bus-Hold Temp. Range XXX Family XXX XX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA Shrink Small Outline Package Thin Shrink Small Outline Package 836 20-Bit Universal Bus Driver with 3-State Outputs 162 Double-Density with Resistors, ±12mA Blank No Bus-Hold 74 –40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459