IDT74LVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O IDT74LVC16244A DESCRIPTION: FEATURES: The LVC16244A 16-bit buffer/driver is built using advanced dual metal CMOS technology. The LVC16244A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides true outputs and symmetrical active-low output-enable (OE) inputs. All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V devices. This feature allows the use of the device as a translator in a mixed 3.3V/5V supply system. The LVC16244A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP, TSSOP, and TVSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1OE 1 1A1 47 2 1A2 46 3 1A3 44 5 43 6 1A4 3OE 25 1Y1 3A1 36 13 3Y1 1Y2 3A2 35 14 3Y2 1Y3 3A3 33 16 1Y4 3A4 32 17 4OE 24 30 19 29 20 2OE 48 2A1 41 8 2Y1 4A1 2A2 40 9 2Y2 4A2 2A3 38 11 2Y3 4A3 27 22 2A4 37 12 2Y4 4A4 26 23 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE MARCH 2003 1 © 2003 Integrated Device Technology, Inc. DSC-4726/3 IDT74LVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION 1OE 1 48 2OE Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +6.5 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C 1Y1 2 47 1A1 IOUT DC Output Current –50 to +50 mA 1Y2 3 46 1A2 mA 4 45 Continuous Clamp Current, VI < 0 or VO < 0 –50 GND IIK IOK GND 1A3 Continuous Current through each VCC or GND mA 44 ICC ISS ±100 1Y3 5 1Y4 6 43 1A4 VCC 7 42 VCC 2Y1 8 41 2A1 2Y2 9 40 GND 10 39 GND 2Y3 11 38 2A3 2Y4 12 37 2A4 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. 2A2 CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 3Y1 13 36 3A1 3Y2 14 35 3A2 GND 15 34 NOTE: 1. As applicable to the device type. 3Y3 16 33 GND 3A3 3Y4 17 32 3A4 VCC 18 31 PIN DESCRIPTION VCC Pin Names 4Y1 19 30 4A1 xAx Data Inputs xYx 3-State Outputs xOE 3-State Output Enable Inputs (Active LOW) 4Y2 20 29 4A2 GND 21 28 GND 4Y3 22 27 4A3 4Y4 23 26 4A4 4OE 24 25 3OE Description FUNCTION TABLE (EACH 4-BIT BUFFER)(1) Inputs xOE SSOP/ TSSOP/ TVSOP TOP VIEW xAx xYx L L L L H H H X Z NOTES: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance 2 Outputs IDT74LVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV µA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 µA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 6mA 2 — IOH = – 12mA 1.7 — 2.2 — VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74LVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Buffer/Driver Outputs enabled CPD Power Dissipation Capacitance per Buffer/Driver Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 34 pF 3 SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol VCC = 3.3V ± 0.3V Parameter Min. Max. Min. Max. Unit tPLH Propagation Delay — 4.7 1.1 4.1 ns tPHL xAx to xYx tPZH Output Enable Time — 5.8 1 4.6 ns tPZL xOE to xYx tPHZ Output Disable Time — 6.2 1.8 5.8 ns tPLZ xOE to xYx tSK(o) Output Skew(2) — — — 1 ns NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF Pulse (1, 2) Generator VIN DISABLE tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Switch VLOAD TIMING INPUT Disable High Enable High GND ASYNCHRONOUS CONTROL All Other Tests Open SYNCHRONOUS CONTROL tSK (x) tPLH2 VOH VT VOL tH tREM tSU tH LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT LVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V Set-up, Hold, and Release Times VOH VT VOL OUTPUT 2 VOH VOH-VHZ 0V VT 0V LVC Link VIH VT 0V tSK (x) tPHZ Enable and Disable Times DATA INPUT tPHL1 VLOAD/2 VOL+VLZ VOL NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Open Drain Disable Low Enable Low tPLZ VLOAD/2 VT LVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test VIH VT 0V CONTROL INPUT Test Circuit for All Outputs OUTPUT 1 VIH VT 0V ENABLE GND VOUT tPLH1 tPHL Propagation Delay LVC Link INPUT tPLH LVC Link D.U.T. RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X LVC IDT XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package PV PA PAG PF Shrink Small Outline Package Thin Shrink Small Outline Package TSSOP - Green Thin Very Small Outline Package 244A 16-Bit Buffer/Driver with 3-State Outputs 16 Double-Density, ±24mA Blank No Bus-hold 74 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459