Datasheet
Serial EEPROM Series Standard EEPROM
WLCSP EEPROM
BRCA016GWZ-W (16Kbit)
General Description
BRCA016GWZ-W series is a serial EEPROM of I2C BUS Interface Method.
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
Completely conforming to the world standard I2C BUS. All controls available by 2 ports of serial clock (SCL)
and serial data (SDA)
Other devices than EEPROM can be connected to the same port, saving microcontroller port.
1.7V to 3.6V Single Power Source Operation most suitable for battery use.
Possible FAST MODE 400KHz operation
Page Write Mode useful for initial value write at factory shipment.
Self-timed Programming Cycle
Low Current Consumption
¾ At Write Operation (5V)
: 0.5mA (Typ)
¾ At Read Operation (5V)
: 0.2mA (Typ)
¾ At Standby Operation (5V)
: 0.1μA (Typ)
Prevention of Write Mistake
¾ Write (write protect) function added
¾ Prevention of write mistake at low voltage
UCSP30L1 Compact Package
¾ W(Typ) x D(Typ) x H(Max)
:1.30mm x 0.77mm x 0.35mm
More than 1 million write cycles
More than 40 years data retention
Noise Filter Built in SCL / SDA terminal
Initial Delivery State FFh
BRCA016GWZ-W
Capacity
Bit Format
Type
Power Source Voltage
Package
16Kbit
2K×8
BRCA016GWZ-W
1.7V to 3.6V
UCSP30L1
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Limit
Unit
Supply Voltage
VCC
-0.3 to +6.5
V
Permissible Dissipation
Pd
220
mW
Storage Temperature
Tstg
-65 to +125
°C
Operating Temperature
Topr
-40 to +85
°C
-
-0.3 to Vcc+1.0
V
Input Voltage/
Output Voltage
Remark
Derate by 2.2mW/°C when operating above Ta=25°C
Memory Cell Characteristics (Ta=25°C, Vcc=1.7V to 3.6V)
Parameter
Write Cycles (1)
Data Retention (1)
Limit
Unit
Min
Typ
Max
100,000
-
-
Times
40
-
-
Years
(1) Not 100% TESTED
○Product structure：Silicon monolithic integrated circuit
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○This product has no designed protection against radioactive rays
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Datasheet
BRCA016GWZ-W (16Kbit)
Recommended Operating Ratings
Parameter
Symbol
Limit
Unit
Power Source Voltage
Vcc
1.7 to 3.6
Input Voltage
VIN
0 to Vcc
V
DC Characteristics
(Unless otherwise specified, Ta=-40°C to +85°C, Vcc=1.7V to 3.6V)
Limit
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Input High Voltage1
VIH1
0.7Vcc
-
Vcc+1.0
V
Input Low Voltage1
VIL1
-0.3
-
+0.3Vcc
V
Output Low Voltage1
VOL1
-
-
0.4
V
IOL=3.0mA , 2.5V≦Vcc≦3.6V (SDA)
Output Low Voltage2
VOL2
-
-
0.2
V
IOL=0.7mA , 1.7V≦Vcc≦2.5V (SDA)
Input Leakage Current
ILI
-1
-
+1
μA
VIN=0 to Vcc
Output Leakage Current
ILO
-1
-
+1
μA
VOUT=0 to Vcc (SDA)
Supply Current (Write)
ICC1
-
-
2.0
mA
Supply Current (Read)
ICC2
-
-
0.5
mA
Standby Current
ISB
-
-
2.0
μA
Vcc=3.6V , fSCL =400kHz, tWR=5ms
Byte Write, Page Write
Vcc=3.6V , fSCL =400kHz
Random Read, Current Read,
Sequential Read
Vcc=3.6V , SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
AC Characteristics
(Unless otherwise specified, Ta=-40°C to +85°C, Vcc=1.7V to 3.6V)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Clock Frequency
fSCL
-
-
400
kHz
Data Clock High Period
tHIGH
0.6
-
-
μs
Data Clock Low Period
tLOW
1.2
-
-
μs
SDA, SCL Rise Time (1)
tR
-
-
0.3
μs
(1)
tF
-
-
0.3
μs
Start Condition Hold Time
tHD:STA
0.6
-
-
μs
Start Condition Setup Time
tSU:STA
0.6
-
-
μs
Input Data Hold Time
tHD:DAT
0
-
-
ns
Input Data Setup Time
tSU:DAT
100
-
-
ns
tPD
0.1
-
0.9
μs
SDA, SCL Fall Time
Output Data Delay Time
tDH
0.1
-
-
μs
tSU:STO
0.6
-
-
μs
Bus Free Time
tBUF
1.2
-
-
μs
Write Cycle Time
tWR
-
-
5
ms
tI
-
-
0.1
μs
WP Hold Time
tHD:WP
1.0
-
-
μs
WP Setup Time
tSU:WP
0.1
-
-
μs
WP High Period
tHIGH:WP
1.0
-
-
μs
Output Data Hold Time
Stop Condition Setup Time
Noise Spike Width(SDA,SCL terminal)
(1) Not 100% TESTED
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Datasheet
BRCA016GWZ-W (16Kbit)
Serial Input / Output Timing
tR
tF
tHIGH
SCL
SCL
tSU:DAT
tHD:STA
tLOW
DATA(1)
tHD:DAT
SDA
SDA
D1
D0
DATA(n)
ACK
ACK
(Input)
(入力)
tPD
tBUF
ｔWR
tDH
Stop
condition
ストップコンディション
WP
SDA
(Output)
(出力)
ｔHD：WP
tSU：WP
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Figure 1-(a). Serial Input / Output Timing
Figure 1-(d). WP Timing at Write Execution
SCL
SCL
tSU:STA
tHD:STA
tSU:STO
DATA(n)
DATA(1)
SDA
SDA
D1
D0
ACK
ACK
tHIGH:WP
START BIT
STOP BIT
Figure 1-(b). Start - Stop Bit Timing
SCL
tWR
WP
○At write execution, in the area from the D0 taken clock rise of the first DATA(1),
to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
Figure 1-(e). WP Timing at Write Cancel
SDA
D0
ACK
WRITE DATA(n)
tWR
STOP
CONDITION
START
CONDITION
Figure 1-(c). Write Cycle Timing
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Datasheet
BRCA016GWZ-W (16Kbit)
Block Diagram
Vｃｃ
VCC
16Kｂｉｔ ＥＥＰＲＯＭ ARRAY
GND
8bit
11bit
ADDRESS
DECODER
SLAVE, WORD
ADDRESS REGISTER
11bit
START
TEST
DATA
REGISTER
WP
STOP
SCL
CONTOROL LOGIC
ACK
HIGH VOLT GEN
SDA
Vcc LEVEL DETECT
Pin Configuration
(BOTTOM VIEW)
B
○
○
○
GND TEST
SDA
A
○
○
○
SCL
VCC
WP
B1
B2
B3
A1
A2
A3
1
2
3
Pin Descriptions
Land No.
Pin Name
I/O
B3
TEST
Input
B2
GND
-
B1
SDA
Input,
Output
A3
VCC
-
Power supply
A2
WP
Input
Write protect
A1
SCL
Input
Serial clock input
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Descriptions
TEST terminal, connect to GND
Ground (0V)
Slave word address
Serial data input
Serial data output
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Datasheet
BRCA016GWZ-W (16Kbit)
Input High Voltage1: VIH 1(V)
Input Low Voltage1: VIL1 (V)
Typical Performance Curves
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 3. Input Low Voltage1 vs Supply Voltage
(SCL,SDA,WP)
Output Low Voltage1: VOL1 (V)
Output Low Voltage2: VOL2 (V)
Figure 2. Input High Voltage1 vs Supply Voltage
(SCL,SDA,WP)
Output Low Current: IOL (mA)
Output Low Current: IOL (mA)
Figure 4. Output Low Voltage1 vs Output Low
Current (VCC=2.5V)
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Figure 5. Output Low Voltage2 vs Output Low Current
(VCC=1.7V)
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Datasheet
BRCA016GWZ-W (16Kbit)
Input Leakage Current: ILI(µA)
Output Leakage Current: ILO(µA)
Typical Performance Curves – Continued
Supply Voltage : VCC(V)
Figure 6. Input Leakage Current
vs Supply Voltage
(SCL, WP)
Figure 7. Output Leakage Current
vs Supply Voltage
(SDA)
Supply Current (Write): ICC1 (mA)
Supply Current (Read): ICC2 (mA)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 8. Supply Current (Write) vs Supply Voltage
(fSCL=400kHz)
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Figure 9. Supply Current (Read) vs Supply Voltage
(fSCL=400kHz)
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Datasheet
BRCA016GWZ-W (16Kbit)
Clock Frequency: fSCL(kHz)
Standby Current: ISB(µA)
Typical Performance Curves – Continued
Supply Voltage : VCC(V)
Figure 10. Standby Current vs Supply Voltage
Figure 11. Clock Frequency vs Supply Voltage
Data Clock High Period: tHIGH(µA)
Data Clock Low Period: tLOW(µs)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 13. Data Clock Low Period
vs Supply Voltage
Figure 12. Data Clock High Period
vs Supply Voltage
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Ta=85℃
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Datasheet
BRCA016GWZ-W (16Kbit)
Start Condition Hold Time: tHD:STA(µs)
Start Condition Setup Time: tSU:STA(µA)
Typical Performance Curves – Continued
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 14. Start Condition Hold Time
vs Supply Voltage
Input Data Hold Time: tHD:DAT(ns)
Input Data Setup Time: tSU:DAT(ns)
Figure 15. Start Condition Setup Time
vs Supply Voltage
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 16. Input Data Hold Time
vs Supply Voltage
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Figure 17. Input Data Setup Time
vs Supply Voltage
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Datasheet
BRCA016GWZ-W (16Kbit)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 18. Output Data Delay Time
vs Supply Voltage
(LOW)
Figure 19. Output Data Delay Time
vs Supply Voltage
(HIGH)
Write Cycle Time: tWR(ms)
Bus Free Time: tBUF(µs)
Output Data Delay Time: tPD(µs)
Output Data Delay Time: tPD(µs)
Typical Performance Curves – Continued
Ta=85℃
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 21. Write Cycle Time vs Supply Voltage
Figure 20. Bus Free Time vs Supply Voltage
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Datasheet
BRCA016GWZ-W (16Kbit)
EFFECTIVE
Noise
Spike Width(SCL HIGH): tl(µs)
EFFECTIVE
Noise Spike Width(SDA HIGH): tl(µs)
Typical Performance Curves – Continued
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 22. Noise Spike Width vs Supply Voltage
(SCL HIGH)
WP Setup Time: tSU:WP(µs)
WP High Period: tHIGH:WP(µs)
Figure 23. Noise Spike Width vs Supply Voltage
(SDA HIGH)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 25. WP High Period
vs Supply Voltage
Figure 24. WP Setup Time
vs Supply Voltage
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Datasheet
BRCA016GWZ-W (16Kbit)
Timing Chart
1.
I2C BUS Data Communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
2
and acknowledge is always required after each byte. I C BUS data communication with several devices is possible by
connecting with 2 communication lines: serial data (SDA) and serial clock (SCL).
Among the devices, there should be a “master” that generates clock and control communication start and end. The rest
become “slave” which are controlled by an address peculiar to each device, like this EEPROM. The device that outputs
data to the bus during data communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-7
SCL
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
DATA
8
9
ACK
1-7
DATA
8
9
ACK
P
STOP
condition
Figure 26. Data Transfer Timing
2.
Start Condition (Start Bit Recognition)
(1) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL
is 'HIGH' is necessary.
(2) This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition
is satisfied, any command cannot be executed.
3.
Stop Condition (Stop Bit Recognition)
(1) Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is
'HIGH'
4.
Acknowledge (ACK) Signal
(1) The acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
a master-slave communication, the device (Ex. µ-COM sends slave address input for write or read command, to
this IC ) at the transmitter (sending) side releases the bus after output of 8bit data.
(2) The device (Ex. This IC receives the slave address input for write or read command from the µ-COM) at the
receiver (receiving) side sets SDA 'LOW' during the 9th clock cycle, and outputs acknowledge signal (ACK signal)
showing that it has received the 8bit data.
(3) This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
(4) After receiving 8bit data (word address and write data) during each write operation, this IC outputs acknowledge
signal (ACK signal) 'LOW'..
(5) During read operation, this IC outputs 8bit data (read data) and detects acknowledge signal (ACK signal) 'LOW'.
When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side,
this IC continues to output data. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer,
recognizes stop condition (stop bit), and ends read operation. Then this IC becomes ready for another
transmission.
5.
Device Addressing
(1) Slave address comes after start condition from master.
(2) The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
(3) Next slave addresses (P2 P1 P0) are upper 3bit of word address, put these and word address ( WA0 to WA7 )
together, 11bit word address ( 2048byte ) of the device specified.
(4) The most insignificant bit ( R / W --- READ / WRITE) of slave address is used for designating write or read
operation, and is as shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
Type
BRCA016GWZ-W
Maximum Number of
Connected Buses
Slave address
1 0 1
0
P2 P1 P0
R/W
1
P0 to P2 are page select bits (Upper 3bit of word address).
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Datasheet
BRCA016GWZ-W (16Kbit)
Write Command
1. Write Cycle
(1) Arbitrary data can be written to this EEPROM. When writing only 1 byte, Byte Write is normally used, and when
writing continuous data of 2 bytes or more, simultaneous write is possible by Page Write cycle. The maximum
number of bytes is specified per device of each capacity. Up to 16 arbitrary bytes can be written.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS
WA
7
1 0 1 0 P2 P1 P0
S
T
O
P
DATA
WA
0
D7
D0
A
C
K
R A
/ C
W K
A
C
K
Figure 27. Byte Write Cycle
S
T
A
R
T
SDA
L IN E
SLAVE
ADDRESS
W
R
I
T
E
WA
7
2A 1A 0
1 0 1 0 AP2P1P0
注)
W ORD
A D D R E S S (n )
R A
/ C
W K
D A TA (n +1 5 )
D A TA (n)
WA
0
D7
A
C
K
S
T
O
P
D0
D0
A
C
K
A
C
K
Figure 28. Page Write Cycle
(2)
(3)
(4)
(5)
Data is written to the address designated by word address (n-th address)
By issuing stop bit after 8bit data input, internal write to memory cell starts.
When internal write is started, command is not accepted for tWR (5ms at maximum).
Using page write cycle, writing in bulk is done as follows: When data of more than 16bytes is sent, the byte in
excess overwrites the data already sent first. (Refer to "Internal Address Increment" in Page 13.)
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Datasheet
BRCA016GWZ-W (16Kbit)
2. Notes on Write Cycle Continuous Input
At SP (stop bit),
write starts.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS（ｎ）
WA
0
WA
7
1 0 1 0 P2P1P0
DATA (n)
R A
/ C
W K
D7
S
T
O
P
DATA (n+15)
D0
A
C
K
D0
1 0 1 0
A
C
K
A
C
K
S
T
A
R
T
Next command
tWR (maximum : 5ms)
Command is not accepted for this period.
Figure 29. Page Write Cycle
3. Notes on Page Write Cycle
List of numbers of page write
Number of Pages
16Byte
Product Number
BRCA016GWZ-W
The above numbers are maximum bytes
for respective types.
Any bytes below these can be written.
In the case BRCA016GWZ-W, 1 page=16bytes, but the page
write cycle write time is 5ms at maximum for 16byte bulk write.
It does not stand 5ms at maximum × 16byte=80ms (Max)
4. Internal Address Increment
Page Write Mode
WA7 ----0
----0
----0
-----
WA4
0
0
0
WA3
0
0
0
WA2
0
0
0
-------------
WA0
0
1
0
Increment
---------
---------
0Eh
0
0
0
WA1
0
0
1
0
0
0
1
1
0
1
1
0
For example, when it is started from address 0Eh,
then, increment is made as below,
1
1
0
0Eh → 0Fh → 00h → 01h ---, please take note.
0
1
0
*
0Eh･･･0E in hexadecimal, therefore, 00001110 becomes a
binary number.
Significant bit is fixed.
No digit up
5. Write Protect (WP) Terminal
Write Protect (WP) Function
When WP terminal is set at Vcc (H level), data rewrite of all addresses is prohibited. When it is set at GND (L level), data
rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not
leave it open.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', write error can be prevented.
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Datasheet
BRCA016GWZ-W (16Kbit)
Read Command
1. Read Cycle
Read cycle is when data of EEPROM is read. Read cycle could be random read cycle or current read cycle. Random
read cycle is a command to read data by designating a specific address, and is used generally. Current read cycle is a
command to read data of internal address register without designating an address, and is used when to verify just after
write cycle. In both the read cycles, sequential read cycle is available where the next address data can be read in
succession.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
S
T
A
R
T
WORD
ADDRESS(n)
WA
7
1 0 1 0 P2P1P0
WA
0
R A *1
/ C
WK
R
E
A
D
SLAVE
ADDRESS
DATA(n)
1 0 1 0 A2A1A0
A
C
K
S
T
O
P
It is necessary to input 'H' to
the last ACK.
D0
D7
A
C
K
R A
/ C
WK
Figure 30. Random Read Cycle
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 P2P1P0
S
T
O
P
DATA(n)
D7
It is necessary to input 'H' to
the last ACK.
D0
A
C
K
R A
/ C
WK
Figure 31. Current Read Cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 P2 P1P0
DATA(n)
D7
R A
/ C
W K
S
T
O
P
DATA(n+x)
D0
D7
A
C
K
D0
A
C
K
A
C
K
Figure 32. Sequential Read Cycle (in the case of Current Read Cycle)
(1) In Random Read Cycle, data of designated word address can be read.
(2) When the command just before current read cycle is random read cycle, current read cycle (each including
sequential read cycle), data of incremented last read address (n)-th, i.e., data of the (n+1)-th address is output.
(3) When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next
address data can be read in succession.
(4) Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal goes from ‘L’ to
‘H’ while SCL signal is 'H' .
(5) When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. To end the read command cycle, be sure to input 'H' to ACK
signal after D0, and the stop condition where SDA goes from ‘L’ to ‘H’ while SCL signal is 'H'.
(6) Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is
asserted from ‘L’ to ‘H’ while SCL signal is 'H'.
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BRCA016GWZ-W (16Kbit)
Software Reset
Software reset is executed to avoid malfunction after power on and during command input. Software reset has several
kinds and 3 kinds of them are shown in the figure below. (Refer to Figure 33(a), Figure 33(b), and Figure 33(c).) Within the
dummy clock input area, the SDA bus is released ('H' by pull up) and ACK output and read data '0' (both 'L' level) may be
output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
Start×2
Dummy clock×14
SCL
1
2
13
Normal command
14
SDA
Normal command
Figure 33-(a) The case of 14 dummy clock +START+START+ command input
SCL
Start
Dummy clock×9
Start
1
2
8
9
Normal command
SDA
Normal command
Figure 33-(b) The case of START +9 dummy clocks +START+ command input
Start×9
SCL
1
2
3
8
7
9
Normal command
SDA
Normal command
Figure 33-(c) START×9+ command input
※
タ
Acknowledge Polling
Start command from START input.
ト
During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic
write execution after write cycle input, next command (slave address) is sent. If the first ACK signal sends back 'L', then it
means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge
polling, next command can be executed without waiting for tWR = 5ms.
To write continuously, R / W = 0, then to carry out current read cycle after write, slave address with R / W = 1 is sent. If
ACK signal sends back 'L', and then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is returned.
First write command
S
T
A
R
T
Write command
S
T
O
P
S
T Slave
A
R Address
T
A
C
K
H
tWR
S
T Slave
A
R Address
T
A
C
K
H
Second Write Command
…
S
T Slave
A
R Address
T
A
C
K
H
S
T Slave
A
R Address
T
A
C Word
K Address
L
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal write,
ACK=LOW is sent back, so input next
word address and data in succession.
Figure 34. Case of Continuous Write by Acknowledge Polling
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BRCA016GWZ-W (16Kbit)
WP Valid Timing (Write Cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. Set the setup
time to rise of D0 taken SCL 100ns or more. The area from the rise of SCL to take in D0 to input the stop condition is cancel
valid area. And, after execution of forced end by WP, standby status gets in.
・Rise of SDA
・Rise of D0 taken clock
SCL
SDA
SCL
D1
D0
ACK
SDA
Enlarged view
SDA
S
T Slave
A
R Address
T
A
C Word
K Address
L
D0
ACK
Enlarged view
A
C D7 D6 D5 D4 D3 D2 D1 D0
K
L
WP Cancel invalid area
A
C
K
L
Data
A
C
K
L
S
T
O
P
WP Cancel valid area
tWR
WP Cancel invalid area
WP
Data is not written.
Figure 35. WP Valid Timing
Command Cancel by Start Condition and Stop Condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure 36)
However, within ACK output area and during data read, SDA bus may output 'L'. In this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. When command is cancelled by
start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined. Therefore, it is not possible to carry out current read cycle in succession. To carry out read cycle in succession,
carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Figure 36. Case of Cancel by Start, Stop Condition during Slave Address Input
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Datasheet
BRCA016GWZ-W (16Kbit)
I/O Peripheral Circuit
1. Pull Up Resistance of SDA terminal
SDA is NMOS open drain, so it requires a pull up resistor. As for this resistance value (RPU), select an appropriate value
from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, operating frequency is limited. The smaller
the RPU, the larger is the supply current (Read).
2. Maximum Value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or lower.
Furthermore, AC timing should be satisfied even when SDA rise time is slow.
(2)The bus’ electric potential A to be determined by the input current leak total (IL) of the device connected to the
bus with output of 'H' to the SDA line and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and
EEPROM including recommended noise margin of 0.2Vcc.
VCC - ILRPU － 0.2Vcc ≧ VIH
BRCA016GWZ-W
Microcontroller
∴
RPU ≦
0.8Vcc－VIH
RPU
IL
SDA Terminal
A
Ex. ) When VCC =3V, IL=10μA, VIH=0.7 VCC,
From (2)
RPU ≦
IL
0.8×3－0.7×3
Bus Line
Capacity
CBUS
-6
10×10
≦ 300 [kΩ]
3.
IL
Figure 37. I/O Circuit Diagram
Minimum Value of RPU
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
VCC－VOL
RPU
≦ IOL
∴
RPU ≧
VCC－VOL
IOL
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including the recommended noise
margin 0.1 of Vcc.
VOLMAX ≦ VIL-0.1 VCC
Ex.) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
From (1)
3－0.4
RPU ≧
≧
3×10
-3
867 [Ω]
And
VOL = 0.4 [V]
VIL = 0.3×3
= 0.9 [V]
Therefore, the condition (2) is satisfied.
4. Pull-up Resistance of SCL Terminal
When SCL control is made at the CMOS output port, there is no need for a pull up resistor. But when there is a time
where SCL becomes 'Hi-Z', add a pull up resistor. As for the pull up resistor value, one of several kΩ to several ten kΩ
is recommended in consideration of drive performance of output port of microcontroller.
5. Process of WP Terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In case of 'L', both are available. If using as an ROM, it is recommended to connect it
to pull up or Vcc. If using both READ and WRITE, control WP terminal or connect it to pull down or GND.
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Datasheet
BRCA016GWZ-W (16Kbit)
Cautions on Microcontroller Connection
1.
RS
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when using CMOS input / output of
tri state to SDA port, insert a series resistance RS between the pull up resistor RPU and the SDA terminal of EEPROM.
This is to control over current that may occur when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. RS also plays the role of protection the SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, RS can be used.
ACK
RPU
SCL
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
Figure 39. Input / Output Collision Timing
Figure 38. I/O Circuit Diagram
2. Maximum Value of RS
The maximum value of RS is determined by the following relations:
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower.
Furthermore, AC timing should be satisfied even when SDA rise time is slow.
A to be determined by RPU and RS the moment when EEPROM outputs 'L' to SDA bus
(2)The bus electric potential ○
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin of 0.1Vcc.
(VCC－VOL)×RS
RPU+RS
VCC
RPU
RS
A
∴ RS ≦
VOL
+ VOL+0.1VCC≦VIL
VIL－VOL－0.1VCC
1.1VCC－VIL
×
RPU
IOL
Example）When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ,
Bus line
capacity CBUS
VIL
from (2),
EEPROM
Microcontroller
RS ≦
0.3×3－0.4－0.1×3
×
1.1×3－0.3×3
20×10
3
≦ 1.67 [kΩ]
Figure 40. I/O Circuit Diagram
3. Minimum Value of RS
The minimum value of RS is determined by over current at bus collision. When over current flows, noises in power source
line and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of the impedance of power source
line in set and so forth. Set the over current to EEPROM at 10mA or lower.
VCC
≦
RS
RPU
'L' output
RS
∴ RS ≧
Over currentⅠ
I
VCC
I
Example）
When VCC=3V, I=10mA
'H' output
RS
Microcontroller
EEPROM
3
-3
10×10
≧ 300[Ω]
Figure 41. I/O Circuit Diagram
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BRCA016GWZ-W (16Kbit)
I/O Equivalence Circuit
1.
Input (SCL, WP)
Figure 42. Input Pin Circuit Diagram
2.
Input / Output (SDA)
Figure 43. Input / Output Pin Circuit Diagram
Power-Up / Down Conditions
At power on, the IC’s internal circuits may go through unstable low voltage area as the Vcc rises, making the IC’s internal
logic circuit not completely reset, hence, malfunction may occur. To prevent this, the IC is equipped with POR circuit and
LVCC circuit. To assure the operation, observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Recommended conditions of tR , tOFF , Vbot
tOFF
Vbot
0
tR
tOFF
Vbot
10ms or below
10ms or longer
0.3V or below
100ms or below
10ms or longer
0.2V or below
Figure 44. Rise Waveform Diagram
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
(1) In the case when the above condition 1 cannot be observed such that SDA becomes 'L' at power on.
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
Figure 45. When SCL= 'H' and SDA= 'L'
tSU:DAT
Figure 46. When SCL='H' and SDA='L'
(2) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(Page 15).
(3) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out (1), and then carry out (2).
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BRCA016GWZ-W (16Kbit)
Low Voltage Malfunction Prevention Function
LVCC circuit prevents data rewrite operation at low power and prevents write error. At LVCC voltage (Typ =1.2V) or
below, data rewrite is prevented.
Noise Countermeasures
1. Bypass Capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a
bypass capacitor (0.1μF) between the IC’s Vcc and GND pins. Connect the capacitor as close to the IC as possible. In
addition, it is also recommended to attach a bypass capacitor between the board’s Vcc and GND.
Operational Notes
1.
Described numeric values and data are design representative values only and the values are not guaranteed.
2.
We believe that the application circuit examples in this document are recommendable. However, in actual use,
confirm characteristics further sufficiently. If changing the fixed number of external parts is desired, make your
decision with sufficient margin in consideration of static characteristics, transient characteristics, and fluctuations of
external parts and our LSI.
3.
Absolute maximum ratings
If the absolute maximum ratings such as supply voltage, operating temperature range and so on are exceeded, LSI
may be destroyed. Do not supply voltage or subject the IC to temperatures exceeding the absolute maximum ratings.
In the case of fear of exceeding the absolute maximum ratings, take physical safety countermeasures such as
adding fuses, and see to it that conditions exceeding the absolute maximum ratings should not be supplied to the
LSI.
4.
GND electric potential
Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is not lower
than that of GND terminal.
5.
Thermal design
Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in
actual operating conditions.
6.
Short between pins and mounting errors
Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong
orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the
pins.
7.
Operating the IC in the presence of strong electromagnetic field may cause malfunction, therefore, evaluate design
sufficiently.
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Datasheet
BRCA016GWZ-W (16Kbit)
Part Numbering
B
R
C
A
0
1
G W
6
Part Number
Z
-
W
E2
Package
GWZ: UCSP30L1(BRCA016GWZ-W)
Packaging and Forming Specification
E2: Embossed tape and reel
Physical Dimension Tape and Reel Information
UCSP30L1
(BRCA016GWZ-W)
UCSP30L1
(BRCA016GWZ-W)
6-φ0.20±0.05
0.05 A B
A
B
B
A
1
0.25±0.05
2
0.35MAX
0.185±0.05
0.06 S
S
0.4
1.30±0.05
0.08±0.05
0.77±0.05
1PIN MARK
3
P=0.4×2
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
)
∗ Order quantity needs to be multiple of the minimum quantity.
Marking Diagram
UCSP30L1 (BRCA016GWZ-W)
(TOP VIEW)
1PIN MARK
Part Number Marking
A B 3
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Datasheet
BRCA016GWZ-W (16Kbit)
Revision History
Date
Revision
5.Sep.2012
25.Feb.2013
001
002
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Changes
New Release
Update some English words, sentences’ descriptions, grammar and formatting.
Update Figure 35. WP Valid Timing.
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Datasheet
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●General Precaution
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ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
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notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
●Precaution on using ROHM Products
1) Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
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serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
2)
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
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a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
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Our Products are designed and manufactured for use under standard conditions and not under any special or
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H2S, NH3, SO2, and NO2
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[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4)
The Products are not subject to radiation-proof design.
5)
Please verify and confirm characteristics of the final or mounted products in using the Products.
6)
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse) is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7)
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8)
Confirm that operation temperature is within the specified range described in the product specification.
9)
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
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Datasheet
●Precaution for Mounting / Circuit board design
1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2)
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
●Precautions Regarding Application Examples and External Circuits
1) If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2)
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
●Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
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isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
●Precaution for Storage / Transportation
1) Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2)
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3)
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4)
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
●Precaution for Product Label
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please consult with ROHM representative in case of export.
●Precaution Regarding Intellectual Property Rights
1) All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2)
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
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Datasheet
●Other Precaution
1) The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
2)
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
3)
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
4)
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
5)
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
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