GAL20V8/883

GAL20V8/883
High Performance E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
I/CLK
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 10 ns Maximum Propagation Delay
— Fmax = 62.5 MHz
— 7 ns Maximum from Clock Input to Data Output
— TTL Compatible 12 mA Outputs
— UltraMOS® Advanced CMOS Technology
I
IMUX
I
CLK
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
I/O/Q
I
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
I
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 24-pin PAL® Devices with Full Function/
Fuse Map/Parametric Compatibility
I
PROGRAMMABLE
AND-ARRAY
(64 X 40)
• 50% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
I
I
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
8 OLMC
I/O/Q
8
I/O/Q
I
I
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
OLMC
OE
I
I
Description
IMUX
I/OE
The GAL20V8/883 is a high performance E2CMOS programmable logic devices processed in full compliance to MIL-STD883. This military grade device combines a high performance
CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed/power performance available
in the 883 qualified PLD market.
Pin Configuration
4
I
CERDIP
2
28
I/O/Q
I
NC
I/CLK
Vcc
I/CLK
I
The generic GAL architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL20V8/883 is capable of emulating all
standard 24-pin PAL® devices with full function/fuse map/parametric compatibility.
I
LCC
26
25
5
I
I
GAL20V8
23
NC
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. Therefore,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are specified.
I
Top View
9
21
I
11
I
I/OE
I/O/Q
19
18
16
NC
14
I
I
12
I
I/O/Q
NC
I
I/O/Q
I/O/Q
GAL
20V8
I
I
I/O/Q
Vcc
I
I/O/Q
I/O/Q
GND
I
24
I/O/Q
I/O/Q
7
1
I
I/O/Q
I/O/Q
6
18
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I
GND
12
13
I/OE
Copyright © 2010 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20v8mil_04
1
April 2010
Devices have been discontinued.
8
Specifications GAL20V8B/883
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage VCC ...................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ................................ –65 to 150°C
Case Temperature with
Power Applied ........................................ –55 to 125°C
CaseTemperature (TC)............................... –55 to 125°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
VIL
VIH
IIL
MIN.
TYP.3
MAX.
UNITS
Input Low Voltage
Vss – 0.5
—
0.8
V
Input High Voltage
2.0
—
Vcc+1
V
0V ≤ VIN ≤ VIL (MAX.)
—
—
-100
μA
0V ≤ VIN ≤ VIL (MAX.)
—
—
-10
μA
Input or I/O High Leakage Current
3.5VIH ≤ VIN ≤ VCC
—
—
10
μA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.5
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Low Level Output Current
—
—
12
mA
High Level Output Current
—
—
–2.0
mA
–30
—
–150
mA
—
75
130
mA
PARAMETER
CONDITION
Input or I/O Low Leakage Current
for -10 Speed Grade
1
Input or I/O Low Leakage Current
for -15 and -20 Speed Grades
IIH
VOL
VOH
IOL
IOH
IOS2
ICC
Output Short Circuit Current
VCC = 5V VOUT = 0.5V TA= 25°C
Operating Power
VIL = 0.5V VIH = 3.0V
L -10/-15/-20
Supply Current
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
2
Devices have been discontinued.
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
Specifications GAL20V8B/883
AC Switching Characteristics
Over Recommended Operating Conditions
PARAMETER
-10
TEST DESCRIPTION
COND1.
fmax3
twh
twl
ten
tdis
-20
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
Input or I/O to Combinational Output
2
10
2
15
2
20
ns
A
Clock to Output Delay
1
7
1
12
1
15
ns
—
Clock to Feedback Delay
—
7
—
12
—
15
ns
—
Setup Time, Input or Feedback before Clock↑
10
—
12
—
15
—
ns
—
Hold Time, Input or Feedback after Clock↑
0
—
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
58.8
—
41.6
—
33.3
—
MHz
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
58.8
—
41.6
—
33.3
—
MHz
A
Maximum Clock Frequency with
No Feedback
62.5
—
50
—
41.6
—
MHz
—
Clock Pulse Duration, High
8
—
10
—
12
—
ns
—
Clock Pulse Duration, Low
8
—
10
—
12
—
ns
B
Input or I/O to Output Enabled
—
10
—
15
—
20
ns
B
OE to Output Enabled
—
10
—
15
—
18
ns
C
Input or I/O to Output Disabled
—
10
—
15
—
20
ns
C
OE to Output Disabled
—
10
—
15
—
18
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
10
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
10
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
3
Devices have been discontinued.
tpd
tco
tcf2
tsu
th
-15
Specifications GAL20V8/883
Switching Waveforms
INPUT or
I/O FEEDBACK
VALID INPUT
tsu
th
CLK
INPUT or
I/O FEEDBACK
VALID INPUT
tco
tpd
COMBINATIONAL
OUTPUT
1/fmax
(external fdbk)
Combinatorial Output
Registered Output
INPUT or
I/O FEEDBACK
OE
tdis
ten
tdis
COMBINATIONAL
OUTPUT
ten
REGISTERED
OUTPUT
Input or I/O to Output Enable/Disable
twh
OE to Output Enable/Disable
twl
CLK
1/ fmax (internal fdbk)
CLK
tcf
1/ fmax
(w/o fb)
REGISTERED
FEEDBACK
Clock Width
fmax with Feedback
4
tsu
Devices have been discontinued.
REGISTERED
OUTPUT
Specifications GAL20V8/883
fmax Descriptions
CLK
CLK
LOGIC
ARRAY
REGISTER
REGISTER
tsu
tco
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
t cf
t pd
CLK
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC
ARRAY
REGISTER
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
+5V
GND to 3.0V
3ns 10% – 90%
1.5V
1.5V
Output Load
R1
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (O/Q)
UNDER TEST
Output Load Conditions (see figure)
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
TEST POINT
R2
R1
R2
CL
390Ω
∞
390Ω
∞
390Ω
750Ω
750Ω
750Ω
750Ω
750Ω
50pF
50pF
50pF
5pF
5pF
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
5
Devices have been discontinued.
LOGIC
ARRAY
Specifications GAL20V8/883
GAL20V8 Ordering Information (MIL-STD-883 and SMD)
Ordering #
Tpd
(ns)
Tsu
(ns)
Tco
(ns)
Icc
(mA)
Package
10
10
7
130
24-Pin CERDIP
15
15
12
15
SMD #
GAL20V8B-10LD/8832
5962-8984004LA
1
5962-89840043A
130
28-Pin LCC
GAL20V8B-10LR/883
130
24-Pin CERDIP
GAL20V8B-15LD/8832
5962-8984003LA
2
5962-89840033A
130
28-Pin LCC
GAL20V8B-15LR/883
130
24-Pin CERDIP
GAL20V8B-20LD/8832
5962-8984002LA
2
5962-89840023A
130
28-Pin LCC
GAL20V8B-20LR/883
Note: Lattice Semiconductor recognizes the trend in military device procurement towards
using SMD compliant devices, as such, ordering by this number is recommended.
1. Discontinued per PCN #06-07.
2. Discontinued per PCN #05A-10.
Part Number Description
6
Devices have been discontinued.
20
12
MIL-STD-883